Semiconductor device and electronic device

Abstract

To provide a semiconductor device which has low power consumption and enables operation.SOLUTION: A semiconductor device has first to third circuits, and first and second cells. The first cell has a first transistor, and a second cell has a second transistor. Also, the first and second transistors operate in a sub-threshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to first current, and the second cell sets current flowing from the second circuit to the second transistor to second current. In such a case, a potential corresponding to the second current is inputted to the first cell. Next, third current is made to flow from a sensor included in the third circuit, and the first cell outputs fourth current corresponding to a change amount of a potential and the first current by changing the potential of a second wiring.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In a neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0005] Non-Patent Document 1 proposes a multiply-and-accumulate circuit using non-volatile memory elements. In this multiply-and-accumulate circuit, each memory element utilizes the subthreshold operation of a transistor having silicon in its channel formation region to output a current corresponding to the multiplication of data corresponding to a multiplier stored in the memory element and input data corresponding to a multiplicand. Furthermore, data corresponding to the multiply-and-accumulate operation is obtained by summing the currents output by the memory elements in each column. Because this multiply-and-accumulate circuit has internal memory elements, it is possible to eliminate the need to read and write data from and to external memory during multiplication and addition. This reduces the number of data transfers due to reads and writes, and is therefore expected to reduce power consumption. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. Summary of the Invention [Problem to be solved by the invention]

[0007] A transistor having silicon in the channel formation region is susceptible to temperature changes in transistor characteristics, field-effect mobility, etc. In particular, when a product-sum operation circuit or the like is formed as an integrated circuit, the temperature of the integrated circuit increases due to heat generated when the circuit is operated, which may change the characteristics of the transistors included in the integrated circuit and prevent correct operation.

[0008] Furthermore, when a multiply-and-accumulate operation is performed using a digital circuit, a digital multiplier circuit multiplies digital data (multiplier data) that serves as a multiplier by digital data (multiplicand data) that serves as a multiplicand. Then, a digital adder circuit adds the digital data (product data) obtained by the multiplication, and obtains digital data (product-and-accumulate data) as the result of the multiply-and-accumulate operation. It is preferable that the digital multiplier circuit and the digital adder circuit are capable of handling multi-bit operations. However, in this case, the circuit scale of each of the digital multiplier circuit and the digital adder circuit must be increased, which may result in an increase in circuit area and power consumption.

[0009] Furthermore, by combining a calculation circuit that performs neural network calculations with a sensor, it may be possible to make electronic devices recognize various information. For example, by combining an optical sensor (e.g., a photodiode) as a sensor with the calculation circuit, it is possible to perform pattern recognition such as face recognition and image recognition from image data obtained by the optical sensor.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing a product-sum operation.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.An object of one embodiment of the present invention is to provide a semiconductor device in which a decrease in operating capability due to heat is suppressed.

[0011] Another object of one embodiment of the present invention is to provide a novel semiconductor device or an electronic device including the semiconductor device.

[0012] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, a first cell, a second cell, a first wiring, and a second wiring. The first cell includes a first transistor, the second cell includes a second transistor, and the third circuit includes a sensor and a third transistor. The first cell is electrically connected to the first circuit via the first wiring, the first cell is electrically connected to the second wiring, the second cell is electrically connected to the second wiring, the sensor is electrically connected to a first terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the second wiring. The first circuit has a function of passing a first current from the first circuit to the first cell via the first wiring, and the second circuit has a function of passing a second current to the second wiring. The sensor also has a function of performing sensing and outputting a third current according to the sensing result, and the third circuit has a function of passing the third current to the second wiring when the third transistor is in an on state. In addition, the first cell has a function of setting the amount of current flowing between the first terminal and the second terminal of the first transistor to the amount of the first current by holding a potential corresponding to the first current at the gate of the first transistor, and the second cell has a function of setting the amount of current flowing between the first terminal and the second terminal of the second transistor to the amount of current flowing in the second wiring by holding a potential corresponding to the current flowing in the second wiring at the gate of the second transistor.

[0014] (2) In the configuration (1) above, the second circuit may have a function of passing a second current from the second circuit to the second cell via the second wiring when the third transistor is in an off state, and applying a first potential corresponding to the amount of the second current to each of the first cell and the second cell via the second wiring from the second circuit. The third circuit may have a function of changing the first potential applied to each of the first cell and the second cell to a second potential by turning on the third transistor and passing a third current from the third circuit to the second wiring. The first cell may have a function of changing the amount of the first current flowing between the first terminal and the second terminal of the first transistor to an amount of a fourth current corresponding to the difference between the first potential and the second potential when the third transistor is switched from an off state to an on state. The amount of the first current and the amount of the fourth current are within the range of the current that flows when the first transistor operates in the subthreshold region, and the amount of the second current, the amount of the third current, and the sum of the amount of the second current and the amount of the third current are within the range of the current that flows when the second transistor operates in the subthreshold region.

[0015] (3) In the above configuration (1) or (2), the channel formation regions of the first transistor and the second transistor may each contain a metal oxide.

[0016] (4) One embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, a first cell, a second cell, a first wiring, and a second wiring. The first cell includes a first transistor, a fourth transistor, and a first capacitor. The second cell includes a second transistor, a fifth transistor, and a second capacitor. The third circuit includes a sensor and a third transistor. The first circuit is electrically connected to the first wiring, the second circuit is electrically connected to the second wiring, and the third circuit is electrically connected to the second wiring. A first terminal of the first transistor is electrically connected to a first terminal of the fourth transistor and the first wiring, a gate of the first transistor is electrically connected to a second terminal of the fourth transistor and a first terminal of the first capacitor, and a second terminal of the first capacitor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the first terminal of the fifth transistor and the second wiring, the gate of the second transistor is electrically connected to the second terminal of the fifth transistor and the first terminal of the second capacitor, and the second terminal of the second capacitor is electrically connected to the second wiring. The sensor is electrically connected to the first terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the second wiring. The first circuit has a function of passing a first current from the first circuit to the first cell via the first wiring, and the second circuit has a function of passing a second current to the second wiring. The sensor has a function of performing sensing and outputting a third current according to the sensing result, and the third circuit has a function of passing the third current to the second wiring when the third transistor is in an on state. The first cell has a function of setting the amount of current flowing between the first terminal and the second terminal of the first transistor to the amount of the first current by holding a potential corresponding to the first current at the gate of the first transistor, and the second cell has a function of setting the amount of current flowing between the first terminal and the second terminal of the second transistor to the amount of current flowing in the second wiring by holding a potential corresponding to the current flowing in the second wiring at the gate of the second transistor.

[0017] (5) In the configuration (4) above, the second circuit may have a function of, when the third transistor is in an off state, passing a second current from the second circuit to the first terminal of the second transistor via the second wiring, and applying a first potential corresponding to the amount of the second current to each of the second terminal of the first capacitance and the second terminal of the second capacitance via the second wiring from the second circuit. The third circuit may have a function of, when the third transistor is in an on state, passing a third current from the third circuit to the second wiring, thereby changing the first potential applied to each of the second terminal of the first capacitance and the second terminal of the second capacitance to the second potential. The first cell may have a function of, when the third transistor is switched from an off state to an on state, changing the amount of the first current flowing between the first terminal and the second terminal of the first transistor to an amount of a fourth current corresponding to the difference between the first potential and the second potential. The amount of the first current and the amount of the fourth current are within the range of the current that flows when the first transistor operates in the subthreshold region, and the amount of the second current, the amount of the third current, and the sum of the amount of the second current and the amount of the third current are within the range of the current that flows when the second transistor operates in the subthreshold region.

[0018] (6) In the above configuration (4) or (5), the channel formation regions of the first transistor, the second transistor, the fourth transistor, and the fifth transistor may each contain a metal oxide.

[0019] (7) In addition, in any one of the configurations (1) to (6) above, the first circuit may include a sixth transistor and a seventh transistor. In particular, it is preferable that the seventh transistor has a first gate and a second gate, a first terminal of the sixth transistor is electrically connected to the first wiring, and a second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor, the first gate of the seventh transistor, and the second gate of the seventh transistor.

[0020] (8) In the above configuration (7), the channel formation regions of the sixth transistor and the seventh transistor may contain a metal oxide.

[0021] (9) In any one of the above configurations (1) to (8), the sensor may have a photodiode.

[0022] (10) One embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (9) above and a housing. The electronic device can perform a product-sum operation with the semiconductor device.

[0023] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0024] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0025] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0026] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0027] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0028] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0030] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0031] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also a parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0032] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0033] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0034] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0035] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0036] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0037] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0038] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0039] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0040] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0041] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," and the like are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0042] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0043] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in defect level density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding hydrogen, and oxygen.

[0044] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0047] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0048] According to one embodiment of the present invention, a semiconductor device capable of performing a product-sum operation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device in which a decrease in operating capability due to heat is suppressed can be provided.

[0049] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0050] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0051] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] 2A to 2C are block diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 3] 3A to 3D are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A to 4C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 5] FIG. 5 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a timing chart showing an example of the operation of the semiconductor device. [Figure 7] FIG. 7 is a block diagram showing a configuration example of a semiconductor device. [Figure 8] 8A to 8C are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 10] FIG. 10A is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device, and FIG. 10B is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 11] 11A and 11B are block diagrams showing examples of the configuration of a circuit included in a semiconductor device, and FIGS. 11C and 11D are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 12] FIG. 12 is a block diagram showing a configuration example of a semiconductor device. [Figure 13] 13A and 13B are block diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 14] FIG. 14 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 15] FIG. 15 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 16] FIG. 16 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 17] FIG. 17 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 18] FIG. 18 is a block diagram showing a configuration example of a semiconductor device. [Figure 19] 19A and 19B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 20] 20A and 20B are block diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 21] 21A and 21B are timing charts showing an example of the operation of the semiconductor device. [Figure 22] 22A and 22B are diagrams illustrating a hierarchical neural network. [Figure 23] FIG. 23 is a block diagram showing a configuration example of a semiconductor device. [Figure 24] FIG. 24 is a block diagram showing a configuration example of a semiconductor device. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] 27A to 27C are cross-sectional views showing examples of the structure of a transistor. [Figure 28] 28A and 28B are cross-sectional views showing examples of the structure of a transistor. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] 30A and 30B are cross-sectional views showing examples of the structure of a transistor. [Figure 31] FIG. 31 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 32] FIG. 32A is a top view showing an example of the configuration of a capacitive element, and FIGS. 32B and 32C are cross-sectional perspective views showing the example of the configuration of a capacitive element. [Figure 33] 33A is a top view showing an example of the configuration of a capacitive element, FIG. 33B is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 33C is a cross-sectional perspective view showing an example of the configuration of a capacitive element. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 35] FIG. 35A is a diagram illustrating the classification of IGZO crystal structures, FIG. 35B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 35C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 36] FIG. 36A is a perspective view showing an example of a semiconductor wafer, FIG. 36B is a perspective view showing an example of a chip, and FIGS. 36C and 36D are perspective views showing an example of an electronic component. [Figure 37] 37A to 37F are perspective views of a package and a module that house an imaging device. [Figure 38] FIG. 38 is a perspective view showing an example of an electronic device. [Figure 39] 39A to 39C are perspective views showing examples of electronic devices. [Figure 40] 40A to 40C are schematic diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0052] In an artificial neural network (hereafter referred to as a neural network), the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining the strength of connections is sometimes called "learning."

[0053] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0054] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0055] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0056] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0057] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0058] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0059] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0060] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0061] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0062] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0063] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0064] (Embodiment 1) In this embodiment, an example of a circuit capable of product-sum operation, which is a semiconductor device of one embodiment of the present invention, will be described.

[0065] <Configuration example 1 of an arithmetic circuit> 1 shows an example of the configuration of an arithmetic circuit that performs a product-sum operation on first data, which is positive or "0", and second data, which is positive or "0". The arithmetic circuit MAC1 shown in FIG. 1 is a circuit that performs a product-sum operation on first data corresponding to the potential held in each cell and input second data, and calculates an activation function using the result of the product-sum operation. Note that the first data and second data can be, for example, analog data or multi-valued data (discrete data).

[0066] The arithmetic circuit MAC1 has a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and conversion circuits ITRZ[1] to ITRZ[n] (where n is an integer greater than or equal to 1).

[0067] The cell array CA has cells IM[1,1] to IM[m,n] (where m is an integer equal to or greater than 1) and cells IMref[1] to IMref[m]. Each of cells IM[1,1] to IM[m,n] has a function of holding a potential corresponding to a current amount according to first data, and cells IMref[1] to IMref[m] have a function of supplying the held potential and a potential according to second data required for performing a product-sum operation to wirings XCL[1] to XCL[m].

[0068] Although the cell array CA in FIG. 1 has cells arranged in a matrix of m rows and n+1 columns, the cell array CA may have any configuration in which the cells are arranged in a matrix of one or more rows and two or more columns.

[0069] Each of cells IM[1,1] to IM[m,n] has, for example, a transistor F1, a transistor F2, and a capacitance C5, and each of cells IMref[1] to IMref[m] has, for example, a transistor F1m, a transistor F2m, and a capacitance C5m.

[0070] In particular, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors F1 included in each of the cells IM[1,1] to IM[m,n] are equal to each other, and it is also preferable that the sizes of the transistors F2 included in each of the cells IM[1,1] to IM[m,n] are equal to each other. It is also preferable that the sizes of the transistors F1m included in each of the cells IMref[1] to IMref[m] are equal to each other, and it is also preferable that the sizes of the transistors F2m included in each of the cells IMref[1] to IMref[m] are equal to each other. It is also preferable that the sizes of the transistors F1 and F1m are equal to each other, and it is also preferable that the sizes of the transistors F2 and F2m are equal to each other.

[0071] By making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor F1 included in each of cells IM[1,1] to IM[m,n] equal and making the size of the transistor F2 included in each of cells IM[1,1] to IM[m,n] equal, each of cells IM[1,1] to IM[m,n] can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, gate, etc. of transistor F1, the potentials of the source, drain, gate, etc. of transistor F2, and the voltages input to each of cells IM[1,1] to IM[m,n]. Similarly, by making the size of the transistor F1m included in each of cells IMref[1] to IMref[m] equal and making the size of the transistor F2m included in each of cells IMref[1] to IMref[m] equal, each of cells IMref[1] to IMref[m] can perform approximately the same operation under the same conditions. The same conditions here refer to, for example, the potentials of the source, drain, gate, etc. of transistor F1m, the potentials of the source, drain, gate, etc. of transistor F2m, and the voltages input to each of cells IMref[1] to IMref[m].

[0072] Unless otherwise specified, the transistors F1 and F1m are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to voltages within a range in which they operate in a linear region. However, one aspect of the present invention is not limited to this. For example, the transistors F1 and F1m may operate in a saturation region when they are on, or may operate in both a linear region and a saturation region.

[0073] Furthermore, unless otherwise specified, the transistors F2 and F2m are considered to operate in the subthreshold region (i.e., in the transistor F2 or F2m, the gate-source voltage is lower than the threshold voltage, more preferably, the drain current increases exponentially with the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to be appropriately biased to voltages within the range in which they operate in the subthreshold region. Therefore, the transistors F2 and F2m also include a case in which they operate such that an off-state current flows between the source and the drain.

[0074] For example, the transistor F1 and / or the transistor F1m is preferably an OS transistor. The channel formation region of the transistor F1 and / or the transistor F1m is preferably an oxide containing at least one of indium, gallium, and zinc. Instead of the oxide, an oxide containing at least one of indium, an element M (e.g., aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) and zinc may be used. The transistor F1 and / or the transistor F1m preferably has the structure of the transistor described in the fifth embodiment.

[0075] By using OS transistors as the transistors F1 and / or F1m, the leakage current of the transistors F1 and / or F1m can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when the transistors F1 and / or F1m are off, the leakage current from the retention node to the write word line can be significantly reduced, thereby reducing the number of refresh operations for the potential of the retention node. Furthermore, reducing the number of refresh operations can reduce the power consumption of the arithmetic circuit. Furthermore, by significantly reducing the leakage current from the retention node to the wiring WCL or XCL, the cell can retain the potential of the retention node for a long time, thereby improving the arithmetic accuracy of the arithmetic circuit.

[0076] Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can be manufactured simultaneously with the transistors F1 and F1m, which may shorten the manufacturing process of the arithmetic circuit. The transistors F2 and / or the transistor F2m can be transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and single-crystal silicon.

[0077] However, when semiconductor devices and the like are highly integrated on a chip, the chip may generate heat due to the operation of the circuit. This heat increases the temperature of the transistor, which can change the characteristics of the transistor, resulting in changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so they are less likely to experience changes in field-effect mobility due to temperature changes and are less likely to experience a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, by using OS transistors, it is easy to perform calculations, processing, and the like, even in high-temperature environments. Therefore, when configuring a semiconductor device that is resistant to heat generation due to operation, it is preferable to use OS transistors as the transistors.

[0078] In each of the cells IM[1,1] to IM[m,n], a first terminal of the transistor F1 is electrically connected to a gate of the transistor F2. A first terminal of the transistor F2 is electrically connected to a wiring VE. A first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2.

[0079] In each of the cells IMref[1] to IMref[m], a first terminal of the transistor F1m is electrically connected to a gate of the transistor F2m, a first terminal of the transistor F2m is electrically connected to a wiring VE, and a first terminal of the capacitor C5m is electrically connected to the gate of the transistor F2m.

[0080] 1, back gates are illustrated for transistors F1, F2, F1m, and F2m. Although the connection configuration of the back gates is not illustrated, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and back gate of transistor F1 may be electrically connected, or the gate and back gate of transistor F1m may be electrically connected. Furthermore, for example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like.

[0081] 1 have back gates, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the transistors F1 and F2 shown in FIG. 1 may have a structure without a back gate, that is, a single-gate transistor. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0082] 1 illustrates n-channel transistors as the transistors F1 and F2, the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors F1 and F2 may be replaced with p-channel transistors.

[0083] The above-described examples of changes to the structure and polarity of the transistors are not limited to transistors F1 and F2. For example, the structure and polarity may be changed in the same way for transistors F1m, F2m, transistors F3[1] to F3[n], and transistors F4[1] to F4[n], which will be described later, as well as for transistors described elsewhere in the specification or shown in other drawings.

[0084] The wiring VE is a wiring for passing a current between the first terminal and the second terminal of the transistor F2 of each of the cells IM[1,1] to IM[m,n], and also functions as a wiring for passing a current between the first terminal and the second terminal of the transistor F2m of each of the cells IMref[1] to IMref[m], as shown in FIG. 1. As an example, the wiring VE functions as a wiring for supplying a constant voltage. The constant voltage may be, for example, a low-level potential or a ground potential.

[0085] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 1, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,1] is designated as node NN[1,1].

[0086] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 1, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,1] is designated as node NN[m,1].

[0087] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 1, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,n] is referred to as node NN[1,n].

[0088] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 1, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,n] is designated as node NN[m,n].

[0089] In cell IMref[1], the second terminal of transistor F1m is electrically connected to line XCL[1], and the gate of transistor F1m is electrically connected to line WSL[1]. The second terminal of transistor F2m is electrically connected to line XCL[1], and the second terminal of capacitor C5m is electrically connected to line XCL[1]. In FIG. 1, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5m in cell IMref[1] is referred to as node NNref[1].

[0090] In cell IMref[m], the second terminal of transistor F1m is electrically connected to wiring XCL[m], and the gate of transistor F1m is electrically connected to wiring WSL[m]. The second terminal of transistor F2m is electrically connected to wiring XCL[m], and the second terminal of capacitor C5m is electrically connected to wiring XCL[m]. In FIG. 1, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5m in cell IMref[m] is referred to as node NNref[m].

[0091] Note that the nodes NN[1,1] to NN[m,n] and the nodes NNref[1] to NNref[m] function as holding nodes for the respective cells.

[0092] In cells IM[1,1] to IM[m,n], for example, when transistor F1 is in the on state, transistor F2 is configured as a diode. When transistor F1 is in the on state and a current of magnitude I flows from wiring WCL to the second terminal of transistor F2, with the constant voltage provided by wiring VE as the ground potential (GND), the potential of the gate (node NN) of transistor F2 is determined according to the current magnitude I. Since transistor F1 is in the on state, the potential of the second terminal of transistor F2 is ideally equal to the gate (node NN) of transistor F2. By turning transistor F1 off, the potential of the gate (node NN) of transistor F2 is maintained. This allows transistor F2 to pass a current of magnitude I between its source and drain, depending on the ground potential of the first terminal of transistor F2 and the potential of the gate (node NN) of transistor F2. In this specification and the like, this operation is referred to as "setting (programming) the amount of current flowing between the source and drain of transistor F2 of cell IM to I."

[0093] The circuit SWS1 includes, for example, transistors F3[1] to F3[n]. A first terminal of the transistor F3[1] is electrically connected to the wiring WCL[1], a second terminal of the transistor F3[1] is electrically connected to the circuit WCS, and a gate of the transistor F3[1] is electrically connected to the wiring SWL1. A first terminal of the transistor F3[n] is electrically connected to the wiring WCL[n], a second terminal of the transistor F3[n] is electrically connected to the circuit WCS, and a gate of the transistor F3[n] is electrically connected to the wiring SWL1.

[0094] As each of the transistors F3[1] to F3[n], for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used. In particular, as each of the transistors F3[1] to F3[n], it is preferable to use an OS transistor.

[0095] The circuit SWS1 functions as a circuit that brings the circuit WCS and each of the wirings WCL[1] to WCL[n] into a conductive state or a non-conductive state.

[0096] The circuit SWS2 includes, for example, transistors F4[1] to F4[n]. A first terminal of the transistor F4[1] is electrically connected to the wiring WCL[1], a second terminal of the transistor F4[1] is electrically connected to the input terminal of the conversion circuit ITRZ[1], and a gate of the transistor F4[1] is electrically connected to the wiring SWL2. A first terminal of the transistor F4[n] is electrically connected to the wiring WCL[n], a second terminal of the transistor F4[n] is electrically connected to the input terminal of the conversion circuit ITRZ[n], and a gate of the transistor F4[n] is electrically connected to the wiring SWL2.

[0097] As each of the transistors F4[1] to F4[n], for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used. In particular, as each of the transistors F4[1] to F4[n], it is preferable to use an OS transistor.

[0098] The circuit SWS2 has a function of bringing the wiring WCL[1] and the conversion circuit ITRZ[1] and the wiring WCL[n] and the conversion circuit ITRZ[n] into a conductive state or a non-conductive state. Although not shown in FIG. 1, the circuit SWS2 also has a function of bringing the wiring WCL and the conversion circuit ITRZ into a conductive state or a non-conductive state in any one of the second to n-1th columns.

[0099] The circuit WCS has a function of supplying data to be stored in each cell of the cell array CA.

[0100] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of supplying a current amount corresponding to reference data or second data, which will be described later, to each of the cells IMref[1] to IMref[m] included in the cell array CA.

[0101] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing first data to the cells IM[1,1] to IM[m,n], the circuit WSD has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. In other words, the wirings WSL[1] to WSL[m] function as write word lines.

[0102] For example, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2. The circuit WSD has a function of bringing the circuit WCS and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL1, and a function of bringing the conversion circuits ITRZ[1] to ITRZ[n] and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL2.

[0103] Each of the conversion circuits ITRZ[1] to ITRZ[n] has, for example, an input terminal and an output terminal. For example, the output terminal of the conversion circuit ITRZ[1] is electrically connected to the wiring OL[1], and the output terminal of the conversion circuit ITRZ[n] is electrically connected to the wiring OL[n].

[0104] Each of the conversion circuits ITRZ[1] to ITRZ[n] has a function of converting a current input to an input terminal into a voltage according to the amount of the current and outputting the voltage from an output terminal. The voltage may be, for example, an analog voltage or a digital voltage. Each of the conversion circuits ITRZ[1] to ITRZ[n] may also have a function-based arithmetic circuit. In this case, for example, the arithmetic circuit may perform a function calculation using the converted voltage, and the calculation result may be output to the wiring OL[1] to wiring OL[n].

[0105] In particular, when performing calculations on a hierarchical neural network, the above-mentioned functions may be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like.

[0106] <<Circuit WCS, Circuit XCS>> Here, specific examples of the circuit WCS and the circuit XCS will be described.

[0107] First, the circuit WCS will be described. Fig. 2A is a block diagram showing an example of the circuit WCS. Note that Fig. 2A also shows the circuit SWS1, transistor F3, wiring SWL1, and wiring WCL to show the electrical connection of the circuit WCS with the peripheral circuits.

[0108] The circuit WCS has, for example, the same number of circuits WCSa as the number of wirings WCL, that is, n circuits WCSa.

[0109] The circuit SWS1 also has transistors F3 equal to the number of wirings WCL, that is, n transistors F3.

[0110] 2A can be any one of the transistors F3[1] to F3[n] included in the arithmetic circuit MAC1 in Fig. 1. Similarly, the wiring WCL can be any one of the wirings WCL[1] to WCL[n] included in the arithmetic circuit MAC1 in Fig. 1.

[0111] Therefore, the wirings WCL[1] to WCL[n] are electrically connected to different circuits WCSa via different transistors F3, respectively.

[0112] The circuit WCSa shown in FIG. 2A includes, as an example, a switch SWW. A first terminal of the switch SWW is electrically connected to the second terminal of the transistor F3, and the second terminal of the switch SWW is electrically connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0113] As the switch SWW, for example, an electrical switch such as an analog switch or a transistor can be applied. Note that, when a transistor is applied as the switch SWW, the transistor can have the same structure as the transistors F1 and F2. Furthermore, in addition to an electrical switch, a mechanical switch may also be applied.

[0114] 2A includes a plurality of current sources CS. Specifically, the circuit WCSa includes a K-bit (2 K value) (K is an integer of 1 or more) as a current amount. In this case, the circuit WCSa has a function of outputting the first data of K The circuit WCSa has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-th bit as a current. K-1 There are individual ones.

[0115] In FIG. 2A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 of the circuit SWS1. The terminal T2 of one current source CS is electrically connected to the wiring DW[1], and the terminals T2 of the two current sources CS are electrically connected to the wiring DW[2]. K-1 Each of the terminals T2 of the current sources CS is electrically connected to a wiring DW[K].

[0116] The multiple current sources CS in the circuit WCSa each supply the same constant current I Wut from the terminal T1. In reality, errors may occur during the manufacturing stage of the arithmetic circuit MAC1 due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each terminal T1 of the multiple current sources CS is WutThe error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of the multiple current sources CS included in the circuit WCSa is Wut The following explanation will be given assuming that there is no error.

[0117] The wirings DW[1] to DW[K] are electrically connected to a current source CS and a constant current I Wut Specifically, for example, when a high-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] outputs a constant current I Wut flows to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] flows as follows: Wut For example, when a high-level potential is applied to the wiring DW[2], the two current sources CS electrically connected to the wiring DW[2] output a total of 2I Wut When a constant current of 2I flows to the second terminal of the transistor F3 and a low-level potential is applied to the wiring DW[2], the current source CS electrically connected to the wiring DW[2] flows through the second terminal of the transistor F3. Wut For example, when a high-level potential is applied to the wiring DW[K], the 2 K-1 The current sources CS are K-1 I Wut When a constant current of 100 V flows to the second terminal of the transistor F3 and a low-level potential is applied to the wiring DW[K], the current source CS electrically connected to the wiring DW[K] has a total of 2 K-1 I Wut It does not output a constant current.

[0118] The amount of current flowing from one current source CS electrically connected to the wiring DW[1] corresponds to the value of the first bit, the amount of current flowing from two current sources CS electrically connected to the wiring DW[2] corresponds to the value of the second bit, and the amount of current flowing from K current sources CS electrically connected to the wiring DW[K] corresponds to the value of the Kth bit. Here, consider the circuit WCSa when K is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DW[1] and a low-level potential is applied to the wiring DW[2]. At this time, a constant current I is applied from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1. Wut Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wire DW[1] and a high level potential is applied to the wire DW[2]. At this time, a constant current of 2I flows from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1. Wut Furthermore, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is applied to the wires DW[1] and DW[2]. At this time, a constant current of 3I flows from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1. Wut flows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to the wire DW[1] and the wire DW[2]. At this time, no constant current flows from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1.

[0119] 2A illustrates the circuit WCSa when K is an integer equal to or greater than 3, but when K is 1, the circuit WCSa in FIG. 2A may be configured without a current source CS electrically connected to the wirings DW[2] to DW[K]. When K is 2, the circuit WCSa in FIG. 2A may be configured without a current source CS electrically connected to the wirings DW[3] to DW[K].

[0120] Next, a specific example of the configuration of the current source CS will be described.

[0121] The current source CS1 shown in FIG. 3A is a circuit applicable to the current source CS included in the circuit WCSa in FIG. 2A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0122] A first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and a second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is electrically connected to the terminal T1, and a gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is also electrically connected to the wiring DW.

[0123] The wiring DW is any one of the wirings DW[1] to DW[n] in FIG. 2A.

[0124] The line VDDL functions as a line that applies a constant voltage, which may be, for example, a high-level potential.

[0125] When the constant voltage applied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, the gate-source voltage of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region current range flows between the first terminal and the second terminal of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of this current is, for example, 1.0×10 -8 A or less, and 1.0 × 10 -12 A or less is more preferable, and 1.0 × 10 -15It is more preferable that the current is less than or equal to I. Also, for example, it is more preferable that the current is in a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the current range when operating in the subthreshold region. Note that the current is the above-mentioned I Wut , or I, as described below. Xut is equivalent to

[0126] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain, and the second terminal of transistor Tr2 functions as a source. Because the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage is 0 V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is turned on when a high-level potential is input to the gate of transistor Tr2, and turned off when a low-level potential is input to the gate of transistor Tr2. Specifically, when transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of transistor Tr1 to terminal T1. When transistor Tr2 is off, the current does not flow from the second terminal of transistor Tr1 to terminal T1.

[0127] Note that the circuit applicable to the current source CS included in the circuit WCSa of FIG. 2A is not limited to the current source CS1 of FIG. 3A. For example, while the current source CS1 is configured such that the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2, the back gate of the transistor Tr2 may be electrically connected to a separate wiring. An example of such a configuration is shown in FIG. 3B. The current source CS2 shown in FIG. 3B is configured such that the back gate of the transistor Tr2 is electrically connected to a wiring VTHL. By electrically connecting the wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to the wiring VTHL via the external circuit or the like, thereby applying the predetermined potential to the back gate of the transistor Tr2. This allows the threshold voltage of the transistor Tr2 to be varied. In particular, increasing the threshold voltage of the transistor Tr2 can reduce the off-state current of the transistor Tr2.

[0128] For example, the current source CS1 has a configuration in which the back gate of transistor Tr1 is electrically connected to the second terminal of transistor Tr1, but a configuration in which a capacitor is used to maintain a voltage between the back gate of transistor Tr2 and the second terminal of transistor Tr2 is also possible. Such a configuration example is shown in FIG. 3C. The current source CS3 shown in FIG. 3C includes, in addition to transistors Tr1 and Tr2, a transistor Tr3 and a capacitor C6. The current source CS3 differs from the current source CS1 in that the second terminal of transistor Tr1 is electrically connected to the back gate of transistor Tr1 via the capacitor C6 and the back gate of transistor Tr1 is electrically connected to the first terminal of transistor Tr3. The current source CS3 also has a configuration in which the second terminal of transistor Tr3 is electrically connected to the wiring VTL and the gate of transistor Tr3 is electrically connected to the wiring VWL. The current source CS3 can apply a high-level potential to the wiring VWL to turn on transistor Tr3, thereby establishing electrical continuity between the wiring VTL and the back gate of transistor Tr1. At this time, a predetermined potential can be input to the back gate of transistor Tr1 from line VTL. Then, by applying a low-level potential to line VWL to turn off transistor Tr3, the capacitor C6 can maintain the voltage between the second terminal of transistor Tr1 and the back gate of transistor Tr1. In other words, by determining the voltage applied to the back gate of transistor Tr1 from line VTL, the threshold voltage of transistor Tr1 can be varied, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0129] Further, for example, as a circuit applicable to the current source CS included in the circuit WCSa of FIG. 2A, the current source CS4 shown in FIG. 3D may be used. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 3C, the back gate of the transistor Tr2 is electrically connected not to the second terminal of the transistor Tr2 but to the wiring VTHL. That is, similar to the current source CS2 of FIG. 3B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential provided by the wiring VTHL.

[0130] In the current source CS4, when a large current flows between the first terminal and the second terminal of the transistor Tr1, in order to flow the current from the terminal T1 to the outside of the current source CS4, it is necessary to increase the on-current of the transistor Tr2. In this case, the current source CS4 applies a high-level potential to the wiring VTHL, lowers the threshold voltage of the transistor Tr2, and increases the on-current of the transistor Tr2, thereby flowing the large current flowing between the first terminal and the second terminal of the transistor Tr1 from the terminal T1 to the outside of the current source CS4.

[0131] By applying the current sources CS1 to CS4 shown in FIGS. 3A to 3D as the current source CS included in the circuit WCSa of FIG. 2A, the circuit WCSa can output a current corresponding to the K-bit first data. Also, the amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal within the range where the transistor F1 operates in the subthreshold region.

[0132] Further, as the circuit WCSa of FIG. 2A, the circuit WCSa shown in FIG. 2B may be applied. The circuit WCSa of FIG. 2B has a configuration in which one current source CS of FIG. 3A is connected to each of the wirings DW[1] to DW[K]. Also, when the channel width of the transistor Tr1[1] is w[1], the channel width of the transistor Tr1[2] is w[2], and the channel width of the transistor Tr1[K] is w[K], the ratio of the respective channel widths is w[1]:w[2]:w[K]=1:2:2 K-1Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCSa shown in FIG. 2B can output a current corresponding to the K-bit first data, similar to the circuit WCSa in FIG. 2A.

[0133] Note that the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3 can be, for example, a transistor that can be used for the transistor F1 and / or the transistor F2. In particular, it is preferable to use OS transistors as the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3.

[0134] Next, a specific example of the circuit XCS will be described.

[0135] 2C is a block diagram showing an example of the circuit XCS, and also shows wiring XCL to show electrical connection between the circuit XCS and peripheral circuits.

[0136] The circuit XCS includes, for example, as many circuits XCSa as there are wirings XCL, that is, the circuit XCS includes m circuits XCSa.

[0137] Therefore, the wiring XCL shown in Fig. 2C can be any one of the wirings XCL[1] to XCL[m] included in the arithmetic circuit MAC1 in Fig. 1. Therefore, a separate circuit XCSa is electrically connected to each of the wirings XCL[1] to XCL[m].

[0138] The circuit XCSa shown in FIG. 2C includes, as an example, a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL, and a second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0139] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0140] The circuit configuration of the circuit XCSa in FIG. 2C can be substantially the same as that of the circuit WCSa in FIG. 3A. Specifically, the circuit XCSa has a function of outputting reference data as a current amount and a function of outputting L bits (2 L and a function of outputting second data of the second input signal (L is an integer of 1 or more) as a current amount. In this case, the circuit XCSa has a function of outputting second data of the second input signal (L is an integer of 1 or more) as a current amount. L The circuit XCSa has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the Lth bit as a current. L-1 There are individual ones.

[0141] Incidentally, the reference data output as a current by the circuit XCSa can be, for example, information in which the value of the first bit is "1" and the values of the second and subsequent bits are "0".

[0142] In FIG. 2C, the terminal T2 of one current source CS is electrically connected to the wiring DX[1], and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DX[2]. L-1 Each of the terminals T2 of the current sources CS is electrically connected to the wiring DX[L].

[0143] The multiple current sources CS in the circuit XCSa are each set to the same constant current I Xut from the terminal T1. The wirings DX[1] to DX[L] are electrically connected to the current source CS and the Xut That is, the circuit XCSa has a function of causing the amount of current corresponding to L-bit information transmitted from the wirings DX[1] to DX[L] to flow through the wiring XCL.

[0144] Specifically, consider the circuit XCSa when L is set to 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high level potential is applied to the wire DX[1] and a low level potential is applied to the wire DX[2]. At this time, a constant current I is applied from the circuit XCSa to the wire XCL. Xut For example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wire DX[1] and a high level potential is applied to the wire DX[2]. At this time, a constant current of 2I flows from the circuit XCSa to the wire XCL. Xut Furthermore, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is applied to the wires DX[1] and DX[2]. At this time, a constant current of 3I flows from the circuit XCSa to the wire XCL. Xut Furthermore, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low level potential is applied to the wires DX[1] and DX[2]. At this time, no constant current flows from the circuit XCSa to the wire XCL. Note that in this specification and other places, this may be rephrased as a current of 0 flowing from the circuit XCSa to the wire XCL. Furthermore, when the current of 0, I output from the circuit XCSa Xut , 2I Xut , 3I Xut The second data output by the circuit XCSa can be, in particular, the amount of current I Xut can be the reference data output by the circuit XCSa.

[0145] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCSa, the constant current I output from each of the terminals T1 of the multiple current sources CS is Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCSa is Xut The following explanation will be given assuming that there is no error.

[0146] 3A to 3D can be used as the current source CS of the circuit XCSa, similar to the current source CS of the circuit WCSa. In this case, the wiring DW shown in FIGS. 3A to 3D can be replaced with the wiring DX. This allows the circuit XCSa to pass a current in the subthreshold current range through the wiring XCL as reference data or L-bit second data.

[0147] 2B. In this case, the circuit WCSa shown in FIG. 2B can be replaced with the circuit XCSa, the wiring DW[1] with the wiring DX[1], the wiring DW[2] with the wiring DX[2], the wiring DW[K] with the wiring DX[L], the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0148] <<Conversion circuit ITRZ[1] to conversion circuit ITRZ[n]>> Here, a specific example of a circuit that can be applied to the conversion circuits ITRZ[1] to ITRZ[n] included in the arithmetic circuit MAC1 in FIG. 1 will be described.

[0149] The conversion circuit ITRZ1 shown in Figure 4A is an example of a circuit that can be applied to the conversion circuits ITRZ[1] to ITRZ[n] in Figure 1. Note that Figure 4A also illustrates a circuit SWS2, wiring WCL, wiring SWL2, and a transistor F4 to show the electrical connection of the conversion circuit ITRZ1 with peripheral circuits. The wiring WCL is any one of the wirings WCL[1] to WCL[n] included in the arithmetic circuit MAC1 in Figure 1, and the transistor F4 is any one of the transistors F4[1] to F4[n] included in the arithmetic circuit MAC1 in Figure 1.

[0150] The conversion circuit ITRZ1 in FIG. 4A is electrically connected to the wiring WCL via a transistor F4. The conversion circuit ITRZ1 is also electrically connected to the wiring OL. The conversion circuit ITRZ1 has a function of converting the amount of current flowing from the conversion circuit ITRZ1 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. In other words, the conversion circuit ITRZ1 has a current-voltage conversion circuit.

[0151] The conversion circuit ITRZ1 in FIG. 4A includes, for example, a resistor R5 and an operational amplifier OP1.

[0152] The inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.

[0153] The wiring VRL functions as a wiring that applies a constant voltage, which may be, for example, a ground potential (GND) or a low-level potential.

[0154] By configuring the conversion circuit ITRZ1 as shown in Figure 4A, the amount of current flowing from the wiring WCL to the conversion circuit ITRZ1 via transistor F4, or the amount of current flowing from the conversion circuit ITRZ1 to the wiring WCL via transistor F4, can be converted into an analog voltage and output to the wiring OL.

[0155] In particular, by setting the constant voltage provided by the line VRL to ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, and the analog voltage output to the line OL can be a voltage based on ground potential (GND).

[0156] Furthermore, although the conversion circuit ITRZ1 in FIG. 4A is configured to output an analog voltage, the circuit configuration applicable to the conversion circuits ITRZ[1] to ITRZ[n] in FIG. 1 is not limited to this. For example, the conversion circuit ITRZ1 may be configured to include an analog-to-digital conversion circuit ADC, as shown in FIG. 4B. Specifically, the conversion circuit ITRZ2 in FIG. 4B is configured such that the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. With this configuration, the conversion circuit ITRZ2 in FIG. 4B can output a digital signal to the wiring OL.

[0157] Also, in the conversion circuit ITRZ2, when the digital signal output to the wiring OL is 1 bit (binary), the conversion circuit ITRZ2 may be replaced with the conversion circuit ITRZ3 shown in FIG. 4C. The conversion circuit ITRZ3 in FIG. 4C has a configuration in which a comparator CMP1 is provided in the conversion circuit ITRZ1 in FIG. 4A. Specifically, in the conversion circuit ITRZ3, the first input terminal of the comparator CMP1 is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, the second input terminal of the comparator CMP1 is electrically connected to the wiring VRL2, and the output terminal of the comparator CMP1 is electrically connected to the wiring OL. The wiring VRL2 functions as a wiring that provides a potential for comparing with the potential of the first terminal of the comparator CMP1. With such a configuration, the conversion circuit ITRZ3 in FIG. 4C outputs a low-level potential or a high-level potential (binary digital signal) to the wiring OL according to the magnitude of the voltage converted from the amount of current flowing between the source and drain of the transistor F4 by the current-voltage conversion circuit and the voltage provided by the wiring VRL2.

[0158] Also, the conversion circuits ITRZ[1] to ITRZ[n] applicable to the arithmetic circuit MAC1 in FIG. 1 are not limited to the conversion circuits ITRZ1 to ITRZ3. For example, when using the arithmetic circuit MAC1 for the arithmetic of a hierarchical neural network, it is preferable that the conversion circuits ITRZ1 to ITRZ3 have an arithmetic circuit of a function type. Further, as the arithmetic circuit of the function type, an arithmetic circuit such as a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function can be used.

[0159] Note that one embodiment of the present invention is not limited to the circuit configuration of the arithmetic circuit MAC1 described in this embodiment. The circuit configuration of the arithmetic circuit MAC1 can be changed depending on the situation. For example, the arithmetic circuit MAC1 may be changed to a configuration without the circuit SWS1, as in the arithmetic circuit MAC1A shown in FIG. 5. In the case of the arithmetic circuit MAC1, the circuit SWS1 can stop the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n]. In the case of the arithmetic circuit MAC1A, however, the circuit WCS can stop the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n]. Specifically, for example, when the circuit WCSa of FIG. 2A is used as the circuit WCSa included in the circuit WCS of the arithmetic circuit MAC1A and the current source CS1 of FIG. 3A is used as the current source CS, a low-level potential can be input to each of the wirings DW[1] to DW[K] and the switch SWW can be turned off. By operating the circuit WCSa in this manner, the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n] can be stopped. In this manner, by stopping the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n], arithmetic can be performed using the arithmetic circuit MAC1A instead of the arithmetic circuit MAC1.

[0160] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0161] 6 shows a timing chart of an operation example of the arithmetic circuit MAC1. The timing chart of FIG. 6 shows fluctuations in the potentials of the wiring SWL1, wiring SWL2, wiring WSL[i] (i is an integer between 1 and m-1), wiring WSL[i+1], wiring XCL[i], wiring XCL[i+1], node NN[i,j] (j is an integer between 1 and n-1), node NN[i+1,j], node NNref[i], and node NNref[i+1] between time T11 and time T23 and in the vicinity thereof. Furthermore, the timing chart of FIG. 6 shows fluctuations in the amount of current I flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM[i,j]. F2[i,j] and the current I flowing between the first and second terminals of transistor F2m included in cell IMref[i] F2m [i] and the current I flowing between the first and second terminals of transistor F2 included in cell IM[i+1,j] F2 [i+1,j] and the current I flowing between the first and second terminals of transistor F2m included in cell IMref[i+1] F2m The respective variations of [i+1] and are also shown.

[0162] It is to be noted that the circuit WCS of the arithmetic circuit MAC1 is the circuit WCS of FIG. 2A, and the circuit XCS of the arithmetic circuit MAC1 is the circuit XCS of FIG. 2C.

[0163] In this operation example, the potential of the wiring VE is set to the ground potential GND. Also, before time T11, the potentials of the nodes NN[i,j], NN[i+1,j], NNref[i], and NNref[i+1] are set to the ground potential GND as an initial setting. Specifically, for example, by setting the initialization potential of the wiring VINIL1 in FIG. 2A to the ground potential GND and turning on the switch SWW, the transistor F3, and the transistors F1 included in the cells IM[i,j] and IM[i+1,j], the potentials of the nodes NN[i,j] and NN[i+1,j] can be set to the ground potential GND. Furthermore, for example, by setting the initialization potential of the wiring VINIL2 in Figure 2C to the ground potential GND and turning on the switch SWX and the transistors F1m included in the cells IMref[i,j] and IMref[i+1,j], the potentials of the nodes NNref[i,j] and NNref[i+1,j] can be set to the ground potential GND.

[0164] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential (denoted as High in FIG. 6) is applied to wiring SWL1, and a low-level potential (denoted as Low in FIG. 6) is applied to wiring SWL2. As a result, a high-level potential is applied to the gates of each of transistors F3[1] to F3[n], causing each of transistors F3[1] to F3[n] to be in an on state, and a low-level potential is applied to the gates of each of transistors F4[1] to F4[n], causing each of transistors F4[1] to F4[n] to be in an off state.

[0165] Also, between time T11 and time T12, a low-level potential is applied to wiring WSL[i] and wiring WSL[i + 1]. As a result, a low-level potential is applied to the gates of transistors F1 included in cells IM[i,1] to IM[i,n] in the i-th row of cell array CA and the gate of transistor F1m included in cell IMref[i], causing transistors F1 and transistor F1m to be in an off state. Also, a low-level potential is applied to the gates of transistors F1 included in cells IM[i + 1,1] to IM[i + 1,n] in the (i + 1)-th row of cell array CA and the gate of transistor F1m included in cell IMref[i + 1], causing transistors F1 and transistor F1m to be in an off state.

[0166] Also, between time T11 and time T12, a ground potential GND is applied to wiring XCL[i] and wiring XCL[i + 1]. Specifically, for example, when the wiring XCL described in FIG. 2C is each of wiring XCL[i] and wiring XCL[i + 1], by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX, the potentials of wiring XCL[i] and wiring XCL[i + 1] can be set to the ground potential GND.

[0167] Furthermore, between time T11 and time T12, in each of the circuits WCSa in FIG. 2A, which are electrically connected to the wirings WCL[1] to WCL[n] via separate transistors F3, the first data is not input to the wirings DW[1] to DW[K]. In this case, it is assumed that a low-level potential is input to each of the wirings DW[1] to DW[K] in the circuit WCSa in FIG. 2A. Furthermore, between time T11 and time T12, in each of the circuits XCSa in FIG. 2C, which are electrically connected to the wirings XCL[1] to XCL[m], the second data is not input to the wirings DX[1] to DX[L]. In this case, it is assumed that a low-level potential is input to each of the wirings DX[1] to DX[L] in the circuit XCSa in FIG. 2C.

[0168] Furthermore, between time T11 and time T12, no current flows through the wiring WCL[j], wiring XCL[i], and wiring XCL[i+1]. F2 [i,j], I F2m [i], I F2 [i+1,j], I F2m [i+1] becomes 0.

[0169] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is applied to the wiring WSL[i]. As a result, a high-level potential is applied to the gate of the transistor F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning on the transistor F1 and the transistor F1m. Also, between time T12 and time T13, a low-level potential is applied to the wirings WSL[1] to WSL[m] other than the wiring WSL[i], turning off the transistor F1 included in the cells IM[1,1] to IM[m,n] other than the i-th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i-th row.

[0170] Furthermore, the ground potential GND has been applied to the wirings XCL[1] to XCL[m] continuously since before time T12.

[0171] <<From time T13 to time T14>> Between time T13 and time T14, a current of a current amount I0[i,j] flows as the first data from the circuit WCS to the cell array CA via the transistor F3[j]. Specifically, when the wiring WCL shown in FIG. 2A is the wiring WCL[j], a signal corresponding to the first data is input to each of the wirings DW[1] to DW[K], and a current I0[i,j] flows from the circuit WCSa to the second terminal of the transistor F3[j]. In other words, the value of the K-bit signal input as the first data is set to α[i,j] (α[i,j] is set to a value between 0 and 2). K -1 or less), then I0[i,j]=α[i,j]×I Wut This becomes:

[0172] Note that when α[i,j] is 0, I0[i,j]=0, so strictly speaking, no current flows from circuit WCSa to cell array CA via transistor F3[j]. However, in this specification, it may be stated that "a current of I0[i,j]=0 flows."

[0173] Between time T13 and time T14, there is a conductive state between the first terminal of transistor F1 included in cell IM[i,j] in the i-th row of cell array CA and wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 included in cells IM[1,j] to IM[m,j] other than the i-th row of cell array CA and wiring WCL[j], so that a current of an amount I0[i,j] flows from wiring WCL[j] to cell IM[i,j].

[0174] Incidentally, when the transistor F1 included in the cell IM[i,j] is turned on, the transistor F2 included in the cell IM[i,j] is configured as a diode connection. Therefore, when a current flows from the wiring WCL[j] to the cell IM[i,j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become approximately equal. This potential is determined by the amount of current flowing from the wiring WCL[j] to the cell IM[i,j] and the potential of the first terminal of the transistor F2 (GND in this case). In this operation example, when a current of the amount I0[i,j] flows from the wiring WCL[j] to the cell IM[i,j], the potential of the gate of the transistor F2 (node NN[i,j]) becomes V g [i,j]. That is, in transistor F2, the gate-source voltage is V g [i,j]-GND, and the amount of current I0[i,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0175] Here, the threshold voltage of transistor F2 is V th [i,j], the amount of current I0[i,j] when the transistor F2 operates in the subthreshold region can be expressed as follows:

[0176]

number

[0177] In addition, I a is V g [i,j] is V th [i,j] is the drain current when J is a correction coefficient determined by temperature, device structure, etc.

[0178] In addition, between time T13 and time T14, the circuit XCS supplies the wire XCL[i] with a current amount I ref0Specifically, when the wiring XCL shown in FIG. 2C is the wiring XCL[i], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCSa to the wiring XCL[i]. ref0 In other words, I ref0 =I Xut This becomes:

[0179] Between time T13 and time T14, the first terminal of the transistor F1m included in the cell IMref[i] is in a conductive state with the wiring XCL[i], so that a current I ref0 A current of flows.

[0180] As with cell IM[i,j], when transistor F1m included in cell IMref[i] is turned on, transistor F2m included in cell IMref[i] is configured as a diode connection. Therefore, when current flows from wiring XCL[i] to cell IMref[i], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i] to cell IMref[i] and the potential of the first terminal of transistor F2m (here, GND), etc. In this operation example, the amount of current I flows from wiring XCL[i] to cell IMref[i]. ref0 As a result of this current flowing, the gate of transistor F2 (node NNref[i]) is V gm [i], and the potential of the wiring XCL[i] at this time is also V gm [i]. That is, in transistor F2m, the gate-source voltage is V gm [i]-GND, and the current flowing between the first and second terminals of transistor F2m is I ref0 is set.

[0181] Here, the threshold voltage of transistor F2m is V thm When [i] is set, the amount of current I when transistor F2m operates in the subthreshold region isref0 can be written as follows. Note that the correction coefficient J is assumed to be the same as that of transistor F2 included in cell IM[i,j]. For example, the device structure and size (channel length, channel width) of the transistors are assumed to be the same. Furthermore, although the correction coefficient J of each transistor varies due to manufacturing variations, it is assumed that the variations are suppressed to a level that allows the discussion below to be carried out with sufficient accuracy for practical use.

[0182]

number

[0183] Here, the weighting coefficient w[i,j], which is the first data, is defined as follows.

[0184]

number

[0185] Therefore, equation (1.1) can be rewritten as follows:

[0186]

number

[0187] The current I output by the current source CS of the circuit WCSa in Figure 2A Wut and the current I output by the current source CS of the circuit XCSa in Figure 2C. Xut If and are equal, then w[i,j]=α[i,j]. That is, I Wut And, I Xut If and are equal, α[i,j] corresponds to the value of the first data, so I Wut And, I Xut Preferably, and are equal to each other.

[0188] <<From time T14 to time T15>> Between time T14 and time T15, a low-level potential is applied to the wiring WSL[i], which applies a low-level potential to the gates of the transistors F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning off the transistors F1 and F1m.

[0189] When the transistor F1 included in the cell IM[i,j] is turned off, the capacitance C5 is charged with V, which is the difference between the potential of the gate of the transistor F2 (node NN[i,j]) and the potential of the wiring XCL[i]. g [i,j]-V gm [i] is held. Also, because the transistor F1 included in the cell IMref[i] is turned off, the capacitor C5m holds 0, which is the difference between the potential of the gate of the transistor F2m (node NNref[i]) and the potential of the wiring XCL[i]. Note that the voltage held by the capacitor C5m may become a non-zero voltage (here, for example, Δ) depending on the transistor characteristics of the transistors F1m and F2m during the operation from time T13 to time T14. In this case, the potential of the node NNref[i] can be considered as the potential of the wiring XCL[i] plus Δ.

[0190] <<From time T15 to time T16>> 2C is the line XCL[i], the potential of the line XCL[i] can be set to the ground potential GND by setting the initialization potential of the line VINIL2 to the ground potential GND and turning on the switch SWX.

[0191] Therefore, the potentials of nodes NN[i,1] to NN[i,n] change due to capacitive coupling by capacitance C5 contained in each of cells IM[i,1] to IM[i,n] in the i-th row, and the potential of node NNref[i] changes due to capacitive coupling by capacitance C5m contained in cell IMref[i].

[0192] The amount of change in the potential of the nodes NN[i,1] to NN[i,n] is the potential obtained by multiplying the amount of change in the potential of the wiring XCL[i] by a capacitive coupling coefficient determined by the configuration of each of the cells IM[i,1] to IM[i,n] included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, etc. In each of the cells IM[i,1] to IM[i,n], when the capacitive coupling coefficient due to the capacitor C5 is p, the potential of the node NN[i,j] of the cell IM[i,j] is calculated by multiplying the potential at the time between time T14 and time T15 by p(V gm [i]-GND) decreases.

[0193] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling by the capacitance C5m included in the cell IMref[i]. If the capacitive coupling coefficient of the capacitance C5m is p, like the capacitance C5, the potential of the node NNref[i] of the cell IMref[i] changes from the potential at the time point between time T14 and time T15 to p(V gm [i]-GND) decreases.

[0194] As a result, the potential of the node NN[i,j] of the cell IM[i,j] drops, so that the transistor F2 is turned off. Similarly, the potential of the node NNref[i] of the cell IMref[i] drops, so that the transistor F2m is also turned off. Therefore, between time T15 and time T16, F2 [i,j], I F2m[i] is 0. Note that from time T14 to time T15 in the timing chart of Figure 6, the potential of node NN[i,j] is lower than ground potential GND, but it may be a potential equal to or higher than ground potential GND if transistor F2 is turned off. Also, the potential of node NNref[i] is ground potential GND (i.e., p = 1), but it may be a potential higher or lower than ground potential GND if transistor F2m is turned off.

[0195] <<From time T16 to time T17>> Between time T16 and time T17, a high-level potential is applied to the wiring WSL[i+1]. As a result, a high-level potential is applied to the gate of the transistor F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning on the transistor F1 and the transistor F1m. Also, between time T16 and time T17, a low-level potential is applied to the wirings WSL[1] to WSL[m] except for the wiring WSL[i+1]. Therefore, the transistor F1 included in the cells IM[1,1] to IM[m,n] other than the i+1th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i+1th row of the cell array CA are turned off.

[0196] Furthermore, the ground potential GND has been applied to the wirings XCL[1] to XCL[m] continuously since before time T16.

[0197] <<From time T17 to time T18>> Between time T17 and time T18, a current of a current amount I0[i+1,j] flows as the first data from the circuit WCS to the cell array CA via the transistor F3[j]. Specifically, when the wiring WCL shown in FIG. 2A is the wiring WCL[j+1], signals corresponding to the first data are input to each of the wirings DW[1] to DW[K], and a current I0[i+1,j] flows from the circuit WCSa to the second terminal of the transistor F3[j]. In other words, the value of the K-bit signal input as the first data is set to α[i+1,j] (α[i+1,j] is 0 to 2). K -1 or less), then I0[i,j]=α[i+1,j]×I Wut This becomes:

[0198] Note that when α[i+1,j] is 0, I0[i+1,j]=0, so strictly speaking, no current flows from circuit WCSa to cell array CA via transistor F3[j]. However, in this specification, as in the case of I0[i,j]=0, it may be stated that "a current of I0[i+1,j]=0 flows."

[0199] At this time, there is a conductive state between the first terminal of transistor F1 included in cell IM[i+1,j] in the i+1th row of cell array CA and wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 included in cells IM[1,j] to IM[m,j] other than the i+1th row of cell array CA and wiring WCL[j], so a current of an amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j].

[0200] Incidentally, when transistor F1 included in cell IM[i+1,j] is turned on, transistor F2 included in cell IM[i+1,j] is configured as a diode. Therefore, when current flows from wiring WCL[j] to cell IM[i+1,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i+1,j] and the potential of the first terminal of transistor F2 (here, GND). In this operation example, when a current of a current amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j], the potential of the gate of transistor F2 (node NN[i+1,j]) becomes V g [i+1,j]. That is, in transistor F2, the gate-source voltage is V g [i+1,j]-GND, and the amount of current I0[i+1,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0201] Here, the threshold voltage of transistor F2 is V th When transistor F2 operates in the subthreshold region, the current I0[i+1,j] can be expressed as follows: Note that the correction coefficient is J, which is the same as that for transistor F2 included in cell IM[i,j] and transistor F2m included in cell IMref[i].

[0202]

number

[0203] In addition, between time T17 and time T18, the circuit XCS supplies the wire XCL[i+1] with the current amount I ref0Specifically, as in the period from time T13 to time T14, when the wiring XCL shown in FIG. 2C is the wiring XCL[i+1], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCSa to the wiring XCL[i+1]. ref0 =I Xut is playing.

[0204] Between time T17 and time T18, a state of conduction is established between the first terminal of the transistor F1m included in the cell IMref[i+1] and the wiring XCL[i+1], so that a current I ref0 A current of flows.

[0205] As with cell IM[i+1,j], when transistor F1m included in cell IMref[i+1] is turned on, transistor F2m included in cell IMref[i+1,j] is configured as a diode connection. Therefore, when current flows from wiring XCL[i+1] to cell IMref[i+1], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i+1] to cell IMref[i+1] and the potential of the first terminal of transistor F2m (here, GND). In this operation example, a current amount I flows from wiring XCL[i+1] to cell IMref[i+1]. ref0 The current flowing through the transistor F2 gate (node NNref[i+1]) is V gm [i+1], and the potential of the wiring XCL[i+1] at this time is also V gm [i+1]. That is, in transistor F2m, the gate-source voltage is V gm [i+1]-GND, and the current flowing between the first and second terminals of transistor F2m is I ref0 is set.

[0206] Here, the threshold voltage of transistor F2m is V thmWhen [i+1,j], the amount of current I when transistor F2m operates in the subthreshold region is ref0 can be written as follows: Note that the correction coefficient J is the same as that of the transistor F2 included in the cell IM[i+1,j].

[0207]

number

[0208] Here, the weighting coefficient w[i+1,j], which is the first data, is defined as follows:

[0209]

number

[0210] Therefore, equation (1.5) can be rewritten as follows:

[0211]

number

[0212] The current I output by the current source CS of the circuit WCSa in Figure 2A Wut and the current I output by the current source CS of the circuit XCSa in Figure 2C. Xut If and are equal, then w[i+1,j]=α[i+1,j]. That is, I Wut And, I Xut If and are equal, α[i+1,j] corresponds to the value of the first data, so I Wut And, I Xut Preferably, and are equal to each other.

[0213] <<From time T18 to time T19>> Between time T18 and time T19, a low-level potential is applied to the wiring WSL[i+1], which applies a low-level potential to the gates of the transistors F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning off the transistors F1 and F1m.

[0214] When the transistor F1 included in the cell IM[i+1,j] is turned off, the capacitance C5 is charged with V, which is the difference between the potential of the gate of the transistor F2 (node NN[i+1,j]) and the potential of the wiring XCL[i+1]. g [i+1,j]-V gm [i+1] is held. Also, because the transistor F1 included in the cell IMref[i+1] is turned off, the capacitor C5m holds 0, which is the difference between the potential of the gate of the transistor F2m (node NNref[i+1]) and the potential of the wiring XCL[i+1]. Note that the voltage held by the capacitor C5m may become a non-zero voltage (here, for example, Δ) depending on the transistor characteristics of the transistors F1m and F2m during the operation from time T18 to time T19. In this case, the potential of the node NNref[i+1] can be considered as the potential of the wiring XCL[i+1] plus Δ.

[0215] <<From time T19 to time T20>> 2C is the wiring XCL[i+1], the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0216] Therefore, the potentials of nodes NN[i,1] to NN[i+1,n] change due to capacitive coupling by capacitance C5 contained in each of cells IM[i+1,1] to IM[i+1,n] in the i+1th row, and the potential of node NNref[i+1] changes due to capacitive coupling by capacitance C5m contained in cell IMref[i+1].

[0217] The change in the potential of the nodes NN[i+1,1] to NN[i+1,n] is calculated by multiplying the change in the potential of the wiring XCL[i+1] by a capacitive coupling coefficient determined by the configuration of each of the cells IM[i+1,1] to IM[i+1,n] included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, etc. In each of the cells IM[i+1,1] to IM[i+1,n], when the capacitive coupling coefficient of the capacitor C5 is set to p, which is the same as the capacitive coupling coefficient of the capacitor C5 in each of the cells IM[i,1] to IM[i,n], the potential of the node NN[i+1,j] of the cell IM[i+1,j] is calculated by multiplying the change in the potential of the wiring XCL[i+1] by p(V gm [i+1]-GND) decreases.

[0218] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to the capacitive coupling by the capacitance C5m included in the cell IMref[i+1]. If the capacitive coupling coefficient of the capacitance C5m is p, like the capacitance C5, the potential of the node NNref[i+1] of the cell IMref[i+1] changes from the potential at the time point between T18 and T19 to p(V gm [i+1]-GND) decreases.

[0219] As a result, the potential of the node NN[i+1,j] of the cell IM[i+1,j] drops, so that the transistor F2 is turned off. Similarly, the potential of the node NNref[i+1] of the cell IMref[i+1] drops, so that the transistor F2m is also turned off. Therefore, between time T19 and time T20, F2[i+1,j], I F2m 6, the potential of node NN[i+1,j] is lower than ground potential GND, but may be higher than ground potential GND if transistor F2 is turned off. Also, the potential of node NNref[i+1] is ground potential GND (i.e., p=1), but may be higher or lower than ground potential GND if transistor F2m is turned off.

[0220] <<From time T20 to time T21>> Between time T20 and time T21, a low-level potential is applied to the wiring SWL1, so that a low-level potential is applied to the gates of the transistors F3[1] to F3[n], turning off the transistors F3[1] to F3[n].

[0221] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential is applied to the wiring SWL2, so that a high-level potential is applied to the gates of the transistors F4[1] to F4[n], turning on the transistors F4[1] to F4[n].

[0222] <<From time T22 to time T23>> Between time T22 and time T23, the circuit XCS transmits the current amount I ref0 x[i] times x[i]I ref0 Specifically, for example, when the wiring XCL shown in FIG. 2C is the wiring XCL[i], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] according to the value of x[i], and a current of x[i]I flows from the circuit XCSa to the wiring XCL[i]. ref0 =x[i]I XutIn this operation example, x[i] corresponds to the value of the second data. At this time, the potential of the line XCL[i] varies from 0 to V gm [i]+ΔV[i].

[0223] When the potential of the wiring XCL[i] changes, the potentials of the nodes NN[i,1] to NN[i,n] also change due to the capacitive coupling of the capacitor C5 included in each of the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA. Therefore, the potential of the node NN[i,j] of the cell IM[i,j] is V g [i,j]+pΔV[i].

[0224] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling of the capacitance C5m included in the cell IMref[i]. Therefore, the potential of the node NNref[i] of the cell IMref[i] is V gm [i]+pΔV[i].

[0225] As a result, between time T22 and time T23, the amount of current I1[i,j] flowing between the first terminal and the second terminal of the transistor F2 and the amount of current I ref1 [i,j] can be written as follows:

[0226]

number

[0227]

number

[0228] From equations (1.9) and (1.10), x[i] can be expressed as follows:

[0229]

number

[0230] Therefore, equation (1.9) can be rewritten as follows:

[0231]

number

[0232] In other words, the amount of current flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM[i,j] is proportional to the product of the first data w[i,j] and the second data x[i].

[0233] In addition, between time T22 and time T23, the circuit XCS transmits the current amount I ref0 x[i+1] is x[i+1] times I ref0 Specifically, for example, when the wiring XCL shown in FIG. 2C is the wiring XCL[i+1], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] according to the value of x[i+1], and a current of x[i+1]I flows from the circuit XCSa to the wiring XCL[i+1]. ref0 =x[i+1]I Xut In this operation example, x[i+1] corresponds to the value of the second data. At this time, the potential of the wiring XCL[i+1] changes from 0 to V gm [i+1]+ΔV[i+1].

[0234] As the potential of the wiring XCL[i+1] changes, the potentials of the nodes NN[i+1,1] to NN[i+1,n] also change due to capacitive coupling by the capacitor C5 included in each of the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA. Therefore, the potential of the node NN[i+1,j] of the cell IM[i+1,j] is V g [i+1,j]+pΔV[i+1].

[0235] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to the capacitive coupling of the capacitance C5m included in the cell IMref[i+1]. Therefore, the potential of the node NNref[i+1] of the cell IMref[i+1] is V gm [i+1]+pΔV[i+1].

[0236] As a result, between time T22 and time T23, the amount of current I1[i+1,j] flowing between the first terminal and the second terminal of the transistor F2 and the amount of current I ref1 [i+1,j] can be written as follows:

[0237]

number

[0238]

number

[0239] From equations (1.13) and (1.14), x[i+1] can be expressed as follows:

[0240]

number

[0241] Therefore, equation (1.13) can be rewritten as follows:

[0242]

number

[0243] In other words, the amount of current flowing between the first terminal and the second terminal of transistor F2 included in cell IM[i+1,j] is proportional to the product of the first data w[i+1,j] and the second data x[i+1].

[0244] Here, consider the total amount of current flowing from the conversion circuit ITRZ[j] to the cells IM[i,j] and IM[i+1,j] via the transistor F4[j] and the wiring WCL[j]. Let I S If [j], then I S [j] can be expressed as follows using equations (1.12) and (1.16):

[0245]

number

[0246] Therefore, the amount of current output from the conversion circuit ITRZ[j] is proportional to the sum of the products of the first data, which are the weighting coefficients w[i,j] and w[i+1,j], and the second data, which are the neuron signal values x[i] and x[i+1].

[0247] In the above example, the sum of the currents flowing through the cells IM[i,j] and IM[i+1,j] is considered, but the sum of the currents flowing through the cells IM[1,j] to IM[m,j] may also be considered. In this case, equation (1.17) can be rewritten as follows:

[0248]

number

[0249] Therefore, even in the case of an arithmetic circuit MAC1 having three or more rows and two or more columns of cell arrays CA, it is possible to perform a product-sum operation as described above. In this case, the arithmetic circuit MAC1 selects one of the multiple columns as a current amount I ref0 , and xI ref0 By using a cell that holds the data, it is possible to simultaneously perform multiply-and-accumulate operations for the remaining number of columns among the multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that realizes high-speed multiply-and-accumulate operations.

[0250] The above-described operation example of the arithmetic circuit MAC1 is suitable for calculating the sum of products of positive first data and positive second data. An operation example for calculating the sum of products of positive or negative first data and positive second data, and an operation example for calculating the sum of products of positive or negative first data and positive or negative second data will be described in the second embodiment.

[0251] Although the transistors included in the arithmetic circuit MAC1 are OS transistors or Si transistors in this embodiment, one embodiment of the present invention is not limited thereto. The transistors included in the arithmetic circuit MAC1 may be, for example, transistors having an active layer made of Ge or the like, transistors having an active layer made of a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe, transistors having an active layer made of a carbon nanotube, or transistors having an active layer made of an organic semiconductor.

[0252] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0253] (Embodiment 2) In the first embodiment, an arithmetic circuit that performs a sum-of-products operation between first data that is positive or "0" and second data that is positive or "0" and an example of its operation was described. In the present embodiment, an arithmetic circuit that can perform a sum-of-products operation between first data that is positive, negative, or "0" and second data that is positive or "0" and a sum-of-products operation between first data that is positive, negative, or "0" and second data that is positive, negative, or "0" will be described.

[0254] <Configuration example 1 of an arithmetic circuit> 7 shows an example of the configuration of an arithmetic circuit that performs a product-sum operation between first data that is positive, negative, or "0" and second data that is positive or "0". The arithmetic circuit MAC2 shown in FIG. 7 has a configuration obtained by modifying the arithmetic circuit MAC1 in FIG. 1. Therefore, in the explanation of the arithmetic circuit MAC2, parts that overlap with the explanation of the arithmetic circuit MAC1 will be omitted.

[0255] The cell array CA shown in Figure 7 has m cells IMref arranged in a column and circuits CES arranged in an m x n matrix. Note that Figure 7 excerpts cell IMref[1], cell IMref[m], circuit CES[1,j], and circuit CES[m,j]. Circuit CES[1,j] has cell IM[1,j] and cell IMr[1,j], and circuit CES[m,j] has cell IM[m,j] and cell IMr[m,j]. Furthermore, in this specification, when describing circuits CES[1,j] to circuit CES[m,j], cell IM[1,j], cell IMr[1,j], cell IM[m,j], cell IMr[m,j], and the like, the [m,n] and other symbols attached to the respective circuits may be omitted.

[0256] The cells IM can have the same configuration as the cells IM[1,1] to IM[m,n] included in the cell array CA of the arithmetic circuit MAC1 in FIG.

[0257] Furthermore, cell IMr can have the same configuration as cell IM. As an example, cell IMr in Fig. 7 is illustrated as having the same configuration as cell IM. Furthermore, in order to distinguish between the transistors, capacitances, etc. included in cell IM and cell IMr, the symbols indicating the transistors and capacitances included in cell IMr are appended with "r."

[0258] Specifically, cell IMr has a transistor F1r, a transistor F2r, and a capacitance C5r. Note that the transistor F1r corresponds to the transistor F1 of cell IM, the transistor F2r corresponds to the transistor F2 of cell IM, and the capacitance C5r corresponds to the capacitance C5 of cell IM. Therefore, for the electrical connection configurations of the transistor F1r, the transistor F2r, and the capacitance C5r, refer to the description of cells IM[1,1] to IM[m,n] in the first embodiment.

[0259] In the cell IMr, the connection point between the first terminal of the transistor F1r, the gate of the transistor F2r, and the first terminal of the capacitor C5r is defined as a node NNr.

[0260] In the circuit CES[1,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[1], the gate of the transistor F1 is electrically connected to the wiring WSL[1], the second terminal of the transistor F1 and the second terminal of the transistor F2 are electrically connected to the wiring WCL[j], the second terminal of the capacitor C5r is electrically connected to the wiring XCL[1], the gate of the transistor F1r is electrically connected to the wiring WSL[1], and the second terminal of the transistor F1r and the second terminal of the transistor F2r are electrically connected to the wiring WCLr[j].

[0261] Similarly, in the circuit CES[m,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[m], the gate of the transistor F1 is electrically connected to the wiring WSL[m], and the second terminals of the transistors F1 and F2 are electrically connected to the wiring WCL[j]. Also, the second terminal of the capacitor C5r is electrically connected to the wiring XCL[m], the gate of the transistor F1r is electrically connected to the wiring WSL[m], and the second terminals of the transistors F1r and F2r are electrically connected to the wiring WCLr[j].

[0262] Each of the wirings WCL[j] and WCLr[j] functions, for example, as a wiring that allows current to flow from the circuit WCS to the cells IM and IMr included in the circuit CES, similar to the wirings WCL[1] to WCL[n] described in Embodiment 1. Also, for example, each of the wirings WCL[j] and WCLr[j] functions as a wiring that allows current to flow from the conversion circuit ITRZD[j] to the cells IM and IMr included in the circuit CES.

[0263] 7, the circuit SWS1 includes a transistor F3[j] and a transistor F3r[j]. A first terminal of the transistor F3[j] is electrically connected to the wiring WCL[j], a second terminal of the transistor F3[j] is electrically connected to the circuit WCS, and a gate of the transistor F3[j] is electrically connected to the wiring SWL1. A first terminal of the transistor F3r[j] is electrically connected to the wiring WCLr[j], a second terminal of the transistor F3r[j] is electrically connected to the circuit WCS, and a gate of the transistor F3r[j] is electrically connected to the wiring SWL1.

[0264] 7, the circuit SWS2 includes a transistor F4[j] and a transistor F4r[j]. A first terminal of the transistor F4[j] is electrically connected to the wiring WCL[j], a second terminal of the transistor F4[j] is electrically connected to the conversion circuit ITRZD[j], and a gate of the transistor F4[j] is electrically connected to the wiring SWL2. A first terminal of the transistor F4r[j] is electrically connected to the wiring WCLr[j], a second terminal of the transistor F4r[j] is electrically connected to the conversion circuit ITRZD[j], and a gate of the transistor F4r[j] is electrically connected to the wiring SWL2.

[0265] The conversion circuit ITRZD[j] is a circuit equivalent to the conversion circuits ITRZ[1] to ITRZ[n] in the arithmetic circuit MAC1, and has the function of generating a voltage corresponding to the difference between the amount of current flowing from the conversion circuit ITRZD[j] to the wiring WCL[j] and the amount of current flowing from the conversion circuit ITRZD[j] to the wiring WCLr[j], and outputting the voltage to the wiring OL[j].

[0266] FIG. 8A shows a specific configuration example of the conversion circuit ITRZD[j]. The conversion circuit ITRZD1 shown in FIG. 8A is an example of a circuit that can be applied to the conversion circuit ITRZD[j] of FIG. 7. Note that FIG. 8A also shows the circuit SWS2, wiring WCL, wiring WCLr, wiring SWL2, transistor F4, transistor F4r, wiring OL, and the like to show the electrical connection of the conversion circuit ITRZD1 with peripheral circuits. Furthermore, the wiring WCL and the wiring WCLr can be, for example, the wiring WCL[j] and the wiring WCLr[j] included in the arithmetic circuit MAC2 of FIG. 7, respectively, and the transistors F4 and F4r can be, for example, the transistors F4[j] and F4r[j] included in the arithmetic circuit MAC2 of FIG. 7.

[0267] The conversion circuit ITRZD1 in FIG. 8A is electrically connected to the wiring WCL via a transistor F4. The conversion circuit ITRZD1 is also electrically connected to the wiring WCLr via a transistor F4r. The conversion circuit ITRZD1 is also electrically connected to the wiring OL. The conversion circuit ITRZD1 has a function of converting the amount of current flowing from the conversion circuit ITRZD1 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZD1 into a first voltage, a function of converting the amount of current flowing from the conversion circuit ITRZD1 to the wiring WCLr or the amount of current flowing from the wiring WCLr to the conversion circuit ITRZD1 into a second voltage, and a function of outputting an analog voltage corresponding to the difference between the first voltage and the second voltage to the wiring OL.

[0268] The conversion circuit ITRZD1 in FIG. 8A includes, for example, a resistor RP, a resistor RM, an operational amplifier OPP, an operational amplifier OPM, and an operational amplifier OP2.

[0269] The inverting input terminal of the operational amplifier OPP is electrically connected to the first terminal of the resistor RP and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OPP is electrically connected to the wiring VRPL. The output terminal of the operational amplifier OPP is electrically connected to the second terminal of the resistor RP and the non-inverting input terminal of the operational amplifier OP2. The inverting input terminal of the operational amplifier OPM is electrically connected to the first terminal of the resistor RM and the second terminal of the transistor F4r. The non-inverting input terminal of the operational amplifier OPM is electrically connected to the wiring VRML. The output terminal of the operational amplifier OPM is electrically connected to the second terminal of the resistor RM and the inverting input terminal of the operational amplifier OP2. The output terminal of the operational amplifier OP2 is electrically connected to the wiring OL.

[0270] The wiring VRPL functions as a wiring that applies a constant voltage. This constant voltage can be, for example, a ground potential (GND) or a low-level potential. The wiring VRML also functions as a wiring that applies a constant voltage. This constant voltage can be, for example, a ground potential (GND) or a low-level potential. The constant voltages applied by the wiring VRPL and the wiring VRML may be equal to each other or different from each other. In particular, by setting the constant voltages applied by the wiring VRPL and the wiring VRML to the ground potential (GND), the inverting input terminal of the operational amplifier OPP and the inverting input terminal of the operational amplifier OPM can each be virtually grounded.

[0271] 8A, the conversion circuit ITRZD1 can convert the amount of current flowing from the line WCL to the conversion circuit ITRZD1 via the transistor F4, or the amount of current flowing from the conversion circuit ITRZD1 to the line WCL via the transistor F4, into a first voltage. Furthermore, the conversion circuit ITRZD1 can convert the amount of current flowing from the line WCLr to the conversion circuit ITRZD1 via the transistor F4r, or the amount of current flowing from the conversion circuit ITRZD1 to the line WCLr via the transistor F4r, into a second voltage. An analog voltage corresponding to the difference between the first voltage and the second voltage can then be output to the line OL.

[0272] Furthermore, although the conversion circuit ITRZD1 in FIG. 8A is configured to output an analog voltage, the circuit configuration applicable to the conversion circuit ITRZD[j] in FIG. 7 is not limited to this. For example, the conversion circuit ITRZD1 may be configured to include an analog-to-digital conversion circuit ADC, as shown in FIG. 8B, similar to FIG. 4B. Specifically, the conversion circuit ITRZD2 in FIG. 8B is configured such that the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP2, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to a wiring OL. With this configuration, the conversion circuit ITRZD2 in FIG. 8B can output a digital signal to the wiring OL. Note that although the conversion circuit ITRZD2 in FIG. 8B is configured to output multiple bits from the wiring OL, it may also be configured to output one bit (binary).

[0273] Furthermore, in the case where the digital signal output to the wiring OL in the conversion circuit ITRZD2 is 1 bit (binary), the conversion circuit ITRZD2 may be replaced with the conversion circuit ITRZD3 shown in FIG. 8C. The conversion circuit ITRZD3 in FIG. 8C, like that in FIG. 4C, is configured by adding a comparator CMP2 to the conversion circuit ITRZD1 in FIG. 8A. Specifically, the conversion circuit ITRZD3 is configured such that a first input terminal of the comparator CMP2 is electrically connected to the output terminal of the operational amplifier OP2, a second input terminal of the comparator CMP2 is electrically connected to a wiring VRL3, and an output terminal of the comparator CMP2 is electrically connected to a wiring OL. The wiring VRL3 functions as a wiring that provides a potential to be compared with the potential of the first terminal of the comparator CMP2. By using such a configuration, the conversion circuit ITRZD3 of Figure 8C can output a low-level potential or a high-level potential (binary digital signal) to the wiring OL depending on the magnitude of the difference between the first voltage converted from the amount of current flowing between the source and drain of transistor F4 and the second voltage converted from the amount of current flowing between the source and drain of transistor F4r, and the voltage provided by the wiring VRL3.

[0274] <<Example of first data retention>> Next, an example will be described in which first data is stored in the circuit CES for performing a product-sum operation between first data that is positive, negative, or "0" and second data that is positive or "0" in the arithmetic circuit MAC2 of Figure 7.

[0275] Since the circuit CES has the cell IM and the cell IMr, the circuit CES can use two circuits, the cell IM and the cell IMr, to hold the first data. That is, the circuit CES can set two current amounts and hold potentials corresponding to the respective current amounts in the cell IM and the cell IMr. Therefore, the first data can be expressed by the current amount set in the cell IM and the current amount set in the cell IMr.

[0276] Here, the positive first data, negative first data, or first data of "0" held in the circuit CES is defined as follows.

[0277] When the circuit CES[1,j] stores positive first data, the cell IM[1,j] is configured, for example, so that a current corresponding to the absolute value of the positive first data flows between the first and second terminals of the transistor F2 of the cell IM[1,j]. Specifically, a potential corresponding to the current is maintained at the gate of the transistor F2 (node NN[1,j]). On the other hand, the cell IMr[1,j] is configured, for example, so that no current flows between the first and second terminals of the transistor F2r of the cell IMr[1,j]. Specifically, the gate of the transistor F2r (node NNr[1,j]) may be maintained at a potential provided by the wiring VE or an initialization potential provided by the wiring VINIL1 of the circuit WCSa of FIG. 2A.

[0278] Furthermore, when negative first data is stored in the circuit CES[1,j], the cell IMr[1,j] is set, for example, so that a current corresponding to the absolute value of the negative first data flows through the transistor F2r of the cell IMr[1,j]. Specifically, a potential corresponding to the current is maintained at the gate of the transistor F2r (node NNr[1,j]). Meanwhile, the cell IM[1,j] is set, for example, so that no current flows through the transistor F2 of the cell IM[1,j]. Specifically, the gate of the transistor F2 (node NN[1,j]) may be maintained at a potential provided by the wiring VE, an initialization potential provided by the wiring VINIL1 of the circuit WCSa of FIG. 2A, or the like.

[0279] Furthermore, when the first data "0" is held in the circuit CES[1,j], for example, the transistor F2 of the cell IM[1,j] and the transistor F2r of the cell IMr[1,j] are set so that no current flows through them. Specifically, the gate of the transistor F2 (node NN[1,j]) and the gate of the transistor F2r (node NNr[1,j]) may be held at a potential provided by the wiring VE, an initialization potential provided by the wiring VINIL1 of the circuit WCSa in FIG. 2A, or the like.

[0280] In addition, for other circuits CES, when holding positive first data or negative first data, similarly to the above-described circuit CES[1,j], it is sufficient to set so that an amount of current corresponding to the first data flows between the cell IM and the wiring WCL or between the cell IMr and the wiring WCLr, and so that no current flows between the cell IM and the wiring WCL or between the cell IMr and the wiring WCLr. Furthermore, when holding first data of "0" in other circuits CES, similarly to the above-described circuit CES[1,j], it is sufficient to set so that no current flows between the cell IM and the wiring WCL or between the cell IMr and the wiring WCLr.

[0281] As an example, when the first data "+3", "+2", "+1", "0", "-1", "-2", and "-3" are stored in the circuit CES, by setting the amount of current flowing from the wiring WCL to the cell IM and the amount of current flowing from the wiring WCLr to the cell IMr as described above, each of the first data "+3", "+2", "+1", "0", "-1", "-2", and "-3" can be defined, for example, as shown in the following table.

[0282] [Table 1]

[0283] 7, consider a case where first data is stored in each of the circuits CES[1,j] to CES[m,j] and second data is input to each of the wirings XCL[1] to XCL[m]. At this time, a low-level potential is applied to the wiring SWL1 to turn off the transistors F3[j] and F3r[j]. At this time, a high-level potential is applied to the wiring SWL2 to turn on the transistors F4[j] and F4r[j]. This brings the conversion circuit ITRZD[j] and the wiring WCL[j] into electrical continuity, which may cause a current to flow from the conversion circuit ITRZD[j] to the wiring WCL[j]. Furthermore, the conversion circuit ITRZD[j] and the wiring WCLr[j] into electrical continuity, which may cause a current to flow from the conversion circuit ITRZD[j] to the wiring WCLr[j]. The total current flowing from the conversion circuit ITRZD[j] to the wiring WCL[j] is I S [j], and the total current flowing from the conversion circuit ITRZD[j] to the wiring WCLr[j] is I Sr [j], taking into consideration the operation example of the arithmetic circuit MAC1 explained in the first embodiment, I S [j] and I Sr [j] can be expressed by the following formula:

[0284]

number

[0285] Note that w[i,j] in equation (2.1) is the value of the first data written to cell IM[i,j], and w r [i,j] is the value of the first data to be written to the cell IMr[i,j]. r When either [i,j] is a non-zero value, w[i,j] or w r By setting the other of [i,j] to a value of "0", the first data held in the circuit CES[i,j] can comply with the definition shown in Table 1, for example.

[0286] The conversion circuit ITRZD[j] calculates, for example, the sum I S [j] is converted into the first voltage, and the total amount of current flowing through the wiring WCLr is calculated as I Sr The conversion circuit ITRZD[j] converts the first voltage to the second voltage. The conversion circuit ITRZD[j] can then output a voltage corresponding to the difference between the first voltage and the second voltage to the wiring OL.

[0287] 8A to 8C each have a circuit configuration that outputs a voltage to the wiring OL, but one embodiment of the present invention is not limited to this. For example, the conversion circuit ITRZD[j] included in the arithmetic circuit MAC2 in FIG. 7 may have a circuit configuration that outputs a current.

[0288] The conversion circuit ITRZD4 shown in FIG. 9 is a circuit that can be applied to the conversion circuit ITRZD[j] included in the arithmetic circuit MAC2 in FIG. 7, and has a circuit configuration that outputs the results of the product-sum operation and the activation function operation as a current amount.

[0289] 9 also illustrates the circuit SWS2, wiring WCL, wiring WCLr, wiring OL, transistor F4, and transistor F4r in order to show the electrical connection of the conversion circuit ITRZD4 with peripheral circuits. The wiring WCL and wiring WCLr may be, for example, the wiring WCL[j] and wiring WCLr[j] included in the arithmetic circuit MAC2 in FIG. 7, and the transistor F4 and transistor F4r may be, for example, the transistor F4[j] and transistor F4r[j] included in the arithmetic circuit MAC2 in FIG.

[0290] The conversion circuit ITRZD4 in FIG. 9 is electrically connected to the wiring WCL via a transistor F4. The conversion circuit ITRZD4 is also electrically connected to the wiring WCLr via a transistor F4r. The conversion circuit ITRZD4 is also electrically connected to the wiring OL. The conversion circuit ITRZD4 has a function of acquiring a differential current between either the amount of current flowing from the conversion circuit ITRZD4 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZD4, and either the amount of current flowing from the conversion circuit ITRZD4 to the wiring WCLr or the amount of current flowing from the wiring WCLr to the conversion circuit ITRZD4. The conversion circuit ITRZD4 also has a function of flowing this differential current between the conversion circuit ITRZD4 and the wiring OL.

[0291] The conversion circuit ITRZD4 in FIG. 9 includes, for example, a transistor F5, a current source CI, a current source CIr, and a current mirror circuit CM1.

[0292] The second terminal of transistor F4 is electrically connected to the first terminal of current mirror circuit CM1 and the output terminal of current source CI, and the second terminal of transistor F4r is electrically connected to the second terminal of current mirror circuit CM1, the output terminal of current source CIr, and the first terminal of transistor F5. The input terminal of current source CI is electrically connected to wiring VHE, and the input terminal of current source CIr is electrically connected to wiring VHE. The third terminal of current mirror circuit CM1 is electrically connected to wiring VSE, and the fourth terminal of current mirror circuit CM1 is electrically connected to wiring VSE.

[0293] A second terminal of the transistor F5 is electrically connected to the wiring OL, and a gate of the transistor F5 is electrically connected to the wiring OEL.

[0294] As an example, the current mirror circuit CM1 has the function of flowing a current amount corresponding to the potential of the first terminal of the current mirror circuit CM1 between the first terminal and the third terminal of the current mirror circuit CM1 and between the second terminal and the fourth terminal of the current mirror circuit CM1.

[0295] The wiring VHE functions as, for example, a wiring that applies a constant voltage. Specifically, the constant voltage may be, for example, a high-level potential.

[0296] The wiring VSE functions as, for example, a wiring that applies a constant voltage. Specifically, the constant voltage may be, for example, a low-level potential, a ground potential, or the like.

[0297] The wiring OEL functions as a wiring for transmitting a signal for switching the transistor F5 on or off, for example. Specifically, for example, a high-level potential or a low-level potential may be input to the wiring OEL.

[0298] The current source CI has a function of supplying a constant current between the input terminal and the output terminal of the current source CI. Also, the current source CIr has a function of supplying a constant current between the input terminal and the output terminal of the current source CIr. In the conversion circuit ITRZD4 of FIG. 9, it is preferable that the magnitude of the current supplied by the current source CI is equal to the magnitude of the current supplied by the current source CIr.

[0299] Here, an example of the operation of the conversion circuit ITRZD4 in FIG. 9 will be described.

[0300] First, the amount of current flowing from the conversion circuit ITRZD4 to the wiring WCL via the transistor F4 is calculated as I SThe amount of current flowing from the conversion circuit ITRZD4 to the wiring WCLr via the transistor F4r is I Sr The amount of current flowing from each of the current sources CI and CIr is set to I0.

[0301] I S is the sum of the currents flowing through the cells IM[1,j] to IM[m,j] located in the j-th column in the arithmetic circuit MAC2 in FIG. Sr is the sum of the amounts of currents flowing through the cells IMr[1,j] to IMr[m,j] located in the j-th column in the arithmetic circuit MAC2 of FIG.

[0302] When a high-level potential is input to the wiring SWL2, the transistors F4 and F4r are turned on. Therefore, the amount of current flowing from the first terminal to the third terminal of the current mirror circuit CM1 is I0-I S In addition, the current mirror circuit CM1 transfers I0-I from the second terminal to the fourth terminal of the current mirror circuit CM1. S A current of flows.

[0303] Next, a high-level potential is input to the wiring OEL, and the transistor F5 is turned on. At this time, the amount of current flowing through the wiring OL is I out Then, I out =I0-(I0-I S )-I Sr =I S -I Sr This becomes:

[0304] Here, in the arithmetic circuit MAC2 of Figure 7, for performing a product-sum operation between first data that is positive, negative, or "0" and second data that is positive or "0," the first data is stored in the circuit CES, and the above example of storing first data should be taken into consideration.

[0305] That is, when positive first data is held in the circuit CES[i,j], the cell IM[i,j] is set so that a current corresponding to the absolute value of the positive first data flows between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j], and the cell IMr[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j]. Also, when negative first data is held in the circuit CES[i,j], the cell IM[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j], and the cell IMr[i,j] is set so that a current corresponding to the absolute value of the negative first data flows between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j]. Furthermore, when the first data of "0" is held in the circuit CES[i,j], the cell IM[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j], and the cell IMr[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j].

[0306] Here, when second data is input to each of the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC2 in Figure 7, the amount of current flowing between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j] and the amount of current flowing between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j] are each proportional to the second data.

[0307] I S is the sum of the currents flowing through the cells IM[1,j] to IM[m,j] located in the j-th column. S is the sum of the currents flowing through the cells IM included in the circuits CES[1,j] to CES[m,j] in which the positive first data is held, and can be expressed in the same way as in equation (2.1), for example. S corresponds to the result of multiply-and-accumulate operation between the absolute value of the positive first data and the second data. Sr is the sum of the currents flowing through the cells IMr[1,j] to IMr[m,j] located in the j-th column. Sris the sum of the currents flowing through the cells IMr included in the circuits CES[1,j] to CES[m,j] in which negative first data is held, and can be expressed in the same way as in equation (2.2), for example. Sr corresponds to the result of a multiply-and-accumulate operation between the absolute value of the negative first data and the second data.

[0308] Therefore, the current flowing through the wiring OL is I out =I S -I Sr corresponds to the difference between the result of the multiplication and accumulation operation between the absolute value of the positive first data and the second data and the result of the multiplication and accumulation operation between the absolute value of the negative first data and the second data. out =I S -I Sr corresponds to the result of a multiplication and accumulation operation between the negative, "0", or positive first data held in the circuits CES[1,j] to CES[m,j] and the second data input to each of the wirings XCL[1] to XCL[m].

[0309] Incidentally, when the sum of the currents flowing through the cells IM[1,j] to IM[m,j] is greater than the sum of the currents flowing through the cells IMr[1,j] to IMr[m,j], that is, when I S I Sr When it is greater than out becomes a current amount greater than 0, and flows from the conversion circuit ITRZD4 to the wiring OL. On the other hand, when the sum of the current amounts flowing through the cells IM[1,j] to IM[m,j] is smaller than the sum of the current amounts flowing through the cells IMr[1,j] to IMr[m,j], that is, when I S I Sr When the voltage is smaller than I, there is a possibility that no current will flow from the wiring OL to the converter circuit ITRZD4. S I Sr When it is smaller than out can be set to approximately 0. Therefore, the transformation circuit ITRZD4 can be considered to function as, for example, an ReLU function.

[0310] The ReLU function can be used, for example, as the activation function of a neural network. In the operation of the neural network, it is necessary to calculate the sum of products of the signal values (which can be, for example, second data) of the neurons in the previous layer and the corresponding weighting coefficients (which can be, for example, first data). It is also necessary to calculate the value of the activation function according to the result of the sum of products. Therefore, when the activation function of the neural network is the ReLU function, the operation of the neural network can be performed by using an arithmetic circuit MAC2 including a conversion circuit ITRZD4.

[0311] The hierarchical neural network will be described later in the fourth embodiment.

[0312] Next, an example of a specific circuit configuration of the conversion circuit ITRZD4 in FIG. 9 will be described.

[0313] The conversion circuit ITRZD4 shown in Fig. 10A is an example of the conversion circuit ITRZD4 in Fig. 9. Specifically, Fig. 10A shows examples of the configurations of the current mirror circuit CM1, the current source CI, and the current source CIr.

[0314] 10A, the current mirror circuit CM1 includes, for example, a transistor F6 and a transistor F6r, the current source CI includes, for example, a transistor F7, and the current source CIr includes, for example, a transistor F7r. Note that the transistors F6, F6r, F7, and F7r are n-channel transistors.

[0315] For example, the first terminal of the current mirror circuit CM1 is electrically connected to the first terminal of the transistor F6, the gate of the transistor F6, and the gate of the transistor F6r, the third terminal of the current mirror circuit CM1 is electrically connected to the second terminal of the transistor F6, the second terminal of the current mirror circuit CM1 is electrically connected to the first terminal of the transistor F6r, and the fourth terminal of the current mirror circuit CM1 is electrically connected to the second terminal of the transistor F6r.

[0316] Also, for example, the output terminal of the current source CI is electrically connected to the first terminal of the transistor F7 and the gate of the transistor F7, and the input terminal of the current source CI is electrically connected to the second terminal of the transistor F7.

[0317] Also, for example, the output terminal of the current source CIr is electrically connected to the first terminal of the transistor F7r and the gate of the transistor F7r, and the input terminal of the current source CIr is electrically connected to the second terminal of the transistor F7r.

[0318] The gate and the first terminal of each of the transistors F7 and F7r are electrically connected, and the second terminal is electrically connected to the wiring VHE. Therefore, the gate-source voltage of each of the transistors F7 and F7r is 0 V, and when the threshold voltages of each of the transistors F7 and F7r are within an appropriate range, a constant current flows between the first terminal and the second terminal of each of the transistors F7 and F7r. In other words, each of the transistors F7 and F7r functions as a current source.

[0319] The configurations of the current sources CI and CIr included in the conversion circuit ITRZD4 in Fig. 9 are not limited to the current sources CI and CIr shown in Fig. 10A. The configurations of the current sources CI and CIr included in the conversion circuit ITRZD4 may be changed depending on the situation.

[0320] For example, each of the current source CI and the current source CIr included in the conversion circuit ITRZD4 in FIG. 9 may be the current source CI (current source CIr) shown in FIG. 10B.

[0321] 10B includes, as an example, a plurality of current sources CSA, each of which includes a transistor F7, a transistor F7s, a terminal U1, a terminal U2, and a terminal U3.

[0322] As an example, the current source CSA outputs a current I between terminals U2 and U1. CSA The current source CI (current source CIr) has a function of flowing, for example, 2 P -When there is one (P is an integer equal to or greater than 1) current source CSA, the current source CI (current source CIr) outputs a current of s × I CSA (s is 0 to 2 P -1 or less).

[0323] In practice, errors may occur during the manufacturing process of the current source CI (current source CIr) due to variations in the electrical characteristics of the transistors included in each current source CSA. Therefore, the constant current I output from each terminal U1 of the multiple current sources CSA may be CSA The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal U1 of the multiple current sources CSA included in the current source CI (current source CIr) is CSA The following explanation will be given assuming that there is no error.

[0324] In one of the multiple current sources CSA, a first terminal of a transistor F7s is electrically connected to the terminal U1, and a gate of the transistor F7s is electrically connected to the terminal U3. A first terminal of the transistor F7 is electrically connected to the gate of the transistor F7 and a second terminal of the transistor F7s. A second terminal of the transistor F7 is electrically connected to the terminal U2.

[0325] The terminal U1 of each of the multiple current sources CSA is electrically connected to the output terminal of the current source CI (current source CIr). Also, the terminal U2 of each of the multiple current sources CSA is electrically connected to the input terminal of the current source CI (current source CIr). In other words, there is electrical continuity between the terminal U2 of each of the multiple current sources CSA and the wiring VHE.

[0326] In addition, the terminal U3 of one current source CSA is electrically connected to the wiring CL[1], and each of the terminals U3 of the two current sources CSA is electrically connected to the wiring CL[2]. P-1 Each of the terminals U3 of the current sources CS is electrically connected to a line CL[P].

[0327] The lines CL[1] to CL[P] receive a constant current I from the electrically connected current source CSA. CSA Specifically, for example, when a high-level potential is applied to the line CL[1], the current source CSA electrically connected to the line CL[1] outputs a constant current I CSA flows to the terminal U1, and when a low-level potential is applied to the wiring CL[1], the current source CSA electrically connected to the wiring CL[1] flows as follows: CSA For example, when a high-level potential is applied to the wiring CL[2], the two current sources CSA electrically connected to the wiring CL[2] output a total of 2I CSA is applied to the terminal U1 as a constant current, and when a low-level potential is applied to the wiring CL[2], the current source CSA electrically connected to the wiring CL[2] has a total of 2I CSA For example, when a high-level potential is applied to the wiring CL[P], the constant current of the P-1 The current sources CSA are P-1 I CSA is applied to the terminal U1 as a constant current, and when a low-level potential is applied to the wiring CL[P], the current source CSA electrically connected to the wiring CL[P] has a total of 2 P-1 I CSAIt does not output a constant current.

[0328] Therefore, the current source CI (current source CIr) can flow a current to the output terminal of the current source CI (current source CIr) by applying a high-level potential to one or more wirings selected from the wirings CL[1] to CL[P]. The amount of the current can be determined by the combination of one or more wirings selected from the wirings CL[1] to CL[P] that input the high-level potential. For example, when a high-level potential is applied to the wirings CL[1] and CL[2] and a low-level potential is applied to the wirings CL[3] to CL[P], the current source CI (current source CIr) supplies a total of 3I to the output terminal of the current source CI (current source CIr). CSA A current of 1000 kJ / s can be passed through the capacitor.

[0329] As described above, by using the current source CI (current source CIr) in FIG. 10B, the amount of current that the current source CI (current source CIr) passes to the output terminal can be changed depending on the situation.

[0330] 9, all transistors included in the conversion circuit ITRZD4 can be OS transistors. Furthermore, since the cell array CA, circuit WCS, circuit XCS, etc. of the arithmetic circuit MAC2 can be configured using only OS transistors, the conversion circuit ITRZD4 can be fabricated simultaneously with the cell array CA, circuit WCS, circuit XCS, etc. Therefore, the fabrication process of the arithmetic circuit MAC2 can be shortened in some cases. This also applies to the case where the current source CI (current source CIr) of FIG. 10B is applied to the current source CI and current source CIr of the conversion circuit ITRZD4 of FIG. 10A.

[0331] For example, since the current source CI and the current source CIr included in the conversion circuit ITRZD4 in FIG. 9 need to pass the same current, each of the current source CI and the current source CIr may be replaced with a current mirror circuit.

[0332] The conversion circuit ITRZD4 shown in Fig. 11A has a configuration in which the current sources CI and CIr included in the conversion circuit ITRZD4 of Fig. 9 are replaced with a current mirror circuit CM2. The current mirror circuit CM2 includes, as an example, a transistor F8 and a transistor F8r. Note that the transistors F8 and F8r are p-channel transistors.

[0333] The first terminal of the transistor F8 is electrically connected to the gate of the transistor F8, the gate of the transistor F8r, the second terminal of the transistor F4, and the first terminal of the current mirror circuit CM1. The second terminal of the transistor F8 is electrically connected to the wiring VHE. The first terminal of the transistor F8r is electrically connected to the second terminal of the transistor F4r and the second terminal of the current mirror circuit CM1. The second terminal of the transistor F8r is electrically connected to the wiring VHE.

[0334] As in the conversion circuit ITRZD4 of FIG. 11A, by replacing the current source CI and the current source CIr included in the conversion circuit ITRZD4 of FIG. 9 with a current mirror circuit CM2, it is possible to make approximately equal amounts of current flow through the connection point between the second terminal of the transistor F4 and the first terminal of the current mirror circuit CM1, and through the connection point between the second terminal of the transistor F4r, the second terminal of the current mirror circuit CM1, and the first terminal of the transistor F5.

[0335] 11A illustrates the current mirror circuit CM2 as being composed of transistors F8 and F8r, but the circuit configuration of the current mirror circuit CM2 is not limited to this. For example, the current mirror circuit CM2 may be configured such that the transistors included in the current mirror circuit CM2 are cascode-connected, as shown in FIG. 11C (described later). In this way, the circuit configuration of the current mirror circuit CM2 in FIG. 11A may be changed depending on the situation.

[0336] 11A may be configured without the current mirror circuit CM1, as in the configuration of the conversion circuit ITRZD4 shown in FIG. 11B. The conversion circuit ITRZD4 shown in FIG. 11B can make the amount of current flowing from the first terminal of the current mirror circuit CM2 to the second terminal of the transistor F4 and the amount of current flowing from the second terminal of the current mirror circuit CM2 to the connection point between the second terminal of the transistor F4r and the first terminal of the transistor F5 approximately equal to each other. Therefore, I S I Sr When the current I flows through the wiring OL in Figure 11B, out is the same as the conversion circuit ITRZD4 in Figure 9. S -I Sr It can be said that:

[0337] The conversion circuit ITRZD4 of Fig. 11B does not have a current mirror circuit CM1, so the circuit area can be reduced compared to the conversion circuit ITRZD4 of Fig. 11A. Furthermore, since there is no steady current flowing from the current mirror circuit CM2 to the current mirror circuit CM1, the conversion circuit ITRZD4 of Fig. 11B can consume less power than the conversion circuit ITRZD4 of Fig. 11A.

[0338] 11B does not show the transistors F8 and F8r, and shows the current mirror circuit CM2 as a block diagram. Therefore, the configuration of the current mirror circuit CM2 in FIG. 11B can be determined depending on the situation, similar to the current mirror circuit CM2 in FIG. 11A.

[0339] For example, the current mirror circuit CM2 included in the conversion circuit ITRZD4 of Fig. 11B may be the current mirror circuit CM2 shown in Fig. 11C. The current mirror circuit CM2 shown in Fig. 11C is configured by adding p-channel transistors F8s and F8sr to the current mirror circuit CM2 shown in Fig. 11B, with transistors F8 and F8s cascode-connected and transistors F8r and F8sr cascode-connected. As shown in Fig. 11C, cascode-connecting the transistors included in the current mirror circuit makes it possible to further stabilize the operation of the current mirror circuit.

[0340] Furthermore, the current mirror circuit CM1 included in the conversion circuit ITRZD4 of Fig. 9 is not limited to the current mirror circuit CM1 shown in Fig. 10A. The configuration of the current mirror circuit CM1 included in the conversion circuit ITRZD4 of Fig. 10A may be changed depending on the situation.

[0341] For example, the current mirror circuit CM1 included in the conversion circuit ITRZD4 of Fig. 9 may be the current mirror circuit CM1 shown in Fig. 11D. The current mirror circuit CM1 shown in Fig. 11D is configured by adding n-channel transistors F6s and F6sr to the current mirror circuit CM1 shown in Fig. 10A, with transistors F6 and F6s cascode-connected and transistors F6r and F6sr cascode-connected. As shown in Fig. 11D, by cascode-connecting the transistors included in the current mirror circuit, the operation of the current mirror circuit can be made more stable.

[0342] <Configuration example 2 of an arithmetic circuit> 12 shows an example of the configuration of an arithmetic circuit that performs a product-sum operation between first data that is positive, negative, or "0" and second data that is positive, negative, or "0". The arithmetic circuit MAC3 shown in FIG. 12 has a configuration obtained by modifying the arithmetic circuit MAC2 in FIG. 7. Therefore, in the description of the arithmetic circuit MAC3, parts that overlap with the descriptions of the arithmetic circuits MAC1 and MAC2 will be omitted.

[0343] The cell array CA shown in Fig. 12 has m circuits CESref arranged in one column and circuits CES arranged in an m x n matrix. Note that Fig. 12 illustrates only the circuit CESref[i] and the circuit CES[i,j].

[0344] The circuit CES[i,j] has a cell IM[i,j], a cell IMr[i,j], a cell IMs[i,j], and a cell IMsr[i,j]. In addition, in this specification, when describing the circuit CES[i,j], the cell IM[i,j], the cell IMr[i,j], the cell IMs[i,j], the cell IMsr[i,j], etc., the [i,j] etc. attached to each reference numeral may be omitted.

[0345] Cells IMs and IMsr can have the same configuration as cell IM. As an example, cells IMs and IMsr in FIG. 12 are illustrated as having the same configuration as cell IM. In addition, to distinguish between the transistors, capacitances, etc. included in cells IM, IMs, and IMsr, the symbols indicating the transistors and capacitances included in cell IMs are marked with "s," and the symbols indicating the transistors and capacitances included in cell IMsr are marked with "sr."

[0346] Specifically, cell IMs has a transistor F1s, a transistor F2s, and a capacitance C5s. Note that transistor F1s corresponds to transistor F1 of cell IM, transistor F2s corresponds to transistor F2 of cell IM, and capacitance C5s corresponds to capacitance C5 of cell IM. Therefore, for the electrical connection configurations of transistor F1s, transistor F2s, and capacitance C5s, refer to the description of cells IM[1,1] to IM[m,n] in the first embodiment.

[0347] Furthermore, cell IMsr has transistors F1sr, F2sr, and a capacitance C5sr. Note that transistor F1sr corresponds to transistor F1 of cell IM, transistor F2sr corresponds to transistor F2 of cell IM, and capacitance C5sr corresponds to capacitance C5 of cell IM. Therefore, as with cell IMs, the electrical connection configurations of transistor F1sr, transistor F2sr, and capacitance C5sr refer to the description of cells IM[1,1] to IM[m,n] in the first embodiment.

[0348] In addition, in cell IMs, the connection point between the first terminal of transistor F1s, the gate of transistor F2s, and the first terminal of capacitance C5s is node NNs, and in cell IMsr, the connection point between the first terminal of transistor F1sr, the gate of transistor F2sr, and the first terminal of capacitance C5sr is node NNsr.

[0349] In the circuit CES[i,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[i], the gate of the transistor F1 is electrically connected to the wiring WSL[i], and the second terminals of the transistors F1 and F2 are electrically connected to the wiring WCL[j]. Also, the second terminal of the capacitor C5r is electrically connected to the wiring XCL[i], the gate of the transistor F1r is electrically connected to the wiring WSL[i], and the second terminals of the transistors F1r and F2r are electrically connected to the wiring WCLr[j].

[0350] The second terminal of the capacitor C5s is electrically connected to the wiring XCLs[i], the gate of the transistor F1s is electrically connected to the wiring WSLs[i], the second terminal of the transistor F1s and the second terminal of the transistor F2s are electrically connected to the wiring WCL[j], the second terminal of the capacitor C5sr is electrically connected to the wiring XCLs[i], the gate of the transistor F1sr is electrically connected to the wiring WSLs[i], and the second terminal of the transistor F1sr and the second terminal of the transistor F2sr are electrically connected to the wiring WCLr[j].

[0351] 12 includes a cell IMref[i] and a cell IMrefs[i]. In this specification, when describing the circuit CESref[i], the cell IMref[i], the cell IMrefs[i], etc., the [i] attached to each reference symbol may be omitted.

[0352] The cell IMrefs can have the same configuration as the cell IMref. As an example, the cell IMrefs in FIG. 12 is illustrated as having the same configuration as the cell IMref. In addition, in order to distinguish the transistors, capacitances, etc. included in the cell IMref and the cell IMrefs from each other, the symbols indicating the transistors and capacitances included in the cell IMrefs are appended with "s."

[0353] Specifically, the cell IMrefs has a transistor F1ms, a transistor F2ms, and a capacitance C5ms. Note that the transistor F1ms corresponds to the transistor F1m of the cell IMref, the transistor F2ms corresponds to the transistor F2m of the cell IMref, and the capacitance C5ms corresponds to the capacitance C5m of the cell IMref. Therefore, for the electrical connection configurations of the transistor F1ms, the transistor F2ms, and the capacitance C5ms, refer to the description of the cells IMref[1] to IMref[m] in the first embodiment.

[0354] In addition, in the cell IMrefs, the connection point between the first terminal of the transistor F1ms, the gate of the transistor F2ms, and the first terminal of the capacitor C5ms is defined as a node NNrefs.

[0355] In the circuit CESref[i], the second terminal of the capacitor C5m is electrically connected to the wiring XCL[i], the gate of the transistor F1m is electrically connected to the wiring WSL[i], the second terminal of the transistor F1m and the second terminal of the transistor F2m are electrically connected to the wiring XCL[i], the second terminal of the capacitor C5ms is electrically connected to the wiring XCLs[i], the gate of the transistor F1ms is electrically connected to the wiring WSLs[i], and the second terminal of the transistor F1ms and the second terminal of the transistor F2ms are electrically connected to the wiring XCLs[i].

[0356] Similar to the wirings XCL[1] to XCL[n] described in embodiment 1, each of the wirings XCL[i] and XCLs[i] functions, for example, as a wiring that passes current from the circuit XCS to the cells IM, IMr, IMs, and IMsr included in the circuit CES, and also, for example, as a wiring that passes current from the circuit XCS to the cells IMref[i] and IMrefs[i] included in the circuit CESref.

[0357] Similar to the wirings WSL[1] to WSL[m] described in embodiment 1, each of the wirings WSL[i] and WSLs[i] functions, for example, as a wiring that transmits a selection signal for writing first data from the circuit WSD to the cells IM, IMr, IMs, and IMsr included in the circuit CES, and also, for example, as a wiring that transmits a selection signal for writing reference data from the circuit WSD to the cells IMref and IMrefs included in the circuit CESref.

[0358] The conversion circuit ITRZD[j] included in the arithmetic circuit MAC3 in Fig. 12 can be a circuit that can be applied to the conversion circuit ITRZD[j] included in the arithmetic circuit MAC2 in Fig. 7. In other words, the conversion circuits ITRZD1 to ITRZD3 shown in Figs. 8A to 8C, for example, can be applied to the conversion circuit ITRZD[j] included in the arithmetic circuit MAC3.

[0359] Next, an example of storing first data in the circuit CES and an example of inputting second data to the circuit CES in order to perform a product-sum operation between first data that is positive, negative, or "0" and second data that is positive, negative, or "0" in the arithmetic circuit MAC3 of Figure 12 will be described.

[0360] Because the circuit CES has cells IM, IMr, IMs, and IMsr, the circuit CES can use four circuits, namely, cells IM, IMr, IMs, and IMsr, to hold first data. That is, the circuit CES can set four current amounts and hold potentials corresponding to the respective current amounts in cells IM, IMr, IMs, and IMsr. Therefore, the first data can be expressed by the current amounts set in cells IM, IMr, IMs, and IMsr.

[0361] Here, the positive first data, negative first data, or first data of "0" held in the circuit CES is defined as follows.

[0362] When positive first data is held in the circuit CES[i,j], the cell IM[i,j] is configured, for example, so that a current corresponding to the absolute value of the positive first data flows through the transistor F2 of the cell IM[i,j], and the transistor F2sr of the cell IMsr[i,j] is configured, for example, so that a current corresponding to the absolute value of the positive first data flows through the transistor F2sr. Specifically, a potential corresponding to the current is held at the gate of the transistor F2 (node NN[i,j]) and the gate of the transistor F2sr (node NNsr[i,j]). The cell IMr[i,j] is configured, for example, so that no current flows through the transistor F2r of the cell IMr[i,j], and the cell IMs[i,j] is configured, for example, so that no current flows through the transistor F2s of the cell IMs[i,j]. Specifically, the gate of transistor F2r (node NNr[i,j]) and the gate of transistor F2s (node NNs[i,j]) may be held at a potential provided by the wiring VE, such as an initialization potential provided by the wiring VINIL1 of the circuit WCSa in Figures 2A and 2B.

[0363] Furthermore, when negative first data is held in the circuit CES[i,j], the cell IMr[i,j] is set, for example, so that a current corresponding to the absolute value of the negative first data flows through the transistor F2r of the cell IMr[1,j], and the transistor F2s of the cell IMs[i,j] is set, for example, so that a current corresponding to the absolute value of the negative first data flows through the transistor F2r. Specifically, the gate of the transistor F2r (node NNr[i,j]) and the gate of the transistor F2s (node NNs[i,j]) are held at potentials corresponding to the current amounts. Furthermore, the cell IM[i,j] is set, for example, so that no current flows through the transistor F2 of the cell IM[i,j], and the cell IMsr[i,j] is set, for example, so that no current flows through the transistor F2sr of the cell IMsr[i,j]. Specifically, the gate of transistor F2 (node NN[i,j]) and the gate of transistor F2sr (node NNsr[i,j]) may be held at a potential provided by the wiring VE, such as an initialization potential provided by the wiring VINIL1 of the circuit WCSa in Figures 2A and 2B.

[0364] Furthermore, when the first data "0" is held in the circuit CES[i,j], for example, the transistor F2 of the cell IM[i,j], the transistor F2r of the cell IMr[i,j], the transistor F2s of the cell IMs[i,j], and the transistor F2sr of the cell IMsr[i,j] are set so that no current flows through each of them. Specifically, the gate of the transistor F2 (node NN[i,j]), the gate of the transistor F2r (node NNr[i,j]), the gate of the transistor F2s (node NNs[i,j]), and the gate of the transistor F2sr (node NNsr[i,j]) may hold a potential provided by the wiring VE, such as an initialization potential provided by the wiring VINIL1 of the circuit WCSa in FIGS. 2A and 2B.

[0365] For other circuits CES, when holding positive first data or negative first data, similarly to the above-described circuit CES[i,j], it is sufficient to set so that an amount of current corresponding to the first data flows between the cell IM and the wiring WCL and between the cell IMsr and the wiring WCLr, or between the cell IMsr and the wiring WCL, and so that no current flows in the other. Furthermore, when holding first data of "0" in other circuits CES, similarly to the above-described circuit CES[i,j], it is sufficient to set so that no current flows between the cell IM and the wiring WCL, between the cell IMsr and the wiring WCLr, between the cell IMsr and the wiring WCL, and between the cell IMsr and the wiring WCLsr.

[0366] As an example, when the first data "+3", "+2", "+1", "0", "-1", "-2", and "-3" are stored in the circuit CES, by setting the amount of current flowing from the wiring WCL to the cell IM, setting the amount of current flowing from the wiring WCLr to the cell IMr, setting the amount of current flowing from the wiring WCL to the cell IMs, and setting the amount of current flowing from the wiring WCLr to the cell IMsr as described above, each of the first data "+3", "+2", "+1", "0", "-1", "-2", and "-3" can be defined, for example, as shown in the following table.

[0367] [Table 2]

[0368] On the other hand, the circuit CES is electrically connected to the wiring XCL and the wiring XCLs as wirings for inputting the second data. Therefore, two signals can be input to the circuit CES as the second data. In other words, the second data can be represented by a signal input to the wiring XCL and a signal input to the wiring XCLs and input to the circuit CES. Here, the positive second data, negative second data, or second data of "0" input to the circuit CES are defined as follows:

[0369] When positive second data is input to the circuit CES[i,j], the cell IMref[i] is set, for example, so that a current corresponding to the absolute value of the positive second data flows through the transistor F2m of the cell IMref[i]. Specifically, a potential corresponding to the current is maintained at the gate of the transistor F2m (node NNref[i]). On the other hand, the cell IMrefs[i] is set, for example, so that no current flows through the transistor F2ms of the cell IMrefs[i]. Specifically, the gate of the transistor F2ms (node NNrefs[i]) may be maintained at a potential provided by the wiring VE or an initialization potential provided by the wiring VINIL2 of the circuit XCSa of FIG. 2C.

[0370] Furthermore, when negative second data is input to the circuit CES[i,j], the cell IMrefs[i] is set, for example, so that a current corresponding to the absolute value of the negative second data flows through the transistor F2ms of the cell IMrefs[i]. Specifically, a potential corresponding to the current is maintained at the gate of the transistor F2ms (node NNrefs[i]). Meanwhile, the cell IMref[i] is set, for example, so that no current flows through the transistor F2m of the cell IMref[i]. Specifically, the gate of the transistor F2m (node NNref[i]) may be maintained at a potential provided by the wiring VE or an initialization potential provided by the wiring VINIL2 of the circuit XCSa of FIG. 2C.

[0371] Furthermore, when the second data "0" is input to the circuit CES[i,j], for example, the transistor F2m of the cell IMref[i] and the transistor F2ms of the cell IMrefs[1] are set so that no current flows through them. Specifically, the gate of the transistor F2m (node NNref[i]) and the gate of the transistor F2ms (node NNrefs[i]) may be held at a potential provided by the wiring VE, an initialization potential provided by the wiring VINIL2 of the circuit XCSa in FIG. 2C, or the like.

[0372] When positive second data or negative second data is input to another circuit CES, similar to the above-described circuit CESref[i], it is set so that an amount of current corresponding to the second data flows between the cell IMref and the wiring XCL or between the cell IMrefs and the wiring XCLs, and no current flows between the cell IMref and the wiring XCL or between the cell IMrefs and the wiring XCLs. Furthermore, when second data of "0" is input to another circuit CES, similar to the above-described circuit CESref[i], it is set so that no current flows between the cell IMref and the wiring XCL and between the cell IMrefs and the wiring XCLs.

[0373] As an example, when the second data "+3", "+2", "+1", "0", "-1", "-2", and "-3" are input to the circuit CES, by setting the amount of current flowing from the wiring XCL to the cell IMref and the amount of current flowing from the wiring XCLs to the cell IMrefs as described above, each of the second data "+3", "+2", "+1", "0", "-1", "-2", and "-3" can be defined, for example, as shown in the following table.

[0374] [Table 3]

[0375] Here, when the first data held in the circuit CES is one of "+3", "+2", "+1", "0", "-1", "-2", or "-3", and the second data input to the circuit CES is one of "+1", "0", or "-1", consider the amount of current flowing from the wiring WCL to the cells IM and IMs of the circuit CES, and the amount of current flowing from the wiring WCLr to the cells IMr and IMsr of the circuit CES.

[0376] For example, when the second data input to the circuit CES is "+1," a potential corresponding to the absolute value of the second data "+1" is input from the wiring XCL to the second terminals of the capacitors C5 and C5r of the circuit CES, and a potential corresponding to the ground potential (GND) is input from the wiring XCLs to the second terminals of the capacitors C5s and C5sr of the circuit CES. Furthermore, when the first data held in the circuit CES is "+3," a potential corresponding to the absolute value of the first data "+3" is held at each of the nodes NN and NNsr, and the ground potential (GND) is held at each of the nodes NNr and NNs. At this time, a current of 3I is applied between the first terminal and the second terminal of the transistor F2 of the circuit CES according to equation (1.12) or equation (1.16). ref0Furthermore, no current flows between the first terminal and the second terminal of each of the transistors F2r, F2s, and F2sr. That is, a current of 3I flows from the wiring WCL to the cell IM. ref0 flows, no current flows from the wiring WCL to the cell IMs, no current flows from the wiring WCLr to the cell IMr, and no current flows from the wiring WCLr to the cell IMsr.

[0377] Also, for example, the second data input to the circuit CES is "+1," and the first data held in the circuit CES is "-3." Therefore, a potential corresponding to the absolute value of the first data, "-3," is held at each of the nodes NNr and NNs, and a ground potential (GND) is held at each of the nodes NN and NNsr. At this time, a current of 3I is applied between the first terminal and the second terminal of the transistor F2r of the circuit CES according to equation (1.12) or equation (1.16). ref0 Furthermore, no current flows between the first terminal and the second terminal of each of the transistors F2, F2s, and F2sr. That is, a current of 3I flows from the wiring WCLr to the cell IMr. ref0 flows, no current flows from the wiring WCL to the cell IM, no current flows from the wiring WCL to the cell IMs, and no current flows from the wiring WCLr to the cell IMsr.

[0378] Furthermore, for example, when the second data input to the circuit CES is "-1," a potential corresponding to the absolute value of the second data, "-1," is input from the wiring XCLs to the second terminals of the capacitors C5s and C5sr of the circuit CES, and a potential corresponding to the ground potential (GND) is input from the wiring XCL to the second terminals of the capacitors C5 and C5r of the circuit CES. Furthermore, when the first data held in the circuit CES is "+3," a potential corresponding to the absolute value of the first data, "+3," is held at each of the nodes NN and NNsr, and the ground potential (GND) is held at each of the nodes NNr and NNs. At this time, a current of 3I is applied between the first terminal and the second terminal of the transistor F2sr of the circuit CES according to equation (1.12) or equation (1.16).ref0 Furthermore, no current flows between the first terminal and the second terminal of each of the transistors F2, F2r, and F2s. That is, a current of 3I flows from the wiring WCLr to the cell IMsr. ref0 flows, no current flows from the wiring WCL to the cell IM, no current flows from the wiring WCLr to the cell IMr, and no current flows from the wiring WCL to the cell IMs.

[0379] Also, for example, the second data input to the circuit CES is "-1", and the first data held in the circuit CES is "-3". Therefore, a potential corresponding to the absolute value of the first data "-3" is held at each of the nodes NNr and NNs, and a ground potential (GND) is held at each of the nodes NN and NNsr. At this time, a current of 3I is applied between the first terminal and the second terminal of the transistor F2s of the circuit CES according to equation (1.12) or equation (1.16). ref0 Furthermore, no current flows between the first terminal and the second terminal of each of the transistors F2, F2r, and F2sr. That is, a current of 3I flows from the wiring WCL to the cell IMs. ref0 flows, no current flows from the wiring WCL to the cell IM, no current flows from the wiring WCLr to the cell IMr, and no current flows from the wiring WCLr to the cell IMsr.

[0380] Furthermore, for example, when the second data input to the circuit CES is "0," the ground potential (GND) is input from the wiring XCL to the second terminals of the capacitors C5 and C5r of the circuit CES, and the ground potential (GND) is input from the wiring XCLs to the second terminals of the capacitors C5s and C5sr of the circuit CES. In this case, no current flows between the first terminal and the second terminal of each of the transistors F2, F2r, F2s, and F2sr, regardless of the value of the first data held in the circuit CES.

[0381] Furthermore, for example, when the first data held in the circuit CES is set to "0," the node NN, the node NNr, the node NNs, and the node NNsr are each held at the ground potential (GND). In this case, no matter what value the second data input to the circuit CES has, no current flows between the first terminal and the second terminal of each of the transistors F2, F2r, F2s, and F2sr.

[0382] The above describes the cases where the first data is "+3", "-3", and "0" and the cases where the second data is "+1", "-1", and "0", but if we consider other cases in the same way, the amount of current flowing through the wiring WCL and wiring WCLr can be summarized as shown in the following table.

[0383] [Table 4]

[0384] As described above, by using the arithmetic circuit MAC2, it is possible to perform a product-sum operation between the first data that is positive, negative, or "0" and the second data that is positive or "0." Also, by using the arithmetic circuit MAC3, it is possible to perform a product-sum operation between the first data that is positive, negative, or "0" and the second data that is positive, negative, or "0."

[0385] Note that one embodiment of the present invention is not limited to the circuit configurations of the arithmetic circuits MAC2 and MAC3 described in this embodiment. The circuit configurations of the arithmetic circuits MAC2 and MAC3 can be changed depending on the situation. For example, the capacitances C5, C5r, C5s, C5sr, C5m, and C5ms included in the arithmetic circuit MAC3 can be gate capacitances of transistors (not shown). Furthermore, in the arithmetic circuit MAC3, if the parasitic capacitances between the nodes NN, NNr, NNs, NNsr, NNref, and NNrefs and the surrounding wirings are large, the capacitances C5, C5r, C5s, C5sr, C5m, and C5ms are not necessarily provided.

[0386] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0387] (Embodiment 3) In this embodiment, a configuration will be described in which any one of the arithmetic circuit MAC1, arithmetic circuit MAC1A, arithmetic circuit MAC2, and arithmetic circuit MAC3 described in the above embodiments is combined with a sensor.

[0388] <Configuration example of an arithmetic circuit to which the current generated by the sensor is input> Fig. 13A shows a configuration example in which an arithmetic circuit MAC1 and a circuit SCA having a sensor are combined, and Fig. 13A shows only the cell array CA of the arithmetic circuit MAC1.

[0389] The circuit SCA includes, for example, sensors SNC[1] to SNC[m]. In Fig. 13A, for example, the sensors SNC[1] to SNC[m] are arranged in a matrix.

[0390] The sensors SNC[1] to SNC[m] have a function of converting sensed information into a current amount and outputting the current amount. The sensors SNC[1] to SNC[m] can be, for example, an optical sensor using a photodiode, a pressure sensor, a gyro sensor, an acceleration sensor, an auditory sensor, a temperature sensor, or a humidity sensor. In particular, by applying an optical sensor to the sensors SNC[1] to SNC[m], the circuit SCA can be part of an image sensor.

[0391] The sensors SNC[1] to SNC[m] are preferably provided in an area close to the outside world to sense information about the outside world. For this reason, the circuit SCA is preferably provided above the arithmetic circuit MAC1, more specifically, above the cell array CA, as shown in FIG. 13A.

[0392] Furthermore, the sensor SNC[i] (where i is an integer between 1 and m) is electrically connected to the wiring XCL[i]. That is, the sensor SNC[1] is electrically connected to the wiring XCL[1], and the sensor SNC[m] is electrically connected to the wiring XCL[m].

[0393] Therefore, when information is sensed in each of sensors SNC[1] to SNC[m], the sensor SNC[1] to sensor SNC[m] passes an amount of current corresponding to the information through the wiring XCL[1] to wiring XCL[m].

[0394] Note that the circuit SCA is preferably configured so that the sensors SNC[1] to SNC[m] can sequentially perform sensing and allow current to flow sequentially through the wirings XCL[1] to XCL[m]. In this case, for example, the circuit SCA may be configured to include signal lines for selecting the sensors SNC[1] to SNC[m], and signals may be sequentially sent to the signal lines to operate the sensors SNC[1] to SNC[m] sequentially.

[0395] Specifically, for example, as shown in FIG. 13B, in the circuit configuration of FIG. 13A, a circuit VINI may be provided in the wirings XCL[1] to XCL[m]. The circuit VINI includes switches SW[1] to SW[m]. First terminals of the switches SW[1] to SW[m] are electrically connected to the wirings XCL[1] to XCL[m], and second terminals of the switches SW[1] to SW[m] are electrically connected to the wiring VINIL3. The wiring VINIL3 functions as a wiring that applies a constant potential, such as a low-level potential or a ground potential. In particular, the constant potential is preferably lower than the potential applied by the wiring VE. Here, consider sequentially turning off the switches SW[1] to SW[m] so that one of the switches SW[1] to SW[m] is turned off and the remaining switches SW are turned on. When the sensors SNC[1] to SNC[m] simultaneously perform sensing, the sensors SNC[1] to SNC[m] pass current through the wirings XCL[1] to XCL[m], respectively. At this time, the wiring XCL electrically connected to the switch SW that is in the on state among the switches SW[1] to SW[m] is in a conductive state with the wiring VINIL3, so the current flows through the wiring VINIL3. As a result, the potential of the wiring XCL electrically connected to the switch SW that is in the on state becomes approximately equal to the constant potential provided by the wiring VINIL3. Meanwhile, the potential of the wiring XCL electrically connected to the switch SW that is in the off state among the switches SW[1] to SW[m] is determined according to the amount of the current.

[0396] Furthermore, for example, if the sensors SNC[1] to SNC[m] are optical sensors configured with photodiodes or the like, a filter may be prepared that allows light to be irradiated onto only one of the sensors SNC[1] to SNC[m]. In this case, since there are m sensors SNC, there are m types of filters. Furthermore, if a filter that does not irradiate any of the sensors SNC[1] to SNC[m] with light is prepared in addition to the sensors SNC[1] to SNC[m], the number of types of filters will be m+1. When light is irradiated onto the circuit SCA, the sensors SNC[1] to SNC[m] can perform sensing sequentially by sequentially switching the filters.

[0397] Furthermore, for example, when the sensors SNC[1] to SNC[m] are optical sensors configured with photodiodes or the like, the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, or the arithmetic circuit MAC3 may be configured so that the sensors SNC[1] to SNC[m] are individually irradiated with light. By configuring the sensors SNC[1] to SNC[m] to be individually irradiated with light, the sensors SNC[1] to SNC[m] can be sequentially irradiated with light, and the sensors SNC[1] to SNC[m] can sequentially perform sensing.

[0398] Here, as an example, an operation example of the arithmetic circuit when the circuit SCA and the circuit VINI in FIG. 13B are provided in the arithmetic circuit MAC1 will be described.

[0399] For this operation example, please refer to the timing chart in Fig. 6. Therefore, among the explanations of the operation example of the arithmetic circuit MAC1 provided with the circuit SCA and the circuit VINI in Fig. 13B, the contents that overlap with the explanation of Operation Example 1 of the arithmetic circuit of the first embodiment will be omitted.

[0400] The constant potential applied by the wiring VINIL3 is set to the ground potential.

[0401] From time T13 to time T15 in the timing chart of FIG. 6, the amount of current I flows from the sensor SNC[i] of the circuit SCA to the wiring XCL[i]. ref0 is playing. ref0 can be, for example, the amount of reference current output by the sensor SNC[i] in FIG. 13B after sensing. In addition, in the circuit VINI, by turning off the switch SW[i], the potential of the wiring XCL[i] becomes, for example, V gm [i] shall be the case.

[0402] 6, the sensors SNC[1] to SNC[m] other than the sensor SNC[i] may or may not perform sensing. At this time, by turning on all of the switches SW[1] to SW[m] other than the switch SW[i], the potentials of the wirings XCL[1] to XCL[m] other than the wiring XCL[i] are set to, for example, the ground potential.

[0403] From time T17 to time T19 in the timing chart of FIG. 6, a current I flows from the sensor SNC[i+1] of the circuit SCA to the wiring XCL[i+1]. ref0 is playing. ref0 can be, for example, the amount of current output by the sensor SNC[i+1] in FIG. 13B after sensing. In addition, in the circuit VINI, by turning off the switch SW[i+1], the potential of the wiring XCL[i+1] can be, for example, V gm It will be [i+1].

[0404] 6, the sensors SNC[1] to SNC[m] other than the sensor SNC[i+1] may or may not perform sensing. At this time, by turning on the switches SW[1] to SW[m] other than the switch SW[i+1], the potentials of the wirings XCL[1] to XCL[m] other than the wiring XCL[i+1] are set to, for example, the ground potential.

[0405] From time T22 to time T23 in the timing chart of FIG. 6, I ref0 x[i] times x[i]I ref0 The amount of current that flows is x[i]I ref0 13B performs sensing and can be output by the sensor SNC[i]. In the circuit VINI, by turning off the switch SW[i], the potential of the wiring XCL[i] can be, for example, V gm [i]+ΔV[i].

[0406] In addition, from time T22 to time T23 in the timing chart of FIG. 6, I ref0 x[i+1] is x[i+1] times I ref0 The current x[i+1]I flows. ref0 can be, for example, a current output by the sensor SNC[i+1] in FIG. 13B when sensing. In addition, in the circuit VINI, by turning off the switch SW[i+1], the potential of the wiring XCL[i+1] can be, for example, V gm [i+1]+ΔV[i+1].

[0407] 6, the amount of current flowing between the conversion circuit ITRZ[j] and the wiring WCL[j] is the sum (corresponding to equation (1.17)) of the amount of current I1[i,j] flowing between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j] and the amount of current I1[i+1,j] flowing between the first terminal and the second terminal of the transistor F2 of the cell IM[i+1,j]. Therefore, the amount of current output from the conversion circuit ITRZ[j] to the wiring WCL[j] is proportional to the sum of the products of the weight coefficients w[i,j] and w[i+1,j], which are the first data, and the neuron signal values x[i] and x[i+1], which are the second data, i.e., x[i]w[i,j]+x[i+1]w[i+1,j].

[0408] The arithmetic circuit MAC1 to which the circuit SCA is applied can perform calculations from the first layer (input layer) to the second layer (middle layer) of a hierarchical neural network, for example. That is, the information (values) sensed by the sensors SNC[1] to SNC[m] correspond to signals transmitted from the first-layer neurons to the second-layer neurons. Furthermore, by storing weighting coefficients between the first-layer neurons and the second-layer neurons in cells IM[1,j] to IM[m,j], the arithmetic circuit MAC1 can calculate the sum of products of the information (values) and the weighting coefficients.

[0409] The hierarchical neural network will be described in detail in the fourth embodiment.

[0410] Fig. 14 illustrates a circuit SCA to which, for example, photodiodes PD[1] to PD[m] are applied as sensors SNC[1] to SNC[m] in Fig. 13A. That is, the circuit SCA in Fig. 14 is assumed to be an image sensor as an example.

[0411] When using an optical sensor in this way, it is desirable that the intensity of the light irradiated onto the optical sensor be within the range of intensity irradiated in the environment in which the optical sensor is used.

[0412] <Configuration example of an arithmetic circuit with a sensor> 13A and 13B, the sensors SNC[1] to SNC[m] may be replaced with a circuit configuration including an element that converts sensed information into a current amount and outputs the current amount, such as a photodiode, and a peripheral circuit for the element. Specifically, for example, in the configuration of the semiconductor device of FIG. 13A, the sensors SNC[1] to SNC[m] may be replaced with circuits SPR[1] to SPR[m] as shown in FIG.

[0413] Each of the circuits SPR[1] to SPR[m] has a sensor SNC that has the function of sensing certain information and the function of converting the information into a current amount and outputting the current amount. Furthermore, each of the circuits SPR[1] to SPR[m] may include not only the sensor SNC but also circuits, elements, etc. that have other functions. Examples of other functions include a switching function that switches between a conductive state and a non-conductive state between the sensor SNC and the wiring XCL, and a function that cuts off the power supply to temporarily stop the sensor SNC.

[0414] 15 also illustrates, as an example, a circuit CIR electrically connected to each of the wirings XCL[1] to XCL[m]. The circuit CIR can be, for example, a circuit that supplies current to the wirings XCL[1] to XCL[m] or a circuit that supplies potential to the wirings XCL[1] to XCL[m], separate from the circuits SPR[1] to SPR[m].

[0415] Although the semiconductor device in FIG. 15 illustrates the cell array CA and the circuit CIR included in the same layer, the configuration of the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, as illustrated in FIG. 16, the circuit CIR may be provided below the cell array CA. For example, as illustrated in FIG. 17, the circuit CIR may be provided in the same layer as the circuit SCA. That is, the circuit SCA and the circuit CIR may be formed on the same substrate. Although not illustrated, for example, the circuit CIR may be provided above the cell array CA and below the circuit SNC. For example, the circuit CIR may be provided in multiple layers. Specifically, for example, a portion of the circuit CIR may be provided in the same layer as the circuit SCA, and the remaining portion of the circuit CIR may be provided below the cell array CA.

[0416] Here, as an example, a configuration of an arithmetic circuit will be described in which each of the circuits SPR[1] to SPR[m] has a switching function for switching between a conductive state and a non-conductive state between the sensor SNC and the wiring XCL.

[0417] The arithmetic circuit MAC4 shown in Fig. 18 is a configuration example that combines the configuration of the arithmetic circuit MAC1 in Fig. 1 or the configuration of the arithmetic circuit MAC2 in Fig. 7 with the circuit SCA shown in Fig. 15. By configuring the arithmetic circuit MAC4 in Fig. 18, it is possible to increase the degree of freedom of the current input to the cell array CA from the wirings XCL[1] to XCL[m]. By increasing the degree of freedom of the current, it is possible to set, for example, a current according to the reference data or second data described in the first embodiment depending on the situation.

[0418] The arithmetic circuit MAC4 shown in FIG. 18 includes a circuit LGC and a circuit LS as an example.

[0419] The circuit LGC is electrically connected to the circuit LS by wirings LXS[1] to LXS[m]. The circuit LS is also electrically connected to the circuit XCS by wirings DXS[1] to DXS[m].

[0420] The circuit XCS has a function of causing a current amount corresponding to the reference data or a current amount corresponding to the second data to flow to each of the wirings XCL[1] to XCL[m] as described in Embodiment 1. As an example, the circuit XCS can have the configuration of the circuit XCS illustrated in FIG.

[0421] 2C is used as the circuit XCS, the amount of current flowing through one of the wirings XCL[1] to XCL[m] is determined according to the combination of potentials input to the wirings DX[1] to DX[L] of the circuit XCSa electrically connected to that wiring. Here, in FIG. 18, the wiring DXS[1] refers to the wirings DX[1] to DX[L] of the circuit XCSa electrically connected to the wiring XCL[1], and the wiring DXS[m] refers to the wirings DX[1] to DX[L] of the circuit XCSa electrically connected to the wiring XCL[m]. In other words, one of the wirings DXS[1] to DXS[m] can be a bus wiring for transmitting a digital signal.

[0422] For example, the circuit LS has a function of level-shifting an input potential to a desired potential. Specifically, the circuit LS level-shifts a potential input from the wiring LXS[1] to a desired potential and outputs the level-shifted potential to the wiring DXS[1]. Therefore, the number of wirings LXS[1] can be the same as the number of wirings DXS[1]. Similarly, the circuit LS level-shifts a potential input from the wiring LXS[m] to a desired potential and outputs the level-shifted potential to the wiring DXS[m]. Therefore, the number of wirings LXS[m] can be the same as the number of wirings DXS[m]. Furthermore, one of the wirings LXS[1] to LXS[m] can be a bus wiring for transmitting digital signals.

[0423] For example, the circuit LGC has a function of sequentially holding data DT input to the circuit LGC and outputting the data DT simultaneously or sequentially in parallel to the wirings LXS[1] to LXS[m] at a desired timing. The data DT here can be, for example, reference data or second data input to the wirings XCL[1] to XCL[m]. That is, the circuit LGC holds the reference data or second data received from outside the circuit LGC and outputs the reference data or second data to the wirings LXS[1] to LXS[m] at a predetermined timing in order to pass a current amount corresponding to the reference data or the second data through the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC4. A specific circuit configuration example of the circuit LGC will be described later.

[0424] If there is no need to level-shift the voltage output from the circuit LGC, the circuit LS may be omitted from the arithmetic circuit MAC4 shown in Figure 18, and each of the wirings LXS[1] to LXS[m] may be electrically connected to each of the wirings DXS[1] to DXS[m].

[0425] Next, a description will be given of the configuration of the circuit SCA shown in Fig. 18. Each of the circuits SPR[1] to SPR[m] included in the circuit SCA includes, for example, a transistor F9 and a sensor SNC.

[0426] In the circuit SPR[1] electrically connected to the wiring XCL[1], a first terminal of the transistor F9 is electrically connected to the wiring XCL[1], a second terminal of the transistor F9 is electrically connected to a first terminal of the sensor SNC, a gate of the transistor F9 is electrically connected to the wiring VTXL, a back gate of the transistor F9 is electrically connected to the wiring VBGL, and a second terminal of the sensor SNC is electrically connected to the wiring VANL.

[0427] In the circuit SPR[m] electrically connected to the wiring XCL[m], a first terminal of the transistor F9 is electrically connected to the wiring XCL[m], a second terminal of the transistor F9 is electrically connected to a first terminal of the sensor SNC, a gate of the transistor F9 is electrically connected to the wiring VTXL, a back gate of the transistor F9 is electrically connected to the wiring VBGL, and a second terminal of the sensor SNC is electrically connected to the wiring VANL.

[0428] As described above, the sensor SNC has a function of sensing information and a function of converting the information into a current amount and outputting the current amount.

[0429] 18 illustrates the transistor F9 as a transistor having a back gate, but one embodiment of the present invention is not limited thereto. For example, the transistor F9 may be a transistor with a single gate structure. The transistor F9 may be, for example, an OS transistor or a Si transistor. In particular, using an OS transistor as the transistor F9 can significantly reduce the off-state current of the transistor F9. Therefore, turning off the transistor F9 can significantly reduce the current generated by the sensor SNC that flows through the wiring XCL.

[0430] For example, the wiring VTXL functions as a wiring for switching the transistor F9 between an on state and an off state, and therefore a high-level potential or a low-level potential is supplied to the wiring VTXL.

[0431] For example, the wiring VANL functions as a wiring for applying a power supply voltage to the sensor SNC. Note that the power supply voltage may be, for example, a high-level potential, a low-level potential, or a ground potential, depending on the configuration of the sensor SNC.

[0432] The wiring VBGL functions as a wiring that applies a constant voltage, for example, which may be a high-level potential, a low-level potential, or a ground potential.

[0433] By applying a desired voltage to the wiring VBGL, the threshold voltage of the transistor F9 included in each of the circuits SPR[1] to SPR[m] can be adjusted. For example, by applying a high-level potential to the wiring VBGL, the threshold voltage of the transistor F9 can be lowered, and for example, by applying a low-level potential to the wiring VBGL, the threshold voltage of the transistor F9 can be increased.

[0434] The sensors SNC included in each of the circuits SPR[1] to SPR[m] have the function of converting sensed information into a current amount and outputting the current amount, similar to the sensors SNC[1] to SNC[m] in Figures 13A and 13B. Furthermore, the sensors SNC can be, for example, an optical sensor using a photodiode, a pressure sensor, a gyro sensor, an acceleration sensor, an auditory sensor, a temperature sensor, a humidity sensor, or the like, as described above.

[0435] As an example, the sensor SNC is configured to include an optical sensor using a photodiode. The circuit SPR[i] in FIG. 19A is configured to include a photodiode PDm in the sensor SNC, with the input terminal (sometimes referred to as an anode) of the photodiode PDm electrically connected to the wiring VANL, and the output terminal (sometimes referred to as a cathode) of the photodiode PDm electrically connected to the second terminal of the transistor F9. Note that the constant voltage applied by the wiring VANL may be a low-level potential, a ground potential, a negative potential, or the like. Therefore, when light is irradiated onto the photodiode PDm, a current flows from the output terminal of the photodiode PDm to the wiring VANL via the input terminal.

[0436] 19A, one mode of inputting current from the line XCL[i] to the cell array CA is, for example, a mode in which the transistor F9 is turned off. By turning off the transistor F9, the current generated in the photodiode PDm does not flow to the line XCL[i]. Therefore, the current flowing from the line XCL[i] to the cell array CA can be a current corresponding to the reference data or the second data generated by the circuit XCS.

[0437] 19A, one mode of inputting current from the line XCL[i] to the cell array CA is to turn on the transistor F9. By turning on the transistor F9, the current flowing from the line XCL[i] to the cell array CA can be set to the difference current between the desired current generated by the circuit XCS and the current generated by the photodiode PDm.

[0438] Incidentally, the circuit configuration of the arithmetic circuit MAC4 may be such that the input terminal and output terminal of the photodiode PDm in FIG. 19A are interchangeable. Specifically, as shown in FIG. 19B, the circuit SPR[i] is configured such that the input terminal of the photodiode PDm is electrically connected to the second terminal of the transistor F9, and the output terminal of the photodiode PDm is electrically connected to the wiring VANL. In this case, the constant voltage applied by the wiring VANL is set to a high-level potential or the like. Therefore, when light is irradiated onto the photodiode PDm, a current flows from the output terminal of the photodiode PDm to the input terminal. Therefore, when light is irradiated onto the photodiode PDm, a current flows from the wiring VANL to the input terminal via the output terminal of the photodiode PDm.

[0439] 19B, one mode of inputting current from the line XCL[i] to the cell array CA is, for example, a mode in which the transistor F9 is turned off. By operating in this mode, similar to turning off the transistor F9 in the circuit SCA of FIG. 19A, the current generated in the photodiode PDm can be prevented from flowing to the line XCL[i], and the current flowing from the line XCL[i] to the cell array CA can be a current corresponding to the reference data or the second data generated by the circuit XCS.

[0440] 19B, one mode of inputting current from the line XCL[i] to the cell array CA is, for example, a mode in which the transistor F9 is turned on. By operating in this mode and turning on the transistor F9, the current flowing from the line XCL[i] to the cell array CA can be the sum of the desired current generated by the circuit XCS and the current generated in the photodiode PDm.

[0441] Also, at this time, by setting the amount of current flowing from the circuit XCS to the wiring XCL[i] to 0, that is, by preventing current from being supplied from the circuit XCS to the wiring SCL[i], the current flowing from the wiring XCL[i] to the cell array CA can be limited to the current generated in the photodiode PDm.

[0442] As described above, by configuring the arithmetic circuit MAC4 of Figure 18, the degree of freedom of the current input to the cell array CA from the wiring XCL[1] to wiring XCL[m] can be increased, and the current corresponding to the reference data or the second data described in embodiment 1 can be set depending on the situation.

[0443] For example, when inputting reference data or second data to the cell array CA of the arithmetic circuit MAC4, if the current generated by the sensor SNC is not used, the transistor F9 included in each of the circuits SPR[1] to SPR[m] can be turned off, and the circuit XCS can generate a current corresponding to the reference data or the second data, and the current can be passed through the wiring XCL[1] to XCL[m].

[0444] Furthermore, for example, when inputting reference data or second data to the cell array CA of the arithmetic circuit MAC4, if the current generated by the sensor SNC is used, the transistor F9 included in each of the circuits SPR[1] to SPR[m] can be turned on to cause the current generated by the sensor SNC to flow through the wirings XCL[1] to XCL[m]. Note that, depending on the circumstances, the amount of current flowing from the circuit XCS to the wirings XCL[1] to XCL[m] may be a desired amount or may be zero.

[0445] 6 in the arithmetic circuit MAC4, for example, between time T13 and time T14 and between time T17 and time T19, the transistor F9 included in the circuits SPR[1] to SPR[m] is turned off, and a current corresponding to the reference data is caused to flow from the circuit XCS to the wirings XCL[1] to XCL[m]. Also, for example, between time T22 and time T23, the amount of current flowing from the circuit XCS to the wirings XCL[1] to XCL[m] is set to 0, and the transistor F9 included in the circuits SPR[1] to SPR[m] is turned on, and a current generated by the sensor SNC is caused to flow to the wirings XCL[1] to XCL[m].

[0446] Furthermore, for example, when inputting reference data or second data to the cell array CA of the arithmetic circuit MAC4, the sum (or difference) of the current generated by the circuit XCS and the current generated by the sensor SNC may be passed through the wirings XCL[1] to XCL[m] as the reference data or second data. When the sensor SNC includes the photodiode PDm shown in FIGS. 19A and 19B, the current flowing from the circuit SCA to the wirings XCL[1] to XCL[m] corresponds to the data captured by the photodiode PDm. By generating correction data for the captured data as currents flowing from the circuit XCS to the wirings XCL[1] to XCL[m], currents corresponding to the corrected captured data can be passed through the wirings XCL[1] to XCL[m] to the cell array CA of the arithmetic circuit MAC4. Examples of such corrections include color correction, which adds intensity to a specific color.

[0447] [Example of circuit LGC configuration] Next, a specific example of the circuit configuration of the circuit LGC will be described. When one of the wirings LXS[1] to LXS[m] is a bus wiring for transmitting a digital signal, it is preferable that the data DT (reference data and the second data) input to the circuit LGC be input as a digital signal. By treating the data DT as a digital signal, the circuit LGC can be configured as a logic circuit.

[0448] When the circuit LGC is configured as a logic circuit, the circuit LGC may have the circuit configuration shown in Fig. 20A, for example. The circuit LGC shown in Fig. 20A includes a shift register SR, latch circuits LTA[1] to LTA[m], latch circuits LTB[1] to LTB[m], and switches SW[1] to SW[m].

[0449] The shift register SR is electrically connected to the wirings SPL, SCL, and SEL[1] to SEL[m].

[0450] The control terminals (sometimes referred to as clock input terminals, enable signal input terminals, etc.) of the latch circuits LTA[1] to LTA[m] are electrically connected to the wirings SEL[1] to SEL[m], and the control terminals of the latch circuits LTB[1] to LTB[m] are electrically connected to the wirings LAT. The input terminals D of the latch circuits LTA[1] to LTA[m] are electrically connected to the wirings DAT, and the output terminals Q of the latch circuits LTA[1] to LTA[m] are electrically connected to the wirings DL[1] to DL[m], respectively. The input terminals D of the latch circuits LTB[1] to LTB[m] are electrically connected to the wirings DL[1] to DL[m], and the output terminals Q of the latch circuits LTB[1] to LTB[m] are electrically connected to the first terminals of the switches SW[1] to SW[m], respectively. The second terminals of the switches SW[1] to SW[m] are electrically connected to the wirings LXS[1] to LXS[m], respectively, and the control terminals of the switches SW[1] to SW[m] are electrically connected to the wirings SWL[1] to SWL[m], respectively.

[0451] The switches SW[1] to SW[m] may be, for example, electrical switches such as analog switches or transistors. Alternatively, the switches SW[1] to SW[m] may be, for example, mechanical switches. When transistors are used as the switches SW[1] to SW[m], the transistors may be OS transistors or Si transistors.

[0452] In addition, each of the switches SW[1] to SW[m] shown in Figure 20A is turned on when a high-level potential is input to the control terminal, and is turned off when a low-level potential is input to the control terminal.

[0453] For example, the wirings SWL[1] to SWL[m] function as wirings for switching the conduction state and the non-conduction state of the switches SW[1] to SW[m].

[0454] For example, the wiring SPL functions as a wiring that transmits a start pulse signal to the shift register SR.

[0455] Moreover, the line SCL functions as a line for transmitting a clock signal to the shift register SR, for example.

[0456] Moreover, the wiring DAT functions as a wiring for transmitting data DT to the circuit LGC, for example.

[0457] Each of the wirings SEL[1] to SEL[m], the wirings DL[1] to DL[m], and the wiring DAT can be used as wirings for transmitting digital signals. Therefore, each of the wirings SEL[1] to SEL[m], the wirings DL[1] to DL[m], and the wiring DAT can be used as bus wiring. Furthermore, the wiring SWL can also be used as a bus wiring.

[0458] For example, the shift register SR has a function of sequentially outputting a high-level potential to the wirings SEL[1] to SEL[m] in accordance with a change in the potential input to the wirings SPL and SCL. Note that the shift register SR cannot output a high-level potential to two or more of the wirings SEL[1] to SEL[m], and when any one of the wirings SEL[1] to SEL[m] outputs a high-level potential, the remaining wirings SEL[1] to SEL[m] output a low-level potential.

[0459] For example, when a high-level potential is input to the wiring SPL as a start pulse signal and the potential rises from a low-level potential to a high-level potential in response to the clock signal from the wiring SCL, the wiring SEL[1] outputs a high-level potential. Subsequently, when a low-level potential is input to the wiring SPL and the potential rises again from a low-level potential to a high-level potential in response to the clock signal from the wiring SCL, the wiring SEL[1] outputs a low-level potential, and the wiring SEL[2] outputs a high-level potential. Furthermore, when a low-level potential is input to the wiring SPL and the potential rises again, for example, a third time in response to the clock signal from the wiring SCL, the wirings SEL[1] and SEL[2] output low-level potentials, and the wiring SEL[3] outputs a high-level potential.

[0460] In this way, each time a potential rise occurs in the clock signal from the wiring SCL, the shift register SR can sequentially output a high-level potential to one of the wirings SEL[1] to SEL[m] and output a low-level potential to the other wirings.

[0461] Each of the latch circuits LTA[1] to LTA[m] and the latch circuits LTB[1] to LTB[m] has the function of becoming enabled when a high-level potential is input to the control terminal, holding the data input to the input terminal D, and outputting the data to the output terminal Q. Note that each of the latch circuits LTA[1] to LTA[m] and the latch circuits LTB[1] to LTB[m] becomes disabled when a low-level potential is input to the control terminal, not holding the data input to the input terminal D, and not outputting the data to the output terminal Q.

[0462] An example of the operation of the circuit LGC will now be described.

[0463] 21A is a timing chart showing an operation example of the circuit LGC. The timing chart shows changes in potentials of the wirings SPL, SCL, SEL[1], SEL[2], SEL[m-1], SEL[m], SWL[1] to SWL[m], and LAT, and also shows data input to the wirings DAT, LXS[1], LXS[2], LXS[m-1], and LXS[m]. Note that in the wirings SPL, SCL, SEL[1], SEL[2], SEL[m-1], SEL[m], SWL, and LAT, high-level potentials are indicated as "High" and low-level potentials are indicated as "Low."

[0464] 21A shows an example of an operation in which the circuit LGC simultaneously outputs data DT to each of the wirings LXS[1] to LXS[m] between time T31 and time T40 and at times around that time. This example of an operation is assumed to be performed, for example, between time T21 and time T23 in the timing chart of FIG.

[0465] Also, assume that, prior to time T31, a low-level potential is input to the wiring LAT, and a low-level potential is input to each of the wirings SWL[1] to SWL[m]. Also, assume that the shift register SR outputs a low-level potential to each of the wirings SEL[1] to SEL[m].

[0466] Between time T31 and time T32, a high-level potential is input to the line SPL as a start pulse signal. Also, a pulse voltage is input to the line SCL as a clock signal. When the rising edge of the pulse voltage of the clock signal is input, the shift register SR acquires the high-level potential, which is the start pulse signal input to the line SPL.

[0467] Between time T32 and time T33, data DT[1] is input to the line DAT. Also, a second pulse voltage is input to the line SCL as a clock signal. When the rising edge of the second pulse voltage of the clock signal is input, the shift register SR outputs a high-level potential to the line SEL[1].

[0468] At this time, the latch circuit LTA[1] is enabled, so it holds the data DT[1] input to its input terminal D and outputs the data DT[1] to its output terminal Q. The data DT[1] is input to the input terminal D of the latch circuit LTB[1]. At this time, a low-level potential is input to the control terminal of the latch circuit LTB[1], so the latch circuit LTB[1] does not hold the data DT[1] input to the input terminal D of the latch circuit LTB[1], and does not output the data DT[1] input to the output terminal Q of the latch circuit LTB[1].

[0469] Between time T33 and time T34, data DT[2] is input to the line DAT. Also, a third pulse voltage is input to the line SCL as a clock signal. When the rising edge of the third pulse voltage of the clock signal is input, the shift register SR outputs a low-level potential to the line SEL[1] and a high-level potential to the line SEL[2].

[0470] At this time, the latch circuit LTA[1] is disabled and does not hold the data DT[2] input to the input terminal D of the latch circuit LTA[1]. Furthermore, the latch circuit LTA[1] continues to hold the data DT[1] from before time T33 and outputs the data DT[1] from the output terminal Q.

[0471] Furthermore, the latch circuit LTA[2] is enabled, so it holds the data DT[2] input to its input terminal D and outputs the data DT[2] to its output terminal Q. The data DT[2] is input to the input terminal D of the latch circuit LTB[2]. At this time, a low-level potential is input to the control terminal of the latch circuit LTB[2], so the latch circuit LTB[2] does not hold the data DT[2] input to the input terminal D of the latch circuit LTB[2], and does not output the data DT[2] input to the output terminal Q of the latch circuit LTB[2].

[0472] Between time T34 and time T35, data DT[3] to DT[m-2] are sequentially input to the wiring DAT, and high-level potentials are sequentially input to the wirings SEL[3] to SEL[m-2] by the shift register SR. As a result, data DT[3] to DT[m-2] are held in the latches LTA[3] to LTA[m-2], respectively. Furthermore, data DT[3] to DT[m-2] are output from the output terminals Q of the latches LTA[3] to LTA[m-2], respectively.

[0473] Between time T35 and time T36, data DT[m-1] is input to the line DAT. Also, the m-th pulse voltage is input to the line SCL as a clock signal. When the rising edge of the m-th pulse voltage of the clock signal is input, the shift register SR outputs a low-level potential to the line SEL[m-2] and a high-level potential to the line SEL[m-1].

[0474] At this time, the latch circuit LTA[m-2] is disabled and does not hold the data DT[m-1] input to the input terminal D of the latch circuit LTA[m-2]. Furthermore, the latch circuit LTA[m-2] continues to hold the data DT[m-2] from before time T35 and outputs the data DT[m-2] from the output terminal Q.

[0475] Furthermore, the latch circuit LTA[m-1] is enabled, so it holds the data DT[m-1] input to its input terminal D and outputs the data DT[m-1] to its output terminal Q. The data DT[m-1] is input to the input terminal D of the latch circuit LTB[m-1]. At this time, because a low-level potential is input to the control terminal of the latch circuit LTB[m-1], the latch circuit LTB[m-1] does not hold the data DT[m-1] input to the input terminal D of the latch circuit LTB[m-1], and does not output the data DT[m-1] input to the output terminal Q of the latch circuit LTB[m-1].

[0476] Between time T36 and time T37, data DT[m] is input to the line DAT. Also, the (m+1)th pulse voltage is input to the line SCL as a clock signal. When the rising edge of the (m+1)th pulse voltage of the clock signal is input, the shift register SR outputs a low-level potential to the line SEL[m-1] and a high-level potential to the line SEL[m].

[0477] At this time, the latch circuit LTA[m-1] is disabled and does not hold the data DT[m] input to the input terminal D of the latch circuit LTA[m-1]. Furthermore, the latch circuit LTA[m-1] continues to hold the data DT[m-1] from before time 36 and outputs the data DT[m-1] from the output terminal Q.

[0478] Furthermore, the latch circuit LTA[m] is enabled, so it holds the data DT[m] input to its input terminal D and outputs the data DT[m] to its output terminal Q. The data DT[m] is input to the input terminal D of the latch circuit LTB[m]. At this time, a low-level potential is input to the control terminal of the latch circuit LTB[m], so the latch circuit LTB[m] does not hold the data DT[m] input to the input terminal D of the latch circuit LTB[m], and does not output the data DT[m] input to the output terminal Q of the latch circuit LTB[m].

[0479] Between time T38 and time T39, a high-level potential is input to the line LAT. As a result, a high-level potential is input to each control terminal of the latch circuits LTB[1] to LTB[m], and each of the latch circuits LTB[1] to LTB[m] is enabled. As a result, the latch circuits LTB[1] to LTB[m] hold the data DT[1] to DT[m] input to their respective input terminals D and output the data DT[1] to DT[m] from their respective output terminals Q.

[0480] Between time T39 and time T40, a high-level potential is input to the wirings SWL[1] to SWL[m]. This turns on the switches SW[1] to SW[m], and electrical continuity is established between the output terminals Q of the latch circuits LTB[1] to LTB[m] and the wirings LXS[1] to LXS[m]. This allows the circuit LGC to simultaneously output data DT[1] to DT[m] from the wirings LXS[1] to LXS[m].

[0481] 21A, the circuit LGC can output the data DT[1] to DT[m] sequentially input to the circuit LGC in parallel to the wirings LXS[1] to LXS[m] simultaneously. This allows desired currents to be simultaneously supplied to the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC4, for example, between time T21 and time T23 in the timing chart of FIG.

[0482] 21A shows an example of an operation in which the circuit LGC simultaneously outputs the data DT to each of the wirings LXS[1] to LXS[m], but the circuit LGC may also sequentially output the data DT to each of the wirings LXS[1] to LXS[m]. The timing chart of FIG. 21B shows an example of an operation in which the circuit LGC sequentially outputs the data DT to each of the wirings LXS[1] to LXS[m]. Note that the operation before time T39 in the timing chart of FIG. 21B is assumed to be the operation example from before time T31 to time T39 in the timing chart of FIG. 21A.

[0483] 21B shows changes in the potentials of the wirings SWL[1], SWL[2], SWL[m-1], and SWL[m], and also shows data input to the wirings LXS[1], LXS[2], LXS[m-1], and LXS[m]. Note that in the wirings SWL[1], SWL[2], SWL[m-1], and SWL[m], high-level potentials are indicated as "High" and low-level potentials are indicated as "Low."

[0484] Between time T39 and time T40, a high-level potential is input to the line SWL[1], which turns on the switch SW[1], establishing electrical continuity between the output terminal Q of the latch circuit LTB[1] and the line LXS[1], thereby transmitting the data DT[1] output from the output terminal Q of the latch circuit LTB to the line LXS[1].

[0485] Between time T40 and time T41, a low-level potential is input to the line SWL[1] and a high-level potential is input to the line SWL[2]. This turns the switch SW[1] off and the switch SW[2] on. Because there is no conduction between the output terminal Q of the latch circuit LTB[1] and the line LXS[1], the data DT[1] output from the output terminal Q of the latch circuit LTB is not transmitted to the line LXS[1]. In addition, there is conduction between the output terminal Q of the latch circuit LTB[2] and the line LXS[2], so the data DT[2] output from the output terminal Q of the latch circuit LTB is transmitted to the line LXS[2].

[0486] Between time T41 and time T42, high-level potentials are sequentially input to the wirings SWL[3] to SWL[m-2], and the switches SW[3] to SW[m-2] are sequentially turned on. As a result, the data DT[3] to DT[m-2] output to the output terminals Q of the latch circuits LTB[3] to LTB[m-2] are sequentially output from the wirings LXS[3] to LXS[m-2], respectively.

[0487] Between time T42 and time T43, a low-level potential is input to the line SWL[m-2] and a high-level potential is input to the line SWL[m-1]. As a result, the switch SW[m-2] is turned off and the switch SW[m-1] is turned on. Because there is no conduction between the output terminal Q of the latch circuit LTB[m-2] and the line LXS[m-2], the data DT[m-2] output from the output terminal Q of the latch circuit LTB is not transmitted to the line LXS[m-2]. In addition, there is conduction between the output terminal Q of the latch circuit LTB[m-1] and the line LXS[m-1], so the data DT[m-1] output from the output terminal Q of the latch circuit LTB is transmitted to the line LXS[m-1].

[0488] Between time T43 and time T44, a low-level potential is input to the line SWL[m-1] and a high-level potential is input to the line SWL[m]. This turns the switch SW[m-1] off and the switch SW[m] on. Because there is no conduction between the output terminal Q of the latch circuit LTB[m-1] and the line LXS[m-1], the data DT[m-1] output from the output terminal Q of the latch circuit LTB is not transmitted to the line LXS[m-1]. Furthermore, because there is conduction between the output terminal Q of the latch circuit LTB[m] and the line LXS[m], the data DT[m] output from the output terminal Q of the latch circuit LTB is transmitted to the line LXS[m].

[0489] The circuit LGC operates up to time T39 in the timing chart shown in Figure 21A, and then operates as shown in the timing chart of Figure 21B, thereby allowing the data DT[1] to data DT[m] sequentially input to the circuit LGC to be sequentially output to the wirings LXS[1] to LXS[m].

[0490] In the operation example of the timing chart shown in Figure 21B, an example is shown in which each of the switches SWL[1] to SWL[m] is sequentially turned on and data DT[1] to data DT[m] is sequentially output to wirings LXS[1] to LXS[m]. However, the operation may also be such that a switch to be turned on is selected from the switches SWL[1] to SWL[m] and data DT is output to a wiring selected from the wirings LXS[1] to LXS[m].

[0491] According to the above-described operation example, for example, between time T13 and time T15 in the timing chart of FIG. 6, or between time T17 and time T19, a desired current can be supplied to any one of the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC.

[0492] 18 included in the semiconductor device of one embodiment of the present invention may be different from the circuit LGC shown in FIG. 20A in the circuit configuration. The circuit LGC shown in FIG. 20A may have a modified circuit configuration depending on the situation. For example, the circuit LGC shown in FIG. 20A may have a configuration in which buffer circuits are provided between each of the switches SW[1] to SW[m] and the wirings LXS[1] to LXS[m] shown in FIG. 20A. The circuit LGC shown in FIG. 20B has a configuration in which buffer circuits BF[1] to BF[m] are provided between each of the switches SW[1] to SW[m] and the wirings LXS[1] to LXS[m]. As shown in FIG. 20B, providing the buffer circuits BF[1] to BF[m] in the circuit LGC stabilizes the electric signals (potentials) output from the circuit LGC to the wirings LXS[1] to LXS[m].

[0493] By using the arithmetic circuit MAC4 shown in FIG. 18, the current generated by the circuit XCS and / or the current generated by the sensor SNC can be input to the cell array CA as the reference data or the current corresponding to the second data.

[0494] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0495] (Fourth embodiment) In this embodiment mode, a hierarchical neural network will be described. Note that the operation of the hierarchical neural network can be performed by using the semiconductor device described in the above embodiment mode.

[0496] <Hierarchical neural network> As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network 100 shown in FIG. 22A shows an example, and the neural network 100 has a first layer through an Rth layer (where R can be an integer equal to or greater than four). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 22A illustrates the (k-1)th layer and the kth layer (where k is an integer equal to or greater than three and equal to or less than R-1) as intermediate layers, and does not illustrate the other intermediate layers.

[0497] Each layer of the neural network 100 has one or more neurons. In FIG. 22A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer greater than or equal to 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0498] In addition, in Figure 22A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i(k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0499] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) Focus on.

[0500] Figure 22B shows the k-th layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 10 shows the signal output from the

[0501] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0502] The degree of signal transmission for signals input from neurons in the previous layer to neurons in the next layer is determined by the connection strength (hereinafter referred to as weighting coefficient) of the synapses connecting those neurons. In the neural network 100, signals output from neurons in the previous layer are multiplied by the corresponding weighting coefficient before being input to neurons in the next layer. Let i be an integer between 1 and m, and the (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer neuron N j (k) The signal input to can be expressed by equation (4.1).

[0503]

number

[0504] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1)is input. At this time, the k-th layer neuron N j (k) The sum of the signals input to j (k) is expressed as equation (4.2).

[0505]

number

[0506] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron signal z1 (k-1) ~z m (k-1) The result of the sum of products of and can be given a bias. When the bias is b, equation (4.2) can be rewritten as the following equation.

[0507]

number

[0508] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined as follows:

[0509]

number

[0510] The function f(u j (k)) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different for each layer. In addition, the activation functions of neurons can be the same or different for each layer.

[0511] The signals, weighting coefficients w, or biases b output by neurons in each layer may be analog or digital values. Digital values may be, for example, binary or ternary. Values with even larger bit counts may also be used. For example, in the case of analog values, activation functions such as linear ramp functions or sigmoid functions may be used. In the case of binary digital values, for example, step functions that output -1 or 1 may be used. Alternatively, step functions that output 0 or 1 may be used. Furthermore, signals output by neurons in each layer may be ternary or more. In this case, activation functions with three values may be used, such as step functions that output -1, 0, or 1, or step functions that output 0, 1, or 2. Furthermore, activation functions that output five values, such as step functions that output -2, -1, 0, 1, or 2, may be used. By using digital values for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to reduce the circuit size, reduce power consumption, or increase the calculation speed. Also, by using analog values for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to improve the accuracy of calculations.

[0512] When an input signal is input to the first layer (input layer), neural network 100 generates an output signal in each layer, from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, using equations (4.1), (4.2) (or (4.3)), and (4.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0513] When the arithmetic circuit MAC1 described in the first embodiment is applied as the hidden layer, the weight coefficient w s[k-1] (k-1) s[k] (k) (where s[k-1] is an integer between 1 and m, and s[k] is an integer between 1 and n) is used as the first data, and the current amount corresponding to the first data is stored in each cell IM of the same column, and the neuron N in the (k-1) layer s[k-1] (k-1) Output signal z from s[k-1] (k-1) is used as the second data, and the current amount according to the second data is passed from the circuit XCS to the wiring XCL of each row, so that the current amount I S In addition, by using the value of the sum of products to calculate the value of the activation function, the value of the activation function is used as a signal to activate the neuron N in the kth layer. s[k] (k) The output signal z s[k] (k) It can be said that:

[0514] In addition, when the arithmetic circuit MAC1 described in the first embodiment is applied to the output layer, the weighting coefficient w s[R-1] (R-1) s[R] (R) (s[R-1] is an integer equal to or greater than 1, and s[R] is an integer equal to or greater than 1 and equal to or less than q) is used as the first data, and the current amount corresponding to the first data is stored in each cell IM of the same column, and the neuron N in the (R-1) layer s[R-1] (R-1) Output signal z from s[R-1](R-1) is used as the second data, and the current amount according to the second data is passed from the circuit XCS to the wiring XCL of each row, so that the current amount I S In addition, by using the value of the sum of products to calculate the value of the activation function, the value of the activation function is used as a signal to activate the neuron N in the Rth layer. s[R] (R) The output signal z s[R] (R) It can be said that:

[0515] The input layer described in this embodiment may function as a buffer circuit that outputs an input signal to the second layer.

[0516] In addition, when the calculation circuit MAC2 in which the conversion circuit ITRZD[j] is the conversion circuit ITRZD4 in FIG. 9 described in the second embodiment is applied as the hidden layer, the weight coefficient w s[k-1] (k-1) s[k] (k) is used as the first data, and the current amount corresponding to the first data is stored in the cells IM and IMr of each circuit CES in the same column, and the neuron N in the (k-1)th layer s[k-1] (k-1) Output signal z from s[k-1] (k-1) is used as the second data, and the current amount according to the second data is passed from the circuit XCS to the wiring XCL of each row, so that the current amount I S , and I Sr The activation function value corresponding to the sum of the products of the first data and the second data can be calculated from the above. In other words, the activation function value is used as a signal to activate the k-th layer neuron N s[k] (k) The output signal z s[k] (k) In addition, since the conversion circuit ITRZD4 is configured to output a current amount corresponding to the value, for example, a neuron N in the kth layer that is input to a plurality of neurons in the (k+1)th layer can be s[k] (k) The output signal z s[k] (k)That is, when the arithmetic circuit MAC2 is applied as the hidden layer of the (k+1)th layer, the neuron N of the kth layer input to the wiring XCL of the arithmetic circuit MAC2 s[k] (k) The output signal z s[k] (k) can be a current output from the conversion circuit ITRZD4 of the arithmetic circuit MAC2 in the k-th hidden layer, without being generated by the circuit XCS.

[0517] Specifically, the above-described hierarchical neural network operation can be performed by using the arithmetic circuit shown in Fig. 23. The arithmetic circuit of Fig. 23 includes, as an example, an arithmetic circuit MAC2-1 having the same configuration as the arithmetic circuit MAC2 of Fig. 7, and an arithmetic circuit MAC2-2 having the same configuration as the arithmetic circuit MAC2 of Fig. 7 but without the circuit XCS. Note that the cell array CA of the arithmetic circuit MAC2-1 has m x n circuits CES arranged in a matrix, and the cell array CA of the arithmetic circuit MAC2-2 has n x t circuits CES (where t is an integer equal to or greater than 1) arranged in a matrix. Furthermore, the wirings OL[1] to OL[n] of the arithmetic circuit MAC2-1 are electrically connected to the wirings XCL[1] to XCL[n] of the arithmetic circuit MAC2-2, respectively.

[0518] For example, in the arithmetic circuit MAC2-1 of FIG. 23, the weight coefficients between the neurons in the (k-1)th layer and the neurons in the kth layer are stored as first data in the circuits CES[1,1] to CES[m,n] of the cell array CA, and the weight coefficients between the neurons in the (k-1)th layer and the neurons in the kth layer are stored as first data in the circuits CES[1,1] to CES[m,n] of the cell array CA. s[k-1] (k-1) Output signal z from s[k-1] (k-1) The amount of current corresponding to the second data is passed from the circuit XCS to the wiring XCL of each row, and the k-th layer neuron N1 (k) Neuron N n (k) Output signal z1 (k) ~z n (k) The output signal z1 (k) ~zn (k) Each of the values can be expressed as the amount of current output from the conversion circuits ITRZD4[1] to ITRZD4[n].

[0519] Here, in the arithmetic circuit MAC2-2 of FIG. 23, the weighting coefficient between the neuron in the kth layer and the neuron in the (k+1)th layer is stored as first data in the circuits CES[1,1] to CES[n,t] of the cell array CA, and the amount of current flowing through the wiring XCL of each row, i.e., the neuron N1 in the kth layer, is stored as first data. (k) Neuron N n (k) Output signal z1 (k) ~z n (k) By using this as the second data, the wiring OL[s[k+1]] (where s[k+1] is an integer between 1 and t) is connected to the (k+1)th layer neuron N s[k+1] (k+1) The output signal z s[k+1] (k+1) can be output.

[0520] As described in the second embodiment, by applying any one of the conversion circuits ITRZD4 shown in FIGS. 9, 10A, and 11A to 11D to the conversion circuits ITRZD4[1] to ITRZD4[n] of the arithmetic circuit MAC2-1 shown in FIG. 23, the conversion circuits ITRZD4[1] to ITRZD4[n] function as a ReLU function. Therefore, for example, when the result of the product-sum operation in the circuits CES[1,j] to CES[m,j] is "negative," the amount of current flowing from the conversion circuit ITRZD4 to the wiring OL[j] is ideally preferably 0. However, in reality, there are cases where a small current flows from the conversion circuit ITRZD4 to the wiring OL[j], or a small current flows from the wiring OL[j] to the conversion circuit ITRZD4.

[0521] For this reason, an example configuration of an arithmetic circuit MAC2-2 for properly performing calculations on the next layer and beyond of a hierarchical neural network is shown in Figure 24. The arithmetic circuit MAC2-2 shown in Figure 24 has a configuration in which the circuits CES arranged in the cell array CA in the arithmetic circuit MAC2 of Figure 7 have been changed from an m x n matrix to an n x t matrix, and the circuit XCS is not provided. Also, because the circuits CES of the cell array CA of the arithmetic circuit MAC2-2 are arranged in an n x t matrix, the values in parentheses such as [ ] attached to the symbols for the wiring, circuits, etc. shown in Figure 24 have also been changed.

[0522] Furthermore, in the arithmetic circuit MAC2-2 of Figure 24, as an example, an example of a circuit configuration is shown in which the arithmetic circuit MAC2-2 is provided with wiring TM[1], wiring TM[n], wiring TH[1,h] (h is an integer greater than or equal to 1 and less than or equal to t), wiring TH[n,h], wiring THr[1,h], and wiring THr[n,h]. In the arithmetic circuit MAC2-2 of Figure 24, wiring TM[1] is electrically connected to the back gate of transistor F2m of cell IMref[1], wiring TM[n] is electrically connected to the back gate of transistor F2m of cell IMref[n], wiring TH[1,h] is electrically connected to the back gate of transistor F2 of cell IM[1,h], wiring THr[1,h] is electrically connected to the back gate of transistor F2r of cell IMr[1,h], wiring TH[n,h] is electrically connected to the back gate of transistor F2 of cell IM[n,h], and wiring THr[n,h] is electrically connected to the back gate of transistor F2r of cell IMr[n,h].

[0523] Applying a low-level potential to each of the wirings TM[1], TM[n], TH[1,h], TH[n,h], THr[1,h], and THr[n,h] can increase the threshold voltage of the transistors having backgates electrically connected to the respective wirings. This prevents a small amount of current flowing through the wiring OL of the arithmetic circuit MAC2-1 from flowing to the wiring VE via the cell IMref of the arithmetic circuit MAC2-2. In other words, the output characteristics of the conversion circuits ITRZD4[1] to ITRZD4[n] can be made closer to the ReLU function. This allows the next-layer calculation of the hierarchical neural network to be performed appropriately.

[0524] Also, for example, the configuration of the arithmetic circuit MAC2-2 in Fig. 24 may be applied to the arithmetic circuit MAC2-1 in Fig. 23. By using such a configuration, it is possible to vary the threshold voltages of the transistors F2, F2r, and F2m included in the arithmetic circuit MAC2-1, similarly to the arithmetic circuit MAC2-2.

[0525] Note that while Figure 24 illustrates wiring TM[1], wiring TM[n], wiring TH[1,h], wiring TH[n,h], wiring THr[1,h], and wiring THr[n,h], the arithmetic circuit MAC2-2 in Figure 24 may be configured, for example, by combining wiring TM[1], wiring TH[1,h], and wiring THr[1,h] into a single wiring, and by combining wiring TM[n], wiring TH[n,h], and wiring THr[n,h] into a single wiring.

[0526] As described above, by configuring the arithmetic circuit shown in Figure 23 to perform hierarchical neural network operations, the value (amount of current) of the neuron output signal output from arithmetic circuit MAC2-1 can be input directly to arithmetic circuit MAC2-2, so that hierarchical neural network operations can be performed continuously, for example, from the first layer. Furthermore, since the output signals output from wiring OL[1] to wiring OL[n] of arithmetic circuit MAC2-1 do not need to be temporarily stored in an external circuit or the like, there is no need to provide a separate storage device required for temporary storage. In other words, by configuring the arithmetic circuit shown in Figure 23, the circuit area can be reduced, and the power required for data transmission for temporary storage can be reduced.

[0527] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0528] (Embodiment 5) In this embodiment, a structural example of the semiconductor device described in the above embodiment and a structural example of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

[0529] <Configuration example of semiconductor device> 25 shows, as an example, a configuration in which a photoelectric conversion element is applied as a photodiode to the sensor SNC in the arithmetic circuit MAC4 described in the third embodiment. Specifically, the semiconductor device shown in FIG. 25 includes a transistor 300, a transistor 500, a capacitor 600, and a photoelectric conversion element 700. FIG. 27A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 27B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 27C is a cross-sectional view of the transistor 300 in the channel width direction.

[0530] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of a small off-state current and a field-effect mobility that does not change even at high temperatures. By using the transistor 500 in a semiconductor device, such as a transistor included in the arithmetic circuit MAC1, arithmetic circuit MAC1A, arithmetic circuit MAC2, arithmetic circuit MAC3, or arithmetic circuit MAC4 described in the above embodiments, a semiconductor device whose operating capability is not degraded even at high temperatures can be realized. In particular, by utilizing the characteristics of a small off-state current, the transistor 500 can be used as the transistor F1 or F1m, allowing a potential written to the cell IM or IMref to be held for a long time.

[0531] The transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistor 300 and the transistor 500, for example. The photoelectric conversion element 700 is provided above the capacitor 600, for example. The capacitor 600 can be a capacitor included in the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3, or the like described in the above embodiments. Depending on the circuit configuration, the capacitor 600 shown in FIG. 25 is not necessarily provided.

[0532] The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. Note that the transistor 300 can be applied to, for example, a transistor included in the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3, or the like described in the above embodiments. Specifically, the transistor 300 can be, for example, a transistor included in an operational amplifier OP1 included in the conversion circuits ITRZ1 to ITRZ3 in FIGS. 4A to 4C. Note that Figure 25 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 through one of a pair of electrodes of the capacitor 600. However, depending on the configuration of the arithmetic circuit MAC1, arithmetic circuit MAC1A, arithmetic circuit MAC2, arithmetic circuit MAC3, etc., one of the source and drain of the transistor 300 may be electrically connected to one of the source and drain of the transistor 500 through one of the pair of electrodes of the capacitor 600, or one of the source and drain of the transistor 300 may be electrically connected to the gate of the transistor 500 through one of the pair of electrodes of the capacitor 600. Furthermore, each terminal of the transistor 300 may not be electrically connected to each terminal of the transistor 500 or each terminal of the capacitor 600.

[0533] As the substrate 311, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0534] 27C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0535] The transistor 300 may be either a p-channel type or an n-channel type.

[0536] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0537] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0538] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0539] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0540] 25 is just an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as shown in FIG. 26. The details of the transistor 500 will be described later.

[0541] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order to cover the transistor 300.

[0542] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0543] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0544] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0545] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0546] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0547] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0548] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0549] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0550] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0551] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 25 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0552] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0553] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0554] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 25, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0555] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0556] Moreover, a wiring layer (not shown) may be provided on the insulator 364 and the conductor 366.

[0557] Although the above describes a wiring layer including the conductor 356 and a wiring layer including the conductor 366, the semiconductor device according to this embodiment is not limited to this. There may be one or less wiring layers similar to the wiring layer including the conductor 356, or there may be three or more wiring layers similar to the wiring layer including the conductor 356. Furthermore, there may be two or more wiring layers similar to the wiring layer including the conductor 366.

[0558] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like.

[0559] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0560] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0561] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0562] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0563] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0564] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0565] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0566] Above the insulator 516 is the transistor 500 .

[0567] As shown in Figures 27A and 27B, the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the surface on which the oxide 530c is formed, and a conductor 560 arranged on the surface on which the insulator 550 is formed. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.

[0568] 27A and 27B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a disposed inside the insulator 550 and a conductor 560b disposed so as to be embedded inside the conductor 560a, as shown in FIGS. 27A and 27B, it is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 550.

[0569] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0570] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 25, 27A, and 27B is merely an example, and the transistor is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0571] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0572] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0573] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0574] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0575] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0576] Here, the conductor 503a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the impurities are less likely to permeate through it). Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through it). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen.

[0577] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0578] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, when the conductivity of the wiring can be maintained at a high level, the conductor 503a is not necessarily provided. While the conductor 503b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0579] The insulators 520, 522, and 524 function as a second gate insulating film.

[0580] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0581] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0582] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0583] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0584] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0585] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0586] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0587] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524, the oxide 530, and the like.

[0588] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0589] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0590] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0591] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0592] 27A and 27B illustrate the insulator 520, the insulator 522, and the insulator 524 as the second gate insulating film having a three-layer stack structure, the second gate insulating film may have a single-layer, two-layer, or four or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0593] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) or a Cloud-Aligned Composite Oxide Semiconductor (CAC-OS). Alternatively, an In-Ga oxide, an In-Zn oxide, an In oxide, or the like may be used for the oxide 530.

[0594] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0595] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which can cause oxygen vacancies in the metal oxide. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V O H functions as a donor and may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in a metal oxide is easily moved by stresses such as heat and an electric field, the reliability of the transistor may be reduced if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0596] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0597] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0598] When a metal oxide is used for the oxide 530, the metal oxide has a wide band gap and is an intrinsic (also called I-type) or substantially intrinsic semiconductor. The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0599] Furthermore, when a metal oxide is...

Claims

1. a first circuit, a second circuit, a third circuit, a first cell, a second cell, a first wiring, and a second wiring; the first circuit is electrically connected to the first wiring; the second circuit is electrically connected to the second wiring; the third circuit is electrically connected to the second wiring, the first circuit has a function of causing a first current to flow from the first circuit to the first cell via the first wiring; the second circuit has a function of causing a second current to flow through the second wiring; the third circuit includes a sensor; the sensor has a function of performing sensing and outputting a third current according to a result of the sensing; the third circuit has a function of causing the third current to flow through the second wiring; the first cell has a function of setting the amount of the first current by holding a potential according to the first current; The second cell has a function of setting the amount of current flowing through the second wiring by holding a potential according to the current flowing through the second wiring. Semiconductor device.

2. In claim 1, the sensor includes a photodiode; Semiconductor device.

3. A semiconductor device according to claim 1 or 2, and a housing, A product-sum operation is performed by the semiconductor device. electronic equipment.

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