Semiconductor Devices

Abstract

To provide a facilitation of semiconductor device assembly while reducing inductance of signal terminal wiring.SOLUTION: A semiconductor device 1 according to an embodiment includes a case 10 and a part 20. The case 10 includes a semiconductor circuit. The part 20 is configured to be attachable to the case 10. The part 20 includes a signal terminal TGU, and a wiring 22 electrically connected to the signal terminal TGU. The wiring 22 includes a contact unit CP that is in contact with an electrode 14 included in the semiconductor circuit when the part 20 is attached to the case 10, a lead unit LP having a first portion provided above the contact unit CP, and a spring unit SP having elasticity and provided between the first portion of the lead unit LP and the contact unit CP.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is a device in which multiple power semiconductors are mounted in a single package. Power modules are called 1-in-1, 2-in-1, 6-in-1, etc. depending on the number of power semiconductors. A known power module has a configuration in which a case containing a semiconductor circuit including power semiconductors is fitted with components having signal terminals connected to the semiconductor circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-335719 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-248907 Summary of the Invention [Problem to be solved by the invention]

[0004] The inductance of the wiring of the signal terminal is reduced, and the assembly of the semiconductor device is simplified. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a case and a component. The case includes a semiconductor circuit. The component is configured to be mountable to the case. The component includes a signal terminal and wiring electrically connected to the signal terminal. The wiring includes a contact portion that contacts an electrode included in the semiconductor circuit when the component is mounted in the case, a lead portion having a portion provided above the contact portion, and a spring portion having elasticity that is provided between a first portion of the lead portion and the contact portion. The case has a base substrate and a first insulating member that surrounds the side of the semiconductor circuit and is provided on the base substrate. The component has a second insulating member to which the lead portions are insert-molded. The first insulating member has first and second claws aligned along the long side. The second insulating member has first and second receiving portions that correspond to the first and second claws, respectively. When the component is attached to the case, the first insulating member and the second insulating member come into contact, and the first and second claws engage with the first and second receiving portions, respectively, thereby fixing the component to the case. The wiring portion is located between the first and second claws. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing an example of a planar layout of a case included in the semiconductor device according to the first embodiment. [Figure 3] FIG. 2 is a plan view showing an example of a planar layout of components included in the semiconductor device according to the first embodiment. [Figure 4] FIG. 1 is a plan view showing an example of a planar layout of a semiconductor device according to a first embodiment. [Figure 5] 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 6] 1A to 1C are cross-sectional views showing cross-sectional structures of the semiconductor device according to the first embodiment before and after assembly. [Figure 7] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a modified example of the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a second embodiment. [Figure 9] 10A to 10C are cross-sectional views showing cross-sectional structures of a semiconductor device according to a second embodiment before and after assembly. [Figure 10] FIG. 11 is a plan view showing an example of a planar layout of components included in a semiconductor device according to a third embodiment. [Figure 11] 10A to 10C are cross-sectional views showing cross-sectional structures of a semiconductor device according to a third embodiment before and after assembly. [Figure 12] 10A to 10C are cross-sectional views showing cross-sectional structures of a semiconductor device according to a modified example of the third embodiment before and after assembly.

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and ratios of the drawings are not necessarily the same as those in reality. In the description of the drawings, the terms "upper side," "lower side," "left side," and "right side" refer to the upper side, lower side, left side, and right side of the drawing to which the reference is made, respectively. In this specification, components having substantially the same functions and configurations are assigned the same reference numerals. Numbers and letters added to the reference numerals are used to refer to the same reference numerals and to distinguish between similar elements.

[0008] [1] First embodiment The semiconductor device 1 according to the first embodiment is a power module. The semiconductor device 1 is applied to, for example, power conversion devices for railway vehicles and industrial equipment for renewable energy power generation systems. The semiconductor device 1 has a configuration in which wiring (leads) having elasticity (springiness) is used to connect a semiconductor circuit inside a case to a signal terminal. The first embodiment will be described below using an example in which the semiconductor device 1 is a 2-in-1 power module.

[0009] [1-1] Circuit configuration of semiconductor device 1 Fig. 1 is a circuit diagram showing an example of the circuit configuration of a semiconductor device 1 according to the first embodiment. As shown in Fig. 1, the semiconductor device 1 includes, for example, terminals TP and TN, a terminal TOUT, terminals TGU and TGL, transistors NMU and NML, inductors L1 and L2, diodes DU and DL, and terminals TMVU, TMVL, TMCU, and TMCL.

[0010] The terminals TP and TN are input terminals of the semiconductor device 1. The terminals TP and TN have positive and negative polarities, respectively, in the circuit configuration of the semiconductor device 1. The terminal TP may be called the "positive terminal." The terminal TN may be called the "negative terminal."

[0011] The terminal TOUT is an output terminal of the semiconductor device 1. The terminal TOUT may be called an "AC (Alternating Current) terminal."

[0012] Each of the terminals TGU and TGL is a control terminal of the semiconductor device 1. The control terminal corresponds to a signal terminal used to control whether or not to drive a power semiconductor element included in the semiconductor device 1. The terminal TGU may be called an "upper gate terminal." The terminal TGL may be called a "lower gate terminal."

[0013] Each of the transistors NMU and NML is, for example, an N-type MOS (Metal-Oxide-Semiconductor) transistor. The transistors NMU and NML are connected in series between the terminals TP and TN. The transistor NMU has a drain terminal connected to the terminal TP, a gate terminal connected to the terminal TGU, and a source terminal connected to a node N1. The transistor NML has a drain terminal connected to the node N2, a gate terminal connected to the terminal TGL, and a source terminal connected to a node N3. The transistor NMU may be called the "upper transistor." The transistor NML may be called the "lower transistor."

[0014] Each of the inductances L1 and L2 is, for example, a parasitic inductance in the circuit configuration of the semiconductor device 1. The inductance L1 is connected between the transistors NMU and NML. Specifically, a first end of the inductance L1 is connected to a node N1. A second end of the inductance L1 is connected to a node N2. The inductance L2 is connected between the transistor NML and the terminal TN. Specifically, a first end of the inductance L2 is connected to a node N3. A second end of the inductance L2 is connected to a node N4. The node N4 is connected to the terminal TN.

[0015] Diode DU is, for example, a parasitic diode of transistor NMU. Diode DL is, for example, a parasitic diode of transistor NML. Between terminals TP and TN, diode DU is connected in parallel with transistor NMU, and diode DL is connected in parallel with transistor NML. Diodes DU and DL each function as a free wheeling diode (FWD).

[0016] Each of the terminals TMVU, TMVL, TMCU, and TMCL is a monitor terminal of the semiconductor device 1. The monitor terminal corresponds to a signal terminal used to monitor the electrical characteristics (for example, voltage and current) of the circuit configuration of the semiconductor device 1.

[0017] Terminals TMVU and TMVL are monitor terminals for the source potentials of the transistors. Terminals TMVU and TMVL are connected to nodes N1 and N3, respectively. That is, terminal TMVU is used to monitor the voltage at the source terminal of transistor NMU. Terminal TMVL is used to monitor the voltage at the source terminal of transistor NML. Terminal TMU may be called the "upper source monitor (sense) terminal." Terminal TML may be called the "lower source monitor (sense) terminal."

[0018] Terminals TMCU and TMCL are monitor terminals for the current flowing through the semiconductor device 1, and are used together with terminals TMVU and TMVL. Terminals TMCU and TMCL are connected to nodes N2 and N4, respectively. The current flowing through transistor NMU can be calculated by detecting the potential difference occurring across inductance L1 (i.e., the potential difference between terminals TMVU and TMCU) and back-calculating the detected potential difference. The current flowing through transistor NML can be calculated by detecting the potential difference occurring across inductance L2 (i.e., the potential difference between terminals TMVL and TMCL) and back-calculating the detected potential difference.

[0019] In the semiconductor device 1, each of the transistors NMU and NML may be an IGBT (Insulated-Gate Bipolar Transistor). A plurality of transistors NMU may be connected in parallel between the terminal TP and the node N1. A plurality of transistors NML may be connected in parallel between the terminal TN and the node N3. The semiconductor device 1 may include signal terminals other than the terminals TGU, TGL, TMVU, TMVL, TMCU, and TMCL. The terminals TMVU, TMVL, TMCU, and TMCL may be omitted from the semiconductor device 1. The number of each terminal may be plural.

[0020] [1-2] Structure of semiconductor device 1 The structure of the semiconductor device 1 will be described below. The semiconductor device 1 has a combination of a case 10 and a component 20. The case 10 includes a semiconductor circuit including a power semiconductor. The component 20 includes at least one control terminal and a wiring (lead). In the following description, a signal terminal provided corresponding to an upper transistor (NMU) will be referred to as a "terminal TMU," and a signal terminal provided corresponding to a lower transistor (NML) will be referred to as a "terminal TML." The structure of the terminal TMU can be applied to both the terminals TMVU and TMCU. The structure of the terminal TML can be applied to both the terminals TMVL and TMCL. The following describes an example in which the semiconductor device 1 includes a pair of terminals TMU and TML.

[0021] [1-2-1] Case 10 floor plan layout 2 is a plan view showing an example of the planar layout of a case 10 included in the semiconductor device 1 according to the first embodiment. As shown in FIG. 2, the case 10 includes, for example, an insulating member 11, insulating substrates 12a and 12b, conductors 13a and 13b, conductors 14a and 14b, conductors 15a and 15b, conductors 16a and 16b, conductors 17a and 17b, and conductors 18a, 18b, 18c, and 18d. The case 10 also includes a base substrate SUB (not shown).

[0022] The base substrate SUB is a support for the semiconductor device 1. The base substrate SUB has a flat plate shape. The base substrate SUB corresponds to the lower part of the container of the semiconductor device 1. The base substrate SUB has, for example, screw holes in the four corners. The base substrate SUB can be fixed to an external device (not shown) of the semiconductor device 1 via the screw holes. The base substrate SUB includes, for example, copper (Cu) or ceramics.

[0023] The insulating member 11 is provided on the base substrate SUB. The insulating member 11 is, for example, an insulator having a rectangular cylindrical shape. The insulating member 11 corresponds to the side of the container of the semiconductor device 1 and is fixed to the base substrate SUB. The insulating member 11 is, for example, a resin part and contains polyphenylene sulfide (PPC). In this specification, a plane parallel to the contact surface between the base substrate SUB and the insulating member 11 is defined as the XY plane. In the XY plane, the long side direction and short side direction of the base substrate SUB are defined as the X direction and the Y direction, respectively. The Z direction corresponds to the direction perpendicular to the XY plane.

[0024] The insulating member 11 also has receiving portions 111a, 111b, 112a, and 112b. The receiving portions 111 and 112 are, for example, recessed portions formed on the inner wall of the insulating member 11. The receiving portions 111 and 112 are used to fasten the case 10 and the component 20, and may have any shape that allows the hooks of the component 20 to catch thereon. The receiving portions 111a and 111b are aligned in the X direction on the upper side of the inner wall of the insulating member 11. The receiving portions 112a and 112b are aligned in the X direction on the lower side of the inner wall of the insulating member 11. The receiving portions 111a and 112a are located on the left side and face each other in the Y direction. The receiving portions 111b and 112b are located on the right side and face each other in the Y direction.

[0025] The insulating substrates 12a and 12b are insulating substrates that support the circuit configuration of the semiconductor device 1. The insulating substrate 12 is provided on the base substrate SUB and is surrounded by the insulating member 11 in a plan view. In other words, the insulating member 11 surrounds the sides of the insulating substrate 12. The insulating substrates 12a and 12b are aligned in the X direction and are located on the left and right sides, respectively. The insulating substrate 12 includes, for example, silicon nitride (SiN).

[0026] Conductors 13a, 14a, 15a, 16a, and 17a are provided on insulating substrate 12a. Conductors 13a, 14a, 15a, 16a, and 17a are spaced apart from one another. Each of conductors 13a, 14a, 15a, 16a, and 17a has a portion extending along the X direction. The portions of conductors 13a, 14a, 15a, 16a, and 17a extending along the X direction are aligned in this order along the Y direction. Conductor 15a also has a portion extending in the Y direction. The portion of conductor 15a extending in the Y direction includes, for example, a portion provided to the left of conductors 13a, 14a, 16a, and 17a.

[0027] Conductors 13b, 14b, 15b, 16b, and 17b are provided on insulating substrate 12b. Conductors 13b, 14b, 15b, 16b, and 17b are spaced apart from one another. Each of conductors 13b, 14b, 15b, 16b, and 17b has a portion extending along the X direction. The portions of conductors 13b, 14b, 15b, 16b, and 17b extending along the X direction are aligned in this order along the Y direction. Conductor 13b has a portion extending in the Y direction. The portion of conductor 13b extending in the Y direction includes, for example, a portion located to the right of conductor 14b. Conductor 15b has a portion extending in the Y direction. The portion of conductor 15b extending in the Y direction includes, for example, a portion located to the right of conductor 16b.

[0028] Each of the conductors 18a, 18b, 18c, and 18d has a terminal portion and a lead, and is insert-molded into the insulating member 11, for example. The terminal portion of each of the conductors 18a, 18b, 18c, and 18d has a portion exposed above the insulating member 11. Each of the conductors 18a and 18b corresponds to the terminal TOUT. The conductors 18a and 18b are aligned in the Y direction on the left side of the insulating member 11. The leads of the conductors 18a and 18b are connected to the conductor 15a. The conductors 18c and 18d correspond to the terminals TP and TN, respectively. The conductors 18c and 18d are aligned in the Y direction on the right side of the insulating member 11. The lead of the conductor 18c is connected to the conductor 13b. The lead of the conductor 18d is connected to the conductor 17b.

[0029] Each of the transistors NMU and NML included in the semiconductor device 1 is, for example, a vertical transistor. In Fig. 2, each of the transistors NMU and NML is represented by a rectangular region without hatching. The bottom surface (the side of the base substrate SUB) of the region corresponds to the drain end of the transistor. Two dots aligned along the X direction in the region correspond to the source end. A dot arranged below the region corresponds to the gate end.

[0030] A plurality of transistors NMU are arranged in the X direction on the conductor 13a. Hereinafter, the transistors NMU on the conductor 13a will be referred to as "transistors NMUa." The drain terminal of each transistor NMUa is connected to the conductor 13a. The gate terminal of each transistor NMUa is connected to the conductor 14a. The source terminal of each transistor NMUa is connected to the conductor 15a.

[0031] A plurality of transistors NMU are arranged in the X direction on the conductor 13b. Hereinafter, the transistors NMU on the conductor 13b will be referred to as "transistors NMUb." The drain terminal of each transistor NMUb is connected to the conductor 13b. The gate terminal of each transistor NMUb is connected to the conductor 14b. The source terminal of each transistor NMUb is connected to the conductor 15b.

[0032] A plurality of transistors NML are arranged in the X direction on the conductor 15a. Hereinafter, the transistors NML on the conductor 15a will be referred to as "transistors NMLa." The drain terminal of the transistor NMLa is connected to the conductor 15a. The gate terminal of the transistor NMLa is connected to the conductor 16a. The source terminal of the transistor NMLa is connected to the conductor 17a.

[0033] A plurality of transistors NML arranged in the X direction are provided on the conductor 15b. Hereinafter, the transistor NML on the conductor 15b will be referred to as "transistor NMLb." The drain terminal of the transistor NMLb is connected to the conductor 15b. The gate terminal of the transistor NMLb is connected to the conductor 16b. The source terminal of the transistor NMLb is connected to the conductor 17b.

[0034] The drains of the transistors NMUa and NMUb are electrically connected. The sources of the transistors NMUa and NMUb are electrically connected to the drains of the transistors NMLa and NMLb. The sources of the transistors NMLa and NMLb are electrically connected. Specifically, the conductors 13a and 13b, the conductors 15a and 15b, and the conductors 17a and 17b are connected to each other by, for example, wire bonding.

[0035] The conductors 13a and 13b may be referred to as drain electrodes of the transistors NMUa and NMUb, respectively. The conductors 14a and 14b may be referred to as gate electrodes of the transistors NMUa and NMUb, respectively. The conductors 15a and 15b may be referred to as source electrodes of the transistors NMUa and NMUb, respectively, or drain electrodes of the transistors NMLa and NMLb, respectively. The conductors 16a and 16b may be referred to as gate electrodes of the transistors NMLa and NMLb, respectively. The conductors 17a and 17b may be referred to as source electrodes of the transistors NMLa and NMLb, respectively.

[0036] [1-2-2] Plan layout of part 20 3 is a plan view showing an example of a planar layout of the component 20 included in the semiconductor device 1 according to the first embodiment. In FIG. 3, a part of the configuration of the case 10 that is arranged overlapping the component 20 after the semiconductor device 1 is assembled is shown by the area enclosed by a two-dot chain line. As shown in FIG. 3, the component 20 includes, for example, an insulating member 21 and conductors 22, 23, 24, and 25.

[0037] The insulating member 21 is, for example, an insulator having a rectangular cylindrical shape. The width in the X direction of the insulating member 21 is, for example, narrower than the width in the X direction of the insulating member 11 of the case 10. The width in the Y direction of the insulating member 21 is, for example, the same as the width in the Y direction of the insulating member 11 of the case 10. The insulating member 21 is, for example, a resin part and contains polyphenylene sulfide.

[0038] The insulating member 21 also has claws 211a, 211b, 212a, and 212b. Each of the claws 211 and 212 has a claw-shaped structure for attaching the component 20 to the case 10. Specifically, each of the claws 211a, 211b, 212a, and 212b has a portion that protrudes inward from the inner wall of the insulating member 11 of the case 10. These portions extend toward the case 10 in the Z direction and then curve outward. Each of the claws 211 and 212 is used to fasten the case 10 and the component 20 together, and may have any shape that allows it to be hooked onto a receiving portion of the case 10. The claws 211a, 211b, 212a, and 212b of the component 20 are arranged so as to be able to face the receiving portions 111a, 111b, 112a, and 112b of the case 10, respectively.

[0039] Each of the conductors 22, 23, 24, and 25 is insert-molded into the insulating member 21. The conductors 22, 23, 24, and 25 are separated from one another. The conductors 22, 23, 24, and 25 correspond to terminals TGU, TMU, TGL, and TML, respectively. That is, the insulating member 21 holds a plurality of signal terminals. The terminal portions of the conductors 22, 23, 24, and 25 correspond to portions exposed above the insulating member 21. Each of the conductors 22, 23, 24, and 25 also has a lead portion LP and a contact portion CP. Each lead portion LP corresponds to a wiring (lead) for connecting the associated terminal and electrode (conductor). Each contact portion CP corresponds to a portion that contacts the electrode (conductor).

[0040] The lead portion LP of the conductor 22 has two portions overlapping with the conductors 14a and 14b, respectively, and two contact portions CP of the conductor 22 are provided so as to overlap with the two portions, respectively. The lead portion LP of the conductor 23 has a portion overlapping with the conductor 15a, and the contact portion CP of the conductor 23 is provided so as to overlap with the portion. The lead portion LP of the conductor 24 has two portions overlapping with the conductors 16a and 16b, respectively, and two contact portions CP of the conductor 24 are provided so as to overlap with the two portions, respectively. The lead portion LP of the conductor 25 has a portion overlapping with the conductor 17a, and the contact portion CP of the conductor 25 is provided so as to overlap with the portion. Note that the terminal portion and the lead portion LP of the conductor corresponding to the signal terminal may be formed integrally or separately. It is sufficient that at least the terminal portion and the lead portion LP of the conductor corresponding to the signal terminal are electrically connected.

[0041] [1-2-3] Planar layout of semiconductor device 1 Fig. 4 is a plan view showing an example of the planar layout of the semiconductor device 1 according to the first embodiment. Fig. 4 corresponds to the planar layout in a state in which components 20 are attached to the case 10, and is shown without showing wiring such as wire bonding inside the case 10. As shown in Fig. 4, the semiconductor device 1 includes, for example, mating portions EPUa, EPUb, EPLa, and EPLb.

[0042] At each of the mating portions EPUa, EPUb, EPLa, and EPLb, the receiving portions of the case 10 arranged opposite to each other are engaged with the claw portions of the component 20. Specifically, at the mating portion EPUa, the receiving portion 111a is engaged with the claw portion 211a. At the mating portion EPUb, the receiving portion 111b is engaged with the claw portion 211b. At the mating portion EPLa, the receiving portion 112a is engaged with the claw portion 212a. At the mating portion EPLb, the receiving portion 112b is engaged with the claw portion 212b. This attaches the component 20 to the case 10, and the component 20 is fixed to the case 10.

[0043] When component 20 is attached to case 10, the two contact portions CP of conductor 22 (terminal TGU) are pressure-contacted to conductors 14a and 14b, respectively. Similarly, the contact portion CP of conductor 23 (terminal TMU) is pressure-contacted to conductor 15a. Similarly, the two contact portions CP of conductor 24 (terminal TGL) are pressure-contacted to conductors 16a and 16b, respectively. Similarly, the contact portion CP of conductor 25 (terminal TML) is pressure-contacted to conductor 17b. The semiconductor device 1 uses wiring having elasticity (springiness) to obtain the pressure (hereinafter referred to as pressure contact force) required to pressure-contact the contact portions CP to the conductors.

[0044] Although not shown, a lid may be provided on the component 20. The lid is, for example, fixed to the component 20 and seals the space in which the circuit of the semiconductor device 1 is provided. The lid is an insulator and contains, for example, polyphenylene sulfide.

[0045] [1-2-4] Cross-sectional structure of semiconductor device 1 FIG. 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of the cross-sectional structure of the semiconductor device 1 according to the first embodiment. FIG. 5 shows an extracted region corresponding to the conductor 22 (terminal TGU) as an example of the structure of the signal terminal of the first embodiment. As shown in FIG. 5, a component 20 is mounted on a case 10. An insulating member 11 and an insulating substrate 12 are provided on a base substrate SUB. Conductors 13 and 14 are provided on the insulating substrate 12. The height of the insulating member 11 is greater than the combined height of the insulating substrate 12 and the conductor 13. An insulating member 21 of the component 20 is provided on the insulating member 11 of the case 10.

[0046] The conductor 22 has a terminal portion (terminal TGU), a lead portion LP, a contact portion CP, and a spring portion SP. The terminal TGU, lead portion LP, spring portion SP, and contact portion CP are provided continuously in this order. The terminal TGU and lead portion LP may be formed separately as long as they are electrically connected. In the conductor 22, the portion where the lead portion LP, spring portion SP, and contact portion CP are provided continuously may be called the "wiring (lead) of the signal terminal." The lead portion LP may be called the "beam portion of the wiring."

[0047] The terminal TGU and lead portion LP have portions that are insert-molded into the insulating member 21. The terminal TGU has a portion that extends in the Z direction, and for example, protrudes upward from the insulating member 21. The lead portion LP has a plate-like portion that extends in the Y direction. The contact portion CP is provided in a plate shape that can come into surface contact with the conductor 14. The contact portion CP has a portion that overlaps the end of the lead portion LP in the Z direction. The end of the lead portion LP and the contact portion CP are connected via the plate-like portion that extends along the Z direction.

[0048] The spring portion SP is provided in a portion between the end of the lead portion LP and the contact portion CP. The spring portion SP may also be called a bent portion. In the spring portion SP, the conductor 22 has a bent shape so as to protrude in a direction parallel to the XY plane. Specifically, in the spring portion SP, the conductor 22 has a bent shape, for example, along the circumference of a semi-ellipse. The spring portion SP has elasticity (springiness). In the semiconductor device 1, the contact portion CP is pressed against the conductor 14 by pressure based on the elasticity of the spring portion SP.

[0049] In the above explanation, the conductor 22 (terminal TGU) has been described as an example of the structure of a signal terminal, but other signal terminals have a similar structure to the terminal TGU. Note that the lead portion LP is preferably configured to be more resistant to deformation than the spring portion SP when the component 20 is attached to the case 10. The lead portion LP may have a portion that is deformed in the Z direction. The shape of the spring portion SP is not limited to a curved plate shape, and may be any shape that has spring properties.

[0050] [1-3] Cross-sectional structure of semiconductor device 1 before and after assembly Fig. 6 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 1 according to the first embodiment before and after assembly. (A) and (B) of Fig. 6 respectively correspond to the state before and after assembly of the semiconductor device 1. Fig. 6 also schematically shows the structure of the semiconductor device 1 to illustrate how the receiving portion of the case 10 and the claw portion of the component 20 engage with each other, and how the terminals TGU and TGL arranged on the upper and lower sides of the component 20 shown in Fig. 3 are connected to the electrodes.

[0051] In the following, of insulating member 11 of case 10, the portion arranged on the upper side of case 10 shown in Fig. 2 will be referred to as "insulating member 11U," and the portion arranged on the lower side of case 10 shown in Fig. 2 will be referred to as "insulating member 11L." Similarly, of insulating member 21 of component 20, the portion arranged on the upper side of component 20 shown in Fig. 3 will be referred to as "insulating member 21U," and the portion arranged on the lower side of component 20 shown in Fig. 3 will be referred to as "insulating member 21L."

[0052] As shown in FIG. 6A, the receiving portion 111 provided on the insulating member 11U and the claw portion 211 provided on the insulating member 21U are arranged to face each other in the Z direction. The receiving portion 112 provided on the insulating member 11L and the claw portion 212 provided on the insulating member 21L are arranged to face each other in the Z direction. The spring portion SP of the conductor 22 (terminal TGU) insert-molded into the insulating member 21U is in a state where no external load is applied. Similarly, the spring portion SP of the conductor 24 (terminal TGL) insert-molded into the insulating member 21L is in a state where no external load is applied. The component 20 is attached to the case 10 when it is pressed into the base substrate SUB.

[0053] As shown in FIG. 6B, when component 20 is attached to case 10, receiving portion 111 and claw portion 211 engage with each other to form engaging portion EPU. Similarly, receiving portion 112 and claw portion 212 engage with each other to form engaging portion EPL. This secures component 20 to case 10. Furthermore, when component 20 is attached to case 10, when contact portion CP of conductor 22 comes into contact with conductor 14, spring portion SP of conductor 22 is deformed by pressure applied in the Z direction via lead portion LP of conductor 22. When component 20 is attached to case 10, a pressure based on the elasticity of spring portion SP of conductor 22 is applied to contact portion CP of conductor 22. In other words, contact portion CP of conductor 22 is pressed against conductor 14 (electrode). As a result, the bottom surface of the contact portion CP of the conductor 22 is pressed against the top surface of the conductor 14 and electrically connected to the conductor 14. Similarly, the bottom surface of the contact portion CP of the conductor 24 is pressed against the top surface of the conductor 16 and electrically connected to the conductor 16.

[0054] [1-4] Effects of the first embodiment Known methods for connecting a signal terminal and a gate terminal of a semiconductor circuit include wire bonding, ultrasonic bonding, and solder bonding. However, when wire bonding is used, the gate wiring becomes longer, which may increase the wiring inductance. Furthermore, the area provided for wire bonding may become dead space. When a ceramic substrate is used as the base substrate, ultrasonic bonding may cause the ceramic substrate to crack. Furthermore, ultrasonic bonding cannot be used when a resin substrate is used as the base substrate. When solder bonding is used, the case cannot withstand the reflow temperature, which may increase the number of manufacturing processes.

[0055] Therefore, the semiconductor device 1 according to the first embodiment includes a component 20 with a signal terminal insert-molded therein. When the component 20 is fitted into the case 10 of the semiconductor device 1, the wiring (leads) of the signal terminal are pressed against the internal circuit by the pressure of the spring portion SP, and are electrically connected to the internal circuit. In other words, the manufacturing process of the semiconductor device 1 does not require additional processes such as wire bonding, ultrasonic bonding, or solder bonding for connecting the signal terminal and the internal circuit, and the number of steps required to assemble the case 10 and the component 20 is reduced.

[0056] This reduces the difficulty of assembly of the semiconductor device 1 and reduces manufacturing costs. Furthermore, the semiconductor device 1 does not require areas for wire bonding or the like for connecting the signal terminals to the internal circuit, so the wiring of the signal terminals can be designed compactly. Designing the wiring of the signal terminals compactly reduces inductance. Therefore, the semiconductor device 1 according to the first embodiment can simplify assembly of the semiconductor device 1 while expanding the area of ​​the main wiring by making the signal wiring compact and reducing the inductance and wiring resistance of the signal terminals and main wiring.

[0057] In the semiconductor device 1, the signal terminals and the internal circuit are fixed to each other without any stress because they are connected by crimping, which improves the reliability of the connection between the signal terminals and the internal circuit.

[0058] In a power module, the external terminals are defined by a standard. Therefore, if a unique standard is used for the signal terminals, versatility is lost. In contrast, in the semiconductor device 1 according to the first embodiment, the signal terminals and electrodes are electrically connected by a simple wiring structure, making it possible to design in accordance with the standard. Therefore, the semiconductor device 1 according to the first embodiment can reduce the design costs of the system that uses the power module.

[0059] [1-5] Modification of the first embodiment The thickness of the wiring of the signal terminal described in the first embodiment does not have to be substantially uniform.

[0060] Fig. 7 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device 1a according to a modification of the first embodiment. As shown in Fig. 7, the semiconductor device 1a according to the modification of the first embodiment includes a case 10 and a component 20a. The component 20a has a configuration in which the conductor 22 (terminal TGU) in the component 20 of the first embodiment is replaced with a conductor 22a.

[0061] The conductor 22a has a terminal portion (terminal TGU), a lead portion LPa, a contact portion CP, and a spring portion SP. The conductor 22a in the lead portion LPa is thicker than other wiring portions (e.g., the spring portion SP and contact portion CP). In other words, the thickness of the conductor 22a (signal terminal wiring) is thicker in the lead portion LPa than in the spring portion SP. This gives the lead portion LPa higher rigidity than the lead portion LP of the first embodiment. Note that the structure of the signal terminals other than the terminal TGU in the modified example of the first embodiment is similar to that of the conductor 22a, so a description thereof will be omitted. The other configurations of the semiconductor device 1a according to the modified example of the first embodiment are the same as those of the first embodiment.

[0062] Deformation of the lead portions LP can cause the contact points between the contact portions CP and the electrodes to become point contacts. In other words, deformation of the lead portions LP can cause variations in the contact state of the contact portions CP. In contrast, the semiconductor device 1 according to the modification of the first embodiment can suppress deformation of the lead portions LP when the component 20a is attached to the case 10 more than in the first embodiment. Therefore, the semiconductor device 1 according to the modification of the first embodiment can suppress variations in the characteristics of the power module based on the contact state of the contact portions CP more than in the first embodiment.

[0063] [2] Second embodiment The semiconductor device 1b according to the second embodiment has a configuration in which the semiconductor circuit and the signal terminal are connected via a spring portion SP having a structure different from that of the semiconductor device 1 according to the first embodiment. The following describes the differences between the second embodiment and the first embodiment.

[0064] [2-1] Cross-sectional structure of semiconductor device 1 Fig. 8 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device 1b according to the second embodiment. As shown in Fig. 8, the semiconductor device 1b according to the second embodiment includes a case 10 and a component 20b. The component 20b has a configuration in which the conductor 22 (terminal TGU) in the component 20 of the first embodiment is replaced with a conductor 22b.

[0065] The conductor 22b has a terminal portion (terminal TGU), a lead portion LP, a contact portion CP, and a spring portion SPa. The spring portion SPa is provided between the end of the lead portion LP and the contact portion CP. The conductor 22b has a loop shape in the spring portion SPa. In other words, in the conductor 22b, the end of the lead portion LP and the contact portion CP are continuously provided via a loop-shaped portion. The spring portion SPa has elasticity (springiness). In the semiconductor device 1b, the contact portion CP is pressed against the conductor 14 by pressure based on the elasticity of the spring portion SPa. Note that the structure of the signal terminals other than the terminal TGU in the second embodiment is similar to that of the conductor 22b, and therefore description thereof will be omitted. The other configurations of the semiconductor device 1b according to the second embodiment are the same as those of the first embodiment.

[0066] [2-2] Cross-sectional structure of semiconductor device 1 before and after assembly Fig. 9 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 1b according to the second embodiment before and after assembly. Fig. 9(A) and (B) respectively correspond to the semiconductor device 1b before and after assembly. Fig. 9 also shows a schematic structure of the semiconductor device 1b to illustrate how the receiving portion of the case 10 and the claw portion of the component 20 are engaged with each other and how the terminals TGU and TGL of the component 20b are connected to the electrodes.

[0067] 9A, the spring portion SPa of the conductor 22b (terminal TGU) insert-molded in the insulating member 21U is in a state where no external load is applied thereto. Similarly, the spring portion SPa of the conductor 24b (terminal TGL) insert-molded in the insulating member 21L is in a state where no external load is applied thereto.

[0068] As shown in FIG. 9B , when component 20b is attached to case 10, mating portions EPU and EPL are formed, similar to the first embodiment, and component 20 is fixed to case 10. Furthermore, during the process of attaching component 20b to case 10, when contact portion CPa of conductor 22b comes into contact with conductor 14, spring portion SPa of conductor 22b is deformed by pressure in the Z direction applied by lead portion LP of conductor 22b. Then, when component 20b is attached to case 10, a pressure-contact force based on the elasticity of spring portion SPa of conductor 22b is applied to contact portion CP of conductor 22b. As a result, the bottom surface of contact portion CPa of conductor 22b is pressed almost uniformly against the top surface of conductor 14, electrically connecting to conductor 14. Similarly, the bottom surface of contact portion CPa of conductor 24 is pressed almost uniformly against the top surface of conductor 16, electrically connecting to conductor 16.

[0069] [2-3] Effects of the second embodiment As described above, in the semiconductor device 1b according to the second embodiment, the spring portion SPa provided on the lead of the signal terminal has a loop shape. This allows the pressure applied to the contact portion CP when the case 10 and the component 20c are assembled to be more uniform than in the first embodiment, as the loop shape collapses. Therefore, the semiconductor device 1c according to the second embodiment can achieve the same effects as the first embodiment, and can suppress variations in the characteristics of the power module based on the contact state of the contact portion CP more than in the first embodiment.

[0070] [3] Third embodiment The semiconductor device 1c according to the third embodiment includes a component 20c that additionally functions as a lid for the case 10. The following describes the third embodiment in terms of the differences from the first and second embodiments.

[0071] [3-1] Planar layout of part 20a Fig. 10 is a plan view showing an example of the planar layout of a component 20c included in a semiconductor device 1c according to the third embodiment. In Fig. 10, portions provided inside or at the bottom of the component 20c are indicated by dashed lines. As shown in Fig. 10, the component 20c includes, for example, an insulating member 21a and conductors 22, 23, 24, and 25.

[0072] The insulating member 21a is, for example, a plate-shaped insulator. Similar to the insulating member 21, the insulating member 21a has claws 211a, 211b, 212a, and 212b. The claws 211a, 211b, 212a, and 212b of the insulating member 21a are used to fasten the case 10 and the component 20c, and are shaped so that they can be hooked onto receiving portions of the case 10. The claws 211a, 211b, 212a, and 212b of the component 20c are arranged so as to be opposite the receiving portions 111a, 111b, 112a, and 112b of the case 10, respectively.

[0073] The terminal portions of the conductors 22, 23, 24, and 25 of the component 20c correspond to the portions exposed above the insulating member 21a. The conductors 22, 23, 24, and 25 of the component 20c are insert-molded into the insulating member 21a. The lead portions LP of the conductors 22, 23, 24, and 25 of the component 20c are provided, for example, inside the insulating member 21a. The other configurations of the semiconductor device 1c according to the third embodiment are the same as those of the first embodiment.

[0074] [3-2] Cross-sectional structure of semiconductor device 1 before and after assembly Fig. 11 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 1c according to the third embodiment before and after assembly. Fig. 11 (A) and (B) correspond to the semiconductor device 1c before and after assembly, respectively. Fig. 11 also shows a schematic structure of the semiconductor device 1c to illustrate how the receiving portion of the case 10 and the claw portion of the component 20c engage with each other and how the terminals TGU and TGL of the component 20c are connected to the electrodes.

[0075] 11A, the spring portion SP of the conductor 22 (terminal TGU) insert-molded into the insulating member 21a is in a state where no external load is applied thereto. Similarly, the spring portion SP of the conductor 24 (terminal TGL) insert-molded into the insulating member 21a is in a state where no external load is applied thereto.

[0076] 11(B), when component 20c is attached to case 10, mating portions EPU and EPL are formed, and component 20c is fixed to case 10, as in the first embodiment. Furthermore, when component 20c is attached to case 10, a pressure contact force based on the elasticity of spring portion SP of conductor 22 is applied to contact portion CP of conductor 22. As a result, the bottom surface of contact portion CP of conductor 22 is pressed against the top surface of conductor 14, and electrically connected to conductor 14. Similarly, the bottom surface of contact portion CP of conductor 24 is pressed against the top surface of conductor 16, and electrically connected to conductor 16.

[0077] [3-3] Effects of the third embodiment As described above, the semiconductor device 1c according to the third embodiment has a configuration in which the insulating member 21a that holds the signal terminals is integrated with the lid of the case 10. When the case 10 and the component 20c are assembled, the semiconductor circuit is disposed in the space surrounded by the case 10 and the insulating member 21a. In other words, the insulating member 21a is also used as the lid of the semiconductor device 1c. As a result, the semiconductor device 1c according to the third embodiment can reduce the number of components and the assembly man-hours. Therefore, the semiconductor device 1c according to the third embodiment can obtain the same effects as the first embodiment and can further reduce the manufacturing costs of the power module.

[0078] [3-4] Modification of the third embodiment In the semiconductor device 1c according to the third embodiment, the receiving portions of the case 10 may be replaced with claw portions, and the claw portions of the component 20c may be replaced with receiving portions. That is, the claw portions for fixing the component 20 may be formed on the case 10 side.

[0079] Fig. 12 is a cross-sectional view showing the cross-sectional structure of a semiconductor device 1d according to a modification of the third embodiment before and after assembly. Fig. 12(A) and (B) respectively correspond to the semiconductor device 1d before and after assembly. Fig. 12 also schematically illustrates the structure of the semiconductor device 1d to show how the claw portions of the case 10a and the receiving portions of the component 20d engage with each other and how the terminals TGU and TGL of the component 20d are connected to the electrodes.

[0080] As shown in Fig. 12, case 10a has a configuration in which insulating members 11U and 11L in case 10 of the first embodiment are replaced with insulating members 11aU and 11aL, respectively. Insulating members 11aU and 11aL have claw portions 113 and 114, respectively. Component 20d has a configuration in which insulating member 21a in component 20c of the third embodiment is replaced with insulating member 21b. Insulating member 21b has receiving portions 213 corresponding to claw portion 113 and receiving portions 214 corresponding to claw portion 114.

[0081] 12A, the claws 113 provided on the insulating member 11aU and the receiving portions 213 provided on the insulating member 21b are arranged to face each other in the Z direction. The claws 113 provided on the insulating member 11aL and the receiving portions 214 provided on the insulating member 21b are arranged to face each other in the Z direction. When the component 20d is pushed into the base substrate SUB, it is attached to the case 10a.

[0082] 12(B), when component 20c is attached to case 10a, mating portions EPU and EPL are formed, and component 20d is fixed to case 10a, as in the first embodiment. Furthermore, when component 20d is attached to case 10, the bottom surface of contact portion CP of conductor 22 is pressed against the top surface of conductor 14, and electrically connected to conductor 14. Similarly, the bottom surface of contact portion CP of conductor 24 is pressed against the top surface of conductor 16, and electrically connected to conductor 16.

[0083] The semiconductor device 1d according to the modification of the third embodiment described above can achieve the same effects as the third embodiment.

[0084] [4] Other In each embodiment, the semiconductor device 1 is described as a 2-in-1 power module, but is not limited to this. The configuration of each embodiment can also be applied to other power modules, such as 1-in-1 and 6-in-1. In each embodiment, the signal terminal wiring is described as being insert-molded into the insulating member 21, but is not limited to this. The signal terminal wiring may also be outsert-molded into the insulating member 21. The embodiments may be combined as appropriate. For example, the spring portion SPa described in the second embodiment may be combined with either the second or third embodiment. The respective structures of the insulating members 11a and 21b described in the modified example of the third embodiment may be combined with either the first or second embodiment. The semiconductor device 1 may include multiple terminals TMU or multiple terminals TML. The number of terminals TMU and TML may be different. The number of signal terminals included in the semiconductor device 1 may be changed as appropriate depending on the design of the semiconductor device 1.

[0085] In this specification, "connection" refers to being electrically connected and does not exclude the presence of another element therebetween. "Electrically connected" may refer to an insulator being interposed between them, as long as it is possible for the two to function in the same way as an electrically connected object. "Planar view" corresponds to, for example, viewing an object in a direction perpendicular to the surface of the base substrate SUB. "Thickness" refers to, for example, the length in a direction perpendicular to the direction in which the wiring extends. The "claw-shaped structure" and "claw portion" can elastically deform when the component 20 is attached to the case 10.

[0086] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0087] 1... semiconductor device, 10... case, 11... insulating member, 12... insulating substrate, 13 to 18... conductor, 20... component, 21... insulating member, 22 to 25... conductor, 111, 112, 213, 214... receiving portion, 113, 114, 211, 212... claw portion, NMU, NML... transistor, DU, DL... diode, L... inductance, TP, TN, TOUT, TGU, TGL, TMU, TML, TMVU, TMVL, TMCU, TMCL... terminal

Claims

1. a case including a semiconductor circuit; a component configured to be attachable to the case, the component including a signal terminal and a wiring electrically connected to the signal terminal; the wiring has a contact portion that comes into contact with an electrode included in the semiconductor circuit when the component is attached to the case, a lead portion having a first portion provided above the contact portion, and a spring portion that is provided between the first portion of the lead portion and the contact portion and has elasticity; the case includes a base substrate and a first insulating member that surrounds a side portion of the semiconductor circuit and is provided on the base substrate; the component has a second insulating member in which the lead portion of the wiring is insert-molded, the first insulating member has a first claw portion and a second claw portion aligned in a long side direction, the second insulating member has a first receiving portion and a second receiving portion provided to correspond to the first claw portion and the second claw portion, respectively; when the component is attached to the case, the first insulating member and the second insulating member come into contact with each other, and the first claw portion and the second claw portion engage with the first receiving portion and the second receiving portion, respectively, thereby fixing the component to the case; The wiring is located between the first claw portion and the second claw portion. Semiconductor device.

2. When the component is attached to the case, the contact portion is pressed against the electrode by a pressure contact force generated by the spring portion. The semiconductor device according to claim 1 .

3. The wiring has a bent shape at the spring portion so as to protrude in a direction parallel to the substrate of the case.

3. The semiconductor device according to claim 1.

4. The wiring has a loop-shaped portion in the spring portion.

3. The semiconductor device according to claim 1.

5. The thickness of the wiring is greater in the lead portion than in the spring portion. The semiconductor device according to claim 1 .

6. the second insulating member has a second portion provided in a plate shape, When the component is attached to the case, the semiconductor circuit is disposed in a space surrounded by the case and the second portion of the first insulating member. The semiconductor device according to claim 1 .

7. the semiconductor circuit includes at least one power semiconductor element; the power semiconductor element is a transistor, the wiring of the signal terminal is connected to the gate electrode of the transistor; The semiconductor device according to claim 1 .

8. The lead portion is bent at two points in a planar direction. The semiconductor device according to claim 1 .

Images