semiconductor devices

Abstract

To improve characteristics of semiconductor devices.SOLUTION: A semiconductor device according to an embodiment includes: a package substrate 7 including a package member 60 and a conductive portion 72; a semiconductor package 1 provided on a first surface of the package substrate 7 inside the package member 60, and connected to the conductive portion 72; a first semiconductor chip 2A provided on the first surface of the package substrate 7 inside the package member 60 and having a first terminal 21A; a second semiconductor chip 2B provided on the first surface of the package substrate 7 inside the package member 60 and having a second terminal 21B; and a connecting component 5 for connecting the first and second terminals 21A, 21B to the conductive portion 72, inside the package member 60.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] To reduce the size and increase the functionality of devices, semiconductor devices with various package structures have been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3439587 specification [Patent Document 2] Japanese Patent Application Publication No. 4-356974 [Patent Document 3] Japanese Patent Application Publication No. 5-110410 Summary of the Invention [Problem to be solved by the invention]

[0004] Improve the characteristics of semiconductor devices. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a package substrate including a package member and a first conductive portion; a semiconductor package provided within the package member on a first surface of the package substrate and connected to the first conductive portion; a first semiconductor chip provided within the package member on the first surface of the package substrate and having a first terminal; and a semiconductor package provided within the package member on the first surface of the package substrate, a first semiconductor chip aligned with the first semiconductor chip in a first direction parallel to a surface of the package substrate; a second semiconductor chip having a second terminal; and a connecting component that connects the first and second terminals to the first conductive portion within the package member. the first conductive portion includes a first portion that is provided between the first semiconductor chip and the second semiconductor chip, is parallel to the surface of the package substrate and aligned with the semiconductor package in a second direction that intersects the first direction, and is connected to the connection component; and a second portion that is continuous with the first portion, is provided between the first portion and the semiconductor package in the second direction, and is connected to the semiconductor package, the second portion having one end that is connected to the first portion and the other end that is connected to the one end of the second portion in the first direction and is adjacent to the first portion via a slit in the second direction. . [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram showing an apparatus including a semiconductor device according to an embodiment. [Figure 2] 1 is a bird's-eye view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 3] FIG. 1 is a plan view showing a structural example of a semiconductor device according to a first embodiment. [Figure 4] FIG. 1 is a plan view showing a structural example of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a structural example of a semiconductor device according to a first embodiment. [Figure 6] FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device according to a first embodiment. [Figure 7] FIG. 10 is a bird's-eye view showing a structural example of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a structural example of a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is a bird's-eye view showing a modified example of the semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a modified example of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to Figures 1 to 10. In the following description, elements having the same functions and configurations will be given the same reference numerals. In addition, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) that are given reference symbols with distinguishing numbers / letters at the end do not need to be distinguished from each other, descriptions (reference symbols) with the numbers / letters at the end omitted are used.

[0008] [Embodiment] (1) First embodiment A semiconductor device according to a first embodiment will be described with reference to FIGS.

[0009] (Configuration example) FIG. 1 is a schematic diagram illustrating an apparatus including a semiconductor device 100 according to this embodiment.

[0010] 1, the semiconductor device 100 of this embodiment is provided in an electric appliance EA. For example, the electric appliance EA is an industrial machine, a power conversion device, an in-vehicle device, a home appliance device, an audio device, a video device, a communication device, or a computer system.

[0011] The semiconductor device 100 is disposed on a module substrate (also called a motherboard or printed wiring board) 900 together with one or more other devices (eg, other semiconductor devices or electronic components) 800, 801.

[0012] The module substrate 900 includes a plurality of wires 91, 92, and 93 and a plurality of terminals 95 and 96. A plurality of wirings 91, 92, 93 are provided on the surface of the module substrate 900 or inside the module substrate 900. Each of the wirings 91, 92, 93 is connected to one or more corresponding terminals of a plurality of terminals (connectors, sockets, or slots) 95, 96, or to devices 100, 800, 801 on the module substrate 900. Each of the terminals 95, 96 is supplied with a corresponding one of various voltages (for example, a power supply voltage or a ground voltage) or signals.

[0013] The semiconductor device 100 is connected to a plurality of wirings 91 and 92 on the module substrate 900. For example, on the module substrate 900, the semiconductor device 100 is connected to a terminal 95 via the wiring 91, and is connected to a semiconductor device 800 (or an electronic component 801) via the wiring 92.

[0014] The semiconductor device 800 includes, for example, a semiconductor integrated circuit or a discrete device. The semiconductor device 800 may be a modularized device including multiple chips and multiple passive elements. The electronic components 801 are passive elements such as capacitors, inductors, resistors, and switches.

[0015] The semiconductor device 800 and the electronic component 801 are connected to the terminals 96 via wiring 93, and are also connected to each other via other wiring.

[0016] FIG. 2 is a schematic bird's-eye view for explaining the structure of the semiconductor device 100 of this embodiment. FIG. 3 is a plan view schematically showing the structure of the front surface (one main surface) side of the semiconductor device 100 of this embodiment. FIG. 4 is a plan view schematically showing the structure of the back surface (the other main surface) side of the semiconductor device 100 of this embodiment. FIG. 5 is a cross-sectional view schematically showing the cross-sectional structure of the semiconductor device 100 of this embodiment. FIG. 5 shows a cross section along line VV in FIG. 3. FIG. 6 is a circuit diagram for explaining the circuit configuration of the semiconductor device 100 of this embodiment.

[0017] 2 to 5, the semiconductor device 100 of this embodiment includes one semiconductor package (also called a package device) 1 and two semiconductor chips 2 (2A, 2B). The semiconductor device 100 of this embodiment is a surface-mount device (SMD).

[0018] One semiconductor package 1 and semiconductor chips 2A, 2B are provided on a package substrate 7. The semiconductor package 1 and semiconductor chips 2A, 2B are covered with a package material (also called insulating resin, sealing resin, or molding resin) 60 on the package substrate 7. In FIG. 2, the package material 60 is indicated by a dashed line frame to ensure visibility. The semiconductor device 100 of this embodiment has a package-in-package (PiP) structure for the semiconductor package 1.

[0019] The package substrate 7 includes a substrate member 79, a lead frame 70, a plurality of die pads 71A and 71B, a plurality of electrodes 72, 73, and 74, and a plurality of terminals 75A, 75B, 76, and 77.

[0020] The substrate member 79 is an insulator. For example, the substrate member 79 is an insulating organic material (e.g., polyimide) or an insulating ceramic. The substrate member 79 supports the lead frame 70, the die pads 71A and 71B, the electrodes 72, 73, and 74, and the terminals 75A, 75B, 76, and 77 within the package substrate 7.

[0021] The lead frame 70, the die pads 71A and 71B, the electrodes 72, 73, and 74, and the terminals 75A, 75B, 76, and 77 are separated from one another. The lead frame 70, the die pads 71A and 71B, the electrodes 72, 73, and 74, and the terminals 75A, 75B, 76, and 77 contain copper (Cu).

[0022] The lead frame 70 is disposed in the region between the region where the electrodes 73 and 74 are provided and the region where the electrode 72 is provided. The upper surface of the lead frame 70 is exposed from the substrate member 79 . The lead frame 70 includes a first lead portion 701 and a second lead portion 702. The two lead portions 701 and 702 are one continuous conductor.

[0023] The first lead portion 701 has a rectangular (linear) shape extending in the X direction when viewed from the Z direction. The second lead portion 702 has a rectangular (linear) shape extending in the Y direction when viewed from the Z direction. The lead frame 70 has a T-shape (or a shape similar to a T) when viewed from the Z direction. The X direction is parallel to the surface of the package substrate 7. For example, the X direction is parallel to the direction in which the two semiconductor chips 2A and 2B are lined up. The Y direction is parallel to the surface of the package substrate 7 and intersects (for example, is perpendicular to) the X direction. The Z direction is perpendicular to the surface of the package substrate 7.

[0024] The first lead portion 701 extends from one end of the package substrate 7 in the X direction to the other end thereof. One end of the first lead portion 701 in the X direction is located near one end of the package substrate 7 in the X direction. The other end of the first lead portion 701 in the X direction is located near the other end of the package substrate 7 in the X direction. The first lead portion 701 passes through a region below the semiconductor package 1 in the Z direction. When viewed from the Z direction, the first lead portion 701 partially overlaps the semiconductor package 1. For example, the first lead portion 701 does not come into direct contact with the semiconductor package 1.

[0025] One end of the second lead portion 702 is connected to the first lead portion 701. The second lead portion 702 passes through a lower region of the semiconductor package 1 in the Z direction and extends from the first lead portion 701 toward the connection terminal 13A side of the semiconductor package 1. The second lead portion 702 extends in the Y direction.

[0026] The lead frame 70 is also called a lead portion, a pad, a conductive portion, a wiring, or a connecting member.

[0027] The top surfaces of the two die pads 71 ​​(71A, 71B) are exposed from the substrate member 79. The die pad 71A is separated from the die pad 71B. The die pad 71 functions as a mounting portion for the semiconductor chip 2 and also functions as a connecting member (electrode, pad) for the semiconductor chip 2. For example, the die pads 71 ​​(71A, 71B) are also called a base portion, a mount portion, or a stage.

[0028] The two die pads 71A and 71B are arranged side by side in the X direction with the electrode 72 sandwiched between them. The die pads 71A and 71B are adjacent to the lead portion 701 in the Y direction. For example, the two die pads 71A and 71B are arranged in the package substrate 7 symmetrically with respect to a line that runs along the Y direction and passes through the center of the package substrate 7 as the axis of symmetry.

[0029] The electrode 72 is provided on one end side in the Y direction of the package substrate 7. When viewed from the Z direction, the electrode 72 is aligned with the semiconductor package 1 in the Y direction. The electrode 72 is provided in the region between the die pads 71A and 71B in the X direction. The upper surface of the electrode 72 is exposed from the substrate member 79.

[0030] The electrode 72 includes two portions (also called electrode portions) 720 and 721. The portion 720 has a rectangular planar shape when viewed from the Z direction. The portion 721 has a hook-like planar shape when viewed from the Z direction. The portions 720 and 721 are one continuous conductor.

[0031] The portion 720 is provided between the two die pads 71 ​​in the X direction.

[0032] The portion 721 is adjacent to the lead portion 702 in the X direction. However, the portion 721 (and the portion 720) is separated from the lead portion 702.

[0033] The electrodes 73 and 74 are provided on the other end side in the Y direction of the package substrate 7. The electrodes 73 and 74 face the electrode 72 with the lead frame 70 interposed therebetween.

[0034] The upper surfaces of the electrodes 73 and 74 are exposed from the substrate member 79. The electrodes 73 and 74 have a rectangular planar shape when viewed from the Z direction. Electrode 73 is separated from electrode 74 .

[0035] The electrodes 72, 73, and 74 are also called lead portions, pads, conductive portions, or connection members.

[0036] The spaces between the lead frame 70 , the die pad 71 and the electrodes 72 , 73 , 74 in the direction parallel to the surface of the package substrate 7 may be filled with the package member 60 or the substrate member 79 .

[0037] In this embodiment, terminals (hereinafter referred to as external connection terminals) 75 (75A, 75B), 76, and 77 are provided on the back surface side of the package substrate 7. The external connection terminals 75, 76, and 77 are terminals for connecting the semiconductor device 100 to other devices (or wiring on the module substrate, or terminals of the module substrate). For example, the external connection terminals 75, 76, and 77 are provided in openings in the substrate member 79.

[0038] The external connection terminal 75A is provided at a position overlapping the die pad 71A in the Z direction. The external connection terminal 75B is provided at a position overlapping the die pad 71A in the Z direction.

[0039] The external connection terminal 75 has a rectangular planar shape when viewed from the Z direction. The external connection terminals 75 are exposed from the substrate member 79 on the back surface side of the package substrate 7. The side surfaces of the external connection terminals 75 may be exposed from the side surfaces of the package substrate 7 so that the external connection terminals 75 have a WF (Wetable Flank) structure.

[0040] 5, the external connection terminals 75 are directly connected (contact) to the die pad 71. However, the external connection terminals 75 may be electrically connected to the die pad 71 on the front surface side of the package substrate 7 via contact portions provided in the substrate member 79. The external connection terminals 75 may be a single conductor continuous with the die pad 71.

[0041] The external connection terminals 76 are provided on the back surface side of the package substrate 7 so as to partially overlap the electrodes 73 in the Z direction. 5, the external connection terminals 76 are directly connected (contact) with the electrodes 73. However, the external connection terminals 76 may be electrically connected to the electrodes 73 on the front surface side of the package substrate 7 via contact portions (not shown) provided in the substrate member 79. The external connection terminals 76 may be a single conductor continuous with the electrodes 73.

[0042] The external connection terminals 77 are provided on the back surface side of the package substrate 7 so as to partially overlap the electrodes 74 in the Z direction. 5, the external connection terminals 77 are directly connected (contact) with the electrodes 74. However, the external connection terminals 77 may be electrically connected to the electrodes 74 on the front surface side of the package substrate 7 via contact portions (not shown) provided in the substrate member 79. The external connection terminals 77 may be a single conductor continuous with the electrodes 74.

[0043] The external connection terminals 76 and 77 have a rectangular planar shape when viewed from the Z direction. The external connection terminals 76, 77 are exposed from the substrate member 79 on the back surface side of the package substrate 7. The side surfaces of the external connection terminals 76, 77 may be exposed from the side surfaces of the package substrate 7 so that the external connection terminals 76, 77 have a WF structure.

[0044] The lead frame 70, die pad 71, and electrodes 72, 73, and 74 on the front side of the package substrate 7 may be called front electrodes (or front pads), and the external connection terminals 75, 76, and 77 on the back side of the package substrate 7 may be called back electrodes (or back pads).

[0045] The semiconductor package 1 is provided on the surface of a package substrate 7. The semiconductor package 1 is disposed above a lead frame 70 in the Z direction. The semiconductor package 1 is disposed in a region between two semiconductor chips 2A and 2B aligned in the X direction. A certain portion of the semiconductor package 1 is sandwiched between the two semiconductor chips 2A and 2B in the X direction. For example, the semiconductor package 1 is disposed in a central region of the package substrate 7.

[0046] The semiconductor package 1 includes a first circuit unit 10 and a second circuit unit 11 in a package member 19. For example, the package member 19 is an insulator including a light-shielding layer.

[0047] The semiconductor package 1 has four connection terminals (also called connection nodes or lead portions) 13A, 13B, 13C, and 13D connected to the circuit portions 10 and 11. The connection terminals 13A and 13B are provided at one end of the semiconductor package 1 in the Y direction. The connection terminals 13C and 13D are provided at the other end of the semiconductor package 1 in the Y direction.

[0048] The connection terminal 13A is connected to the second lead portion 702 of the lead frame 70 via a conductive member (not shown), such as a conductive paste or solder. The connection terminal 13B is connected to the portion 721 of the electrode 72 via a conductive member. The connection terminal 13C is connected to the electrode 73 via a conductive member. The connection terminal 13D is connected to the electrode 74 via a conductive member.

[0049] Here, the dimension W2 of the second lead portion 702 in the width direction (X direction) is smaller than the dimension W1 of the first lead portion 701 in the width direction (Y direction). In this way, the size of the portion 702 of the lead frame 70 connected to the connection terminal 13A is reduced. This makes it possible to suppress the spread of the conductive material (solder or conductive paste) due to wetting of the conductive material in this embodiment. As a result, short circuits between the connection portions (for example, a short circuit between the connection terminal 13A and the electrode 72, or a short circuit between the connection terminal 13A and the die pad 71B) caused by the spread of the conductive material are prevented. Accordingly, the distance between the connection portions can be reduced, and the area of ​​the package substrate 7 can be reduced.

[0050] Furthermore, the portion 721 of the electrode 72 that is connected to the connection terminal 13B has a hook-like shape. This forms a slit in a portion between the portion 721 and the portion 720. This makes it possible to suppress the conductive material from spreading due to wetting. As a result, short circuits between terminals (for example, short circuits between the connection terminal 13B and the die pad 71B) caused by the spreading of the conductive material are prevented.

[0051] The semiconductor chip 2A is provided on a die pad 71A on the surface of the package substrate 7. The semiconductor chip 2B is provided on a die pad 71B on the surface of the package substrate 7.

[0052] The two semiconductor chips 2A and 2B partially sandwich the semiconductor package 1 in the X direction. For example, the semiconductor chips 2A and 2B are arranged on the surface of the package substrate 7 in a layout symmetrical between the left and right sides, with a line AX passing through the center of the semiconductor package 1 in the XY plane (a line passing through the center of the package substrate 7 in the XY plane) as the axis of symmetry. The line AX as the axis of symmetry is along the Y direction.

[0053] For example, the semiconductor chip 2A is provided in a region between the line AX and one end of the package substrate 7 in the X direction, surrounded by the lead frame 70 and the electrodes 72. For example, the semiconductor chip 2B is provided in a region between the line AX and the other end of the package substrate 7 in the X direction, surrounded by the lead frame 70 and the electrodes 72.

[0054] For example, the semiconductor chips 2A and 2B are provided in the region between the lead portion 701 of the lead frame 70 and one end of the package substrate 7 in the Y direction (the end on the side where the electrodes 72 are provided).

[0055] In semiconductor chips 2A and 2B having a symmetrical layout, the distance Da between the line AX and a line along the Y direction passing through the center of semiconductor chip 2A is substantially equal to the distance Db between the line AX and a line along the Y direction passing through the center of semiconductor chip 2B.

[0056] In semiconductor chips 2A and 2B having a symmetrical layout, the distance Dc between the end of semiconductor chip 2A and the end of package substrate 7 in the Y direction is substantially equal to the distance Dd between the end of semiconductor chip 2B and the end of package substrate 7 in the Y direction.

[0057] The semiconductor chips 2A and 2B are bare chips (bare dies) of semiconductor elements. The semiconductor chips 2A and 2B are sealed on the package substrate 7 by a package member 60. The size of the semiconductor chips 2A and 2B is smaller than the size of the semiconductor package 1. For example, the dimensions (thickness, height) of the semiconductor chips 2A and 2B in the Z direction are smaller than the dimensions of the semiconductor package 1 in the Z direction.

[0058] The semiconductor chip 2A has a chip component 25A including an element portion 200A and a wiring layer (e.g., a multi-layer wiring structure). The semiconductor chip 2A has a plurality of pads (also called connection terminals, connection nodes, or electrodes) 20A, 21A, and 23A within the chip component 25A. The pads 20A, 21A, and 23A are connected to the element portion 200A within the chip component 25A. Elements are formed on a semiconductor substrate within the element portion 200A.

[0059] Pads 20A and 21A are provided on the upper surface of chip component 25A. Pad 23A is provided on the lower surface of chip component 25A. The lower surface of chip component 25A is the surface on the die pad 71A side. The upper surface of chip component 25A faces the lower surface of chip component 25A in the Z direction.

[0060] The pad 20A is connected by a bonding wire 80A to a lead portion 701 of the lead frame 70. For example, the pad 20A is connected to a portion of the lead portion 701 on one end side in the X direction.

[0061] The pad 21A is connected to a portion 720 of the electrode 72 by a connecting part (hereinafter referred to as a connector) 5. In this way, the pad 21A is electrically connected to the semiconductor package 1 via the connector 5 and the electrode 72.

[0062] The pad 23A is connected to the die pad 71A via a conductive member 69A such as solder or conductive paste, thereby connecting the pad 23A to the external connection terminal 75A via the die pad 71A.

[0063] The semiconductor chip 2B has a chip component 25B including an element portion 200B (and a wiring layer). The semiconductor chip 2B has a plurality of pads (also called connection nodes, connection terminals, or electrodes) 20B, 21B, and 23B within the chip component 25B. The pads 20B, 21B, and 23B are connected to the element portion 200B within the chip component 25B. Elements are formed on a semiconductor substrate within the element portion 200B.

[0064] Pads 20B and 21B are provided on the upper surface of chip component 25B. Pad 23B is provided on the lower surface of chip component 25B. The lower surface of chip component 25B is the surface on the die pad 71B side. The upper surface of chip component 25B faces the lower surface of chip component 25B in the Z direction.

[0065] The pad 20B is connected to the lead portion 701 of the lead frame 70 by a bonding wire 80B in common with the pad 20A. For example, the pad 20B is connected to the other end of the lead portion 701 in the X direction.

[0066] The pad 21B is connected to the portion 720 of the electrode 72 in common with the pad 21A by the connector 5. As a result, the pad 21B is electrically connected to the semiconductor package 1 via the connector 5 and the electrode 72.

[0067] The pad 23B is connected to the die pad 71B via the conductive member 69B, thereby connecting the pad 23B to the external connection terminal 75B via the die pad 71B.

[0068] For example, the semiconductor device 100 of this embodiment is a photorelay.

[0069] In this case, the semiconductor package 1 is a photocoupler (optical coupling device). The photocoupler includes an optically coupled isolation circuit.

[0070] Each semiconductor chip 2 is a semiconductor element. For example, the semiconductor chip 2 is a field effect transistor. As a more specific example, the semiconductor chip 2 is a MOS transistor (for example, a power MOS transistor).

[0071] The semiconductor package 1 and the two semiconductor chips 2 are electrically connected to each other via various connecting members 5, 70, and 72.

[0072] As shown in FIG. 6, the photocoupler 1 includes a light-emitting element 10 and a light-receiving element 11 as components of an optically coupled insulating circuit.

[0073] The light emitting element 10 is, for example, an LED (Light Emitting Diode). One node (e.g., cathode) of the light-emitting element 10 is connected to the connection terminal 13C. The other node (e.g., anode) of the light-emitting element is connected to the connection terminal 13D. The connection terminals 13C and 13D are input terminals of the photocoupler 1. An input voltage for controlling the photorelay 100 is applied to the connection terminals 13C and 13D via the electrodes 73 and 74 of the package substrate 7 and the external connection terminals 76 and 77.

[0074] The light receiving element 11 is, for example, a photodiode array. The light receiving element 11 includes, for example, several to several tens of photodiodes 110 connected in series. The light receiving element 11 may also be a phototransistor.

[0075] One node (for example, a cathode) of the light receiving element 11 is connected to the connection terminal 13B. The other node (for example, an anode) of the light receiving element 11 is connected to the connection terminal 13A. The connection terminals 13A and 13B are output terminals of the photocoupler 1.

[0076] The MOS transistors 2A and 2B are, for example, enhancement-type n-channel MOS transistors. The MOS transistors 2A and 2B are used to control the transmission of signals from the photorelay 100. The signals transmitted by the photorelay 100 may be DC signals or AC signals.

[0077] The gate (G) of the MOS transistor 2A is connected to the pad 20A. The source (S) of the MOS transistor 2A is connected to the pad 21A. The drain (D) of the MOS transistor 2A is connected to the pad 23A.

[0078] The gate (G) of the MOS transistor 2B is connected to the pad 20B. The source (S) of the MOS transistor 2B is connected to the pad 21B. The drain (D) of the MOS transistor 2B is connected to the pad 23B.

[0079] The gate of the MOS transistor 2A and the gate of the MOS transistor 2B are commonly connected to the anode 13A of the light receiving element 11 via a bonding wire 80 and a lead frame 70.

[0080] The source of the MOS transistor 2A and the source of the MOS transistor 2B are commonly connected to the cathode 13B of the light receiving element 11 via the connector 5 and the electrode 72.

[0081] The drain of the MOS transistor 2A is connected to an external connection terminal 75A via a die pad 71 A. The drain of the MOS transistor 2B is connected to an external connection terminal 75B via a die pad 71B.

[0082] The external connection terminals 76 and 77 serve as input terminals of the photorelay serving as the semiconductor device 100 of this embodiment. The external connection terminals 75A and 75B serve as output terminals of the photorelay serving as the semiconductor device 100 of this embodiment.

[0083] In the photocoupler 1, the light emitting element 10 outputs light in accordance with the voltage applied to the external connection terminals 76 and 77. In this way, the light emitting element 10 converts an electrical signal into an optical signal.

[0084] The light receiving element 11 receives an optical signal from the light emitting element 10. The light receiving element 11 generates a voltage of 7V to several tens of volts in accordance with the received optical signal. In this way, the light receiving element 11 converts the optical signal into an electrical signal. The light receiving element 11 supplies the generated voltage to the MOS transistor 2 as the gate voltage of the MOS transistor 2 via the lead frame 70 and the bonding wire 80.

[0085] Each of the MOS transistors 2A and 2B is driven in response to a voltage generated by the light receiving element 11. The MOS transistors 2A and 2B output a current in response to a voltage applied to their gates. Therefore, when the MOS transistors 2A and 2B are in the on state, the photorelay 100 transmits a signal.

[0086] In the photocoupler 1, when the light-emitting element 10 is turned off, the output of voltage from the light-receiving element 11 is stopped. Therefore, the MOS transistors 2A and 2B are turned off. As a result, the output terminals 75A and 75B of the photorelay 100 are electrically non-conductive. Therefore, when the MOS transistors 2A and 2B are turned off, the photorelay 100 does not transmit signals.

[0087] In this manner, the photorelay serving as the semiconductor device 100 of this embodiment operates.

[0088] Returning to FIGS. 2 to 5, the structure of the semiconductor device 100 will be described.

[0089] In this embodiment, the connector 5 connects the pads 21A and 21B (for example, the sources of the MOS transistors 2A and 2B) of the two semiconductor chips 2A and 2B to the electrodes 72 on the package substrate .

[0090] The connector 5 is a plate-shaped conductor and includes, for example, copper. The connector 5 has a concave cross-sectional shape when viewed from the Y direction. The connector 5 includes first, second, third, fourth, and fifth plate portions 50A, 50B, 51, 52A, and 52B. The first to fifth plate portions 50A, 50B, 51, 52A, and 52B are one continuous conductive layer (e.g., a copper plate).

[0091] The first, second, and third plate portions 50A, 50B, and 51 extend in a direction parallel to the surface of the package substrate 7. The position of the third plate portion 51 in the Z direction is lower (toward the package substrate 7) than the positions of the first and second plate portions 50A and 50B in the Z direction. The first and second plate portions 50A and 50B are adjacent to each other in a direction parallel to the surface of the package substrate 7 (for example, the X direction). The position of the third plate portion 51 in the X direction is located at the center of the connector 5.

[0092] The fourth and fifth plate portions 52A, 52B extend in a vertical direction (e.g., a direction perpendicular to) the surface of the package substrate 7. For example, the fourth and fifth plate portions 52A, 52B are inclined at a certain angle in the Z direction. The fourth and fifth plate portions 52A, 52B are adjacent to each other in a direction parallel to the surface of the package substrate 7 (e.g., the X direction).

[0093] The fourth plate portion 52A is provided between the first plate portion 50A and the third plate portion 51. The fifth plate portion 52B is provided between the second plate portion 50B and the third plate portion 51.

[0094] One end of the first plate portion 50A in the X direction is connected to the pad 21A of the semiconductor chip 2A via a conductive member 67A such as solder or conductive paste. The first plate portion 50A partially (or entirely) overlaps the pad 21A in the Z direction. The top surface of the pad 21A is covered by the first plate portion 50A.

[0095] The other end of the first plate portion 50A in the X direction is connected to one end of the fourth plate portion 52A in the Z direction. The other end of the fourth plate portion 52A in the Z direction is connected to one end of the third plate portion 51 in the X direction. The one end of the third plate portion 51 in the X direction is an end on the semiconductor chip 2A side and an end on the die pad 71A side.

[0096] One end of the second plate portion 50B in the X direction is connected to the pad 21B of the semiconductor chip 2B via a conductive member 67B. The second plate portion 50B partially (or entirely) overlaps with the pad 21B in the Z direction. The upper surface of the pad 21B is covered by the second plate portion 50B.

[0097] The other end of the second plate portion 50B in the X direction is connected to one end of the fifth plate portion 52B in the Z direction. The other end of the fifth plate portion 52B in the Z direction is connected to the other end of the third plate portion 51 in the X direction. The other end of the third plate portion 51 in the X direction is the end on the semiconductor chip 2B side and the end on the die pad 71B side.

[0098] The third plate portion 51 is connected to the electrode 72 via the conductive member 68. The third plate portion overlaps with a portion 720 of the electrode 72 in the Z direction.

[0099] The volume and cross-sectional area of ​​the plate-shaped connector 5 in the width direction (Y direction) of the connector are larger than the volume and cross-sectional area of ​​the bonding wire.

[0100] Therefore, in the semiconductor device 100 of this embodiment, the connector 5 allows a current having a relatively large current value to flow between the semiconductor package 1 and the semiconductor chip 2.

[0101] The semiconductor device 100 of this embodiment is not limited to a photorelay. The semiconductor package 1 is not limited to a photocoupler. For example, the semiconductor package 1 may be a discrete device such as a transistor, or a semiconductor circuit (for example, an integrated circuit). The semiconductor elements of the semiconductor chip 2 are not limited to field effect transistors. For example, the semiconductor chip 2 may include bipolar transistors or IGBTs (Insulated Gate Bipolar Transistors). The semiconductor chip 2 may also be a semiconductor circuit.

[0102] (summary) In the semiconductor device 100 of this embodiment, a semiconductor package 1 and a plurality of semiconductor chips 2 are provided on a package substrate 7. The semiconductor package 1 and the plurality of semiconductor chips 2 are covered with a package material (resin) 60 on a package substrate 7.

[0103] Thus, in this embodiment, the semiconductor package 1 including the optical device is doubly covered by the package member 19 and another package member 60 . On the other hand, the semiconductor chip 2 is a bare chip and is covered only by the package member 60 on the package substrate 7.

[0104] Therefore, in this embodiment, the encapsulated device 1 and the unencapsulated device 2 are provided on the same package substrate 7. This allows the semiconductor device 100 of this embodiment to alleviate restrictions on the material of the package member 60 that seals the devices 1 and 2 on the package substrate 7 when the devices 1 and 2 are sealed. Therefore, the semiconductor device 100 of this embodiment can relatively easily achieve a double mold structure.

[0105] Furthermore, in this embodiment, the use of an unpackaged bare chip (semiconductor chip 2) can prevent a decrease in the space utilization rate within the semiconductor device 100. As a result, the semiconductor device 100 of this embodiment has a high degree of freedom in package structure. Therefore, the semiconductor device 100 of this embodiment can contribute to the miniaturization of semiconductor devices.

[0106] When the semiconductor elements constituting the semiconductor device 100 are mounted in the form of semiconductor chips on a package substrate 7 of a certain area as in this embodiment, the size of the semiconductor elements can be made larger than when the semiconductor elements are mounted in a package on the package substrate 7 of the same area. This allows the on-resistance of the semiconductor device 100 of this embodiment to be reduced.

[0107] In this embodiment, the external connection terminals 75, 76, and 77 of the package substrate 7 are provided on the back surface side of the package substrate 7. This allows the semiconductor device 100 of this embodiment to reduce the mounting area of ​​the semiconductor device 100 on the module substrate 900.

[0108] In this embodiment, the package substrate 7 includes a lead frame 70. The lead frame 70 has a predetermined shape (wiring pattern) and is provided within the package substrate 7 as a conductive portion (wiring) of the package substrate 7. As a result, the semiconductor device 100 of this embodiment can simplify the connection between the conductive portion of the package substrate 7 and the devices 1 and 2 provided on the package substrate 7.

[0109] In this embodiment, the two semiconductor chips 2A and 2B are arranged on the package substrate 7 in a layout that is symmetrical with respect to the semiconductor package 1. This allows the semiconductor device 100 of this embodiment to supply signal voltages from the semiconductor package 1 substantially equally to the two semiconductor chips 2A and 2B. As a result, the semiconductor device 100 of this embodiment can stabilize its operation.

[0110] Furthermore, the semiconductor device 100 of this embodiment can contribute to miniaturization of the semiconductor device 100 (for example, reduction in area) due to the bilaterally symmetrical layout of the two semiconductor chips 2A and 2B on the package substrate 7.

[0111] In this embodiment, a plate-shaped connecting component (connector) 5 electrically connects multiple semiconductor chips 2 to electrodes 72 of a package substrate 7. By increasing the volume and cross-sectional area of ​​the connecting component 5, the current flowing between the semiconductor chip 2 and the semiconductor package 1 via the connecting component 5 (and the electrodes 72) can be increased. As a result, the semiconductor device 100 of this embodiment can reduce the on-resistance of the semiconductor chip 2 and the semiconductor device 100. The semiconductor device 100 of this embodiment can increase the current output from the semiconductor device 100.

[0112] Furthermore, the surface area of ​​the connecting component 5 through which a large current flows is larger than the surface area of ​​the bonding wire. As a result, in the semiconductor device 100 of this embodiment, the heat dissipation characteristics of the semiconductor chip 2 and the semiconductor device 100 are improved.

[0113] In this embodiment, by connecting the semiconductor chip 2 and the package substrate 7 with the connecting parts 5, the process of mounting components on the package substrate 7 can be simplified.

[0114] According to this embodiment, the use of the connection parts 5 (and the lead frame 70) improves the acceptability and tolerance for misalignment of the semiconductor package 1 and the semiconductor chip 2 on the package substrate 7.

[0115] The semiconductor device 100 of this embodiment can improve the degree of freedom in mounting the semiconductor package 1 and the semiconductor chip 2 on the package substrate 7 in the assembly process of the semiconductor device 100 (for example, adjustment of the mounting order).

[0116] When the connecting part 5 is formed of a plate-shaped conductor so as to have a concave cross-sectional structure as in this embodiment, the manufacturing cost of the semiconductor device 100 can be reduced.

[0117] As described above, the semiconductor device 100 of this embodiment has improved characteristics.

[0118] (2) Second embodiment A semiconductor device according to a second embodiment will be described with reference to FIGS.

[0119] Fig. 7 is a schematic bird's-eye view for explaining the structure of the semiconductor device 100 of this embodiment. Fig. 8 is a cross-sectional view that schematically shows the cross-sectional structure of the semiconductor device 100 of this embodiment.

[0120] As shown in FIGS. 7 and 8, in the semiconductor device 100 of this embodiment, the structure of a connector (connecting part) 5A is different from the structure of the connector 5 of the semiconductor device 100 of the first embodiment.

[0121] The connector 5A includes a first portion 55 and a second portion 56. The first portion 55 is a single conductor that is continuous with the second portion 56. The connector 5A includes copper.

[0122] The first portion 55 extends along the XY plane. The first portion 55 spans the two semiconductor chips 2A and 2B. The first portion 55 is connected to the pads 21A and 21B of the semiconductor chips 2A and 2B, respectively, by conductive members 67A and 67B such as solder or conductive paste.

[0123] The second portion 56 is provided between the first portion 55 and the electrode 72. The second portion 56 is connected to the electrode 72 by a conductive member 68.

[0124] The connector 5A has a T-shaped cross section when viewed from the Y direction.

[0125] In this embodiment, the connector 5A can ensure a larger volume. Due to the increased volume of the connector 5A, the heat dissipation characteristics of the connector 5A are improved.

[0126] Furthermore, the increase in the volume (cross-sectional area) of the connector 5A increases the current flowing between the semiconductor chip 2 and the electrode 72. As a result, the semiconductor device 100 of this embodiment can reduce the on-resistance.

[0127] Therefore, the semiconductor device 100 of this embodiment has improved characteristics.

[0128] (3) Variations A modified example of the semiconductor device of the embodiment will be described with reference to FIGS.

[0129] Fig. 9 is a schematic bird's-eye view for explaining an example of a modified example of the semiconductor device 100 of the embodiment. Fig. 10 is a cross-sectional view for explaining an example of a modified example of the semiconductor device 100 of the present embodiment.

[0130] As shown in FIGS. 9 and 10, in the semiconductor device 100 of this modified example, the semiconductor chips 2A and 2B are connected to the electrodes 72 of the package substrate 7 by bonding wires 89 (89A and 89B).

[0131] The pads 21A of the semiconductor chip 2A are connected to the electrodes 72 via a plurality of bonding wires 89A. The plurality of bonding wires 89A are connected between the pads 21A and the electrodes 72 in parallel.

[0132] The pad 21B of the semiconductor chip 2B is connected to the electrode 72 via a plurality of bonding wires 89B. The plurality of bonding wires 89B are connected between the pad 21B and the electrode 72 in parallel.

[0133] A plurality of bonding wires 89 are bonded to the pads 21 and the electrodes 72 by the same wire bonding process as that used to connect the pads 20 and the lead frame 70 .

[0134] The pads 20 of the semiconductor chip 2 may be connected to the lead frame 70 using a plate-shaped connecting component (connector) instead of the bonding wires 80.

[0135] (4) Other In the embodiment, an example is shown in which the semiconductor device 100 includes an optical coupling device and a plurality of semiconductor elements. However, as long as the semiconductor device 100 of the embodiment has a structure including a semiconductor package 1 and a plurality of semiconductor chips 2, the device type of the semiconductor package 1 and the device type of the semiconductor chip 2 are not limited.

[0136] The number of semiconductor packages 1 included in the semiconductor device 100 of the embodiment may be two or more. The number of semiconductor chips 2 included in the semiconductor device 100 of the embodiment may be three or more. In the semiconductor device 100 of the embodiment, a semiconductor package 1 and a semiconductor chip 2 are provided on the front surface side of a package substrate 7. However, a semiconductor package, a semiconductor chip, and various conductive parts may be provided on both the front and back surfaces of the package substrate 7.

[0137] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0138] 100: semiconductor device, 1: semiconductor package, 2A, 2B: semiconductor chip, 20A, 20B, 21A, 21B, 23A, 23B: pad, 5: connecting component, 7: package substrate, 70: lead frame, 71A, 71B: die pad, 72, 73, 74: electrode, 75A, 75B, 77, 78: external connection terminal.

Claims

1. a package substrate including a package member and a first conductive portion; a semiconductor package provided on a first surface of the package substrate within the package member and connected to the first conductive portion; a first semiconductor chip provided on the first surface of the package substrate within the package member and having a first terminal; a second semiconductor chip provided on the first surface of the package substrate within the package member, aligned with the first semiconductor chip in a first direction parallel to a surface of the package substrate, and having a second terminal; a connection part that connects the first and second terminals to the first conductive part within the package member; Equipped with The first conductive portion a first portion provided between the first semiconductor chip and the second semiconductor chip, aligned with the semiconductor package in a second direction parallel to the surface of the package substrate and intersecting the first direction, and connected to the connection component; a second portion continuous with the first portion, provided between the first portion and the semiconductor package in the second direction, and connected to the semiconductor package; Including, The second portion is one end connected to the first portion; the other end connected to the one end of the second portion in the first direction and adjacent to the first portion via a slit in the second direction; having Semiconductor devices.

2. The connecting part is a third portion provided on the first terminal; a fourth portion provided on the second terminal; a fifth portion provided on the first conductive portion; a sixth portion provided between one end of the third portion and one end of the fifth portion; a seventh portion provided between one end of the fourth portion and the other end of the fifth portion; Contains The semiconductor device of claim 1 .

3. The connecting part is an eighth portion extending in the first direction and spanning the first terminal and the second terminal; a ninth portion provided between the first conductive portion and the eighth portion; Contains The semiconductor device of claim 1 .

4. The package substrate is a second conductive portion including a first lead portion and a second lead portion continuous with the first lead portion; further comprising the first lead portion extends from a first end side of the package substrate toward a second end side of the package substrate in the first direction, passing below the semiconductor package in a third direction perpendicular to the first surface; the second lead portion extends from the first lead portion toward the first conductive portion in the second direction, passing below the semiconductor package in the third direction; A semiconductor device according to any one of claims 1 to 3.

5. the first semiconductor chip has a third terminal; the second semiconductor chip has a fourth terminal; the third terminal is connected to the first lead portion via a first wire; the fourth terminal is connected to the first lead portion via a second wire; The semiconductor device of claim 4 .

6. The package substrate is a first die pad on which the first semiconductor chip is disposed; a second die pad on which the second semiconductor chip is disposed; a third conductive portion connected to a fifth terminal of the semiconductor package; a fourth conductive portion connected to a sixth terminal of the semiconductor package; a first connection terminal provided on a second surface of the package substrate facing the first surface in a third direction perpendicular to the first surface, overlapping the first die pad in the third direction, and connected to the first die pad; a second connection terminal provided on the second surface side, overlapping with the second die pad in the third direction, and connected to the second die pad; a third connection terminal provided on the second surface side, overlapping with the third conductive portion in the third direction, and connected to the third conductive portion; a fourth connection terminal provided on the second surface side, overlapping with the fourth conductive portion in the third direction, and connected to the fourth conductive portion; further comprising: A semiconductor device according to any one of claims 1 to 4.

7. the semiconductor package is disposed in a region between the first semiconductor chip and the second semiconductor chip; the first and second semiconductor chips are arranged on the package substrate symmetrically with respect to a line passing through the center of the semiconductor package. A semiconductor device according to any one of claims 1 to 6.

8. the semiconductor package includes an optical coupling device; each of the first and second semiconductor chips includes a transistor; A semiconductor device according to any one of claims 1 to 7.

9. A package substrate including a first package member and a first conductive portion; a semiconductor package provided on a first surface of the package substrate within the first package member, including a circuit covered with a second package member different from the first package member, and connected to the first conductive portion; a first semiconductor chip provided on the first surface of the package substrate in the first package member, the first semiconductor chip having a first terminal; a second semiconductor chip provided on the first surface of the package substrate within the first package member, the second semiconductor chip having a second terminal; a connecting component including a plate-shaped conductor that spans the first and second semiconductor chips within the package member and connects the first and second terminals to the first conductive portion; Equipped with the first semiconductor chip is aligned with the second semiconductor chip in a first direction parallel to the first surface; the semiconductor package is disposed in a region between the first semiconductor chip and the second semiconductor chip; the first and second semiconductor chips are arranged on the package substrate symmetrically with respect to a line passing through the center of the semiconductor package. Semiconductor devices.

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