Semiconductor Devices

Abstract

To provide a semiconductor device which can suppress leakage current between wiring and a connection electrode connected to a floating node.SOLUTION: A semiconductor device includes a first insulator, a first conductor over the first insulator, a second conductor over the first insulator, and a second insulator over the first insulator, the first conductor, and the second conductor. The first conductor and the second conductor contain a metal A (one kind or a plurality of kinds of aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, magnesium, beryllium, indium, and ruthenium). The metal A is detected in an interface between the first insulator and the second insulator by an energy dispersive X-ray spectroscopy (EDX). At least, the second insulator includes a groove exposing the first insulator, between the first conductor and the second conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device. .

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter It is related to.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The present invention is applicable to display devices (liquid crystal display devices, light-emitting display devices, etc.), power generation devices, and the like. devices (including thin-film solar cells, organic thin-film solar cells, etc.), projection devices, lighting devices, electro-optical devices, A power storage device, an imaging device, an electronic device, and the like can be said to include a semiconductor device. [Background technology]

[0004] In recent years, a technique for manufacturing an integrated circuit in which a layer provided with a transistor and a layer provided with a capacitor are stacked has been developed. Transistors and capacitors are fabricated using plugs formed across wiring and layers. It is driven by electrically connecting it via

[0005] For example, in the same layer as the connection electrode connected to the floating node, Wiring to which different potentials are applied may be formed. When electrodes and wiring are formed, residues of the conductor may remain on the insulator. Depending on the material, the connection electrode connected to the floating node and the wiring formed on the same layer There is a possibility that a leak current occurs between the wiring and the Even when other wirings are formed in the same layer, the residues are not present in the area between the wirings. When a potential is applied to a wiring, the potential applied to other wiring may interfere with the potential. There is.

[0006] In recent years, transistors using oxide semiconductors (typically In-Ga-Zn oxide) have become The development of oxide semiconductors is becoming more active, and they are also used in integrated circuits. As far back as 1988, the use of crystalline In-Ga-Zn oxide in semiconductor devices was disclosed. In 1995, a transistor using an oxide semiconductor was developed (see Patent Document 1). A transistor has been invented and its electrical characteristics have been disclosed (see Patent Document 2). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 63-239117 [Patent Document 2] Special table Hei 11-505377 Summary of the Invention [Problem to be solved by the invention]

[0008] One embodiment of the present invention is to provide a semiconductor device having a memory cell and a wiring which form a path through which leakage current flows. One of the objects is to block the interference and improve the retention characteristics of the memory.

[0009] One embodiment of the present invention is a method for reducing leakage current between a connection electrode connected to a floating node and a wiring. It is an object of the present invention to provide a semiconductor device capable of suppressing current. One of the objects of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long time. One embodiment of the present invention is a semiconductor device capable of suppressing leakage current between wirings. One of the goals is to provide a place for

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising: a first insulator; a first conductor on the first insulator; and a second conductor on the first insulator. a second conductor, a first insulator, the first conductor, and a second insulator on the second conductor; The first conductor and the second conductor are made of metal A (aluminum, copper, tungsten, etc.). Stainless steel, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, magnesium, and beryl one or more of sodium, indium, and ruthenium, At the interface between the first insulator and the second insulator, metal A is observed by energy dispersive X-ray spectroscopy (EDX ) method, and the second insulator is a first insulator between the first conductor and the second conductor. The semiconductor device has a groove that exposes an insulator.

[0012] In the above, the first conductor includes a first transistor and a capacitor. One of the source or drain of the transistor is electrically connected to one of the electrodes of the capacitor element. In the above, it is preferable that the channel formation region of the first transistor is made of gold. Preferably, the metal oxide is formed.

[0013] Furthermore, one aspect of the present invention is a semiconductor device including a first insulator, a first conductor on the first insulator, and a first insulating film. a second conductor on the insulator, and a second conductor on the first insulator, the first conductor, and the second conductor; The capacitor includes an insulator and a capacitance element, and the first conductor and the second conductor are made of a metal A (aluminum). Aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, One or more of magnesium, beryllium, indium, and ruthenium the first conductor has a function of one of the electrodes of the capacitor element, and the first insulator; Metal A is detected at the interface with the second insulator by the EDX method, and the second insulator is and a second conductor, and a groove exposing the first insulator is provided between the first conductor and the second conductor. .

[0014] In the above, a first transistor is provided, and the first conductor is a source of the first transistor. It is preferable that the first electrode is electrically connected to either the source or the drain. The channel formation region of the transistor is preferably formed in a metal oxide.

[0015] In the above, a second transistor is provided, and the first conductor is connected to the second transistor. It is preferable that the gate of the transistor is electrically connected to the gate of the transistor.

[0016] In the above, the first conductor and the second conductor are made of at least Al and Cu. It is preferable to have at least one.

[0017] In one embodiment of the present invention, a first conductor is formed on a first insulator, and the first conductor is Metal A (aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel , molybdenum, magnesium, beryllium, indium, and one of the following: ruthenium a resist mask patterned on the first conductor, The first conductor is formed by etching using a resist mask, and the second conductor is formed by etching the first conductor. After forming the second conductor and the third conductor, impurities are added to the first insulator. A resist mask is removed by a material removal process, and the first insulator, the second conductor, and the third A second insulator is formed on the conductor, and a first insulator is formed between the second conductor and the third conductor. This is a method for manufacturing a semiconductor device, in which a groove that exposes an insulating material is formed in a second insulating material.

[0018] In the above, the impurity removal step preferably includes a cleaning treatment using pure water. In the above, the first conductor preferably contains at least one of Al and Cu. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a leakage current between a memory cell and a wiring included in a semiconductor device can be reduced. This can block the path and improve memory retention characteristics.

[0020] According to one aspect of the present invention, a leakage current between a connection electrode connected to a floating node and a wiring is It is possible to provide a semiconductor device capable of suppressing the leakage current. Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device capable of suppressing leakage current between wirings can be provided. Can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional schematic views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional schematic views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional schematic views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a transistor used in a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view illustrating a capacitor used in a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a transistor used in a semiconductor device according to one embodiment of the present invention. [Figure 11]1 is a circuit diagram illustrating a circuit of a semiconductor device (memory device) according to one embodiment of the present invention. [Figure 12] 1A and 1B are a cross-sectional view and a top view illustrating a structure of a semiconductor device (memory device) according to one embodiment of the present invention. [Figure 13] 1A and 1B are a cross-sectional view and a top view illustrating a structure of a semiconductor device (memory device) according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a transistor used in a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. [Figure 16] Schematic cross-sectional diagram and cross-sectional STEM image of the evaluation sample. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely diagrammatic representations and are not limited to the shapes or values shown in the drawings. In this case, the same reference numerals are used in common between different drawings to designate the same parts or parts having similar functions. In addition, when referring to the same function, the hatch pattern is used. In some cases, the same symbol is not attached.

[0025] In addition, in order to make the invention easier to understand, especially in the top view (also called "plan view"), In some cases, the description of some components may be omitted. In addition, some hidden lines may be omitted. There is a match.

[0026] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. Therefore, for example, "first" may be changed to "second" " or "third" etc. as appropriate. The ordinal numbers used to identify an aspect of the present invention may not match. There is a match.

[0027] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in explaining the relationship with reference to the drawings. The values change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0028] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) A channel forming region is provided between the source and the drain through the channel forming region. In this specification and the like, the channel formation region is , refers to the region through which current mainly flows.

[0029] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably. .

[0030] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a composition. The content of oxygen is preferably 55 atomic % or more and 65 atomic % or less, and nitrogen is preferably 100 atomic % or more. 1 atomic % to 20 atomic %; silicon is 25 atomic % to 35 atomic %; hydrogen is 0.1 The concentration range of silicon dioxide is 10 atomic % or more. The composition of the material is one in which the nitrogen content is higher than the oxygen content, and preferably the nitrogen content is 55 atomic % to 65 atomic %; oxygen 1 atomic % to 20 atomic %; silicon 25 atomic % % or more and 35 atomic % or less, and hydrogen is contained in the concentration range of 0.1 atomic % or more and 10 atomic % or less To say something.

[0031] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0032] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement transistors. The transistors shown in this specification are normally-off type field effect transistors. Unless otherwise specified, the transistors are n-channel transistors. The threshold voltage (also called "Vth") of Make it something large.

[0033] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0034] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0035] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0036] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0037] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0038] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0039] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0040] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0041] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0042] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0043] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0044] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0045] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from permeating. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I get angry.

[0046] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. 1 to 10. For clarity, in FIGS. 1 to 10, the semiconductor The configuration of the device is partially omitted in the drawing.

[0047] <Configuration example of semiconductor device> Part of the structure of a semiconductor device according to one embodiment of the present invention is shown in FIG. 1(A) is a schematic top view of the configuration of the device shown in FIG. 1(B). It should be noted that in the top view of FIG. 1(B) and the like, the groove 250 is not shown in FIG. Therefore, the grooves 250 are shown with a hatched pattern.

[0048] In the cross-sectional views of FIG. 1(A), patterned conductors, semiconductors, and insulators are Although some of the edges of the semiconductor device shown in this embodiment are at right angles, The end portion may also be rounded.

[0049] The semiconductor device shown in FIG. 1 includes a substrate 210, an insulator 212, an insulator 213, and a conductor 22. 0, conductor 221, conductor 222, conductor 223, conductor 226, and conductor 22 7, membrane 240a, membrane 240b, and groove 250.

[0050] The semiconductor device shown in FIG. 1 has a conductor 220 on a substrate 210. An insulator 212 is provided on the substrate 210 and the conductor 220 so as to cover the conductor 220. In addition, a conductor 221 is provided on the insulator 212. An insulator 213 is provided on the insulator 212 and the conductor 221 so as to cover them. In addition, the conductor 226 and the conductor 227 are provided in the same layer on the insulator 213. A film 240a is provided on the conductor 226 so as to cover the conductor 226. A film 240b is provided on the conductor 227 so as to cover the conductor 227. A groove 250 is provided in the insulator 213 between 26 and the conductor 227 .

[0051] 1, the insulator 212 and the insulator 220 are connected to each other. The first opening is formed between the first electrode 13 and the conductive material 222. The conductor 220 is electrically connected to the conductor 226 via the conductor 222. The semiconductor device shown in FIG. 2 has a second opening in the insulator 213 to reach the conductor 221. A conductor 223 is provided inside the second opening. 21 is electrically connected to the conductor 226. That is, the conductors 220 and 221 are are electrically connected via conductor 226.

[0052] The conductor 220 and the conductor 221 may be formed in the same layer. The body 221 may be formed in a layer below the conductor 220 .

[0053] For example, the conductor 226 may be a floating node (FN), or The conductor 227 may function as a connection electrode connected to the The wiring is made of metal A with low electrical resistance (metal A is aluminum, Copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, magnesium metal A is a metal material such as sulphur, beryllium, indium, or ruthenium, or It is preferable to use a conductor containing metal A or gold for the conductor 226 or the conductor 227. When a conductor containing Group A is used, after forming the conductor 226 or conductor 227, a cleaning process is performed. During the cleaning process, metal may be removed from the end of the conductor 226 or conductor 227. A small amount of metal A is dissolved, and a residue 230 of metal A (see FIG. 6) is left on the surface of the insulator 213. It may be formed.

[0054] After the conductor 226 or conductor 227 is formed, the conductor 226 or conductor 227 is removed by ashing or a resist remover. When the resist mask is removed, the conductor 226 or the conductor 2 A small amount of metal A melts from the end of 27, and a residue of metal A 23 is left on the surface of the insulator 213. The residue 230 of the metal A may be a conductor 226 or a conductor. In some cases, the conductive material 227 may be formed on the top or side surface thereof.

[0055] The residue 230 of metal A formed on the surface of the insulator 213 was observed by a transmission electron microscope (TEM). This was confirmed by observation using a Transmission Electron Microscope. It is so thin that it is difficult to detect it by energy dispersive X-ray spectroscopy (EDX). Dispersive X-ray spectroscopy (DXS) shows that Metal A is detected. However, the residue 230 of metal A is A leakage current may occur between the conductive layer 226 and the conductive layer 227 formed in the same layer. For example, 10 -21 A(zA), 10 -24 A (yA) is required. In this case, even a small amount of residue 230 of metal A may affect the leakage current. There is a high probability that this will happen.

[0056] Therefore, a film 240 is provided on the conductor 226, the conductor 227, and the insulator 213 (see FIG. 7.) Next, in the region between the conductor 226 and the conductor 227, the film 240 and By providing a groove 250 in the insulator 213, a part of the insulator 213 is exposed. In the specification, the groove 250 is a groove in which at least a part of the film 240 on the insulator 213 is removed. The groove 250 is formed around the conductor 226 when viewed from above, and has a cross section of When viewed from the above, the position of the bottom surface of the groove 250 is the bottom surface of the conductor 226 (the surface in contact with the insulator 213). Lower than the position.

[0057] By forming the groove 250, the surface of the insulator 213 in the region where the groove 250 is formed is The residue 230 of the metal A is removed together with the film 240. The metal A residue 230a can be separated into the metal A residue 230b. , the conductor 226, the conductor 227, and the insulator 213, the film 240 is provided on the groove. When forming 250, the conductor 226, the conductor 227, and the residue 230 of the metal A are This can prevent metal A from dissolving and forming residue of metal A. This suppresses leakage current between the conductor 226 and the conductor 227 via the residue 230 of the metal A. It becomes possible to control it.

[0058] As shown in FIG. 2, the residue 230 of the metal A and the film 240 are partially removed to form an insulating film. In this case, the position of the bottom surface of the groove 250 is the same as the bottom surface (insulation) of the conductor 226. The height is the same as the position of the surface in contact with the edge 213.

[0059] As shown in FIG. 3, a groove 250 is formed around the conductor 226, and a groove 250 is formed around the conductor 227. By using such a configuration, the groove 250a may be formed around the periphery of the conductor 226. It is more efficient to form grooves around all the conductors in the same layer than to form grooves only around the conductors. This allows for greater design freedom.

[0060] Also, as shown in FIG. 4(A), a groove 250b may be formed around the conductor 221. By adopting such a configuration, the conductor 221 and the conductor existing in the same layer as the conductor 221 are It is possible to suppress the leakage current between the semiconductor device and the body (not shown). In this case, a groove 250 is formed around the conductor 226, but instead of the groove 250, the conductor 2 A groove 250a may be formed around the periphery of 27.

[0061] Also, as shown in FIG. 4(B), a groove 250c may be formed around the conductor 220. By adopting such a configuration, the conductor 220 and the conductor existing in the same layer as the conductor 220 can be It is possible to suppress the leakage current between the semiconductor device and the body (not shown). In this case, a groove 250 is formed around the conductor 226, but instead of the groove 250, the conductor 2 A groove 250a may be formed around the periphery of 27.

[0062] Also, for example, the conductor 222, the conductor 223, and the conductor 226 may be treated as one conductor. The damascene or dual damascene method can be used to provide the damascene or dual damascene method. By using a dual damascene method, the conductor 222, the conductor 223, and the conductor 22 Copper can be used as a material for the conductor having the function of 6.

[0063] In the above case, the conductors 222, 223, and 226 have the functions of The conductor 2 is embedded in the insulator 212 and the insulator 213. The conductor 227 may be embedded in the insulator 213 by providing the conductor 227 in the same process. The chemical mechanical polishing (Chemical Mechanical Polishing) method is a dual damascene method in which a conductor is deposited and then polished. The wiring and conductors are polished by the Al Mechanical Polishing (CMP) method. During the CMP process, the conductor other than the insulator 213 is removed. As a conductor having the functions of the conductor 222, the conductor 223, and the conductor 226 on the surface thereof There may be a small amount of copper remaining. 223, and a conductor having the function of the conductor 226 and a conductor 227 formed adjacent thereto. A leakage current may occur between the

[0064] Therefore, the conductors 222, 223, and 226 have the functions of the conductors 222, 223, and 226. A film 240 is provided on the conductor 222, the conductor 223, and the insulator 213. and a film 240 in the region between the conductor having the function of the conductor 226 and the conductor 227; A groove 250 is provided in the insulator 213 to expose a portion of the insulator 213. In this case, the groove 250 is formed so that the conductors 222, 223, and 224 are aligned in a plane perpendicular to the plane of the groove 250 when viewed from above. The groove 250 is formed around the conductor having the function of 6, and when viewed in cross section, the position of the bottom surface of the groove 250 is The upper surface of the conductor (insulator 222), the conductor 223, and the conductor 226 Therefore, the copper residue is lower than the level of the conductor 22. 2, the conductor 223, and the conductor having the function of the conductor 226 and the conductor 227 This makes it possible to suppress the peak current.

[0065] Alternatively, the copper residue and part of the film 240 may be removed to expose the insulator 213. At this time, the position of the lower surface of the groove 250 is such that the functions of the conductors 222, 223, and 226 are The height is the same as the position of the upper surface of the functional conductor (the same plane as the upper surface of the insulator 213).

[0066] <Method for manufacturing semiconductor device> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 5 to 7 show a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1 and 5 to 7, the conductor 226 provided in the same layer is A process of forming a groove 250 between the conductive material 227 and the conductive material 227 will be described.

[0067] First, a substrate 210 is prepared.

[0068] A conductor 220 is formed on the substrate 210. The conductor 220 may have a single layer structure. Alternatively, an insulator or the like may be provided between the substrate 210 and the conductor 220. It doesn't matter if it's a structure.

[0069] Next, the insulator 212 is formed on the conductor 220 so as to cover the conductor 220. The insulator 212 may have a single layer structure or a laminated structure. Sputtering method, Chemical Vapor Deposition (CVD) tion) method, molecular beam epitaxy (MBE) axy method or pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method ) method, etc.

[0070] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0071] The insulator 212 may be formed so that the upper surface thereof is flat. For example, the insulator 212 may be formed as follows: The upper surface of the insulator 212 may be flat when the insulator 212 is formed. After forming the insulator 212, the insulator 212 is formed so as to be parallel to a reference plane such as the rear surface of the substrate. The planarization may be achieved by removing the surface from the top surface. The planarization process includes CMP and dry etching. The upper surface of the body 212 does not have to be flat.

[0072] Next, the conductor 221 is formed on the insulator 212. The conductor 221 has a single-layer structure. Alternatively, a laminated structure may be used.

[0073] Next, the insulator 213 is formed on the conductor 221 so as to cover the conductor 221. The insulator 213 may have a single layer structure or a laminated structure. The insulator that can be used for the insulator 212 can be used. As with the insulator 212, the upper surface may be formed to have flatness.

[0074] Next, a second opening is formed in the insulator 213 so as to reach the conductor 221. Forming a first opening in the insulator 212 and the insulator 213 to reach the insulator 220 Hereinafter, the opening may be referred to as a via hole or a contact hole.

[0075] Here, the first opening and the second opening are via holes in which plugs are provided, and In many cases, the aspect ratio is required. Therefore, the shapes of the first opening and the second opening are For this formation, anisotropic dry etching is preferably used.

[0076] Next, a conductor 223 is formed to fill the second opening. The conductor 222 is formed so as to fit in the conductor 223. The materials of the conductor 222 and the conductor 223 may be metal materials, alloy materials, or the like. Conductive materials such as metal nitride materials and metal oxide materials can be used in a single layer or in a laminated form. High-melting-point materials such as tungsten and molybdenum are used, which have both heat resistance and electrical conductivity. It is preferable to use tungsten. Alternatively, aluminum or copper It is preferable to form the wiring layer from a low-resistance conductive material such as the above. The line resistance can be reduced.

[0077] The first opening and the second opening may be formed at the same time, or may be formed in separate steps. The conductor 222 and the conductor 223 may be formed at the same time. They may be formed in separate processes.

[0078] Here, the first opening and the second opening are formed in separate steps, and the conductor 222 and the conductor A method for forming the body 223 in a separate process will now be described.

[0079] For example, after forming the insulator 212, a first wire is inserted into the insulator 212 so as to reach the conductor 220. forming an opening to become the second opening, and forming a first conductor in the opening to become the first opening; Next, when forming the conductor 221, a plug or Then, the conductor that will become the plug or the wiring, the insulator 21 2 and the conductor 221. The insulator 213 is formed on the plug or the conductor 221. and a second opening that reaches the conductor 221. Then, the second conductor and the second opening are formed in the opening that will become the first opening. The first conductive material 223 is formed in the first opening and the second opening at the same time. The conductor, which is the plug or wiring, and the second conductor are connected to each other. 222 can be formed.

[0080] Next, the insulator 213, the conductor 222, and the conductor 223 may be subjected to a polishing process. The polishing process may be mechanical polishing, chemical polishing, CMP, or the like.

[0081] A conductor 225 is formed on the insulator 213, the conductor 222, and the conductor 223 (FIG. 5.) The conductor 225 may have a single layer structure or a multilayer structure. The conductor 225 used as the wiring is a metal A having a low electrical resistance (Metal A is , aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum metal materials such as buten, magnesium, beryllium, indium, and ruthenium, Alternatively, it is preferable to use a conductor containing metal A.

[0082] A patterned resist mask is formed on the conductor 225. The resist mask It may be formed by using a lithography method or the like.

[0083] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the exposed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. Dry etching or wet etching or dry etching In addition to the etching process, a wet etching process is performed, or in addition to the etching process, a Dry etching can be performed.

[0084] Next, using a resist mask, one part of the conductor 225 is removed until the top surface of the insulator 213 is exposed. By etching the portions, the conductors 226 and 227 are formed (see FIG. 6). It is preferable to use dry etching for this etching.

[0085] The dry etching equipment is a capacitively coupled plasma (CCP) with parallel plate electrodes. Capacitively Coupled Plasma etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power supplies are applied to the electrodes may also be used. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power supply having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device may be, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0086] After etching, the resist mask is removed. The resist mask is removed by ashing or other methods. Dry etching is performed, or wet etching is performed using a special remover. or wet etching is performed in addition to dry etching, or This can be achieved by performing a dry etching process in addition to the wet etching process.

[0087] By carrying out the above-mentioned dry etching or other treatment, the etching gas or the like The impurities may adhere to or diffuse into the surface or interior of the insulator 213. Examples include fluorine or chlorine.

[0088] A process for removing the above impurities is carried out. For example, a cleaning process is preferably carried out. For example, wet cleaning using cleaning fluid, plasma treatment using plasma, or heat treatment These cleaning methods may be combined as appropriate.

[0089] For wet cleaning, oxalic acid, phosphoric acid, hydrofluoric acid, etc. are diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be used. Washing may also be performed.

[0090] In FIG. 6, the side surfaces of the conductors 226 and 227 are in contact with the upper surface of the insulator 213. However, the semiconductor device shown in this embodiment is not limited to this. For example, the side surfaces of the conductors 226 and 227 are 30° to the top surface of the insulator 213. It may also have a tapered shape inclined at an angle of 0° or more and less than 90°.

[0091] After the conductor 225 is etched to form the conductors 226 and 227, In order to prevent corrosion of the electric conductor 226 and the electric conductor 227, cleaning may be performed. After the process of removing the resist mask, as shown in FIG. 6, the insulator 213, the conductor 226, and Residues 230 of metal A may be formed on the surface of the conductive material 227. Between the conductor 226 serving as a connection electrode and the conductor 227 serving as a wiring, via the residue 230 There is a high probability that leakage current will occur.

[0092] Therefore, as shown in FIG. 7, the insulator 213, the residue 230 of the metal A, the conductor 226, and A film 240 is formed on the conductor 227. For example, an insulator is used as the film 240. Alternatively, a semiconductor or a conductor may be used.

[0093] Next, a part of the surface of the insulator 213 in the area overlapping the groove 250 is removed so as to reach the insulator 213. By removing the metal A residue 230 and the film 240, the groove 2 is 50 is provided so as to surround the conductor 226 (see FIG. 1(B)). By this, the membrane 240 is separated into membranes 240a and 240b. It is preferable to use the same material as the insulator 213 as the material. Therefore, it is preferable to use a material that allows both the insulator 213 and the film 240 to be removed. When the groove 250 is formed, the surface of the film 240 and the insulator 213 in the area overlapping the groove 250 is In addition, the material of the film 240 does not contain the metal A. Alternatively, the film 240 may be made of a material containing metal A. After removing the film 240 in the area overlapping the groove 250, no residue of the metal A is formed. It should be noted that the metal A residue 230 and the film 240 are formed on a part of the surface of the insulator 213. The grooves 250 may be formed in separate steps.

[0094] As a result of the above, the residue 230 of the metal A is separated into the insulator 213, the conductor 226, and the film 240a. The residue 230a of the metal A formed between the insulator 213 and the conductor 227 and the film 24 0b and the residue 230b of metal A formed between the metal A and the residue 230b. The electrical connection between the conductor 226 and the conductor 227 via the residue 230 of metal A is broken. It is possible.

[0095] Through the above steps, a semiconductor device according to one embodiment of the present invention can be manufactured. By having 0, it is possible to suppress the leakage current between the conductor 226 and the conductor 227. It becomes Noh.

[0096] Alternatively, by providing the groove 250, the distance between the conductor 226 and the conductor 227 can be narrowed. Therefore, a semiconductor device that can be miniaturized or highly integrated can be realized.

[0097] <Specific examples of semiconductor devices> A specific example of the structure of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG. do.

[0098] Here, the conductor 220 is a part that constitutes a transistor, and the conductor 221 is a capacitor. A case where it is a part of the element will be described.

[0099] For example, the conductor 220 may be the source (source region or source electrode) of a transistor or The conductor 221 can function as one of the drains (drain region or drain electrode). The conductor 227 can function as one electrode of a capacitor. The conductor 226 is connected to one of the source and drain of the transistor and one of the electrodes of the capacitor. Since the two electrodes are electrically connected, the conductor 226 is sometimes called a connection electrode. The functions of the conductor 221 and the conductor 220 may be interchanged.

[0100] When viewed from above, the groove 250 is provided so as to surround the conductor 226. For example, As shown in FIG. 1B, a groove 250 is provided around the outer edge of the conductor 226. The groove 250 is formed to separate at least the conductor 226 from other conductors formed in the same layer. It is sufficient to provide the conductor 226 between the conductors 226, and it is not necessary to provide the conductor 226 along the outer edge of the conductor 226. The conductor 226 has an outer shape, and the conductor 226 is drawn as if drawing a rectangle inside. The groove 250 may be formed in a square shape regardless of the shape of the conductor 226. A closed shape that has a shape, a polygon other than a square, a circle, or a curve can be done.

[0101] The width of the groove 250 may be appropriately designed depending on the semiconductor device to be manufactured. 6 and the conductor 227, a distance is maintained so that no leakage current occurs. Alternatively, only the film 240a on the conductor 226 may be left, and the film 240b and the film 240c may be left. A part of the surface of the insulator 213 in the area not overlapping with 40a may be removed.

[0102] With the above configuration, the charge (flash) stored in the capacitor of the memory cell included in the semiconductor device can be The voltage input to the Fault Node (FN) can be maintained for a long period of time. In addition, a transistor including an oxide semiconductor, which is characterized by an extremely small off-state current, By providing a floating capacitor in the memory cell, the charge stored in the capacitance element of the memory cell The voltage input to the switching node (FN) can be maintained for a long period of time.

[0103] Therefore, a semiconductor device capable of retaining data for a long period of time can be provided.

[0104] In the configuration of the semiconductor device shown above, one of the conductors 220 and 221 is a transformer. The conductor 220 and the conductor 221 function as either the source or the drain of the transistor. Although an example is shown in which the other electrode functions as one electrode of a capacitor element, the present invention is not limited to this. For example, one of the conductors 220 and 221 may be the source or drain of a transistor. The conductor 220 functions as one of the drain electrodes and one of the electrodes of the capacitor element. In some cases, the other of the conductor 220 and the conductor 221 is not formed. One of the conductive bodies 221 functions as either the source or the drain of the transistor, and the conductive body 2 26 has a function of one electrode of the capacitor element, and the other of the conductor 220 and the conductor 221 It may not be formed.

[0105] In addition, in the configuration example of this embodiment, a semiconductor device having a transistor and a capacitor element This is an example, but not limited to, of a first transistor, a capacitor, and For example, the semiconductor device may include a conductor 220 and a second transistor. One of the bodies 221 functions as either the source or the drain of the first transistor and as a capacitor. The other of the conductor 220 and the conductor 221 functions as a second electrode. In some cases, the conductor 220 and the conductor One of the bodies 221 functions as either the source or the drain of the first transistor. The other of the conductor 220 and the conductor 221 functions as the gate of the second transistor. The electrode 226 may function as one electrode of a capacitor.

[0106] <Transistor configuration example> A structural example of a transistor provided in the semiconductor device described in this embodiment will be described with reference to FIG. This will be used to explain.

[0107] The transistor must have a small leakage current (off-state current) when it is off. By using a transistor with low off-state current as a transistor, A capacitor element electrically connected to either the source or drain of the transistor via a connection electrode. The charge given to one electrode can be maintained for a long period of time. As a transistor, a transistor having an oxide semiconductor in a channel formation region (oxide semiconductor transistor Oxide semiconductor transistors have low off-state current and are silicon-containing. The semiconductor device shown in this embodiment has an advantage that the semiconductor device can be formed by overlapping with a transistor. By using an oxide semiconductor transistor as the transistor, The data retention performance of the semiconductor device shown in FIG.

[0108] FIG. 8A is a top view of a transistor 400a included in the semiconductor device described in this embodiment. FIG. 8(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 8(A). That is, FIG. 8C shows a cross-sectional view of the transistor 400a in the channel length direction. 1A is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 8(A) shows a cross-sectional view in the channel width direction of the semiconductor device. In the top view of FIG. 8(A), some of the semiconductor devices are not shown for clarity. The channel length direction of the transistor is the direction parallel to the substrate. In the semiconductor device, the source (source region or source electrode) and the drain (drain region or The channel width direction refers to the direction in which carriers move between the substrate and the drain electrode. It means a direction perpendicular to the channel length direction in a plane parallel to the plate.

[0109] As shown in FIGS. 8A, 8B, and 8C, the transistor 400a is and an insulator 401 and an insulator 301 disposed so as to be embedded in the insulator 301. The conductor 310 (conductor 310a and conductor 310b) placed on the conductor 310 The insulators 302, 303, and 402 are arranged, and the insulators 302 and 303 are arranged on the insulator 402. oxide 406a disposed on oxide 406a; oxide 406b disposed on oxide 406a; Conductors 416a1 and 416a2 are arranged on 406b at a distance apart. and oxide 406b, conductor 416a1, and oxide 416a2 disposed on the conductor. an insulating material 412 disposed on the oxide 406c; and The conductor 404 (conductor 404) is disposed on the insulator 412 so as to overlap the object 406b. a, conductor 404b, and conductor 404c).

[0110] In addition, the insulator 402, the oxide 406a, the oxide 406b, the oxide 406c, and the conductor 416 a1, the conductor 416a2, the insulator 412, the conductor 404, etc., are disposed on the insulator 410. can be.

[0111] The conductor 310 is provided in an opening formed in the insulator 301. A conductor 310a is formed in contact with the inner wall of the conductor 310a, and a conductor 310b is formed further inside. Here, the height of the upper surfaces of the conductors 310a and 310b and the upper surface of the insulator 301 are The heights of the conductors 310 can be made to be approximately the same. The conductor 310 can function as one of the gate electrodes.

[0112] Here, the conductor 310a is made of a conductive material that is difficult for impurities such as water and hydrogen to permeate. In addition, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. It is preferable to use a single layer or a laminated layer. This prevents impurities such as water and hydrogen from diffusing from the lower layer to the upper layer through the conductor 310. The conductor 310a can be a hydrogen atom, a hydrogen molecule, a water molecule, an oxygen atom, an oxygen molecule, or the like. nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. It is preferable that at least one of the impurities is difficult to permeate. The same applies to the case where the conductive material 310a is difficult to permeate oxygen. By having the function of suppressing oxidation, the conductivity of the conductor 310b can be prevented from decreasing due to oxidation. You can do this.

[0113] The insulator 401 is a barrier that prevents impurities such as water and hydrogen from entering the transistor from the lower layer. The insulator 401 is an insulating material that is difficult for impurities such as water and hydrogen to penetrate. It is preferable to use a conductive material, for example, aluminum oxide. This prevents impurities such as water and hydrogen from diffusing into the upper layer of the insulator 401. The insulator 401 can be a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or the like. At least one of impurities such as nitrogen oxide molecules (N2O, NO, NO2, etc.) and copper atoms is transmitted through the In the following, the insulating material through which impurities are less likely to permeate will be described. The same applies when describing the

[0114] The insulator 401 is made of insulating material that is difficult for oxygen (for example, oxygen atoms, oxygen molecules, etc.) to penetrate. It is preferable to use a material such that oxygen contained in the insulator 402 can diffuse downward. This can effectively supply oxygen to the oxide 406b. It is possible.

[0115] The insulator 303 is made of an insulating material that is difficult for impurities such as water and hydrogen, and oxygen to permeate. It is preferable to use, for example, aluminum oxide, hafnium oxide, etc. As a result, impurities such as water and hydrogen from the layer below the insulator 303 are transported to the layer above the insulator 303. Furthermore, oxygen contained in the insulator 402 can be prevented from diffusing into the lower layer. This can suppress the diffusion of the particles in different directions.

[0116] The insulator 402 is preferably formed using an insulator from which oxygen is released when heated. Specifically, thermal desorption spectroscopy (TDS) The amount of oxygen released, converted to oxygen atoms, was 1.0 × 10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 More than It is preferable to use an oxygen source containing oxygen. The oxygen released by heating is also called "excess oxygen." By providing such an insulator 402 in contact with the oxide 406a, the oxide 406b In addition, the surface temperature of the membrane during the TDS analysis The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. .

[0117] In addition, the concentration of impurities such as water, hydrogen, and nitrogen oxides in the insulator 402 is reduced. For example, the amount of hydrogen desorbed from the insulator 402 is preferably 500 W / m when the surface temperature of the film is 500 W / m in TDS. In the range of 0°C to 500°C, the amount of desorption converted into hydrogen molecules is Converted to 2 x 10 15 molecules / cm 2 Less than 1 × 10 1 5 molecules / cm 2 Less than or equal to 5 × 10 14 molecules / cm 2 The following is fine.

[0118] The insulators 302, 303, and 402 can function as gate insulating films. Note that in the transistor 400a, the insulators 302, 303, and The insulating film in which the insulating film 401 and the insulator 402 are stacked is used. For example, the gate insulating film may be made of an insulator 302 and an insulator 303. 3, and insulator 402 may be used in either two or one layer.

[0119] The transistor described in this embodiment includes the oxide 406a, the oxide 406b, and the oxide 406b described later. It is preferable to have oxide 406c.

[0120] The oxide 406a is preferably disposed on the top surface of the insulator 402. Preferably, 6b is disposed on top of oxide 406a.

[0121] The oxide 406b also has a first region, a second region, and a third region. The region is sandwiched between the first region and the second region in the top view. Transistor 400a has a conductor 416a1 on and in contact with a first region of oxide 406b. The conductor 416a2 is located on and in contact with the second region of the oxide 406b. Either the first region or the second region of b can function as a source region, and the other can function as a drain region. The third region of the oxide 406b can function as a channel forming region. It is possible.

[0122] The oxide 406c is in contact with the third region of the oxide 406b, and is connected to the oxide 406a and the oxide 406b. 6b, conductor 416a1, and conductor 416a2. The oxide 406c may cover the side surfaces of the oxide 406a and the oxide 406b. As shown in FIG. 8C, the side surfaces of the oxide 406a and the oxide 406b in the channel width direction It is preferable that the oxide 406c is in contact with the other of the gate electrodes. The gate insulating film 412 functions as a gate insulating film. The image forming apparatus is arranged so as to cover the entire area.

[0123] The oxide 406c is disposed so as to cover the entire oxide 406a and the oxide 406b. For example, the side surfaces of the oxide 406a and the oxide 406b in the channel length direction may be oxide. Alternatively, the electrode 406 may be configured to be in contact with the oxide 406c.

[0124] In this embodiment, the oxide used in the transistor has the above-described three-layer structure. One embodiment of the present invention is not limited to this. For example, one of the oxides 406a and 406c Alternatively, a two-layer structure may be used, either above or below the oxide 406a, or between the oxide 406b and the oxide 406c. It may also be a four-layer structure having one of the semiconductors described below above or below the semiconductor 406c. Alternatively, the oxide 406a may be formed on the oxide 406b, the oxide 406c may be formed on the oxide 406c, or the oxide 406b may be formed on the oxide 406c. The oxide 406a, the oxide 406b, and the oxide 406c are disposed at two or more positions below the oxide 406a, the oxide 406b, and the oxide 406c. The compound 406c is an n-layer structure (n is an integer of 5 or more).

[0125] The conductor 416a1 and the conductor 416a2 are spaced apart from each other, and the oxide 406 Preferably, the conductor 416a1 is disposed in contact with the top surface of the source electrode b. The conductor 416a1 can function as either a source or drain electrode, and the conductor 416a2 can function as either a source or drain electrode. It can function as the other of the in-electrodes.

[0126] As shown in FIGS. 8A and 8B, one side end of the conductor 416a1 is covered with an oxide 40. It is preferable that one side edge of 6a and one side edge of oxide 406b are approximately aligned. Similarly, one side end of the conductor 416a2 is connected to the other side end of the oxide 406a and It is preferable that the other side edge of the oxide 406b is approximately aligned with the other side edge of the oxide 406b. As a result, the side surfaces of the oxide 406a and the oxide 406b are in contact with the conductor 416a1 and the conductor Therefore, the oxides on the sides of the oxide 406a and the oxide 406b are not in contact with the oxide 406a. The element is drawn into the conductor 416a1 and the conductor 416a2, and the oxide 406a and This can prevent oxygen vacancies from being formed on the side surfaces of the oxide 406b. Conductor 416a1 and conductor 416a2 are formed on the sides of oxide 406a and oxide 406b. This can prevent the intrusion of impurities.

[0127] Here, the distance between the side end of the conductor 416a1 and the side end of the conductor 416a2 facing each other is The distance, i.e., the channel length of the transistor, is 10 nm to 300 nm, typically 20 nm. The length shall be between 100m and 180nm.

[0128] In addition, the angle between the side and bottom surfaces of the conductor 416a1 and the conductor 416a2 facing each other is It is preferable that the conductor 416a1 and the conductor 416b1 have a taper angle of less than 90°. The angle between the side and bottom surfaces of 6a2 facing each other is between 45° and 75°. By forming the conductor 416a1 and the conductor 416a2 in this manner, The oxide 406c has a covering property to cover the step portion formed by the conductor 416a1 and the conductor 416a2. Therefore, the oxide 406c is not easily broken and the oxide is not easily oxidized. This can prevent the object 406b and the insulator 412 from coming into contact with each other.

[0129] A barrier film 417a1 is provided in contact with the upper surface of the conductor 416a1. It is preferable that a barrier film 417a2 is provided in contact with the upper surface of the barrier film 417a1. The barrier film 417a2 has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. The barrier film 417a1 and the barrier film 417a2 may be made of, for example, aluminum oxide. As a result, the conductors 416a1 and 416a2 can be This can prevent excess oxygen from being used in the oxidation. The oxidation of conductor 416a1 and conductor 416a2 It is possible to prevent the electrical resistance from increasing. It can be measured using a terminal method or the like.

[0130] In addition to the insulator 412 and the oxide 406c, a conductive material is provided between the conductor 404 and the conductor 416a1. By providing the barrier film 417a1, the parasitic Similarly, the capacitance can be reduced by providing an insulator between the conductor 404 and the conductor 416a2. The barrier film 417a2 is provided in addition to the insulating film 412 and the oxide 406c. Therefore, in this embodiment, the parasitic capacitance between the conductor 416a2 and the conductor 416a3 can be reduced. The transistor shown in this embodiment has excellent frequency characteristics. The barrier film 7a1 and the barrier film 417a2 may not be provided.

[0131] The insulator 412 can function as a gate insulating film and is disposed on the top surface of the oxide 406c. The insulator 412 is preferably a material that releases oxygen when heated, similar to the insulator 402. It is preferable to form the insulating layer 412 by forming the insulating layer 412 on the oxide 406c. By providing the oxide 406b in contact with the surface, oxygen can be effectively supplied to the oxide 406b. Similar to the insulator 402, the concentration of impurities such as water and hydrogen in the insulator 412 is reduced. It is preferable that

[0132] The conductor 404 is a laminate of the conductor 404a, the conductor 404b, and the conductor 404c. It is preferable that the conductor 404a is disposed on the insulator 412, and the conductor 404 Conductor 404b is disposed on top of insulating layer 404a, and conductive layer 404c is disposed on top of insulating layer 404b. The edge 412 and the conductor 404 have an overlapping region with the oxide 406b. The sides of conductor 404a, conductor 404b, and conductor 404c are approximately aligned. The conductive layer 404 functions as the other gate electrode. The width of the conductive material 404 in the channel length direction is 10 nm or more and 300 nm or less, preferably 20 nm or less. The length shall be between 100m and 180nm.

[0133] One of the conductor 310 and the conductor 404 can function as a gate electrode, and the other can function as a back gate. The gate electrode and back gate electrode form the semiconductor channel region. The back gate electrode may be at the same potential as the gate electrode. The potential of the back gate electrode may be set to the ground potential or any other potential. By changing them independently, the threshold voltage of the transistor can be changed. can.

[0134] The conductor 404a is preferably a conductive metal oxide. 406a, oxide 406b, or oxide 406c. In particular, among In-Ga-Zn oxides, those with high conductivity and low metal atom counts can be used. Metal oxides with a ratio of [In]:[Ga]:[Zn]=4:2:3 to 4.1 and nearby values By providing such a conductor 404a, the conductor 404 Therefore, the permeation of oxygen into the conductor 404b and the conductor 404c can be suppressed. The oxidation of conductor 404b and conductor 404c reduces the electric potential of conductor 404b and conductor 404c. In addition, the supply of excess oxygen to the oxide 406b can prevent the increase in the air resistance. This makes it possible to

[0135] The conductor 404b is formed by adding impurities such as nitrogen to the conductor 404a to increase the conductivity of the conductor 404a. For example, titanium nitride may be used for the conductor 404b. It is preferable that:

[0136] The conductor 404c can be made of a metal with low resistance, such as tungsten.

[0137] Here, the conductor 404, which functions as a gate electrode, is surrounded by the insulator 412 and the oxide 406c. The oxide 406b is formed on the upper surface of the oxide 406b in the vicinity of the third region and on the side surface in the channel width direction. Therefore, the electric field of the conductor 404, which functions as a gate electrode, The upper surface and the side surface in the channel width direction of the oxide 406b in the vicinity of the third region are electrically surrounded. The electric field of the conductor 404 electrically surrounds the channel forming region. The structure of the transistor is a surrounded channel (s-channel) structure. Therefore, the upper surface of the oxide 406b in the vicinity of the third region and the side surface in the channel width direction are Since a channel can be formed in the source and drain, a large current can flow between the source and drain. In addition, the third oxide 406b can increase the current (ON current) when the oxide 406b is turned on. The top surface and the side surface in the channel width direction near the region are surrounded by the electric field of the conductor 404. Therefore, the current (off current) when the device is not conducting can be reduced.

[0138] It is also preferable that a barrier film 418 is provided on the conductor 404. The film 418 is preferably made of a material that is difficult for oxygen to permeate, such as aluminum oxide. This allows excess oxygen in the surrounding area to be used for oxidation of the conductor 404. In this way, the barrier film 418 functions as a gate electrode that protects the gate. The barrier film 418 functions as a cap.

[0139] <Example of capacitance element configuration> A structural example of a capacitor provided in the semiconductor device described in this embodiment will be described with reference to FIG. And explain.

[0140] FIG. 9A is a cross-sectional view of a capacitor 80a included in the semiconductor device described in this embodiment. The capacitor 80a includes a conductor 82, an insulator 83, and a conductor 84. ) a conductor 82 is provided on an insulator 81, and an insulating layer 83 is provided to cover the conductor 82. A body 83 is provided, a conductor 84 is provided to cover the insulator 83, and an insulator 84 is provided on the conductor 84. A rim 85 is provided.

[0141] Here, the insulator 83 is provided so as to contact the side surface of the conductor 82, and the conductor 84 is provided so as to contact the side surface of the insulator 82. It is preferable that the conductive material 82 is provided so as to contact the side surface of the protrusion 3. Since not only the surface but also the side surface of the conductor 82 can function as a capacitance element, the capacitance value can be made larger.

[0142] The conductor 82 functions as one electrode of the capacitor 80a, and the conductor 84 functions as one electrode of the capacitor 80b. The insulator 83 functions as the dielectric of the capacitance element 80a.

[0143] The conductors 82 and 84 may be, for example, boron, nitrogen, oxygen, fluorine, or silicon. , phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium Sodium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin When a conductor containing one or more of tantalum and tungsten is used in a single layer or a multilayer, For example, the material may be an alloy or compound, and may be a conductor containing aluminum, copper, and titanium. Conductors containing tin, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductor 82 and conductor containing titanium and nitrogen may be used. The film of the body 84 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. This can be done.

[0144] The insulator 83 may be, for example, aluminum oxide, aluminum oxynitride, or magnesium oxide. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Use an insulator containing one or more selected from zinc oxide, hafnium oxide, tantalum oxide, etc. In particular, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen Doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0) Nitrogen-doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z> 0)), hafnium oxide, yttrium oxide, or other high-k materials are preferably used. In addition, when a high-k material is used as the insulator 83, the capacitance can be increased by heat treatment. In some cases, it is possible to increase the value. By using such high-k materials, Even if the insulator 83 is made thick, the capacitance value of the capacitive element 80a can be sufficiently ensured. By making the thickness of the conductive material 3 thicker, the leakage current occurring between the conductive material 82 and the conductive material 84 can be suppressed. The insulator 83 can be formed by a sputtering method, a CVD method, an MBE method, a PL method, or the like. This can be done using the D method, ALD method, etc.

[0145] The insulators 81 and 85 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, ma, or the like. Magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium , including yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum The insulator may be used in a single layer or a laminated layer. For example, the insulator 81 and the insulator 85 may be used in a single layer or a laminated layer. Examples include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, and nitride. Silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, acid zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide The insulators 81 and 85 may be formed by sputtering or CVD. The insulator 85 can be formed by using an MBE method, a PLD method, an ALD method, or the like. Organosilane gas (e.g., TEOS (Tetra-Ethyl-Ortho-Silic Alternatively, a film may be formed using a nitrile-based film.

[0146] 9B, the capacitor element 80b is arranged such that the conductor 84 overlaps the upper surface of the conductor 82. 9(A) in that it is formed in the same manner as the capacitor element 80a shown in FIG. In B), the side of the conductor 84 is arranged so as to be substantially aligned with the side of the conductor 82. However, the capacitive element 80b is not limited to this.

[0147] 9C, an insulator 86 having an opening on the insulator 81 is provided. The conductor 82 is provided in the opening, which is the same as that shown in FIG. Here, the opening of the insulator 86 and the upper surface of the insulator 81 form a capacitor element 80a. The space formed can be regarded as a groove, and the conductor 82 is preferably provided along the groove. 9(C), the upper surface of the insulator 86 and the upper surface of the conductor 82 are approximately flush with each other. They may be formed to match.

[0148] An insulator 83 is provided on the conductor 82, and a conductor 84 is provided on the insulator 83. In this case, the conductor 84 overlaps with the conductor 82 in the groove through the insulator 83. In addition, it is preferable that the insulator 83 is provided so as to cover the upper surface of the conductor 82. By providing the insulator 83 in this manner, the leakage current between the conductor 82 and the conductor 84 is reduced. In addition, the side surface of the insulator 83 and the side surface of the conductor 84 are approximately aligned. In this way, the capacitive element 80c may be provided in a concave or It is preferable that the capacitor element 80c has a cylindrical shape. The top surfaces of the insulating material 82, the insulating material 83, and the conductive material 84 may have polygonal shapes other than squares. Alternatively, the shape may be a circle including an ellipse.

[0149] In addition, in a capacitor element 80d shown in FIG. 9D, a conductor 82b having a convex shape is disposed on the conductor 82a. It differs from the capacitive element 80a shown in FIG. 9(A) in that it is disposed in contact with the upper surface. The capacitor 80d is provided on the insulator 81 and is connected to the conductor 82 (the conductor 82a and the conductor 8 2b), an insulator 83, and a conductor 84.

[0150] In the conductor 82 that functions as one electrode of the capacitor 80d, By forming a structure having such a convex shape, the capacitance per projection area of the capacitor element can be increased. Therefore, it becomes possible to reduce the area of the semiconductor device, to increase the integration density, and to miniaturize the device.

[0151] <Substrate> The substrate 210 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates. There are various substrates, such as zirconia substrates (yttria-stabilized zirconia substrates), and resin substrates. The substrate may be, for example, a semiconductor substrate such as silicon or germanium, or silicon carbide. , silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates that have an insulating region inside the semiconductor substrate. Semiconductor substrates, such as SOI (Silicon On Insulator) substrates Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. is a substrate in which a conductor or semiconductor is provided on an insulating substrate, or a semiconductor substrate in which a conductor or an insulating and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate having an element mounted thereon may be used. Examples of the elements include capacitance elements, resistance elements, switch elements, light-emitting elements, and memory elements.

[0152] A flexible substrate may be used as the substrate 210. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to a flexible substrate 210. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, foil, or the like made of woven fibers may be used. In addition, the substrate 210 may have a property of returning to its original shape when the bending or pulling is stopped. Alternatively, the substrate 210 may have a property of not returning to its original shape. is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and The substrate 210 has a region with a thickness of preferably 15 μm or more and 300 μm or less. As a result, the weight of the semiconductor device having the transistor can be reduced. By making the material thinner, it may be possible to make it stretchable even when glass is used, or to make it easy to bend or stretch. When tension is released, the product may return to its original shape. This can reduce the impact on the semiconductor device on the substrate 210. A conductor device can be provided.

[0153] The substrate 210, which is a flexible substrate, may be made of, for example, metal, alloy, resin, glass, or The substrate 210, which is a flexible substrate, can be made of a material having a linear expansion coefficient of 1000 kJ / cm. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester, poly Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, making it suitable for flexible substrates. 210 is suitable.

[0154] <Insulator> The insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. , metal oxide nitrides, metal nitride oxides, etc.

[0155] The transistor is surrounded by an insulator that prevents impurities such as hydrogen and oxygen from passing through. By using the insulator 40, the electrical characteristics of the transistor can be stabilized. 1. If an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen is used, In addition, the insulator 303 has a function of suppressing the permeation of impurities such as hydrogen and oxygen. An insulator may be used. The insulators 401 and 303 are different from the insulator 402 and the like. It is preferable to form the insulating layer using an insulating material that is difficult for impurities such as water and hydrogen to permeate.

[0156] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include oxides. Aluminum oxide, aluminum oxynitride, magnesium oxide, gallium oxide, germanium oxide tungsten oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride, and aluminum nitride The material may be a single layer or a multilayer.

[0157] When the insulator 401 contains aluminum oxide, the oxide 406a, the oxide 406b, and the It is possible to prevent impurities such as hydrogen from being mixed into the oxide 406c. For example, when the insulator 401 contains aluminum oxide, the oxide 406a and the oxide 406b and the out-diffusion of excess oxygen added to the oxide 406c can be reduced. .

[0158] The insulators 301, 302, 402 and 412 may be, for example, boron. hydrogen, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, argon Zn, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium Insulators containing tungsten or tantalum may be used in a single layer or in a multilayer structure. The insulator 301, the insulator 302, the insulator 402 and the insulator 412 may be silicon oxide or Preferably, the insulating layer comprises silicon oxynitride or silicon oxynitride.

[0159] The insulators 302, 303, 402, and 412 are gate insulating films. It is preferable to use an insulator with a high relative dielectric constant because it functions as an insulator. 2. The insulators 303, 402 and 412 are made of gallium oxide, hafnium oxide, etc. , oxides with aluminum and hafnium, oxides with aluminum and hafnium oxide nitrides with silicon and hafnium; oxides with silicon and hafnium; It is preferable that the insulator 302, the insulator 303, and the like have an oxynitride. The insulators 402 and 412 are made of silicon oxide or silicon oxynitride and have a dielectric constant of It is preferable to have a laminated structure of silicon oxide and silicon oxynitride. Since capacitors are thermally stable, they can be used in combination with insulators with high dielectric constants. For example, aluminum oxide, gas oxide, By having sodium or hafnium oxide on the oxide 406c side, silicon oxide or oxide The silicon contained in the silicon nitride can be prevented from being mixed into the oxide 406b. Also, for example, silicon oxide or silicon oxynitride can be used on the oxide 406c side. This allows the formation of a mixture of aluminum oxide, gallium oxide, or hafnium oxide with silicon oxide or A trap center may be formed at the interface between the silicon oxynitride and the silicon dioxide. The center captures electrons, shifting the threshold voltage of the transistor in the positive direction. It may be possible to do so.

[0160] The insulator 410 preferably has a low dielectric constant. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the insulating material has a silicon oxide or resin having pores. 410 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the layer has a laminated structure of silicon or silicon oxide having pores and a resin. Silicon oxide and silicon oxynitride are thermally stable and can be combined with resin. By using the resin, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.), poly Examples include imide, polycarbonate, and acrylic.

[0161] The barrier film 417 (barrier film 417a1 and barrier film 417a2) is made of hydrogen or the like. Alternatively, an insulator having a function of suppressing the permeation of impurities and oxygen may be used. 7a1 and the barrier film 417a2 prevent the excess in the oxide 406c and the insulator 412 from It is possible to prevent oxygen from diffusing into the conductor 416a1 and the conductor 416a2. Cut.

[0162] The barrier film 417 may be made of, for example, aluminum oxide, magnesium oxide, or gallium oxide. , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide metal oxides such as silicon dioxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride etc. can be used.

[0163] <Conductors> The conductors 404, 310, 416a1, and 416a2 are made of aluminum. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten Iron, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Use a material containing one or more metal elements selected from the group consisting of sodium, indium, and ruthenium. In addition, it is possible to use polycrystalline silicon containing impurity elements such as phosphorus. Semiconductors with high electrical conductivity, silicides such as nickel silicide, etc. may also be used.

[0164] Also applicable to oxide 406 (oxide 406a, oxide 406b and oxide 406c) Alternatively, a conductive material containing oxygen and a metal element contained in a metal oxide may be used. Conductive materials containing the above-mentioned metal elements and nitrogen may also be used. For example, titanium nitride, Nitrogen-containing conductive materials such as tantalum oxide (TTA) may also be used. TO: Indium Tin Oxide), indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide with titanium dioxide, indium zinc oxide, silicon-doped indium Indium tin oxide may be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, the oxide 406a, the oxide 406b, and the oxide The hydrogen contained in the outer insulator 406c may be trapped. It may be possible to capture hydrogen that is mixed in from sources such as

[0165] Alternatively, a plurality of conductive layers made of the above materials may be stacked. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen is also available. Also, the material containing the metal element, the conductive material containing oxygen, and the nitrogen A laminated structure in which a conductive material containing the above is combined may also be used.

[0166] When an oxide semiconductor is used for a channel formation region of a transistor, The laminated structure is a combination of the material containing the metal element and the conductive material containing oxygen. In this case, it is preferable to use a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the channel formation region side, the conductive material The oxygen released from the ions is easily supplied to the channel formation region.

[0167] For example, the conductor 310b may be made of a conductive material such as tungsten or polysilicon. The conductor 310a in contact with the insulator 401 may be made of, for example, titanium or titanium nitride. A barrier layer (diffusion prevention layer) such as tantalum or tantalum nitride can be used as a laminate or a single layer. do.

[0168] The insulator 401 is made of an insulating material that is difficult for impurities to penetrate, and the conductor By using a conductive material that is difficult for impurities to penetrate for 310a, the impurities This further suppresses diffusion, thereby further improving the reliability of the transistor. can be done.

[0169] Furthermore, the barrier film 417a1, the barrier film 417a2, and the barrier film 418 are formed of impurities. A conductive material that is difficult to penetrate may be used. When a conductive material is used for the barrier film 418, oxygen is not easily released or absorbed. It is preferable to use a conductive material that is not easily damaged.

[0170] <Metal oxides> The oxide 406 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). It is preferable to use metals that can be used as the oxide 406 according to the present invention. The oxide will be explained.

[0171] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that the material contains yttrium, tin, etc. Also, boron, silicon, titanium, etc. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One selected from odymium, hafnium, tantalum, tungsten, magnesium, etc. One or more types may be included.

[0172] Here, the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. Let us consider the case where the element M is aluminum, gallium, yttrium, tin, etc. Other elements that can be used for element M include boron, silicon, titanium, Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium However, the elements M and H are also included. In some cases, a combination of the above elements may be used.

[0173] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). It may also be called hydroxybenzoxanthate (hydroxybenzoxanthate).

[0174] [Metal oxide composition] Hereinafter, a CAC(Cl) compound that can be used in a transistor disclosed in one embodiment of the present invention will be described. This paper explains the structure of the oud-Aligned Composite OS.

[0175] In this specification and the like, CAAC (c-axis aligned crystal ), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration. Represents.

[0176] CAC-OS or CAC-metal oxide is a material that has the function of conductivity in some parts. The material has an insulating function in part and a semiconductor function in the whole. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a material, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0177] In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region are formed at the nanoparticle level in the material. The conductive and insulating regions may be separated by a thin film. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0178] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0179] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxidized de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, In the narrow gap component, carriers mainly flow. The component having a wide gap acts complementary to the component having a narrow gap. Carriers also flow into the wide-gap component in conjunction with the component with a wide gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, a high current driving force, i.e., a large on-current, is obtained when the transistor is in a conducting state. Furthermore, high field-effect mobility can be obtained.

[0180] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a matrix composite.

[0181] [Metal oxide structures] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis alignable oxide semiconductor) gned crystalline oxide semiconductor), polycrystalline nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) us-like oxide semiconductor), amorphous oxide semiconductor, etc. There is.

[0182] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0183] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. In addition, the distortion may have a lattice arrangement such as a pentagon or heptagon. In CAAC-OS, clear grain boundaries are observed even near the strain. It is not possible to confirm the formation of grain boundaries due to distortion of the lattice arrangement. This is because the CAAC-OS has oxygen atoms in the ab-plane direction. The atomic arrangement is not dense, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by the above.

[0184] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when part of the element M in the (M,Zn) layer is replaced with indium, (In,M, Zn) layer. Also, when part of the indium in the In layer is replaced with element M, , (In,M) layer.

[0185] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of oxide semiconductors can be degraded by the inclusion of impurities and the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable.

[0186] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0187] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS.

[0188] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and nc The compound may have two or more of -OS and CAAC-OS.

[0189] [Transistors with oxide semiconductors] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0190] Note that by using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be obtained. Furthermore, a highly reliable transistor can be realized. .

[0191] In addition, an oxide semiconductor with low carrier density is preferably used for the transistor. When the carrier density of the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is In this specification and the like, the impurity concentration is low and the defect level density is low. A low density of recessed levels is called high purity intrinsic or substantially high purity intrinsic. Conductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Not yet less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. That's fine.

[0192] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0193] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There are cases where this happens.

[0194] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0195] [impurities] Here, the influence of each impurity in an oxide semiconductor will be described.

[0196] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0197] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 Do the following:

[0198] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. Therefore, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is The degree is 5×10 in SIMS. 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Below, further Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0199] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that the SIM is reduced as much as possible. The hydrogen concentration obtained by S is 1×10 20 atoms / cm 3 Less than 1x1 0 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than, More preferably, 1 × 10 18 atoms / cm 3 Less than.

[0200] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0201] <Modification of Transistor> The transistor described in this embodiment is not limited to that shown in FIG. Modified examples of the transistor described in this embodiment will be described with reference to FIGS. In the following description, the components having the same reference numerals as the transistor 400a are referred to as the transistors The corresponding description in 400a can be taken into consideration.

[0202] The transistor 400c shown in FIGS. 10A, 10B, and 10C will be described. 400c is an insulator 401 and an insulator 301 disposed on a substrate (not shown), and an insulator A conductor 310 is disposed so as to be embedded in the insulator 301, and a conductor 31 0, an insulator 302 disposed on the insulator 302, and an insulator 303 disposed on the insulator 302. An insulator 402 is disposed on the insulator 303, and an oxide 40 is disposed on the insulator 402. 6a, and an oxide 406b disposed in contact with at least a portion of the top surface of the oxide 406a; An oxide 406c is disposed on the oxide 406b, and an insulating layer is disposed on the oxide 406c. The insulator 412, the conductor 404 disposed on the insulator 412, and the insulator 404 disposed on the conductor 404 The insulator 419a is connected to the insulator 412, the conductor 404, and the insulator 419a. The insulator 419b is disposed in contact with the upper surface of the oxide 406c and is disposed in contact with the upper surface of the insulator 419b. and an insulator 409 arranged in contact with the side surface of the substrate. In addition, it is preferable that the upper surface of the insulator 419b is substantially flush with the upper surface of the insulator 419a. , the insulator 409 includes the insulator 419a, the insulator 402, the insulator 419b, the oxide 406a, It is preferably provided to cover oxide 406b and oxide 406c.

[0203] The transistor 400c does not have the conductor 416a1 and the conductor 416a2. The point having the insulator 409, the insulator 419a, and the insulator 419b, and the oxide 406a , oxide 406b, and oxide 406c in regions 426a, 426b, and 4 The transistor 400 differs from the transistor 400a in that a transistor 26c is formed.

[0204] As shown in FIG. 10(B), the region 426a is sandwiched between the region 426b and the region 426c. The regions 426b and 426c are regions whose resistance is reduced by forming the insulator 409. Therefore, the region 426b and the region 426c are more conductive than the region 426a. In this specification, the region 426b and the region 426c may be referred to as a conductor. 26c is a film formed by adding impurity elements such as hydrogen and nitrogen contained in the film forming atmosphere of the insulator 409. As a result, the added impurities are concentrated in the region of the oxide 406 that contacts the insulator 409. Oxygen vacancies are formed by impurity elements, and the impurity elements then enter the oxygen vacancies, The carrier density increases and the resistance decreases.

[0205] Therefore, regions 426b and 426c contain less hydrogen and nitrogen than region 426a. It is preferable that at least one of the concentrations is large. The concentration of hydrogen or nitrogen can be measured by SIMS or the like. Measurement can be performed using the following formula:

[0206] The regions 426b and 426c are formed by an element that forms an oxygen vacancy or an element that is not related to the oxygen vacancy. The resistance is reduced by adding elements that can be captured. Typical examples of such elements include Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Representative examples of rare gas elements include helium, neon, argon, krypton, and and xenon. Therefore, the region 426b and the region 426c may contain one or more of the above elements. Alternatively, a configuration including a plurality of such components may be used.

[0207] As shown in FIG. 10B, the region 426b and the region 426c are formed by the oxide 406a and the oxide 406b. The oxide 406b is formed at least in the area where the oxide 406c overlaps with the insulator 409. 4, where region 426b of oxide 406b can function as one of a source region and a drain region. The region 426c of the oxide 406b functions as the other of the source and drain regions. Additionally, the region 426a of the oxide 406b can function as a channel formation region.

[0208] In the transistor 400c, as shown in FIG. 10B, the region 426b and the region 426 The region of the oxide 406 in contact with the insulator 409, the region of the insulator 419b, and the region of the insulator 412 It is preferable that the regions 426b and 426c are formed in the vicinity of both ends of the The area of the region 426c that overlaps with the conductor 404 is called an overlap region (Lov region). By creating a structure with a Lov region, the chalcogenide 406 Since no high resistance region is formed between the channel formation region and the source and drain regions, This can increase the on-state current and mobility of the transistor.

[0209] When viewed from above perpendicularly to the substrate, the position of the side surface of the insulator 419a is 12, it is preferable that the position of the insulator 419a is approximately the same as the position of the side surface of the conductor 404. It is preferable to form the insulator 419a by using the LD method. The film can be formed to a thickness of about 20 nm or less, preferably about 5 nm or more and 10 nm or less. Here, the insulator 419a has a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. It is preferable to use an insulating material having such a property, for example, aluminum oxide or hafnium oxide. It is preferable to use the following.

[0210] The insulator 419b is in contact with the side surfaces of the insulator 412, the conductor 404, and the insulator 419a. The upper surface of the insulator 419b is generally aligned with the upper surface of the insulator 419a. The insulator 419b is preferably formed by an ALD method. The thickness of the insulator 419b is set to about 1 nm or more and 20 nm or less, preferably 1 nm or more and 3 nm or less. The film can be formed to a thickness of about 1 nm, for example.

[0211] Here, the insulator 419b, like the insulator 419a, is a material that can absorb impurities such as water and hydrogen, and acids. It is preferable to use an insulating material that has the function of suppressing the permeation of oxygen, such as aluminum oxide. It is preferable to use aluminum, hafnium oxide, or the like. It is possible to prevent oxygen from diffusing to the outside. This can prevent impurities such as water and hydrogen from entering the object 406.

[0212] In this way, by providing the insulators 419b and 419a, it is possible to prevent the generation of gas such as water and hydrogen. An insulator that has the function of suppressing the permeation of impurities and oxygen, and is attached to the top and side surfaces of the conductor 404. and the side of the insulator 412. 412, impurities such as water and hydrogen can be prevented from mixing with the oxide 406. In this way, the insulator 419b serves as a support for protecting the side surfaces of the gate electrode and the gate insulating film. The insulator 419a acts as a top barrier to protect the top surface of the gate electrode. , it works.

[0213] The insulator 419b is formed by depositing an insulating film using the ALD method and then performing anisotropic etching. The insulating film is formed by contacting the side surfaces of the insulator 412, the conductor 404, and the insulator 419a. It is preferable to leave the insulating film with a thin film thickness as described above. In addition, at this time, the insulating layer 419b can be easily formed on the conductor 404. By providing the insulator 419a, a part of the insulator 419a is removed by the anisotropic etching. Even if the insulator 419b is removed, the portion of the insulator 419b that is in contact with the insulator 412 and the conductor 404 is sufficiently left. It is possible.

[0214] The insulator 409 includes an insulator 419a, an insulator 419b, an oxide 406a, an oxide 406b, The oxide 406c is provided over the insulator 402. Here, the insulator 409 is an insulating material. The insulating member 419b is provided in contact with the upper surfaces of the insulating member 419a and the insulating member 419b, and is also provided in contact with the side surface of the insulating member 419b. The insulator 409 also prevents impurities such as water and hydrogen from permeating, as well as oxygen. For example, silicon nitride is used as the insulator 409. Silicon, silicon oxide nitride, silicon oxide nitride, aluminum nitride, aluminum oxide nitride It is preferable to use a film or the like. By forming such an insulator 409, Oxygen penetrates into the region 426b and the region 426c through the region 9. By supplying oxygen to the oxygen vacancies in 426c, it is possible to prevent the carrier density from decreasing. Furthermore, impurities such as water and hydrogen permeate through the insulator 409 and enter the regions 426b and 426c. and prevents the regions 426b and 426c from expanding excessively toward the region 426a. It is possible.

[0215] As shown in FIGS. 10A, 10B, and 10C, the transistor 400c has the following configuration from the top: Oxide 406a, oxide 406b, and oxide 406c when viewed perpendicular to the substrate However, the present embodiment is not limited to this. The oxide 406c may cover the side surfaces of the oxide 406a and the oxide 406b. At this time, the side surfaces of the oxide 406a and the oxide 406b in the channel width direction are connected to the oxide 406c. Furthermore, the oxide 406a and the oxide 406b are preferably in contact with each other in the channel length direction. The side surface of the oxide 406c may be in contact with the oxide 406c.

[0216] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0217] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0218] (Embodiment 2) In this embodiment, an example of a semiconductor device (memory device) according to one embodiment of the present invention will be described. do.

[0219] <Circuits of semiconductor devices (memory devices)> FIG. 11 illustrates a circuit example of a semiconductor device (memory device) according to one embodiment of the present invention.

[0220] The semiconductor device shown in FIG. 11A includes a transistor 280 using a first semiconductor material and a second semiconductor material. The semiconductor device includes a transistor 400 made of the semiconductor material of the second embodiment and a capacitor 80.

[0221] The first and second semiconductor materials have different energy gaps. For example, the first semiconductor material is preferably a semiconductor material other than an oxide semiconductor (silicon (strained) (including silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.) The semiconductor material of 2 can be an oxide semiconductor. Transistors using crystalline silicon or the like can easily operate at high speed. A transistor using such a material has a low off-state current.

[0222] The transistor 400 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 400 is small, the transistor 400 can be used as a semiconductor. By using it in a physical device (memory device), it is possible to retain memory contents for a long period of time. In other words, no refresh operation is required, or the frequency of refresh operation is extremely low. Since it is possible to use a semiconductor device (memory device) with a minimum number of power consumption, power consumption can be reduced sufficiently. It is possible.

[0223] In FIG. 11A, a first wiring 3001 is electrically connected to the source of the transistor 280. The second wiring 3002 is electrically connected to the drain of the transistor 280. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 400. The fourth wiring 3004 is electrically connected to the gate of the transistor 400. The gate of transistor 280 and the source or The other end of the drain is electrically connected to one of the electrodes of the capacitor 80 and is connected to a fifth wiring 3005 is electrically connected to the other electrode of the capacitor element 80. In addition, in FIG. The gate of transistor 280 and the other of the source and drain of transistor 400; The connection point between one electrode of the capacitance element 80 and the floating node (FN) is indicated. By making the transistor 400 non-conductive, the floating node (FN) The potential applied to one of the electrodes of the capacitor 80 and the gate of the transistor 280 is maintained. It can be held.

[0224] In the semiconductor device illustrated in FIG. 11A, the potential of the gate of the transistor 280 can be held. By utilizing this feature, it is possible to write, store, and read information as follows.

[0225] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 400 is set to a potential at which it becomes conductive, thereby making the transistor 400 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 280 and the capacitor 80 is electrically connected to one of the electrodes of the floating node. A predetermined charge is applied to the gate of the transistor 280 (write). The charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor 4 00 is set to a potential at which the transistor 400 is in a non-conducting state, , the charge given to the floating node is retained (retained).

[0226] Since the non-conducting current of transistor 400 is very small, the charge on the floating node remains constant for a long time. is maintained over time.

[0227] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the floating The second wiring 3002 takes on different potentials depending on the amount of charge held in the switching node. If the transistor 280 is an n-channel type, a High The apparent threshold voltage Vth_H when the h level charge is applied is The apparent threshold voltage Vth_L when a low-level charge is applied to the gate of 0 Here, the apparent threshold voltage is the voltage at which the transistor 280 is turned on. The potential of the fifth wiring 3005 required to achieve the "state" is therefore By setting the potential of 005 to V0 between Vth_H and Vth_L, floating For example, in a write operation, the charge applied to the floating node can be determined. When a high level charge is applied to the node, the potential of the fifth wiring 3005 becomes V0 (>Vth_H), the transistor 280 is in a "conducting state." When a low-level charge is applied to the floating node, even if the potential of the fifth wiring 3005 becomes V0 (<Vth_L), the transistor 280 remains in the "non-conducting state" . Therefore, by determining the potential of the second wiring 3002, the information stored in the floating node can be read out.

[0228] Also, by arranging the semiconductor devices shown in Fig. 11(A) in a matrix, a memory device (memory cell array) can be constructed.

[0229] When the memory cells are arranged in an array, at the time of reading, the information of the desired memory cell must be read out. For example, in a memory cell from which information is not read, the transistor 280 is made non-conducting regardless of the charge applied to the floating node. That is, by applying a potential lower than Vth_H to the fifth wiring 3005, a configuration that allows only the information of the desired memory cell to be read can be achieved. Or, in a memory cell from which information is not read, the transistor 280 is made conducting regardless of the charge applied to the floating node. That is, by applying a potential higher than Vth_L to the fifth wiring 3005, a configuration that allows only the information of the desired memory cell to be read can be achieved. In the above, an example of holding two types of charges in the floating node is shown

[0230] , but the semiconductor device according to the present invention is not limited to this. For example, the floating node of the semiconductor device may be configured to hold three or more types of charges. By adopting such a configuration, the semiconductor device can be made multi-valued to increase the storage capacity.

[0231] The semiconductor device shown in FIG. 11B includes a transistor 280, a first wiring 3001, and a second wiring 3002. 11A in that the second wiring 3002 is not provided. In this case, data writing and reading can be performed in the same manner as in the semiconductor device shown in FIG. and holding operations are possible.

[0232] The reading of data from the semiconductor device shown in FIG. 11B will be described. When the third wiring 3003 in a floating state is brought into a conductive state, the third wiring 3003 and the capacitor element 80 are brought into a conductive state. The charge is redistributed between the third wiring 3003 and the capacitance element 80. As a result, The amount of change in the potential of the third wiring 3003 is determined by the potential of one of the electrodes of the capacitor 80. The potential at the node 81 varies depending on the potential at the node 81 (or the charge stored in the capacitor 80).

[0233] For example, the potential of one of the electrodes of the capacitance element 80 is V, the capacitance of the capacitance element 80 is C, and the third wiring 3 The capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed is V B0, the potential of the third wiring 3003 after the charge redistribution is (CB×VB0+ Therefore, the state of the memory cell is such that the electrodes of the capacitance element 80 If one of the potentials has two states, V1 and V0 (V1>V0), then the potential V1 is maintained. The potential of the third wiring 3003 when is the potential of the third wiring 3003 when the potential V0 is maintained (=(CB×VB0+C× V0) / (CB+C)).

[0234] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0235] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor in which a second semiconductor material is applied is used as the transistor 400. The structure may be such that the photodiode is stacked on the driving circuit.

[0236] In the semiconductor device described in this embodiment, an oxide semiconductor is used for a channel formation region, and an off-state current By applying transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is not required or the refresh operation is Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0237] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the reliability of the transistors is dramatically improved. Since the data is written in the memory, high-speed operation can be easily achieved.

[0238] The semiconductor device shown in FIG. 11C includes a transistor 290 and a sixth wiring 3006. 11(A)。 In this case, the semiconductor device shown in FIG. By operating in the same way as the device, it is possible to write and store information. The transistor 290 may be the same as the transistor 280 described above.

[0239] The sixth wiring 3006 is electrically connected to the gate of the transistor 290. One of the source and drain of 290 is electrically connected to the source of transistor 280. The other of the source and drain of the transistor 290 is electrically connected to a third wiring 3003. .

[0240] The above storage device may be implemented, for example, by a CPU (Central Processing Unit). In addition to the DSP (Digital Signal Processor), LSI, PLD (Programmable Logic Device) etc. I. It can also be applied to RF (Radio Frequency) tags.

[0241] <Configuration 1 of semiconductor device (memory device)> A configuration of a semiconductor device (memory device) according to one embodiment of the present invention will be described below.

[0242] FIG. 12 is a top view and a cross-sectional view of a semiconductor device 1000b according to one embodiment of the present invention. 12(B) is a top view of the semiconductor device 1000b. 12(B) is a cross-sectional view taken along the dashed line xy. For clarity, some elements are omitted in the illustration.

[0243] The semiconductor device 1000b includes a transistor 400, a transistor 280, and a capacitance element 80. The transistor 400, the transistor 280, and the capacitance element 8 shown in FIG. 11A. 0, respectively.

[0244] The semiconductor device 1000b uses an n-type semiconductor as the substrate 501. The transistor 280 is , a channel forming region 283, a high concentration p-type impurity region 285, an insulator 286, and a conductor 287 , and a sidewall 288. A low concentration p-type impurity region 284 is formed in the region overlapping the sidewall 288. The insulator 286 can function as a gate insulator. The conductor 287 can function as a gate conductor. The transistor 280 can function as a transistor having a channel forming region 283 formed in a part of the substrate 501. is formed.

[0245] The low concentration p-type impurity region 284 is formed by forming the conductor 287 after the conductor 287 is formed and before the sidewall 288 is formed. 7 as a mask to introduce impurity elements. That is, the lightly doped p-type impurity region 284 can be formed by self-alignment. After the formation of the low concentration p-type impurity region 28, a high concentration p-type impurity region 285 is formed. 4 has the same conductivity type as the high concentration p-type impurity region 285, and the concentration of the impurity that gives the conductivity type is The low concentration p-type impurity region 284 is lower than the high concentration p-type impurity region 285. It may not be necessary to provide it depending on the circumstances.

[0246] The transistor 280 is electrically isolated from other transistors by an isolation region 514. The element isolation region is formed by LOCOS (Local Oxidation of Silicon) silicon) method and STI (Shallow Trench Isolation) method etc. can be used.

[0247] The semiconductor device 1000b also includes an insulator 504 and an insulator 505 that cover the transistor 280. The semiconductor device 1000b has an insulator 534 and an insulator 536 on the insulating film 505. A conductor 522 is provided on an insulator 505 .

[0248] The conductor 522 is formed by connecting the insulator 504 and the conductor 521 provided in a part of the insulator 505. 280 via a ground potential.

[0249] A wiring layer may be provided over the insulator 536. For example, in FIG. 2, an insulator 103, and an insulator 104 are laminated in this order. , insulator 103, insulator 102, insulator 536, and insulator 534 are provided with conductor 525 The conductor 525 functions as a plug or a wiring.

[0250] In addition, the semiconductor device 1000b has an insulator 102, an insulator 103, an insulator 104, insulator 106, insulator 107 and insulator 108. In addition, the insulators 114, 115, and 539 are formed on the transistor 400. The conductor 527, the insulator 116, and the capacitor 80 are disposed on the insulator 539. The capacitance element 80 includes a conductor 527, an insulator 116, and a conductor 84. 527, the insulator 116 and the insulator 537 that covers the capacitive element 80.

[0251] The conductor 527 serves as one electrode of the capacitor 80, and the conductor 84 serves as the other electrode of the capacitor 80. In addition, in the insulator 116, the conductor 527 and the conductor 84 function as electrodes. The region sandwiched between functions as a dielectric.

[0252] The conductor 527 is formed by the insulator 539, the insulator 115, the insulator 114, and the barrier film 417. The source or drain of the transistor 400 is connected to the conductor 526 provided in a part of the are electrically connected.

[0253] In addition, a conductor 529 is provided over the insulator 537, and an insulator 538 is provided over the conductor 529. The conductor 529 is connected to the conductor 84 via the conductor 528 provided in a part of the insulator 537. are electrically connected.

[0254] Insulator 102, insulator 103, insulator 104, insulator 106, insulator 107, insulator 10 8, insulator 114, insulator 115, insulator 116, insulator 534, insulator 536, insulator The insulators 539, 537, and 538 are the same as the insulators shown in the above embodiment. The conductors 521, 522, and 523 can be formed using the same materials and methods. Conductor 525, conductor 526, conductor 527, conductor 528, and conductor 529 are the same as those described above. The conductive layer can be formed using the same materials and methods as those for the conductors shown in the embodiments.

[0255] In addition, the conductor 521, the conductor 522, the conductor 525, the conductor 526, the conductor 527, the conductor The conductive body 528 and the conductive body 529 are formed by using a damascene method, a dual damascene method, or the like. You may do so.

[0256] <Configuration 2 of semiconductor device (memory device)> In the semiconductor device 1000 shown in FIG. 13, the capacitor element 80 is formed in the same layer as the transistor 400. 12. In this respect, the semiconductor device 1000 differs from the semiconductor device 1000b shown in FIG.

[0257] 13A and 13B are a top view and a cross-sectional view of a semiconductor device 1000 according to one embodiment of the present invention. 3(B) is a top view of the semiconductor device 1000. FIG. 13(A) is a dot-and-dash diagram of FIG. 13(B). It is to be noted that in the top view of FIG. 13(B), for clarity of the drawing, Some elements are omitted in the illustration.

[0258] The semiconductor device 1000 includes a transistor 400, a transistor 280, and a capacitance element 80. The transistor 400, the transistor 280, and the capacitor 80 shown in FIG. 11A, the transistor 400, the transistor 280, and the capacitance element 8 0, respectively.

[0259] As shown in FIG. 13, one of the source and drain of the transistor 400 is connected to the capacitor element 80. The conductor 84 serves as one electrode of the capacitor 80. In this case, the barrier film of the transistor 400 (for example, the barrier film 417a2), the transistor 400 (e.g., oxide 406c), and the gate dielectric of transistor 400. (e.g., insulator 412) and one of the source and drain of transistor 400. The area extending over the conductive material functions as the dielectric of the capacitor element 80. The conductor that is either the source or drain of transistor 400 and conductor 84 form a transistor. The barrier film of the transistor 400, the oxide of the transistor 400, and the gate of the transistor 400 The overlapping region with the insulating film interposed therebetween functions as a capacitance element 80.

[0260] With the above structure, when the capacitor 80 is manufactured in parallel with the transistor 400, In this case, the capacitor element 80 can be manufactured without adding any extra steps.

[0261] According to one embodiment of the present invention, leakage current between memory cells can be reduced. According to one embodiment of the present invention, a memory device with high productivity can be provided. According to this, it is possible to realize a storage device that can retain information for a long period of time even when the supply of power is stopped. Even if the power supply is cut off, the information can be retained for more than one year, or even more than ten years. Therefore, the storage device of one embodiment of the present invention can be regarded as a nonvolatile memory. The structure described in this embodiment mode may be combined with structures described in other embodiments as appropriate. It can also be applied to electronic devices. For example, It can be applied to storage devices, CPUs, etc. that have such a function. It can also be applied to display devices. For example, the present invention can be applied to pixel circuits and driving circuits of a display device.

[0262] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0263] (Embodiment 3) In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described.

[0264] Next, a transistor 400d shown in FIGS. 14A, 14B, and 14C will be described. 14A and 14B are a top view and a cross-sectional view of a transistor 400d. 14(B) is a top view of the 400d shown in FIG. 14(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. In the top view of FIG. 14(A), some elements are omitted for clarity. There are.

[0265] The transistor 400d can be fabricated in parallel with the transistor 400a. The transistor 400d is fabricated in parallel with the transistor 400a. In this case, the transistor 400d can be manufactured without adding any additional steps. .

[0266] The transistor 400d includes oxide layers 406a spaced apart from each other on the insulator 402. 1 and oxide 406a2, and oxide 406 arranged in contact with the top surface of oxide 406a1. b1 and an oxide 406b2 disposed in contact with the top surface of the oxide 406a2, The object 406c is the top surface of the insulator 402, the side surfaces of the oxide 406a1 and the oxide 406a2, and in that it is disposed in contact with the side surfaces of the oxide 406b1 and the oxide 406b2. Therefore, it is different from the transistor 400a.

[0267] The oxides 406a1 and 406a2, and the oxides 406b1 and 406b2 are , similar to the oxide 406a and oxide 406b of the transistor 400a, respectively. The oxide 406a1 and the oxide 406b1 can be formed using the oxide The oxide 406a2 and the oxide 406b2 are connected to the oxide 406c, the insulator 412, and the conductor 406b. The electrodes are formed facing each other with the conductive material 404 interposed therebetween.

[0268] The conductor 416a1 is formed to overlap the oxide 406a1 and the oxide 406b1. The conductor 416a2 can be formed by overlapping the oxide 406a2 and the oxide 406b2. The oxide 406a1 and the oxide 406b1, or the oxide The oxide 406a2 and oxide 406b2 form the source or drain region of transistor 400d. It can function as either a rain area.

[0269] The oxide 406c of the transistor 400d is the same as the oxide 406c of the transistor 400a. The oxide 406c can be formed using the oxide 406a1 and the oxide 406b. The region sandwiched between the oxide 406a2 and the oxide 406b1 and the oxide 406b2 is a region of the It functions as a channel forming region.

[0270] The oxide 406c, which serves as the active layer of the transistor 400d, is As with oxide 406c, oxygen deficiency is reduced and impurities such as water and hydrogen are reduced. This increases the threshold voltage of the transistor 400d above 0V, The current can be reduced and Icut can be made very small. The drain current when the voltage of the gate that controls the switching operation of the transistor is 0V. The distance between the conductor 416a1 and the conductor 416a2 of the transistor 400d is set to The distance between the conductor 416a1 and the conductor 416a2 of the transistor 400a is set to be larger than that between the conductor 416a1 and the conductor 416a2 of the transistor 400a. This makes the threshold voltage of the transistor 400d higher than that of the transistor 400a. The off-state current can be reduced, and Icut can be made smaller.

[0271] The transistor 400d controls the back gate voltage of the transistor 400a. For example, the top gate and back gate of transistor 400d can be The source of transistor 400d is diode-connected, and the source of transistor 400e is diode-connected. In this configuration, the back gate of the transistor 400a is connected. When the back gate is held at a negative potential, the gate-source potential of the transistor 400d is The voltage at the transistor 400d and the voltage between the back gate and the source are 0V. Since Icut is very small, this configuration allows transistors 400a and Even if the transistor 400d is not supplied with power, the back gate of the transistor 400a is negatively charged. The potential can be maintained for a long period of time.

[0272] As described above, one embodiment of the present invention provides a semiconductor device with high reliability. It is possible.

[0273] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0274] (Fourth embodiment) In this embodiment, an electronic device including a transistor according to one embodiment of the present invention will be described. We will explain about this.

[0275] <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. Specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention will be described.

[0276] 15(A) is an external view showing an example of an automobile. The automobile 2980 includes a body 2981, It has wheels 2982, a dashboard 2983, and lights 2984. The car 2980 is equipped with an antenna, a battery, etc.

[0277] The information terminal 2910 shown in FIG. 15B includes a housing 2911, a display unit 2912, a microphone 291 7, speaker unit 2914, camera 2913, external connection unit 2916, and operation switch 2 The display portion 2912 includes a display panel using a flexible substrate and a touch panel. The information terminal 2910 is also provided with an antenna, a battery, and a display screen inside the housing 2911. The information terminal 2910 is, for example, a smartphone, a mobile phone, a tablet, It can be used as a laptop information terminal, tablet personal computer, e-book reader, etc. This can be done.

[0278] A notebook personal computer 2920 shown in FIG. 15C includes a housing 2921, a display unit 2922, a keyboard 2923, and a pointing device 2924. The notebook personal computer 2920 has an antenna, a battery, and the like inside the housing 2921. It has a terry, etc.

[0279] The video camera 2940 shown in FIG. 15(D) includes a housing 2941, a housing 2942, a display unit 29 43, an operation switch 2944, a lens 2945, and a connection part 2946. The switch 2944 and the lens 2945 are provided in the housing 2941. 3 is provided in a housing 2942. A video camera 2940 is provided in a housing 2941. The housing 2941 and the housing 2942 are provided with an antenna, a battery, etc. on the side. 2946, and the angle between the housing 2941 and the housing 2942 is 46. The housing 2942 relative to the housing 2941 Depending on the angle, the orientation of the image displayed on the display unit 2943 can be changed, and the image can be displayed / hidden. Switching can be done.

[0280] An example of a bangle-type information terminal is shown in FIG. 15(E). The information terminal 2950 has a housing 2951. The information terminal 2950 includes a housing 2951 and a display unit 2952. The display unit 2952 is supported by a curved housing 2951. The display unit 2952 is provided with a display panel using a flexible substrate. It is possible to provide a flexible, lightweight, and easy-to-use information terminal 2950.

[0281] FIG. 15F shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, Display unit 2962, band 2963, buckle 2964, operation switch 2965, input / output terminal The information terminal 2960 also includes an antenna, a The information terminal 2960 is equipped with a battery, etc., and functions as a mobile phone, e-mail, and document reader / writer. It can be used for various applications such as music playback, internet communication, and computer games. It can be executed.

[0282] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by touching the The operation switch 2965 is used to start the application. In addition to settings, you can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning on and off the power saving mode, turning on and off the power saving mode, etc. The operating system installed in the information terminal 2960 controls the operation of the operation switch 29 You can also set up to 65 functions.

[0283] The information terminal 2960 is also capable of performing standardized short-range wireless communication. For example, by communicating with a wireless headset, you can make hands-free calls. The information terminal 2960 is also provided with an input / output terminal 2966, and can be connected to other information terminals. Data can be exchanged directly through the connector. Charging can also be performed via the input / output terminal 2966. It may also be powered by a line.

[0284] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used to store control information for the above-described electronic devices. The semiconductor device according to one aspect of the present invention can store the data, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0285] The structure shown in this embodiment mode may be appropriately combined with structures described in other embodiment modes or examples. It is possible to implement this in combination. [Example]

[0286] In this example, aluminum (Al) is used as an example of the metal A described in the first embodiment. The residues when wiring containing the metal oxide were formed were evaluated.

[0287] <Sample composition> In this section, the configurations of Samples 1A to 1D used in this example will be described.

[0288] The structures shown in FIG. 16A were formed as Samples 1A to 1D. 213, a conductor 226, and a conductor 227.

[0289] First, a silicon wafer was prepared as a substrate (not shown). Next, an insulator 2 was formed on the substrate. As 13, a silicon oxide film was formed to a thickness of 100 nm by thermal oxidation.

[0290] Next, a first titanium film is formed on the insulator 213 by sputtering to a thickness of 20 nm. A first titanium nitride film was formed on the first titanium film by sputtering. The first titanium nitride film was deposited to a thickness of 0 nm, and then aluminum was deposited on the first titanium nitride film by sputtering. A 100 nm thick silicon film was formed on the aluminum film by sputtering. A second titanium film was formed to a thickness of 5 nm, and a second titanium film was deposited on the second titanium film by sputtering. Then, a second titanium nitride film was formed to a thickness of 45 nm. 5, a first titanium film, a first titanium nitride film, an aluminum film, and a second titanium A laminated structure of the first titanium nitride film and the second titanium nitride film was formed.

[0291] Next, a resist mask is patterned on the conductor 225 using a lithography method. was formed.

[0292] Next, the sample is subjected to the first and second processes through a resist mask. The etching was performed under the conditions of the first treatment: pressure 1.9 Pa, upper electrode power 450 W, Bias power 100 W, flow rate of 60 sccm BCl3, flow rate of 20 sccm Cl2, The first treatment was carried out in a mixed atmosphere with the substrate temperature at 70°C. It went for seconds.

[0293] The second treatment was carried out under the conditions of a pressure of 2.0 Pa, an upper electrode power of 500 W, a bias power of 50 W, and a flow rate of 80 The treatment was carried out for 15 seconds at a substrate temperature of 70° C. in an atmosphere of CF4 at a flow rate of 1 sccm.

[0294] By the above etching, the conductor 225 is processed to form the conductors 226 and 227. The sample immediately after the etching was designated as Sample 1A.

[0295] Next, a cleaning process was carried out using pure water (hereinafter referred to as "pure water cleaning"). The sample was designated as Sample 1B.

[0296] The first ashing was performed on the sample 1B. The first ashing was performed at a pressure of 0.67 Pa. The power supply was 2000 W, the bias power was 50 W, and the flow rate was 200 sccm under the atmosphere of O2. It lasted for 15 seconds.

[0297] Next, the second ashing was carried out. The second ashing was carried out at a pressure of 12.0 Pa and a power supply power of 2. 000W, bias power 0W, flow rate 200sccm O2 atmosphere, 15 seconds The sample after the second ashing was designated as Sample 1C.

[0298] The resist mask was removed from Sample 1C using a resist stripper. The sample after removing the burrs was designated as Sample 1D.

[0299] Cross-sectional observation was performed on Samples 1A to 1D. The presence or absence of aluminum (Al) residue was evaluated by elemental analysis.

[0300] <Cross-section observation of sample> The cross-sections of Samples 1A to 1D were observed using a scanning transmission electron microscope (STEM). Transmission Electron Microscope The observation device used was the HD-2300 manufactured by Hitachi High-Technologies Corporation. The accelerating voltage was 16(B) shows the area surrounded by the dotted line in FIG. 16(A) of Sample 1A. FIG. 16(C) is a cross-sectional STEM image of the sample 1B surrounded by the dotted line shown in FIG. 16(A). Fig. 16(D) shows a cross-sectional STEM image of the area of sample 1C indicated by the dotted line in Fig. 16(A). Figure 16(E) is a cross-sectional STEM image of the enclosed area of sample 1D shown in Figure 16(A). This is a cross-sectional STEM image of the area enclosed by the dotted line.

[0301] 16B to 16E, in Samples 1A to 1D, the conductor 226 and the conductor It was confirmed that the insulator 227 was formed. In addition, a part of the surface of the insulator 213 was removed. On the other hand, the cross-sectional STEM images of specimens 1A to 1D show that the Al residue No residue 230 was observed on the surface of the insulator 213.

[0302] <Elemental analysis of samples> Elemental analysis of the surface regions of the insulators 213 of Samples 1A to 1D was performed using EDX. The EDX measurement device used was the HD-2300 manufactured by Hitachi High-Technologies Corporation. The device used was an EDX Si(Li) detector manufactured by EDAX.

[0303] In EDX measurement, each point in the analysis area of the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this example, EDX analysis of the surface region of the insulator 213 indicated by dots in FIGS. The peaks in the spectrum are due to electron transitions to the K shell of C atoms, electron transitions to the K shell of O atoms, and F atoms. electron transition to the K shell of Al atom, electron transition to the K shell of Si atom, Pt electron transitions to the M shell of an atom, electron transitions to the K shell of a Cu atom, and electron transitions to the K shell of a Ga atom The ratio of each atom was calculated.

[0304] The table below shows the ratio of atoms present in the surface region of the insulator 213 of Samples 1A to 1D.

[0305] [Table 1]

[0306] As shown in Table 1, the ratio of Al atoms in the surface region of the insulator 213 of sample 1A is 0.5 atom. The ratio of Al atoms in the surface region of the insulator 213 of sample 1B was 1.0 The ratio of Al atoms in the surface region of the insulator 213 of sample 1C was The Al atoms in the surface region of the insulator 213 of sample 1D were 1.8 atomic %. The ratio was 3.6 atomic %. Compared with sample 1A, the insulator 213 of sample 1B It was found that the ratio of Al atoms in the surface region was high. It was confirmed that Al residue 230 was formed on the surface of the insulator 213. Compared with A, the ratio of Al atoms in the surface region of the insulator 213 of specimens 1C and 1D is large. In other words, ashing with oxygen and resist stripping using a resist remover were found to be effective. By removing the mask, Al residue 230 is formed on the surface of the insulator 213. was confirmed.

[0307] As described above, the structure shown in this embodiment can be used in appropriate combination with other embodiment modes. [Explanation of symbols]

[0308] FN Floating Node 80 Capacitor element 80a Capacitor 80b Capacitor element 80c Capacitor 80d Capacitor 81 Insulator 82 Conductors 82a Conductor 82b Conductor 83 Insulator 84 Conductors 85 Insulator 86 Insulator 102 Insulator 103 Insulator 104 Insulator 106 Insulator 107 Insulators 108 Insulator 114 Insulator 115 Insulator 116 Insulator 210 Substrate 212 Insulator 213 Insulator 220 Conductors 221 Conductors 222 Conductors 223 Conductors 225 Conductors 226 Conductors 227 Conductors 230 Metal A residue 230a Metal A residue 230b Metal A residue 240 membrane 240a membrane 240b membrane 250 groove 250a groove 250b groove 250c groove 280 transistors 283 Channel formation region 284 Low concentration p-type impurity region 285 High concentration p-type impurity region 286 Insulators 287 Conductors 288 Side wall 290 transistors 301 Insulators 302 Insulators 303 Insulators 310 Conductors 310a Conductor 310b conductor 400 transistors 400a transistor 400c transistor 400d transistor 401 Insulator 402 Insulator 404 Conductors 404a Conductor 404b Conductor 404c conductor 406 Oxide 406a Oxide 406a1 Oxides 406a2 Oxides 406b Oxide 406b1 Oxides 406b2 Oxides 406c oxide 409 Insulator 410 Insulator 412 Insulator 416a1 Conductors 416a2 Conductor 417 Barrier membrane 417a1 Barrier film 417a2 Barrier film 418 Barrier membrane 419a Insulator 419b Insulator 426a area 426b area 426c area 501 PCB 504 Insulator 505 Insulator 514 Element isolation region 521 Conductors 522 Conductors 525 Conductors 526 Conductors 527 Conductors 528 Conductors 529 Conductors 534 Insulator 536 Insulator 537 Insulator 538 Insulator 539 Insulator 1000 Semiconductor device 1000b semiconductor device 2910 Information terminal 2911 Case 2912 Display section 2913 Camera 2914 Speaker section 2915 Operation switch 2916 External connection part 2917 Mike 2920 Notebook Personal Computer 2921 Case 2922 Display section 2923 keyboard 2924 Pointing Device 2940 video camera 2941 Case 2942 Case 2943 Display section 2944 Operation switch 2945 Lens 2946 Connection 2950 Information terminal 2951 Case 2952 Display section 2960 Information Terminal 2961 Case 2962 Display section 2963 bands 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 icons 2980 Automobiles 2981 Body 2982 wheels 2983 Dashboard 2984 Light 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring

Claims

1. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitance element; one of a source and a drain of the second transistor is electrically connected to one electrode of the capacitor; a gate of the first transistor is electrically connected to one electrode of the capacitor; a first insulating layer disposed above the gate of the second transistor; a first conductive layer that is disposed so as to be in contact with an upper surface of the first insulating layer and has a function of electrically connecting a gate of the first transistor and one electrode of the capacitor; a second insulating layer having a first region that functions as a gate insulating layer of the second transistor and a second region that functions as a dielectric layer of the capacitive element; a second conductive layer disposed above the second region and functioning as the other electrode of the capacitance element; a third insulating layer having a region in contact with a side surface of the first conductive layer and a region in contact with a top surface of the first conductive layer; a fourth insulating layer having a region in contact with the upper surface of the third insulating layer; a gate of the first transistor does not overlap with an oxide semiconductor of the second transistor; the first insulating layer has a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer; the fourth region is a region in which the film thickness of the first insulating layer is smaller than that of the third region, the fourth insulating layer has a region in contact with an upper surface of the first insulating layer in the fourth region; an oxide semiconductor layer included in the second transistor has a region overlapping with the second region; In a plan view, a channel width direction of the second transistor is a first direction, In a plan view, a channel length direction of the second transistor is a second direction, a width of the oxide semiconductor layer in a region overlapping with the second region in the first direction in a plan view is larger than a channel width of the second transistor; a width of the second conductive layer in the second direction in a plan view is greater than a channel length of the second transistor; a width of the second conductive layer in the second direction in a plan view is larger than a width of a gate of the second transistor; In a plan view, the width of the second conductive layer in the first direction is larger than the width of the first conductive layer.

2. In claim 1, The semiconductor device, wherein the oxide semiconductor contains at least indium or zinc.

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