Display device

Abstract

To provide a liquid crystal display device in which a pixel, including a thin film transistor using an oxide semiconductor, has an improved aperture ratio.SOLUTION: The liquid crystal display device includes a plurality of pixels each including the thin film transistor and a pixel electrode. The pixel is electrically connected to first wiring functioning as a scan line. The thin film transistor includes an oxide semiconductor layer over the first wiring via a gate insulating film. The oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. The pixel electrode and the oxide semiconductor layer overlap with each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device and to an electronic device equipped with the liquid crystal display device. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of glass substrates. On the other hand, thin film transistors using crystalline silicon have high field effect mobility. However, a crystallization process such as laser annealing is required, and enlarging the glass substrate is essential. However, it has the characteristic of not being adaptable.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-G Thin film transistors were fabricated using a-Zn-O oxide semiconductors and used as switches in liquid crystal display devices. Patent Document 1 discloses a technique used in a switching element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-99887 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors that use oxide semiconductors for the channel region are made of amorphous silicon. The field-effect mobility is higher than that of thin film transistors using the same in the panel region. A pixel including a thin film transistor formed using an oxide semiconductor is used in a liquid crystal display device or the like. It is expected to be applied to display devices. It is also expected to be applied to 3D displays, 4k2k displays, and other displays. In LCD devices with added value, the area per pixel is expected to become smaller. On the other hand, there is a demand for a liquid crystal display device having pixels with an improved aperture ratio.

[0006] Therefore, the present invention provides a pixel having a thin film transistor using an oxide semiconductor. An object of the present invention is to provide a liquid crystal display device that can improve the display efficiency. [Means for solving the problem]

[0007] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a pixel electrode. The thin film transistor is electrically connected to a first wiring that functions as a scan line. an oxide semiconductor layer provided on a wiring of the first gate electrode via a gate insulating film, The first wiring is provided so as to extend beyond the region where the first wiring is provided, and the pixel electrode and the oxide semiconductor layer and are provided so as to overlap each other.

[0008] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a pixel electrode. , electrically connected to a first wiring functioning as a scanning line and a second wiring functioning as a signal line. The thin film transistor is formed on an oxide film provided on the first wiring via a gate insulating film. The oxide semiconductor layer is provided so as to extend beyond the region where the first wiring is provided. The second wiring extends on the gate insulating film on the first wiring and is connected to the oxide semiconductor layer. The liquid crystal display device has a pixel electrode and an oxide semiconductor layer that overlap each other.

[0009] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a pixel electrode. , electrically connected to a first wiring functioning as a scanning line and a second wiring functioning as a signal line. The thin film transistor is formed on an oxide film provided on the first wiring via a gate insulating film. The oxide semiconductor layer is provided so as to extend beyond the region where the first wiring is provided. The second wiring is formed on the gate insulating film on the first wiring and the interlayer insulating film on the gate insulating film. The pixel electrode and the oxide semiconductor layer are overlapped with each other. It is a liquid crystal display device. [Effects of the Invention]

[0010] When manufacturing a pixel having a thin film transistor using an oxide semiconductor, it is necessary to improve the aperture ratio. Therefore, a liquid crystal display device having a high-definition display portion can be obtained. [Brief explanation of the drawings]

[0011] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a liquid crystal display device. [Figure 2] FIG. 1 is a cross-sectional view illustrating a liquid crystal display device. [Figure 3] FIG. 1 is a top view illustrating a liquid crystal display device. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a liquid crystal display device. [Figure 5] FIG. 1 is a top view illustrating a liquid crystal display device. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a liquid crystal display device. [Figure 7] FIG. 1 is a circuit diagram illustrating a liquid crystal display device. [Figure 8]FIG. 1 is a circuit diagram illustrating a liquid crystal display device. [Figure 9] 1A and 1B are a circuit diagram and a timing chart illustrating a liquid crystal display device. [Figure 10] FIG. 1 is a circuit diagram illustrating a liquid crystal display device. [Figure 11] FIG. 1 is a circuit diagram illustrating a liquid crystal display device. [Figure 12] 1A and 1B are diagrams illustrating electronic devices. [Figure 13] 1A and 1B are diagrams illustrating electronic devices. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a liquid crystal display device. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. It should be noted that the present invention is not limited to the following description. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. and the repeated explanation will be omitted.

[0013] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0014] In this specification, terms such as first, second, and third are used to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0015] (Embodiment 1) In this embodiment, as an example, a thin film transistor (hereinafter also referred to as a TFT) and the T The electrodes (also simply called pixel electrodes) connected to the FT are shown. The liquid crystal display device will be explained. Note that a pixel is an element provided in each pixel of the display device, for example, For example, thin film transistors, electrodes that function as pixel electrodes, and wiring are used to generate electrical signals. A pixel is a group of elements that control the display of a color filter. Each pixel can be used to control one color element whose brightness can be controlled. Therefore, for example, in the case of a color display device consisting of RGB color elements, The smallest unit of an image is made up of three pixels: an R pixel, a G pixel, and a B pixel. , an image can be obtained using a plurality of pixels.

[0016] When we say that A and B are connected, we mean that A and B are electrically connected. This includes the case where A and B are directly connected, and the case where A and B are directly connected. Specifically, the object is an object that has an electrical effect. A and B are connected via a switching element, and when the switching element is turned on, A and When A and B are connected via a resistor element, and both ends of the resistor element When the potential difference generated at the terminals is small enough not to affect the operation of the circuit including A and B, However, when considering the circuit operation, it is acceptable to regard the part between A and B as the same node. This represents the case where the

[0017] First, a top view of a pixel is shown in FIG. 1(A). The structure of the TFT shown in FIG. 1(A) is as follows: It has a bottom-gate structure, and the oxide semiconductor that forms the channel region from the gate wiring On the other side of the layer, there is a wiring layer that becomes the source electrode and drain electrode of the TFT. A staggered configuration is shown.

[0018] The pixel 100 shown in FIG. 1A includes a first wiring 101 functioning as a scan line, a second wiring 102 functioning as a signal line, and a third wiring 103 functioning as a gate line. The functional second wiring 102A, the oxide semiconductor layer 103, the capacitance line 104, and the pixel electrode 105 are The pixel 100 shown in FIG. 1A includes an oxide semiconductor layer 103 and a pixel electrode 105. A third wiring 102B is provided for electrically connecting the thin film transistor 106. can be.

[0019] The first wiring 101 also functions as a gate of the thin film transistor 106. The wiring 102A is connected to one of the source electrode or the drain electrode of the thin film transistor 106. The third wiring 102B also functions as one electrode of the storage capacitor. It also functions as the other of the source electrode and the drain electrode of the capacitor 106. The line 104 is a wiring that functions as the other electrode of the storage capacitor. The capacitor line 104 is provided in the same layer, and the second wiring 102A and the third wiring 102B are provided in the same layer. The third wiring 102B and the capacitor line 104 are provided so as to partially overlap each other. This forms a storage capacitor for the liquid crystal element.

[0020] Note that the oxide semiconductor layer 103 included in the thin film transistor 106 is formed on the first wiring 101. The oxide semiconductor layer 103 is provided on the first wiring. It is provided outside the area where 101 is provided.

[0021] Note that A protrudes from B when looking at the top view of the stacked elements A and B. In this case, the ends of the elements do not coincide, and A extends outward beyond the end of B.

[0022] FIG. 1(B) shows the cross-sectional structure between the dashed line A1 and A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), a gate electrode is formed on a substrate 111 via an underlayer 112. The first wiring 101 and the capacitor line 104 are provided. A gate insulating film 113 is provided to cover the line 104. An oxide semiconductor layer 103 is provided on the second wiring. The oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B are provided. An acid film functioning as a passivation film is formed on the wiring 102A and the third wiring 102B. An oxide insulating layer 114 is provided. An opening is formed in the oxide insulating layer 114. The pixel electrode 105 and the third wiring 102B are connected in the opening. The wiring 102B and the capacitance line 104 form a capacitance element with the gate insulating film 113 as a dielectric. are.

[0023] The pixels shown in FIGS. 1A and 1B are formed by disposing a plurality of pixels on a substrate 700 as shown in FIG. 701 are arranged in a matrix on a substrate 700. 7 shows a configuration including a display unit 702, a scanning line driver circuit 703, and a signal line driver circuit 704. The pixel 701 is supplied with a first wiring 101 connected to a scanning line driving circuit 703. The scanning signal applied determines whether each row is in a selected state or a non-selected state. The pixel 701 selected by the signal is connected to the second line driver circuit 704. Line 102A provides a video voltage (also called an image signal, a video signal, or video data). will be provided.

[0024] In FIG. 7, a scanning line driver circuit 703 and a signal line driver circuit 704 are provided on a substrate 700. However, either the scanning line driver circuit 703 or the signal line driver circuit 704 The pixel portion 702 may be provided on the substrate 700. Alternatively, only the pixel portion 702 may be provided on the substrate 700. It may also be configured so that

[0025] In FIG. 7, a pixel section 702 has a plurality of pixels 701 arranged in a matrix (stripe arrangement). It should be noted that the pixels 701 do not necessarily have to be arranged in a matrix. For example, the pixels 701 may be arranged in a delta arrangement or a Bayer arrangement. The display method in the element section 702 is either the progressive method or the interlace method. In addition, the color elements controlled by pixels when displaying colors are RGB ( It is not limited to three colors (R is red, G is green, B is blue), but may be more than three, for example, RGBW ( W is white), or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may differ for each dot of the color element.

[0026] In FIG. 7, the first wiring 101 and the second wiring 102A are arranged in a number equal to the number of pixels in the row and column directions. The first wiring 101 and the second wiring 102A are wires that form pixels. The number of sub-pixels (also called sub-pixels) or the number of transistors in a pixel In addition, the number of the first wiring 101 and the second wiring 102 may be increased between pixels. The pixel 701 may be driven by sharing the pixel 102A.

[0027] In FIG. 1A, the shape of the TFT is shown as if the second wiring 102A is rectangular. However, the shape of the third wiring 102B is such that it surrounds the third wiring 102B (specifically, U-shaped or C-shaped), The area of the region where carriers move may be increased to increase the amount of current that flows.

[0028] The width of the first wiring 101 other than the region that will become the thin film transistor 106 is partially narrowed. By reducing the width of the first wiring, the aperture ratio of the pixel can be reduced. Improvements can be made.

[0029] The aperture ratio represents the area through which light passes per unit area. When the area occupied by the non-transmitting material becomes larger, the aperture ratio decreases and the area occupied by the light-transmitting material becomes larger. The larger the area occupied, the higher the aperture ratio. By reducing the area occupied by the overlapping wiring, the capacitance line, and the size of the thin film transistor, This will improve the rate of speaking.

[0030] The thin film transistor has at least three regions including a gate, a drain, and a source. An element having terminals, and a channel region between a drain region and a source region, A current can be passed through the drain region, the channel region, and the source region. The source and drain vary depending on the transistor structure and operating conditions, so it is difficult to know which is which. It is difficult to determine whether the source or drain is the source or drain. The region that functions as a gate may not be called a source or drain. For example, they may be written as the first terminal and the second terminal. These may be referred to as the first electrode and the second electrode, or as the first region and the second region. There are cases where this happens.

[0031] Next, the method for manufacturing a pixel will be explained based on the top view and cross-sectional view shown in Figure 1(A) and (B). 2 will be used to explain.

[0032] First, a glass substrate can be used as the light-transmitting substrate 111. Preventing diffusion of impurities from the substrate 111 or ensuring close contact with each element provided on the substrate 111 The structure shown here is one in which a base film 112 is provided to improve the performance. There is no need to provide a

[0033] Next, a conductive layer is formed on the entire surface of the substrate 111, and then a first photolithography process is performed. A resist mask is formed, and unnecessary portions are removed by etching to form the first wiring 101, The capacitor line 104 is formed. At this time, at least the first wiring 101 and the end of the capacitor line 104 are The cross section at this stage is shown in Figure 2(A).

[0034] The first wiring 101 and the capacitance line 104 are made of a low resistance material such as aluminum (Al) or copper (Cu). It is desirable to form it from a conductive material, but aluminum alone has poor heat resistance and is prone to corrosion. Therefore, it is formed by combining with a heat-resistant conductive material. Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), An element selected from chromium (Cr), neodymium (Nd), scandium (Sc), or Alloys containing the above elements, or alloys containing a combination of the above elements, or alloys containing the above elements It is formed from a nitride containing the components.

[0035] In addition, the wiring and the like that constitute the TFT can be formed using inkjet or printing methods. These allow fabrication at room temperature, in low vacuum, or on large substrates. Since it can be manufactured without using a photomask, the transistor layout can be It can be easily changed. Furthermore, since there is no need to use resist, the material cost is low. This reduces the number of processes. In addition, resist masks can be formed using inkjet or printing methods. Resist can be formed only in the required areas using inkjet or printing methods. By forming a resist mask by exposure and development, it is possible to This allows for lower costs.

[0036] In addition, a multi-tone mask is used to create a resist mask having multiple (typically two types) of thickness regions. A block may be formed, and wiring and the like may be formed.

[0037] Next, an insulating film (hereinafter referred to as a gate insulating film 113) is formed on the first wiring 101 and the capacitance line 104. The gate insulating film 113 is formed by sputtering or the like.

[0038] For example, the gate insulating film 113 is formed using a silicon oxide film by a sputtering method. Of course, the gate insulating film 113 is not limited to such a silicon oxide film, and may be a nitride oxide film. Other insulating films such as silicon dioxide film, silicon nitride film, aluminum oxide film, and tantalum oxide film The insulating film may be formed as a single layer or a laminated structure made of these materials.

[0039] Before forming an oxide semiconductor film, a reverse sintering process was performed in which argon gas was introduced to generate plasma. It is preferable to remove dust adhering to the surface of the gate insulating film 113 by sputtering. Instead of the argon atmosphere, nitrogen, helium, etc. may be used. It may be carried out in an atmosphere containing oxygen, N2O, etc. Also, in an argon atmosphere, Cl2 Alternatively, the reaction may be carried out in an atmosphere containing CF4 or the like.

[0040] Next, an oxide semiconductor is deposited on the gate insulating film 113 by plasma treatment of the surface of the gate insulating film 113. After the treatment, the oxide semiconductor is deposited without being exposed to the air. This results in a higher field-effect transport rate compared to silicon-based semiconductor materials such as amorphous silicon. The oxide semiconductor can be, for example, zinc oxide (ZnO), oxide Tin oxide (SnO2) can also be used. In addition, adding In or Ga to ZnO It is also possible to do so.

[0041] InMO3(ZnO) as an oxide semiconductor x A thin film expressed as (x>0) can be used. M can be gallium (Ga), iron (Fe), nickel (Ni), manganese (M n) and cobalt (Co). M can be Ga, or it can be any of the above other than Ga, such as Ga and Ni or Ga and Fe. In some cases, a metal element is contained. In addition, in the above oxide semiconductor, the metal contained as M is In addition to the transition metal elements, Fe, Ni and other transition metal elements, or the oxides of these transition metals, may be present as impurity elements. For example, the oxide semiconductor layer is made of In-Ga-Zn-O. A membrane can be used.

[0042] Oxide semiconductor (InMO3(ZnO) x (x>0) film) as In-Ga-Zn-O system film Instead of InMO3(ZnO), M can be another metal element. x (x>0) membrane may be used In addition to the above, oxide semiconductors include In-Sn-Zn-O, In-Al-Z nO system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system , In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, A Zn—O-based oxide semiconductor can be used.

[0043] Note that in this embodiment, an In—Ga—Zn—O-based oxide semiconductor is used. The target used is In2O3:Ga2O3:ZnO=1:1:1. The distance between the target and the sample was 100 mm, the pressure was 0.6 Pa, the DC power was 0.5 kW, and the acid The film is formed in a nitrogen atmosphere (oxygen flow rate 100%). This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and improves film thickness distribution. This is preferable because the thickness becomes uniform.

[0044] The oxide semiconductor film was formed in the same chamber as the previous reverse sputtering. Alternatively, the film may be formed in a chamber different from the chamber in which the previous reverse sputtering was performed.

[0045] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias pulse. The sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used when:

[0046] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0047] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0048] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0049] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than 750°C, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. In this case, the heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is protected from exposure to the atmosphere, preventing water and hydrogen from re-entering the oxide semiconductor layer. In this embodiment, a process for dehydrating or dehydrogenating an oxide semiconductor layer is performed. From the heating temperature T, use the same furnace to a temperature that is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the temperature T. Dehydration or dehydrogenation under a rare gas (helium, neon, argon, etc.) atmosphere is not possible. Do the following.

[0050] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. A rare gas such as argon or nitrogen, which hardly reacts with the material to be treated by heat treatment. An inert gas is used.

[0051] The oxide semiconductor layer is subjected to a heat treatment at a temperature of 400°C or higher and lower than 750°C. This dehydration and dehydrogenation of the carbon dioxide prevents subsequent re-impregnation with water (H2O).

[0052] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0053] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or more, In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the crystallinity is high. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. It may also be a conductive film.

[0054] The oxide semiconductor layer becomes oxygen-deficient after the first heat treatment for dehydration or dehydrogenation. The oxide semiconductor layer after the first heat treatment has a lower resistance than the oxide semiconductor film immediately after deposition. The carrier concentration is also increased, preferably to 1×10 18 / cm 3 have a carrier concentration of This becomes an oxide semiconductor layer.

[0055] Next, a second photolithography step is performed to form a resist mask and etch the The unnecessary portions are removed by this process to form the oxide semiconductor layer 103 made of an oxide semiconductor. The first heat treatment on the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The etching method used in this case is wet etching or dry etching. The cross section at this stage is shown in Figure 2(B).

[0056] Next, a conductive film made of a metal material is formed on the oxide semiconductor layer by sputtering or vacuum deposition. The conductive film material is an element selected from Al, Cr, Ta, Ti, Mo, and W, or Examples include alloys containing the above elements or alloys that combine the above elements. In addition, when heat treatment is performed at 200 to 600°C, the conductive film must be heat-resistant enough to withstand this heat treatment. It is preferable to use aluminum alone, which has problems such as poor heat resistance and susceptibility to corrosion. Therefore, it is formed by combining it with a heat-resistant conductive material. Heat-resistant conductive material combined with Al Titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo ), chromium (Cr), neodymium (Nd), Sc (scandium), or is an alloy containing the above elements, an alloy combining the above elements, or It is formed from nitrides containing elements.

[0057] Here, the conductive film has a single-layer structure of a titanium film. The conductive film may also have a two-layer structure. Alternatively, a titanium film may be laminated on an aluminum film. An aluminum film containing Nd (Al-Nd) is layered on top of the Ti film, and then The conductive film may be a single layer of aluminum film containing silicon. It may also have a layered structure.

[0058] Next, a third photolithography process is performed to form a resist mask and then etching is performed. The unnecessary portions are removed to form the second wiring 102A and the third wiring 102B made of the conductive film. The etching method used in this case is either wet etching or dry etching. For example, ammonia hydrogen peroxide solution (31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: water The conductive film of the Ti film was etched by wet etching using a SiO2 / SiO2 ratio of 5:2:2. The second wiring 102A and the third wiring 102B are selectively etched to form the oxide semiconductor layer 10 The cross section at this stage is shown in Figure 2(C).

[0059] In addition, depending on the etching conditions, the oxide semiconductor The exposed areas of the layer may be etched, in which case the second wiring 102A and the third wiring The oxide semiconductor layer 103 in the region sandwiched between the wirings 102B is formed on the first wiring 101 by the second wiring 102B. The thickness of the oxide semiconductor layer is thinner than that of the oxide semiconductor layer in the region where the line 102A and the third wiring 102B overlap. do.

[0060] Next, the gate insulating film 113, the oxide semiconductor layer 103, the second wiring 102A, the third wiring 102B, and the An oxide insulating layer 114 is formed on the oxide semiconductor layer 102B. The first wiring 101 is in contact with the oxide insulating layer 114 with the gate insulating film 113 interposed therebetween. A region of the oxide semiconductor layer 103 overlapping with the first and second gate electrodes serves as a channel formation region.

[0061] The oxide insulating layer 114 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer can be formed by any suitable method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer. In this embodiment mode, a silicon oxide film is formed as the oxide insulating layer by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. In this embodiment, the substrate temperature is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. In air, oxygen, or a mixture of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used under an oxygen and rare gas atmosphere. A silicon oxide film can be formed by sputtering. The oxide insulating layer formed in contact with the body layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, an inorganic insulating film is used to block these substances from entering from the outside, typically an oxide film. A silicon film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. Note that the oxide insulating layer formed by a sputtering method is particularly dense, and impurities may be introduced into the adjacent layer. It can be used as a single layer as a protective film to suppress the diffusion phenomenon. Using a target doped with phosphorus (P) or boron (B), phosphorus (P) or boron (B) is doped into the oxide insulating layer. B) can also be added.

[0062] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0063] Note that the oxide insulating layer 114 is provided over and in contact with a region that serves as a channel formation region of the oxide semiconductor layer. It also functions as a channel protection layer.

[0064] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 300°C or lower) is performed. 50°C or less) may be carried out in an inert gas atmosphere or a nitrogen gas atmosphere. A second heat treatment is carried out at 250°C for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer 103 is heated in a state where a part of the oxide semiconductor layer 103 is in contact with the oxide insulating layer 114 .

[0065] The oxide semiconductor layer 103 whose resistance is reduced by the first heat treatment is in contact with the oxide insulating layer 114. When the second heat treatment is performed in this state, the region in contact with the oxide insulating layer 114 becomes an oxygen-excess state. As a result, the oxide insulating layer 114 of the oxide semiconductor layer 103 is in contact with the oxide insulating layer 114. The semiconductor layer 103 is made I-type (high resistance) in the depth direction.

[0066] Next, an opening 121 is formed in the oxide insulating layer 114 by a fourth photolithography process. The conductive film having light-transmitting properties is formed by forming a conductive film having light-transmitting properties. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The transparent conductive film (abbreviated as O) is formed by sputtering or vacuum deposition. Other materials for the conductive film include Al-Zn-O-based films containing nitrogen, i.e., Al-Zn-ON-based A film, a Zn-O-based film containing nitrogen, or a Sn-Zn-O-based film containing nitrogen may also be used. The zinc composition ratio (atomic %) of the Al-Zn-ON film is 47 atomic % or less. The aluminum composition ratio (atomic %) in the film is larger than the aluminum composition ratio (atomic %) in the film. %) is larger than the composition ratio (atomic %) of nitrogen in the film. It is done using a hydrochloric acid solution. However, since etching ITO is particularly prone to leaving residue, Indium oxide-zinc oxide alloy (In2O3-ZnO) to improve etching processability may also be used.

[0067] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0068] Next, a fifth photolithography step is performed to form a resist mask and then to perform etching. The unnecessary portions are removed to form the pixel electrode 105. The cross section at this stage is shown in FIG. Shown below.

[0069] In this way, a pixel having a thin film transistor 106 can be fabricated. These are arranged in a matrix to correspond to the individual pixels, forming a pixel section. This can be used as one of the substrates for manufacturing a sub-matrix liquid crystal display device. For convenience, this document refers to such a substrate as an active matrix substrate.

[0070] In an active matrix liquid crystal display device, pixels arranged in a matrix are By driving the element electrodes, a display pattern is formed on the screen. When a voltage is applied between the pixel electrode and the counter electrode corresponding to the pixel electrode, The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation is applied to the display panel. The display element such as a liquid crystal element is provided on the pixel electrode 105. do.

[0071] The advantages of the configuration of this embodiment described with reference to FIGS. 1 and 2 will be explained with reference to FIGS. 3(A) and 3(B). A detailed explanation will be given below.

[0072] 3A and 3B are enlarged views of the oxide semiconductor layer and its vicinity in the top view of FIG. 1A. In addition, the width of the oxide semiconductor layer 103 in FIG. 3A (W1 in FIG. 3A) is increased. The diagram shown in FIG. 3B corresponds to the width of the oxide semiconductor layer 103 (W2 in FIG. 3B). handle.

[0073] In the top view of the pixel in FIG. 1A in this embodiment, as shown in FIGS. In addition, an oxide semiconductor is formed on the first wiring 101 without branching the wiring from the first wiring 101. The second wiring 102A and the third wiring 102B are formed in the oxide semiconductor layer. The channel region formed between the first wiring 101 and the second wiring 102 is formed in an overlapping region on the first wiring 101. When the channel region of the oxide semiconductor layer 103 is irradiated with light, the TFT characteristics are varied. Therefore, the wiring branched from the first wiring 101 is used to ensure light blocking. This is a factor that reduces the aperture ratio of the pixel. An oxide semiconductor layer is provided over and overlaps with the first wiring 101, and a wiring branched from the first wiring 101 is formed. By not forming wiring, the aperture ratio can be improved. By using a light-transmitting oxide semiconductor layer as the semiconductor layer, is formed in a region that is shifted from the region where it overlaps with the first wiring 101, and the pixel Even if the electrode 105 overlaps the display, the aperture ratio is not reduced and display can be performed. Cut.

[0074] By forming an oxide semiconductor layer with a pattern larger than the specified size, it is possible to Even if the oxide semiconductor layer is formed at a position that is out of alignment, there is no problem of malfunction and a decrease in aperture ratio. Therefore, it is possible to provide a good display without any problem. This makes it easier to produce risk substrates, improving yields.

[0075] As described above, by using the structure described in this embodiment, a thin film using an oxide semiconductor When manufacturing a pixel having a film transistor, the aperture ratio can be improved. As a result, a liquid crystal display device having a high-definition display portion can be obtained.

[0076] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0077] (Embodiment 2) An example of configuring pixels of a display device having a TFT configuration different from that of the above embodiment will be described below.

[0078] A top view of a pixel having a structure different from that of Embodiment 1 is shown in FIG. The TFT structure shown in Figure 1 is a bottom gate structure, and the channel is On the opposite side of the oxide semiconductor layer that will become the gate region, A so-called inverted staggered structure having line layers is shown.

[0079] The pixel 400 shown in FIG. 4A includes a first wiring 401 functioning as a scan line, a second wiring 402 functioning as a signal line, and a third wiring 403 functioning as a gate line. The functional second wiring 402A, the oxide semiconductor layer 403, the capacitor line 404, and the pixel electrode 405 are In addition, a third insulating film for electrically connecting the oxide semiconductor layer 403 and the pixel electrode 405 is provided. The first wiring 401 has a thin film transistor 406. The second wiring 402A also functions as the gate of the transistor 406. The third wiring 402B also functions as one of the source electrode and the drain electrode. The wiring that functions as the other of the source electrode or drain electrode and one electrode of the storage capacitor. The capacitor line 404 is a wiring that functions as the other electrode of the storage capacitor.

[0080] The first wiring 401 and the capacitance line 404 are provided in the same layer, and the second wiring 402A and the The third wiring 402B and the capacitance line 404 are provided in the same layer. They are partially overlapped to form a storage capacitor for the liquid crystal element. The oxide semiconductor layer 403 of the gate electrode 406 is formed on the first wiring 401 by a gate insulating film (not shown). The oxide semiconductor layer 403 is provided between the first wiring 401 and the oxide semiconductor layer 403. It is provided outside the area.

[0081] FIG. 4(B) shows the cross-sectional structure between the dashed line A1 and A2 in FIG. 4(A). In the cross-sectional structure shown in FIG. 4(B), a gate electrode is formed on a substrate 411 via an underlayer 412. The first wiring 401 and the capacitor line 404 are provided. A gate insulating film 413 is provided to cover the line 404. An oxide semiconductor layer 403 is provided on the second wiring 401. The oxide semiconductor layer 403, the second wiring 402A, and the third wiring 402B are provided. An acid film that functions as a passivation film is formed on the wiring 402A and the third wiring 402B. An oxide insulating layer 414 is provided. An opening is formed in the oxide insulating layer 414. The pixel electrode 405 and the third wiring 402B are connected in the opening. The wiring 402B and the capacitance line 404 form a capacitance element with the gate insulating film 413 as a dielectric. are.

[0082] The pixels shown in FIGS. 4A and 4B are the same as those described in FIGS. 1A and 1B of the first embodiment. Similarly, a plurality of pixels 701 arranged in a matrix on a substrate 700 in FIG. The explanation regarding FIG. 7 is the same as that in the first embodiment.

[0083] The cross-sectional view shown in FIG. 4(B) is the same as the cross-sectional view shown in FIG. 1(B). The method is the same as that explained in FIG. 2 in the first embodiment.

[0084] The advantages of the configuration of this embodiment described with reference to FIGS. 4(A) and 4(B) are shown in FIGS. 5(A) and 5(B). ) will be used for detailed explanation.

[0085] 5A and 5B are enlarged views of the oxide semiconductor layer and its vicinity in the top view of FIG. 4A. In addition, the width of the oxide semiconductor layer 403 in FIG. 5A (W1 in FIG. 5A) is increased. The diagram shown in FIG. 5B corresponds to the width (W2 in FIG. 5B) of the oxide semiconductor layer 403. handle.

[0086] In the top view of the pixel in FIG. 4A in this embodiment, as shown in FIGS. In addition, an oxide semiconductor is formed on the first wiring 401 without branching the wiring from the first wiring 401. The second wiring 402A and the third wiring 402B are formed in the oxide semiconductor layer. The channel region formed between the first wiring 401 and the second wiring 402 is formed in an overlapping region on the first wiring 401. In addition, in this embodiment, the oxide semiconductor layer 403 is a gate insulating layer over the first wiring 401. The insulating film extends to contact the second wiring 402A and the third wiring 402B. The semiconductor layer 403 has a channel region that is irradiated with light, which causes variations in the TFT characteristics. Therefore, it is necessary to reliably block light by using wiring branched from the first wiring 401. This has also been a factor in reducing the aperture ratio of the pixel. An oxide semiconductor layer is provided so as to overlap the first wiring 401, and a wiring branched from the first wiring 401 is formed. and a second wiring 402A extending on the gate insulating film on the first wiring 401. The third wiring 402B is in contact with the oxide semiconductor layer 403, thereby improving the aperture ratio. In addition, a light-transmitting oxide semiconductor layer can be used as a semiconductor layer of a thin film transistor. By using the first wiring 401, the oxide semiconductor layer can be moved from a region overlapping with the first wiring 401 to a region overlapping with the first wiring 402 at a design position. Even if the pixel electrode 405 is formed in a region shifted from the pixel electrode 405 and overlaps the pixel electrode 405, the aperture ratio is not reduced. The display can be performed without any need for a

[0087] The second wiring 402A and the third wiring 402B extending over the first wiring 401 shown in FIG. The second wiring 402B may be provided so as to overlap the first wiring 401. 2A and the third wiring 402B may be routed in a meandering manner, The wiring may be arranged in a straight line.

[0088] By forming an oxide semiconductor layer with a pattern larger than the specified size, it is possible to Even if the oxide semiconductor layer is formed at a position that is out of alignment, there is no problem of malfunction and a decrease in aperture ratio. Therefore, it is possible to provide a good display without any problem. This makes it easier to produce risk substrates, improving yields.

[0089] As described above, by using the structure described in this embodiment, a thin film using an oxide semiconductor When manufacturing a pixel having a film transistor, the aperture ratio can be improved. As a result, a liquid crystal display device having a high-definition display portion can be obtained.

[0090] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0091] (Embodiment 3) An example of configuring pixels of a display device having a TFT configuration different from that of the above embodiment will be described below.

[0092] 6A and 6B are top views and cross-sectional views of a pixel different from the configuration of Embodiment 2. The structure of the top view shown in FIG. 6(A) is the same as that shown in FIG. 4(A). The structure shown in the cross section of FIG. 6(B) is the same as that shown in the cross section of FIG. The difference from the previous structure is that an insulating layer 601A is provided between the first wiring 401 and the second wiring 402A. and an insulating layer 601 between the first wiring 401 and the third wiring 402B. 6(A) is provided. 4, an insulating layer 601 is formed between the capacitor line 404 and the second wiring 402A. A configuration having A is shown.

[0093] A second wiring 402A and a third wiring 402B are extended on the first wiring 401 and the capacitance line 404. When the first wiring 401 and the second wiring 402 are provided in a separated state, depending on the thickness of the gate insulating film 413, The wiring 402A, the first wiring 401 and the third wiring 402B, and the capacitance line 404 and the second wiring 402B are connected to each other. Therefore, a parasitic capacitance occurs between the wiring 402A and the wiring 402B. As shown in FIG. 6, the insulating layers 601A and 601B are provided to reduce parasitic capacitance and prevent errors. It is possible to reduce malfunctions and the like.

[0094] As described above, by using the structure described in this embodiment, a thin film using an oxide semiconductor When manufacturing a pixel having a film transistor, the aperture ratio can be improved. In this embodiment, in addition to the configuration of the second embodiment, it is possible to reduce the parasitic capacitance. Therefore, the liquid crystal display device has a high-definition display portion and is capable of reducing malfunctions. It is possible.

[0095] (Fourth embodiment) In this embodiment, a pixel configuration and pixel operation applicable to a liquid crystal display device will be described. explain.

[0096] FIG. 8A is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. The pixel includes a transistor 881, a liquid crystal element 882, and a capacitor 883. The gate of the transistor 881 is electrically connected to a wiring 885. The second terminal of the transistor 881 is electrically connected to the first terminal of the liquid crystal element 882. The second terminal of the liquid crystal element 882 is electrically connected to the wiring 887. A first terminal of the capacitor 883 is electrically connected to a first terminal of the liquid crystal element 882. The second terminal of the element 883 is electrically connected to the wiring 886 .

[0097] The wiring 884 can function as a signal line. The signal line is a line that receives an input from outside the pixel. The wiring 885 functions as a scanning line. The scan line is a wiring for controlling the on / off of the transistor 881. The wiring 886 can function as a capacitor line. The wiring is for applying a predetermined voltage to the two terminals. The transistor 881 acts as a switch. The capacitor 883 can function as a storage capacitor. The storage capacitor keeps applying the signal voltage to the liquid crystal element 882 even when the switch is off. The wiring 887 can function as a counter electrode. The counter electrode is a wiring for applying a predetermined voltage to the second terminal of the liquid crystal element 882. The functions that each wiring can have are not limited to these, and various functions can be performed. For example, by changing the voltage applied to the capacitance line, the voltage applied to the liquid crystal element can be The voltage can also be adjusted.

[0098] FIG. 8B is a diagram showing an example of a pixel configuration that can be applied to a liquid crystal display device. 8A, the pixel configuration example shown in FIG. 8B is different from the pixel configuration example shown in FIG. 8A in that the wiring 887 is omitted. The second terminal of the liquid crystal element 882 and the second terminal of the capacitor element 883 are electrically connected. Except for this difference, the pixel configuration is the same as the example shown in FIG. 8(A). The pixel configuration example shown in FIG. 8B is particularly suitable for liquid crystal elements in a lateral electric field mode (IPS mode, FFS mode). This is because the liquid crystal element is in the horizontal electric field mode. In this case, the second terminal of the liquid crystal element 882 and the second terminal of the capacitor element 883 are formed on the same substrate. Therefore, the second terminal of the liquid crystal element 882 and the second terminal of the capacitor element 883 can be electrically connected. This is because it is easy to efficiently connect the pixels. Therefore, the wiring 887 can be omitted, which simplifies the manufacturing process and reduces manufacturing costs. This can reduce the

[0099] A plurality of pixel configurations shown in FIG. 8(A) or FIG. 8(B) can be arranged in a matrix. In this way, the display section of the liquid crystal display device is formed, and various images can be displayed. FIG. 9A shows a pixel configuration in which a plurality of pixels shown in FIG. 8A are arranged in a matrix. 9A is a diagram showing a circuit configuration in the case where a plurality of pixels included in a display unit are displayed. The figure shows four pixels extracted from the pixel. The pixel in the i-th column and j-th row (i and j are natural numbers) The pixel located at is expressed as pixel 880_i,j, and the pixel 880_i,j is connected to a wiring 884 _i, wiring 885_j, and wiring 886_j are electrically connected to each other. For 880_i+1,j, wiring 884_i+1, wiring 885_j, wiring 886_j Similarly, for the pixel 880_i,j+1, the wiring 884_i, The pixel 880_j+1 is electrically connected to the wiring 885_j+1 and the wiring 886_j+1. For i+1, j+1, wiring 884_i+1, wiring 885_j+1, wiring 886_j +1. Each wiring is electrically connected to multiple pixels belonging to the same column or row. In the pixel configuration shown in FIG. 9A, the wiring 887 is The opposing electrode is common to all pixels, so the wiring 887 is The natural numbers i and j are not used. Therefore, even in the configuration in which the wiring 887 is shown, the wiring 887 is not essential and can be omitted by sharing it with other wiring, etc.

[0100] The pixel configuration shown in FIG. 9(A) can be driven in various ways. The LCD is driven by a method called "burn-in" which prevents deterioration of the LCD element. FIG. 9B shows a case where dot inversion driving, which is one of AC driving methods, is performed. 9A. The timing chart of the voltages applied to the respective wirings in the pixel configuration shown in FIG. This is a diagram showing a gate in which AC driving is performed by performing dot inversion driving. In this case, the flickering that is visible can be suppressed. , a signal 985_j input to a wiring 885_j, a signal 985_j input to a wiring 885_j+1 85_j+1, signal 984_i input to wiring 884_i, signal 984_i input to wiring 884_i+1 9 shows the signal 984_i+1 supplied to the line 886, and the voltage 986 supplied to the line 886.

[0101] In the pixel configuration shown in FIG. 9A, in a pixel electrically connected to the wiring 885_j, The switch in the jth gate selection period is in the selected state (on state) during one frame period. In the jth gate selection period, the gate is in a non-selected state (off state). After the jth gate selection period, the j+1th gate selection period is provided. In this way, all pixels are selected in sequence within one frame period. In the timing chart, when the voltage is in a high state (high level), the switching When the voltage is low (low level), the switch is in a non-selected state.

[0102] In the timing chart shown in FIG. 9B, the jth gate in the kth frame (k is a natural number) During the port selection period, a positive signal voltage is applied to the wiring 884_i used as a signal line, A negative signal voltage is applied to the wiring 884_i+1. In one gate selection period, a negative signal voltage is applied to the wiring 884_i. A positive signal voltage is applied to +1. After that, each signal line is As a result, in the kth frame, the pixel 8 80_i,j is applied with a positive signal voltage, pixel 880_i+1,j is applied with a negative signal voltage, and pixel 880 _i,j+1 has a negative signal voltage, and pixel 880_i+1,j+1 has a positive signal voltage. Then, in the k+1th frame, In this case, a signal voltage having a polarity opposite to that of the signal voltage written in the k-th frame is written. As a result, in the (k+1)th frame, the pixel 880_i,j receives a negative signal voltage, A positive signal voltage is applied to pixel 880_i+1,j, a positive signal voltage is applied to pixel 880_i,j+1, and a positive signal voltage is applied to pixel 880_i,j+2. A negative signal voltage is applied to each of the elements 880_i+1, j+1. In the same frame, signal voltages of different polarities are applied to adjacent pixels. Furthermore, the polarity of the signal voltage in each pixel is reversed every frame. The dot inversion driving method is the one that suppresses the deterioration of the liquid crystal element while maintaining the display quality. This can reduce the flicker that is visible when the entire image or part of the image being displayed is uniform. In addition, the wiring 886 is added to all wirings 886 including the wiring 886_j and the wiring 886_j+1. The voltage can be a constant voltage. Although the signal voltage is indicated only as polarity, in reality, various The signal voltage value can be set as follows. In this example, the polarity is inverted for each dot (pixel). However, the present invention is not limited to this, and the polarity can be reversed for each set of pixels. For example, by inverting the polarity of the signal voltage written every two gate selection periods, This reduces the power consumption required for writing. It is also possible to invert the polarity for each line (source line inversion) or to invert the polarity for each line (gate line inversion). It is also possible to reverse the image.

[0103] Next, the liquid crystal element is a vertical alignment (VA) liquid crystal display, typically an MVA mode or a PVA mode. This section describes a pixel configuration and driving method that are particularly preferable for the VA mode. The LCD panel has many advantages, such as no rubbing process required during manufacturing, minimal light leakage during black display, and low driving voltage. However, the image quality deteriorates when the screen is viewed from an angle (narrow viewing angle). In order to widen the viewing angle in the VA mode, the following problems are encountered: As shown in (B), a pixel configuration having multiple sub-pixels in one pixel is used. In the pixel configuration shown in FIG. 10(A) and FIG. 10(B), the pixel 1080 is An example of a case where two sub-pixels (a first sub-pixel 1080-1 and a second sub-pixel 1080-2) are included. The number of sub-pixels in one pixel is not limited to two, and various numbers are possible. The larger the number of sub-pixels, the wider the viewing angle can be. The plurality of sub-pixels can have the same circuit configuration. The following description will be given assuming that the first subpixel 108 has the same circuit configuration as that shown in FIG. 0-1 includes a transistor 1081-1, a liquid crystal element 1082-1, and a capacitance element 1083-1. The connections between the components are in accordance with the circuit configuration shown in FIG. 8(A). Similarly, the second subpixel 1080-2 includes a transistor 1081-2 and a liquid crystal element 1082- 2, and a capacitance element 1083-2, and the respective connections are as shown in FIG. This will be in accordance with the road configuration.

[0104] The pixel configuration shown in FIG. 10(A) uses a scanning line for two sub-pixels that make up one pixel. There are two wires 1085 (wire 1085-1 and wire 1085-2) that are used as signal lines. 1084 is used as a capacitor line, and one wiring 1086 is used as a capacitor line. In this way, by sharing the signal line and the capacitance line between two sub-pixels, The throughput can be improved and the signal line driver circuit can be simplified. This reduces manufacturing costs and the number of connections between the LCD panel and the driver circuit IC. The pixel configuration shown in FIG. 10(B) is a pixel configuration in which two sub-pixels are arranged in a single pixel. For each pixel, there is one wiring 1085 used as a scanning line, and one wiring 10 The wiring 1084 has two wirings 1084 (wiring 1084-1 and wiring 1084-2) and is used as a capacitance line. In this way, the scanning lines and the capacitance lines are connected to two sub-pixels. By sharing the same element, the aperture ratio can be improved, and the total number of scanning lines can be reduced. This allows the gate line selection period per pixel to be reduced sufficiently even in high-resolution LCD panels. This allows the time to be increased to write an appropriate signal voltage to each pixel.

[0105] 11(A) and 11(B) show the pixel configuration shown in FIG. 10(B) in which the liquid crystal element is This is an example that shows the electrical connection state of each element after replacing it with the shape of a pixel electrode. 11(A) and 11(B), the electrode 1088-1 represents the first pixel electrode, The electrode 1088-2 represents the second pixel electrode. The electrode 1088-1 corresponds to the first terminal of the liquid crystal element 1082-1 in FIG. 10(B), and the The pixel electrode 1088-2 corresponds to the first terminal of the liquid crystal element 1082-2 in FIG. 10(B). That is, the first pixel electrode 1088-1 corresponds to the source of the transistor 1081-1. The second pixel electrode 1088-2 is electrically connected to either the drain or the gate of the transistor 1. On the other hand, in FIG. 11(B), In this case, the connection relationship between the pixel electrode and the transistor is reversed. 88-1 is electrically connected to either the source or the drain of the transistor 1081-2. The second pixel electrode 1088-2 is connected to the source or drain of the transistor 1081-1. It is assumed that one of them is electrically connected to the other.

[0106] In the pixel of this embodiment, by combining with the configuration of the above embodiment, When manufacturing pixels equipped with thin film transistors using nitride semiconductors, it is necessary to improve the aperture ratio. It is possible.

[0107] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0108] (Embodiment 5) In this embodiment, an electronic device including the liquid crystal display device described in the above embodiment will be described. An example will be described.

[0109] FIG. 12A shows a portable gaming machine, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, recording medium reading unit 9672, etc. The portable gaming machine shown in FIG. 12(A) can be used to play a program or data recorded on a recording medium. It also has the function of reading out data and displaying it on the display, and of sharing information with other portable gaming machines via wireless communication. The portable gaming machine shown in FIG. 12(A) has the following functions. The functions are not limited to these, and various functions can be provided.

[0110] FIG. 12B shows a digital camera, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 , etc. The digital camera with a television receiving function shown in FIG. 12(B) can have: Functions for taking still images, shooting videos, and automatically or manually correcting captured images Function, function to acquire various information from the antenna, image taken or acquired from the antenna It has the function of saving the captured information, displaying the captured image or the information obtained from the antenna on the display. It should be noted that the digital camera with television reception function shown in FIG. The functions of the mobile camera are not limited to these, and the mobile camera may have a variety of functions.

[0111] FIG. 12C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, etc. A television receiver has the functions of processing television radio waves and converting them into image signals, It has functions such as converting signals suitable for display and converting the frame frequency of image signals. It should be noted that the functions of the television receiver shown in FIG. 12(C) are not limited to these. It can have a variety of functions.

[0112] FIG. 13A shows a computer, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, pointing devices 9681, external connection points The computer shown in FIG. 13(A) can store various information. (still images, videos, text images, etc.) on the display, Functions for controlling processing by means of wireless or wired communication, the ability to connect to various computer networks using the communication function, It can have a function to transmit or receive data, etc. The functions possessed by the computer are not limited to these, and the computer may have a variety of functions.

[0113] Next, FIG. 13B shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, microphone 9638, etc. The mobile phone shown in the figure has the function of displaying various information (still images, videos, text images, etc.). , calendar, date or time, etc., on the display, and the function to operate the information displayed on the display Or editing functions, functions to control processing by various software (programs), etc. The functions of the mobile phone shown in FIG. 13(B) are not limited to these. It can have a variety of functions.

[0114] Next, FIG. 13C shows an electronic paper (also called an E-book), which has a housing 9630, a surface The electronic pen 9630 shown in FIG. 13(C) may have a display unit 9631, operation keys 9635, etc. The user can display various information (still images, videos, text images, etc.), a calendar, , the function to display the date or time on the display unit, and the function to operate or edit the information displayed on the display unit Functions, functions to control processing by various software (programs), etc. The functions of the electronic paper shown in FIG. 13(C) are not limited to these. It can have a variety of functions.

[0115] The electronic device described in this embodiment has a plurality of pixels constituting a display unit, each of which has an aperture ratio It is possible to improve the

[0116] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Example]

[0117] In this example, it was confirmed to what extent a liquid crystal display device can be improved by using a thin film transistor including an oxide semiconductor layer. We estimate how the aperture ratio of each pixel will improve, and show the results.

[0118] In a thin film transistor having an oxide semiconductor, a gate is connected to the gate electrode to turn the transistor off. The current that flows through the transistor when a voltage is applied (hereinafter referred to as leakage current) is 0.1 pA. While thin-film transistors with amorphous silicon have a current of several hundred nA or less, Therefore, in a thin film transistor having an oxide semiconductor, it is necessary to reduce the storage capacitance. That is, in a pixel provided with a thin film transistor having an oxide semiconductor, The aperture ratio is improved compared to pixels in which thin film transistors having amorphous silicon are provided. Here, we will roughly estimate how much the aperture ratio will improve. The leakage current of the thin film transistor using the oxide semiconductor layer was set to 1×10 -13 (A) , the leakage current of a thin film transistor using amorphous silicon is 1 × 10 -11 (A) The following explanation will be given assuming that this is the case.

[0119] Another parameter for estimating the pixel aperture ratio is the panel size of 3.4 inches. The display gradation is 256 gradations, the input voltage is 10V, and one frame is 1.66 x 10 - 2 The display time is set to (seconds). The dielectric constant of the gate insulating film is set to 3.7 (F / m), Thickness 1 x 10 -7 This is explained as (m).

[0120] First, apply the above parameters to a panel with 540 x RGB x 960 pixels (called the first panel). The area of the storage capacitor and the aperture ratio when applied are roughly estimated. The pixel size is 26 (μm) × 78 (μm), that is, 2.03 × 10 -9 (m 2 ) Of this, the area excluding the area occupied by wiring and TFT is 1.43 × 10 -9 (m 2 )and The area occupied by the wiring and TFT is 6.00 × 10 -10 (m 2 )

[0121] In order to provide a storage capacitor having a minimum capacitance value in the first panel, a semiconductor layer having an oxide semiconductor layer is used. The pixel has a thin-film transistor that -14 (F). In this case, The required capacitance area is 1.30 x 10 -10 (m 2 ) and the ratio of the area of the storage capacitor to the pixel is The ratio is 6.4% and the aperture ratio is 64.0%. To make a storage capacitor with a capacitance value, a thin film transistor having amorphous silicon is used. With 4.25 x 10 pixels -12 (F). In this case, the required capacity area is 1.3 0×10 -8 (m 2 ), and the ratio of the area of the storage capacitor to the pixel is 639.9(%). In other words, a storage capacitor larger than the size of the pixel is required.

[0122] In addition, the above parameters are applied to a panel with a pixel count of 480 x RGB x 640 (called the second panel). The area of the storage capacitor and the aperture ratio when the above are applied are roughly estimated. In this case, the pixel size is 36 (μm) × 108 (μm), or 3.89 × 10 -9 (m 2 )and Of this, the area excluding the area occupied by the wiring and TFT is 3.29 × 10 -9 (m 2 ), and the area occupied by the wiring and TFT is 6.00 × 10 -10 (m 2 )

[0123] In order to provide a storage capacitor having a minimum capacitance value required in the second panel, a semiconductor layer having an oxide semiconductor layer is used. The pixel has a thin-film transistor that -14 (F). In this case, The required capacitance area is 1.30 x 10 -10 (m 2 ) and the ratio of the area of the storage capacitor to the pixel is The ratio is 3.3% and the aperture ratio is 81.2%. To make a storage capacitor with a capacitance value, a thin film transistor having amorphous silicon is used. With 4.25 x 10 pixels -12(F). In this case, the required capacity area is 1.3 0×10 -8 (m 2 ), and the ratio of the area of the storage capacitor to the pixel is 333.8(%). In other words, a storage capacitor larger than the size of the pixel is required.

[0124] In the first and second panels described above, a thin film transistor having an oxide semiconductor layer is Since the leakage current of the capacitor is very small, the capacitance line for forming the storage capacitor can be omitted. Specifically, the top view and cross section of the case where the capacitance line is omitted are shown in FIG. The top view of the pixel shown in FIG. 14A is the same as that described in Embodiment 1. This corresponds to the top view of FIG. 1(A) with the capacitance lines omitted. As can be seen from the top view and the cross-sectional view shown in FIG. 14B, a thin film transistor having an oxide semiconductor layer is formed. By using a transistor, the area occupied by the pixel electrode 105 can be expanded. In other words, the aperture ratio can be improved. Also, as can be seen from the cross-sectional view shown in FIG. By using a thin film transistor having an oxide semiconductor layer, the capacitance line can be reduced and the pixel The area occupied by the electrode 105 can be expanded, that is, the aperture ratio can be improved. In addition, under the conditions of the first panel in FIGS. 14(A) and (B), the aperture ratio is 70 14(A) and (B) can be improved to 0.4(%). Under the conditions of the lens, the aperture ratio can be improved to 84.5%.

[0125] As explained above, the higher the resolution of the panel, the more the oxide semiconductor required to improve the aperture ratio. It is clear that there are great advantages to using a conductor layer in a thin film transistor. [Explanation of symbols]

[0126] 100 pixels 101 Wiring 102 Wiring 103 Oxide semiconductor layer 104 Capacitance Line 105 pixel electrode 106 Thin-film transistor 111 Substrate 112 Base film 113 Gate insulating film 114 Oxide insulating layer 121 Opening 400 pixels 401 Wiring 402 Wiring 403 Oxide semiconductor layer 404 Capacitance Line 405 pixel electrode 406 Thin Film Transistor 411 Substrate 412 Base film 413 Gate insulating film 414 Oxide insulating layer 700 boards 701 pixels 702 pixel section 703 Scanning line driving circuit 704 Signal Line Driver Circuit 880 pixels 881 Transistor 882 Liquid crystal element 883 Capacitor 884 Wiring 885 Wiring 886 Wiring 887 Wiring 984 signal 985 signal 986 Voltage 102A wiring 102B wiring 1080 pixels 1081 Transistor 1082 Liquid crystal element 1083 Capacitor 1084 Wiring 1085 Wiring 1086 Wiring 1088 pixel electrodes 402A Wiring 402B wiring 601A Insulation Layer 601B Insulation layer 9630 chassis 9631 Display section 9633 Speaker 9635 Operation Key 9636 Connection terminal 9638 Microphone 9672 Recording medium reading unit 9676 Shutter button 9677 Image receiving unit 9680 External connection port 9681 Pointing Device

Claims

1. A display device having a pixel portion including at least a first transistor and a second transistor, a first conductive layer electrically connected to one of the source and drain of the first transistor and one of the source and drain of the second transistor, the first conductive layer having a region extending in a first direction; a first oxide semiconductor layer including a channel formation region of the first transistor; a second oxide semiconductor layer including a channel formation region of the second transistor; a second conductive layer having a region overlapping with the first oxide semiconductor layer and functioning as a gate electrode of the first transistor; a third conductive layer having a region located above the second conductive layer and a region in contact with a top surface of the first oxide semiconductor layer, the third conductive layer being electrically connected to the other of the source and the drain of the first transistor; a first insulating layer having a region located above the third conductive layer; a fourth conductive layer having a region in contact with an upper surface of the third conductive layer in the opening of the first insulating layer and functioning as a first pixel electrode; a fifth conductive layer having a region overlapping with the second oxide semiconductor layer and functioning as a gate electrode of the second transistor; the fourth conductive layer does not overlap with the first oxide semiconductor layer in a plan view, the fourth conductive layer does not overlap with the fifth conductive layer in a plan view; a fourth conductive layer overlapping with the second oxide semiconductor layer in a plan view;

2. A display device having a pixel portion including at least a first transistor and a second transistor, a first conductive layer electrically connected to one of the source and drain of the first transistor and one of the source and drain of the second transistor, the first conductive layer having a region extending in a first direction; a first oxide semiconductor layer including a channel formation region of the first transistor; a second oxide semiconductor layer including a channel formation region of the second transistor; a second conductive layer having a region overlapping with the first oxide semiconductor layer and functioning as a gate electrode of the first transistor; a third conductive layer having a region located above the second conductive layer and a region in contact with a top surface of the first oxide semiconductor layer, the third conductive layer being electrically connected to the other of the source and the drain of the first transistor; a first insulating layer having a region located above the third conductive layer; a fourth conductive layer having a region in contact with an upper surface of the third conductive layer in the opening of the first insulating layer and functioning as a first pixel electrode; a fifth conductive layer having a region overlapping with the second oxide semiconductor layer and functioning as a gate electrode of the second transistor; the fourth conductive layer does not overlap with the first oxide semiconductor layer in a plan view, the fourth conductive layer does not overlap with the fifth conductive layer in a plan view; the fourth conductive layer overlaps with the second oxide semiconductor layer in a plan view; A display device, wherein a channel length direction of the first transistor is a direction intersecting the first direction.

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