Compound semiconductor substrate and method for manufacturing the same

Abstract

The compound semiconductor substrate has a main surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. A ripple-like pattern caused by the impurities is observed in an X-ray topography image of the main surface. The ripple-like pattern has a shape corresponding to a portion of ripples spreading concentrically from a wave source. The ripple-like pattern corresponds to a portion of ripples spreading concentrically from the wave source. The value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 or more and 0.9 or less.

Description

[Technical Field]

[0001] The present disclosure relates to a compound semiconductor substrate and a method for manufacturing the compound semiconductor substrate. [Background technology]

[0002] International Publication No. 2020 / 245215 (Patent Document 1) describes a method for manufacturing semiconductor crystals using the vertical Bridgman method or the vertical gradient freezing method, and a manufacturing apparatus equipped with multiple crucibles. Compound semiconductor substrates are typically manufactured by slicing compound semiconductor crystals into disks. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 245215 Summary of the Invention

[0004] A compound semiconductor substrate according to the present disclosure has a primary surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. A ripple-like pattern caused by the impurities is observed in an X-ray topography image of the primary surface. The ripple-like pattern has a shape corresponding to a portion of ripples extending concentrically from a wave source. The value obtained by dividing the distance between the center of the primary surface and the wave source by the radius of the primary surface is 0.1 or more and 0.9 or less. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view schematically illustrating the configuration of a compound semiconductor substrate according to this embodiment. [Figure 2] FIG. 2 is a schematic side view showing the configuration of the compound semiconductor substrate according to this embodiment. [Figure 3] FIG. 3 is a schematic diagram illustrating the ripple pattern. [Figure 4]FIG. 4 is a cross-sectional view showing the configuration of a compound semiconductor crystal manufacturing apparatus according to this embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a flow diagram that schematically shows a method for manufacturing a compound semiconductor substrate according to this embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a crucible in which a seed crystal, a compound semiconductor raw material, and a sealing material are placed. [Figure 8] FIG. 8 is a cross-sectional view showing a process of growing a crystal. [Figure 9] FIG. 9 is a cross-sectional view illustrating a method for manufacturing a compound semiconductor substrate according to a first comparative example. [Figure 10] FIG. 10 is a cross-sectional view showing a method for manufacturing a compound semiconductor substrate according to a second comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0006] [Problem to be solved by this disclosure] Defects such as cracks and chips may occur in compound semiconductor substrates manufactured by slicing compound semiconductor crystals, which reduces the slicing yield in the manufacture of compound semiconductor substrates.

[0007] An object of the present disclosure is to provide a compound semiconductor substrate and a method for manufacturing the compound semiconductor substrate that can improve the slicing yield.

[0008] [Effects of this disclosure] According to the present disclosure, it is possible to provide a compound semiconductor substrate and a method for manufacturing the compound semiconductor substrate that can improve the slicing yield.

[0009] [Outline of the embodiment] First, an outline of an embodiment of the present disclosure (hereinafter also referred to as the present embodiment) will be described.

[0010] (1) A compound semiconductor substrate according to the present disclosure has a primary surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. A ripple-like pattern due to the impurities is observed in an X-ray topography image of the primary surface. The ripple-like pattern has a shape corresponding to a portion of ripples extending concentrically from a wave source. The value obtained by dividing the distance between the center of the primary surface and the wave source by the radius of the primary surface is 0.1 or more and 0.9 or less. This allows for improved slicing yield.

[0011] (2) In the compound semiconductor substrate according to (1) above, the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface may be 0.3 or more and 0.7 or less, thereby effectively improving the slicing yield.

[0012] (3) In the compound semiconductor substrate according to (2), the value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface may be 0.4 or more and 0.6 or less, thereby effectively improving the slicing yield.

[0013] (4) According to any one of the compound semiconductor substrates (1) to (3) above, the diameter of the main surface may be 100 mm or more and 205 mm or less.

[0014] (5) The compound semiconductor substrate according to any one of (1) to (4) above may be formed of gallium arsenide, and the impurity may include at least one of silicon, boron, tellurium, and zinc.

[0015] (6) The compound semiconductor substrate according to any one of (1) to (4) above may be made of indium phosphide, and the impurities may include at least one of sulfur, tin, and zinc.

[0016] (7) The method for manufacturing a compound semiconductor substrate according to the present disclosure uses a vertical boat method. The method for manufacturing a compound semiconductor substrate includes the following steps: A seed crystal and a raw material are placed inside a crucible; A raw material melt is prepared by melting a portion of the seed crystal and the raw material; A compound semiconductor crystal is grown by solidifying the raw material melt; In the step of growing the compound semiconductor crystal, the solid-liquid interface is convex in the vertically upward direction; The value obtained by dividing the radial distance of the crucible between the central axis of the crucible and the apex of the solid-liquid interface by half the inner diameter of the crucible is 0.1 or more and 0.9 or less. This improves the slicing yield.

[0017] [Details of the embodiment] Hereinafter, details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, individual planes are indicated by ().

[0018] (compound semiconductor substrate) First, the configuration of the compound semiconductor substrate according to this embodiment will be described. FIG. 1 is a schematic plan view showing the configuration of a compound semiconductor substrate 100 according to this embodiment. FIG. 2 is a schematic side view showing the configuration of the compound semiconductor substrate 100 according to this embodiment. As shown in FIGS. 1 and 2, the compound semiconductor substrate 100 has a first main surface 1, a second main surface 2, and an outer peripheral surface 3. The compound semiconductor substrate 100 is formed of either gallium arsenide (GaAs) or indium phosphide (InP). The crystal structure of the compound semiconductor substrate 100 is cubic.

[0019] 2, the second main surface 2 is opposite the first main surface 1. The outer peripheral surface 3 is continuous with each of the first main surface 1 and the second main surface 2. The ridge line between the first main surface 1 and the outer peripheral surface 3 is defined as an outer edge 8.

[0020] The direction from the first main surface 1 toward the second main surface 2 is parallel to the growth direction of the compound semiconductor crystal during the manufacture of the compound semiconductor substrate 100. The thickness of the compound semiconductor substrate 100 in the direction from the first main surface 1 toward the second main surface 2 is, for example, less than 1 mm.

[0021] 1 shows the configuration of a compound semiconductor substrate 100 viewed perpendicularly to a first main surface 1. As shown in FIG. 1, the shape of the first main surface 1 when viewed perpendicularly to the first main surface 1 is, for example, circular. The first main surface 1 has a center A. The center A is, for example, the center of the outer edge 8.

[0022] The first main surface 1 is, for example, a (100) plane. The first main surface 1 may be inclined with respect to the (100) plane. When the first main surface 1 is inclined with respect to the (100) plane, the inclination angle (off angle) of the first main surface 1 with respect to the (100) plane is, for example, not less than 0° and not more than 15°.

[0023] The diameter D of the first main surface 1 is, for example, 100 mm or more and 205 mm or less. The diameter D may be 4 inches (101.6 mm) or more, or 6 inches (152.4 mm) or more. The diameter D may be, for example, 8 inches (203.2 mm) or less. The diameter D is the longest distance between two different points on the outer edge 8. The radius of the first main surface 1 (first radius R1) is half of the diameter D.

[0024] At least one of a notch, an orientation flat (OF), and an index flat (IF) may be provided on the outer peripheral surface 3. When at least one of a notch, an OF, and an IF is provided on the outer peripheral surface 3, the center of a circle that overlaps with the arc-shaped portion of the outer edge 8 when viewed perpendicularly to the first main surface 1 is defined as the center A of the first main surface 1.

[0025] The compound semiconductor substrate 100 contains impurities. When the compound semiconductor substrate 100 is made of GaAs, the impurities include at least one of silicon (Si), boron (B), tellurium (Te), and zinc (Zn). When the compound semiconductor substrate 100 is made of InP, the impurities include at least one of sulfur (S), Sn, and Zn. The concentration of the impurities in the compound semiconductor substrate 100 is, for example, 1.0×10 16 Over 9.0 x 10 19 or less, preferably 1.0 × 10 16 Over 8.0 x 10 18 More preferably, it is 9.0×10 or less. 17 Over 4.5 x 10 18 The following is the result.

[0026] <Ripple pattern> In the compound semiconductor substrate 100 according to this embodiment, a ripple-like pattern P is observed in an X-ray topography image of the first main surface 1. Fig. 3 is a schematic diagram illustrating the ripple-like pattern. In Fig. 3, the ripple-like pattern P is indicated by a dashed line.

[0027] As shown in Figure 3, ripple-like pattern P has a shape equivalent to a part of ripples spreading concentrically from wave source X. Note that the "ripple-like pattern" refers to a pattern that can be likened to the wave pattern (ripples) that appears when an object falls onto the water surface and spreads in multiple circles. The "wave source" of a ripple-like pattern refers to the point where the waves in the ripple-like pattern are generated.

[0028] The ripple pattern P is formed, for example, by a circle 91 and an arc 92 that is convex in a direction from the wave source X toward the center A. In the ripple pattern P, the number of circles 91 and the number of arcs 92 are not particularly limited. The ripple pattern P may be formed only by arcs 92. The center of the circle 91 and the center of the circle that overlaps with the arc 92 are set as the wave source X. The wave source X is located on the first main surface 1. In other words, the wave source X is located inside the outer edge 8. The wave source X is spaced apart from the center A.

[0029] The central deviation ratio is the value obtained by dividing the distance (first distance E1) between the center A of the first main surface 1 and the wave source X by the radius (first radius R1) of the first main surface 1. When the central deviation ratio is 1 or less, the wave source X is located inside the outer edge 8. Conversely, when the central deviation ratio is greater than 1, the wave source X is located outside the outer edge 8. When the central deviation ratio is 0, the wave source X overlaps with the center A.

[0030] According to the compound semiconductor substrate 100 of this embodiment, the center offset rate is 0.1 or more and 0.9 or less. The center offset rate may be 0.2 or more and 0.8 or less, 0.3 or more and 0.7 or less, 0.4 or more and 0.6 or less, or 0.45 or more and 0.55 or less.

[0031] Next, a method for confirming the ripple pattern using X-ray topography (XRT) is described. For XRT, for example, the XRTmicron (trademark) manufactured by Rigaku Corporation or the JVSensus-600 (trademark) series manufactured by Bruker can be used. XRT is a method for evaluating the internal structure of a crystal.

[0032] In capturing an X-ray topography image, transmission XRT is performed. Specifically, X-rays are irradiated onto the second main surface 2. The intensity of the X-rays that are reflected by the diffraction plane of the compound semiconductor substrate 100, pass through the first main surface 1, and exit the compound semiconductor substrate 100 is measured. An X-ray topography image of the first main surface 1 is created by representing the intensity of the X-rays as shades of color across the entire surface of the first main surface 1. By observing the shades of color in the X-ray topography image, a ripple-like pattern P can be confirmed.

[0033] If the angle between the diffraction plane and the X-ray is the incident angle θ (also called the Bragg angle), the lattice constant of the crystal is d, and the wavelength of the X-ray is λ, the incident angle θ, lattice constant d, and wavelength λ satisfy the following formula 1. In formula 1, n is an integer. Formula 1 is also called the Bragg condition. nλ=2dsinθ (Formula 1) When capturing an X-ray topography image, the X-ray target is Mo (Mo Kα). When the wavelength λ is set to 0.062 nm, a transmission image is captured using the following Bragg angles. Specifically, when capturing an X-ray topography image of a compound semiconductor single crystal substrate 100 made of GaAs, if the diffraction plane is the (022) plane, the Bragg angle is set to 8.94°. Also, if the diffraction plane is the (040) plane, the Bragg angle is set to 12.69°. When capturing an X-ray topography image of InP, if the diffraction plane is the (022) plane, the Bragg angle is set to 8.60°. If the diffraction plane is the (040) plane, the Bragg angle is set to 12.21°. A highly sensitive, high-resolution CCD camera, "XTOP" (manufactured by Rigaku Corporation), is used as an X-ray intensity detector.

[0034] The ripple pattern P is caused by impurities. Specifically, it is believed that the ripple pattern P is caused by the distribution of the concentration of impurities added to the compound semiconductor substrate 100 as dopants or the like. In an X-ray topography image of the compound semiconductor substrate 100, the X-ray intensity is higher in areas with high impurity concentrations than in areas with low impurity concentrations. Therefore, it is believed that the ripple pattern P can be confirmed by visualizing the distribution of impurity concentrations in the compound semiconductor substrate 100 using XRT.

[0035] (Compound semiconductor crystal manufacturing equipment) Next, the configuration of compound semiconductor crystal manufacturing apparatus 300 according to this embodiment (hereinafter also simply referred to as manufacturing apparatus 300) will be described. Fig. 4 is a cross-sectional schematic diagram showing the configuration of compound semiconductor crystal manufacturing apparatus 300 according to this embodiment. As shown in Fig. 4, manufacturing apparatus 300 mainly includes crucible 40, crucible holder 49, heating unit 48, heat insulator 50, and a high-pressure vessel (not shown).

[0036] The crucible 40 is made of a material that can withstand the heat generated when melting the raw materials. Specifically, the crucible 40 is made of, for example, pyrolytic boron nitride (pBN). The crucible 40 has a seed crystal holding portion 41 and a crystal growth portion 42.

[0037] The crucible 40 has a cylindrical shape. The central axis of the crucible 40 is defined as a first central axis C1. The crucible 40 opens in a vertically upward direction 111. The vertically upward direction 111 is the same direction as the growth direction of the compound semiconductor crystal 400 described below. The direction opposite to the vertically upward direction 111 is defined as a vertically downward direction 112. The first central axis C1 extends along the vertically upward direction 111. The direction perpendicular to the first central axis C1 and extending from the first central axis C1 toward the crystal growth portion 42 is defined as a radial direction 113.

[0038] The seed crystal holding portion 41 has a cylindrical shape with a bottom. The seed crystal holding portion 41 holds a seed crystal. The seed crystal holding portion 41 opens in a vertically upward direction 111. The crystal growth portion 42 holds a raw material. The crystal growth portion 42 is connected to the seed crystal holding portion 41. The crystal growth portion 42 is provided in the vertically upward direction 111 relative to the seed crystal holding portion 41. The crystal growth portion 42 has an increased diameter portion 42a and a straight body portion 42b.

[0039] The increased diameter portion 42a is continuous with the seed crystal holding portion 41. The increased diameter portion 42a has an annular shape. The increased diameter portion 42a surrounds the first central axis C1. As the increased diameter portion 42a moves away from the seed crystal holding portion 41 in the vertically upward direction 111, the inner diameter and the outer diameter of the increased diameter portion 42a each increase.

[0040] The body portion 42b is continuous with the increased diameter portion 42a. The body portion 42b is provided in the vertically upward direction 111 relative to the increased diameter portion 42a. The body portion 42b has a hollow cylindrical shape. When viewed in the vertically downward direction 112, the body portion 42b has a circular shape. The body portion 42b surrounds the first central axis C1. The inner diameter of the body portion 42b is, for example, 100 mm or more. The inner diameter of the body portion 42b is the inner diameter of the crucible 40. Half of the inner diameter of the crucible 40 is set to the second radius R2.

[0041] The heating unit 48 heats the crucible 40. Specifically, the heating unit 48 heats the crucible 40 by supplying power to the heating unit 48. The heating unit 48 is, for example, a resistance heater. From another perspective, the crucible 40 is heated by, for example, a resistance heating method. The heating unit 48 may be a coil. From another perspective, the crucible 40 may be heated by a high-frequency induction heating method.

[0042] The heating unit 48 has a cylindrical outer shape. The heating unit 48 surrounds the crucible 40. The heating unit 48 is spaced apart from the crucible 40. The central axis of the heating unit 48 is defined as a second central axis C2. The second central axis C2 may be parallel to the first central axis C1. The second central axis C2 is spaced apart from the first central axis C1.

[0043] The second central axis C2 is located between the first central axis C1 and the crucible 40. The distance between the first central axis C1 and the second central axis C2 in the radial direction 113 is set to be a second distance E2. The value obtained by dividing the second distance E2 by the radius (second radius R2) of the crucible 40 is, for example, not less than 0.1 and not more than 0.9. The second distance E2 may be the same as the first distance E1 in the compound semiconductor substrate 100 described above (see FIG. 3).

[0044] The heating section 48 has, for example, an upper heating member 48a and a lower heating member 48b. The upper heating member 48a surrounds the crystal growth section 42. When viewed in the vertically downward direction 112, the upper heating member 48a has a ring-shaped configuration. The lower heating member 48b is provided vertically downward in the direction 112 relative to the upper heating member 48a. The lower heating member 48b surrounds the seed crystal holder 41. When viewed in the vertically downward direction 112, the lower heating member 48b has a ring-shaped configuration.

[0045] The crucible holder 49 holds the crucible 40. The crucible holder 49 surrounds the seed crystal holder 41 and the diameter increasing portion 42a. The heat insulating material 50 surrounds the crucible 40 and the heating portion 48. The high-pressure vessel (not shown) surrounds the crucible 40 and the heating portion 48. The high-pressure vessel is made of, for example, metal. The manufacturing apparatus 300 may also have a vessel (not shown) that surrounds the crucible 40. The vessel is made of quartz.

[0046] Fig. 5 is a schematic cross-sectional view taken along line VV in Fig. 4. As shown in Fig. 5, the crucible 40 is eccentric with respect to the heating unit 48. The first central axis C1 is positioned in the radial direction 113 with respect to the second central axis C2. The central axis of the insulating material 50 overlaps with the second central axis C2. In other words, in a cross-sectional view, the heating unit 48 and the insulating material 50 are arranged concentrically with the second central axis C2 at the center.

[0047] (Method of manufacturing a compound semiconductor substrate) Next, a method for manufacturing the compound semiconductor substrate 100 according to this embodiment will be described. The compound semiconductor substrate 100 is manufactured using a vertical boat method. In this specification, the vertical boat method includes, for example, a vertical Bridgman (VB) method, a vertical gradient freeze (VGF) method, and a hybrid method that combines the VB method and the VGF method.

[0048] 6 is a flow diagram that schematically illustrates a method for manufacturing a compound semiconductor substrate 100 according to this embodiment. As shown in FIG. 6, the method for manufacturing a compound semiconductor substrate 100 according to this embodiment mainly includes a step (S10) of preparing a manufacturing apparatus, a step (S20) of arranging raw materials, a step (S30) of melting the raw materials, a step (S40) of growing a crystal, and a step (S50) of cutting the crystal.

[0049] First, a step (S10) of preparing a manufacturing apparatus is performed. Specifically, the manufacturing apparatus 300 (see FIGS. 4 and 5) according to the present embodiment described above is prepared. In the step (S10) of preparing a manufacturing apparatus, a boron oxide (BO) film (not shown) may be formed on the surface of the crucible 40 by heating the crucible 40 in an oxygen atmosphere. The boron oxide film functions as a sealant.

[0050] Next, a step (S20) of arranging the raw materials is performed. Fig. 7 is a cross-sectional view showing crucible 40 in which seed crystal 84, compound semiconductor raw material 85, and sealing material 86 are arranged. For ease of explanation, heat insulating material 50 is not shown in Fig. 7 and subsequent figures.

[0051] As shown in FIG. 7 , a seed crystal 84 is placed inside the seed crystal holder 41. The seed crystal 84 is made of either GaAs or InP. The seed crystal 84 may contain an element that the compound semiconductor substrate 100 described above contains as an impurity. A plurality of compound semiconductor raw materials 85 are placed on the seed crystal 84. Each of the plurality of compound semiconductor raw materials 85 is made of a polycrystalline compound semiconductor.

[0052] When the seed crystal 84 is made of GaAs, the compound semiconductor raw material 85 is also made of GaAs. Similarly, when the seed crystal 84 is made of InP, the compound semiconductor raw material 85 is also made of InP. Each of the plurality of compound semiconductor raw materials 85 is, for example, cylindrical in shape. The plurality of compound semiconductor raw materials 85 are stacked on the seed crystal 84. An impurity raw material (not shown) is placed inside the crucible 40. The impurity raw material is made of an element contained as an impurity in the compound semiconductor substrate 100 described above. In the step (S20) of placing the raw material, a trace amount of carbon, carbon dioxide, or carbon monoxide may be introduced into the crucible 40.

[0053] 7, a sealant 86 may be disposed on the plurality of compound semiconductor raw materials 85. The sealant 86 is formed of, for example, boron oxide. The sealant 86 has a cylindrical shape. The sealant 86 suppresses decomposition of the compound semiconductor.

[0054] Next, the step (S30) of melting the raw material is performed. The crucible 40 is heated by supplying power to the heating unit 48. The power supplied to the upper heating member 48a is greater than the power supplied to the lower heating member 48b. Therefore, the temperature of the crucible 40 increases with increasing distance from the bottom of the crucible 40 in the vertically upward direction 111. This melts a portion of the seed crystal 84 and the compound semiconductor raw material 85. The melted portion of the seed crystal 84 and the compound semiconductor raw material 85 become a raw material melt 87. The raw material melt 87 comes into contact with the remaining portion of the seed crystal 84. The sealing material 86 melts, turning the sealing material 86 into a liquid sealing material 88. The liquid sealing material 88 covers the raw material melt 87. Thus, the raw material melt 87 is prepared.

[0055] Next, the step of growing a crystal (S40) is carried out. FIG. 8 is a schematic cross-sectional view showing the step of growing a crystal. As shown in FIG. 8, for example, crucible 40 is pulled down along arrow B. The direction of arrow B is the same as vertically downward direction 112. The speed at which crucible 40 is pulled down is, for example, 0.1 mm / h or more and 10.0 mm / h or less. The temperature of a portion of raw material melt 87 close to the remainder of seed crystal 84 decreases. As raw material melt 87 in contact with the remainder of seed crystal 84 solidifies, compound semiconductor crystal 400 grows on seed crystal 84.

[0056] Because the crucible 40 is eccentric with respect to the heating unit 48, the amount of heat that the crucible 40 receives from the heating unit 48 is uneven. As a result, in a plane perpendicular to the first central axis C1, the temperature of the portion of the raw material melt 87 closest to the central axis (second central axis C2) of the heating unit 48 is lowest. Therefore, the solid-liquid interface S between the compound semiconductor crystal 400 and the raw material melt 87 is convex in the vertically upward direction. The second central axis C2 may pass through the apex T of the solid-liquid interface S. The apex T is the portion of the solid-liquid interface S that is closest to the opening of the crucible 40 in the vertically upward direction 111.

[0057] The distance in the radial direction 113 between the first central axis C1 and the apex T of the solid-liquid interface S is defined as a third distance E3. The value obtained by dividing the third distance E3 by the second radius R2 is 0.1 or more and 0.9 or less. The value obtained by dividing the third distance E3 by the second radius R2 may be 0.2 or more and 0.8 or less, 0.3 or more and 0.7 or less, 0.4 or more and 0.6 or less, or 0.45 or more and 0.55 or less. The third distance E3 may be the same as the first distance E1 (see FIG. 3) of the compound semiconductor substrate 100 described above. The third distance E3 may be the same as the second distance E2 (see FIGS. 4 and 5).

[0058] As the crucible 40 continues to be lowered, growth of the compound semiconductor crystal 400 continues. After crystal growth is completed, the power supply to the heating unit 48 is reduced. Finally, the power supply is stopped. This causes the temperatures of the heating unit 48, the crucible 40, and the compound semiconductor crystal 400 to gradually decrease. In this manner, the compound semiconductor crystal 400 is produced. The maximum diameter of the compound semiconductor crystal 400 is substantially the same as the inner diameter of the crucible 40. Note that the cross section shown in FIG. 8 is a cross section including the first central axis C1 and the vertex T.

[0059] Next, a crystal cutting step (S50) is carried out. For example, a wire saw is used to slice the compound semiconductor crystal 400 along a plane perpendicular to the growth direction of the compound semiconductor crystal 400. This results in the compound semiconductor substrate 100. Thereafter, the surface of the compound semiconductor substrate 100 may be polished, or the compound semiconductor substrate 100 may be cleaned. In this manner, the compound semiconductor substrate 100 is manufactured.

[0060] Next, the effects of the compound semiconductor substrate and the method for manufacturing the compound semiconductor substrate according to this embodiment will be described.

[0061] Typically, the compound semiconductor substrate 100 is manufactured by slicing the compound semiconductor crystal 400 into a disk shape. In the manufactured compound semiconductor substrate 100, defects due to slicing may occur. Specifically, after slicing, defects such as cracks and chips may occur in the compound semiconductor substrate 100. This reduces the slicing yield in the manufacture of the compound semiconductor substrate 100.

[0062] When the compound semiconductor crystal 400 grows, the raw material melt 87 solidifies from the portion of the raw material melt 87 that has a low temperature on a plane perpendicular to the central axis of the crucible 40. Specifically, the raw material melt 87 solidifies, for example, from the apex T of the solid-liquid interface S along a direction that extends radially outward from the second central axis C2. Therefore, a temperature difference occurs between the portion of the raw material melt 87 close to the apex T and the portion of the raw material melt 87 far from the apex T. This temperature difference causes residual strain in the compound semiconductor crystal 400.

[0063] The distribution of residual strain corresponds to the temperature distribution of the raw material melt 87. Specifically, in a plane perpendicular to the central axis (first central axis C1) of the crucible 40, the residual strain is small in the portion of the compound semiconductor crystal 400 that solidified relatively quickly, and the residual strain is large in the portion of the compound semiconductor crystal 400 that solidified relatively slowly. From another perspective, the residual strain of the compound semiconductor crystal 400 increases with increasing distance from the second central axis C2.

[0064] 9 is a cross-sectional view showing a method for manufacturing a compound semiconductor substrate according to a first comparative example. As shown in FIG. 9, when the second central axis C2 and the first central axis C1 overlap, the raw material melt 87 solidifies radially outward from the first central axis C1. Therefore, in the compound semiconductor crystal 400, residual strain is distributed point-symmetrically around the first central axis C1. In this case, it is believed that the residual strain is more likely to be released when the compound semiconductor crystal 400 is sliced. This makes the compound semiconductor substrate 100 more susceptible to cracking and chipping.

[0065] 10 is a cross-sectional view schematically illustrating a method for manufacturing a compound semiconductor substrate according to a second comparative example. As shown in FIG. 10, if the distance between the first central axis C1 and the second central axis C2 (second distance E2) is excessively long, it is believed that residual strain will be excessively large in portions of the compound semiconductor crystal 400 that are far from the second central axis C2. Portions of the compound semiconductor crystal 400 with excessively large residual strain are likely to become starting points for cracks and chips in the compound semiconductor substrate 100 when the compound semiconductor crystal 400 is sliced. Therefore, if the second distance E2 is excessively long, the slicing yield will decrease in the manufacture of the compound semiconductor substrate 100.

[0066] In the compound semiconductor substrate 100 according to this embodiment, a ripple-like pattern P is observed in an X-ray topography image of the first main surface 1. The value obtained by dividing the distance between the center A of the first main surface 1 and the wave source X of the ripple-like pattern P by the radius of the first main surface 1 (center deviation rate) is 0.1 or more and 0.9 or less.

[0067] During the crystal growth process, the crystal growth rate is not necessarily constant. Changes in the crystal growth rate cause slight changes in the impurity segregation coefficient. This causes slight variations in the impurity concentration distribution in the compound semiconductor crystal 400. This impurity concentration distribution is thought to resemble the shape of the solid-liquid interface S. Therefore, the shape of the ripple-like pattern P caused by the impurities resembles the shape of the solid-liquid interface S during crystal growth. Therefore, the position of the wave source X of the ripple-like pattern P corresponds to the position of the apex T of the solid-liquid interface S. Note that, as shown in FIG. 10, when the second central axis C2 passes outside the crucible 40, the position of the wave source X corresponds to the position of the second central axis C2.

[0068] When the center deviation rate is excessively small, residual strain is distributed point-symmetrically around the center A of the first main surface 1 in the compound semiconductor substrate 100, as in the case where the second central axis C2 and the first central axis C1 overlap (see FIG. 9). This makes it more likely that cracks and chips will occur when slicing the compound semiconductor crystal 400 in the manufacture of the compound semiconductor substrate 100. This reduces the slicing yield.

[0069] In the compound semiconductor substrate 100 according to this embodiment, the center offset rate is 0.1 or more, which prevents residual strain from being distributed point-symmetrically around the center A. From another perspective, it can be considered that the residual strain in the compound semiconductor substrate 100 is dispersed. Therefore, in the manufacture of the compound semiconductor substrate 100, when the compound semiconductor crystal 400 is sliced, it is possible to prevent cracks and chips from occurring. This can therefore improve the slicing yield.

[0070] If residual strain is distributed point-symmetrically around the center A in the compound semiconductor substrate 100, the compound semiconductor substrate 100 may be deformed by heating when an epitaxial layer is formed on the compound semiconductor substrate 100. This reduces the yield of the epitaxial substrate. The compound semiconductor substrate 100 according to this embodiment prevents residual strain from being distributed point-symmetrically around the center A. This prevents the compound semiconductor substrate 100 from being deformed due to residual strain when the compound semiconductor substrate 100 is heated when an epitaxial layer is formed on the compound semiconductor substrate 100. This improves the yield of epitaxial substrates when the compound semiconductor substrate 100 is used to manufacture the epitaxial substrates.

[0071] When the center deviation rate is excessively large, similar to the case where the second distance E2 described above is excessively long (see FIG. 10), residual strain becomes excessively large in the portion of the compound semiconductor substrate 100 far from the wave source X. Therefore, when slicing the compound semiconductor crystal 400, this portion is likely to become the starting point for cracks and chips in the compound semiconductor substrate 100. This reduces the slicing yield.

[0072] According to the compound semiconductor substrate 100 of this embodiment, the center offset rate is 0.9 or less, which prevents excessively large residual strain in the compound semiconductor substrate 100. This makes it possible to prevent cracks and chips from occurring when slicing the compound semiconductor crystal 400 in the manufacture of the compound semiconductor substrate 100. This makes it possible to improve the slicing yield.

[0073] If the compound semiconductor substrate 100 has a portion with excessively large residual strain, the portion with excessively large residual strain may be deformed by heating when an epitaxial layer is formed on the compound semiconductor substrate 100. This reduces the yield of the epitaxial substrate. The compound semiconductor substrate 100 according to this embodiment prevents the residual strain from becoming excessively large. Therefore, even if the compound semiconductor substrate 100 is heated when an epitaxial layer is formed on the compound semiconductor substrate 100, deformation of the compound semiconductor substrate 100 due to the residual strain can be prevented. This improves the yield of epitaxial substrates when epitaxial substrates are manufactured using the compound semiconductor substrate 100.

[0074] According to the method for manufacturing compound semiconductor substrate 100 in accordance with this embodiment, in the step (S40) of growing a crystal, solid-liquid interface S is convex in vertically upward direction 111. The value obtained by dividing the distance in radial direction 113 between first central axis C1 and vertex T of solid-liquid interface S (third distance E3) by half the inner diameter of crucible 40 (second radius R2) is equal to or greater than 0.1 and equal to or less than 0.9.

[0075] When the value obtained by dividing the third distance E3 by the second radius R2 is 0.1 or more, the second central axis C2 is sufficiently spaced from the first central axis C1. This prevents residual strain from being distributed point-symmetrically around the first central axis C1 in the compound semiconductor crystal 400. This prevents cracks and chips from occurring when slicing the compound semiconductor crystal 400. This improves the slicing yield.

[0076] By setting the value obtained by dividing the third distance E3 by the second radius R2 to 0.9 or less, excessive residual strain is prevented from becoming large in the compound semiconductor crystal 400. This makes it possible to prevent cracks and chips from occurring when slicing the compound semiconductor crystal 400. This in turn improves the slicing yield.

[0077] The above describes a method for manufacturing compound semiconductor substrate 100 using the vertical boat method. However, when first main surface 1 has a diameter D of about 4 inches or less, compound semiconductor substrate 100 according to this embodiment can be manufactured using a pulling method (Czochralski method).

[0078] In the above description, the heating unit 48 of the manufacturing apparatus 300 has a cylindrical shape, but the heating unit 48 may have a parallel plate shape. Specifically, the heating unit 48 may be formed of, for example, two flat plates. The crucible 40 is disposed between the two flat plates. The two flat plates are parallel to each other. The second central axis C2 passes through the center of the space between the two flat plates. [Example]

[0079] (Sample preparation) The influence of the center deviation rate on the slicing yield was investigated. First, compound semiconductor substrates 100 according to Samples 1-1 to 1-13 were prepared. Specifically, the compound semiconductor substrates 100 were prepared according to the manufacturing method of the compound semiconductor substrate 100 according to the present embodiment described above. Samples 1-1 and 1-11 to 1-13 were comparative examples. Samples 1-2 to 1-10 were examples.

[0080] In Samples 1-1 to 1-13, the compound semiconductor substrate 100 was formed of GaAs. The compound semiconductor substrate 100 contained Si as an impurity. The diameter D of the first main surface 1 was 4 inches (101.6 mm). The center offset ratio was changed in Samples 1-1 to 1-13. The center offset ratio was equal to or greater than 0 and equal to or less than 1.5.

[0081] (Evaluation method) For all samples, the impurity concentration, dislocation density, average value of residual strain (hereinafter also referred to as |Sr-St|), and slice yield were measured.

[0082] Glow Discharge Mass Spectrometry (GDMS) was used to measure the impurity concentration. In GDMS, a glow discharge is generated in an argon (Ar) atmosphere using the sample as the cathode, and the Ar gas collides with the sample, sputtering the sample's constituent elements. The elements released by the sputtering are ionized in the Ar plasma. The ionized constituent elements are measured using a mass spectrometer. A semi-quantitative value is calculated by correcting the ion intensity ratio between the sample's main constituent element and the target element (impurity element) using a relative sensitivity coefficient. The calculated semi-quantitative value was used as the impurity concentration of the sample.

[0083] In this technical field, dislocations correspond to etch pits confirmed using the measurement method described below. Therefore, the number of dislocations can be indirectly measured by measuring the number of etch pits. In this specification, dislocation density is measured by measuring the number of etch pits.

[0084] When the compound semiconductor substrate 100 is made of GaAs, molten potassium hydroxide is prepared for dislocation density measurement. The temperature of the molten potassium hydroxide is set to 600°C. The first main surface 1 of the compound semiconductor substrate 100 is immersed in the molten potassium hydroxide for 45 minutes. This forms etch pits on the first main surface 1. Next, the first main surface 1 is observed using an optical microscope. Specifically, a plurality of measurement regions are set on the first main surface 1. Each of the plurality of measurement regions has a size of 1 mm x 1 mm. The interval between the plurality of measurement regions is set to 1 mm.

[0085] The number of etch pits measured in the measurement area was calculated by multiplying the area of the measurement area (1 cm 2 ) was used as the dislocation density in the measurement area. The sum of the dislocation densities in each of the measurement areas was divided by the total number of the measurement areas to obtain the dislocation density of the first main surface 1. As the optical microscope, for example, an "ECLIPSE (registered trademark) LV150N" manufactured by Nikon Corporation can be used. The magnification was 100 times.

[0086] The residual strain (|Sr-St|) in the first principal surface 1 is expressed as the absolute value of the difference between the radial strain component (Sr) and the tangential strain component (St). The direction of the residual strain is divided into the radial direction and the tangential direction. The radial direction is the direction of extension of a line segment connecting the central axis that passes through the center A of the first principal surface 1 and is perpendicular to the first principal surface 1 with the above-mentioned arbitrarily specified point. The tangential direction is the direction perpendicular to the radial direction at that point. The tangential direction is also called the circumferential direction.

[0087] |Sr−St| on the first principal surface 1 can be measured using the photoelastic method described in Appl. Phys. Lett. 47 (1985) pp. 365-367. First, the first principal surface 1 is polished. This allows the arithmetic mean roughness Ra of the first principal surface 1 to be 0.1 nm or more and 0.5 nm or less. Next, |Sr−St| was measured over the entire surface of the first principal surface 1 using the photoelastic method. In the photoelastic method, |Sr−St| is expressed by the following equation 2.

[0088]

number

[0089] In the above formula 2, λ is the wavelength of the light used for measurement. d is the thickness of the compound semiconductor substrate 100 used for measurement. n0 is the refractive index. δ is the phase difference caused by the birefringence of the compound semiconductor substrate 100 used for measurement. φ is the principal vibration azimuth angle. P 11 , P 12 , P 44 is the photoelastic constant.

[0090] According to the photoelastic method, |Sr−St| can be obtained by measuring the phase difference δ and the principal vibration azimuth angle φ. |Sr−St| was measured over the entire first principal surface 1, and the average value of |Sr−St| over the first principal surface 1 was obtained.

[0091] The slicing yield was determined by the following method. Specifically, 1,000 compound semiconductor substrates 100 were prepared for each sample. Among the 1,000 compound semiconductor substrates 100, good compound semiconductor substrates 100 that were not cracked or chipped by slicing were counted. The rate of good compound semiconductor substrates 100 among the 1,000 compound semiconductor substrates 100 was determined as the slicing yield. In other words, the number of good compound semiconductor substrates 100 divided by 1,000 was determined as the slicing yield.

[0092] (Measurement results)

[0093] [Table 1]

[0094] Table 1 shows the measurement results for Samples 1-1 to 1-13. As shown in Table 1, the impurity concentration in Samples 1-1 to 1-13 was 9.0×10 17 / cm 3 Over 1.1 x 10 18 / cm 3 The dislocation density was 11 / cm 2 More than 16 pieces / cm 2 The average value of |Sr-St| was 4.5×10 -6 Over 5.2 x 10 -6 It was as follows.

[0095] For sample 1-1, whose center offset ratio was 0, the slicing yield was 91.3%. For samples whose center offset ratio was 1 or more (samples 1-11 to 1-13), the slicing yield was 92.1% or less. On the other hand, for samples whose center offset ratio was 0.1 or more and 0.9 or less (samples 1-2 to 1-10), the slicing yield was 94.3% or more. Furthermore, for samples whose center offset ratio was 0.3 or more and 0.7 or less (samples 1-4 to 1-8), the slicing yield was 97.4% or more. Furthermore, for samples whose center offset ratio was 0.4 or more and 0.6 or less (samples 1-5 to 1-7), the slicing yield was 98.5% or more.

[0096] From the above, it was confirmed that the slice yield can be improved by the samples according to the examples compared to the samples according to the comparative examples. Also, it was confirmed that the slice yield can be effectively improved by the center deviation ratio being 0.3 or more and 0.7 or less. Also, it was confirmed that the slice yield can be more effectively improved by the center deviation ratio being 0.4 or more and 0.6 or less. [Example]

[0097] (Sample preparation) Next, the influence of the center offset rate on the slicing yield was investigated when the diameter D of the first main surface 1 was 6 inches or 8 inches. First, compound semiconductor substrates 100 according to Samples 2-1 to 2-13 and 3-1 to 3-13 were prepared. The compound semiconductor substrates 100 according to Samples 2-1 to 2-13 and 3-1 to 3-13 were prepared using the same method as the compound semiconductor substrates 100 according to Samples 1-1 to 1-13, except that the inner diameters of the crucibles 40 were different.

[0098] In Samples 2-1 to 2-13 and 3-1 to 3-13, the compound semiconductor substrate 100 was formed of GaAs. The compound semiconductor substrate 100 contained Si as an impurity. In Samples 2-1 to 2-13, the diameter D of the first main surface 1 was 6 inches. In Samples 3-1 to 3-13, the diameter D of the first main surface 1 was 8 inches.

[0099] (Evaluation method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured using the methods described above.

[0100] (Evaluation results)

[0101] [Table 2]

[0102] [Table 3]

[0103] Table 2 shows the measurement results for Samples 2-1 to 2-13. Table 3 shows the measurement results for Samples 3-1 to 3-13.

[0104] As shown in Table 2, the impurity concentration in samples 2-1 to 2-13 was 9.0 × 10 17 / cm 3 Over 1.2 x 10 18 / cm 3 The dislocation density was 10 / cm 2 More than 20 pieces / cm 2 The average value of |Sr-St| was 4.1×10 -6 Over 5.5 x 10 -6 It was as follows.

[0105] For sample 2-1, whose center offset ratio was 0, the slicing yield was 91.1%. For samples whose center offset ratio was 1 or more (samples 2-11 to 2-13), the slicing yield was 91.9% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 2-2 to 2-10), the slicing yield was 94.1% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 2-4 to 2-8), the slicing yield was 97.2% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 2-5 to 2-7), the slicing yield was 98.3% or more.

[0106] As shown in Table 3, the impurity concentration in Samples 3-1 to 3-13 was 9.0 × 10 17 / cm 3 Over 1.2 x 10 18 / cm 3 The dislocation density was 10 / cm 2 More than 20 pieces / cm 2 The average value of |Sr-St| was 4.1×10-6 Over 5.5 x 10 -6 It was as follows.

[0107] For sample 3-1, whose center offset ratio was 0, the slicing yield was 90.7%. For samples whose center offset ratio was 1 or more (samples 3-11 to 3-13), the slicing yield was 91.5% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 3-2 to 3-10), the slicing yield was 93.1% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 3-4 to 3-8), the slicing yield was 96.8% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 3-5 to 3-7), the slicing yield was 97.9% or more.

[0108] From the above, it was confirmed that even when the diameter D of the first main surface 1 is 6 inches or 8 inches, the slicing yield can be improved by keeping the center deviation rate between 0.1 and 0.9. [Example]

[0109] (Sample preparation) Next, the influence of the center offset rate on the slicing yield was investigated when the impurity contained in the compound semiconductor substrate 100 was Zn or B. First, the compound semiconductor substrates 100 according to Samples 4-1 to 4-13 and 5-1 to 5-13 were prepared. The compound semiconductor substrates 100 according to Samples 4-1 to 4-13 and 5-1 to 5-13 were prepared using the same method as the compound semiconductor substrates 100 according to Samples 2-1 to 2-13, except that the impurity elements were different.

[0110] In Samples 4-1 to 4-13 and 5-1 to 5-13, compound semiconductor substrate 100 was formed of GaAs. Diameter D of first main surface 1 was 6 inches. In Samples 4-1 to 4-13, compound semiconductor substrate 100 contained Zn as an impurity. In Samples 5-1 to 5-13, compound semiconductor substrate 100 contained B as an impurity.

[0111] (Evaluation method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured using the methods described above.

[0112] (Evaluation results)

[0113] [Table 4]

[0114] [Table 5]

[0115] Table 4 shows the measurement results for Samples 4-1 to 4-13. Table 5 shows the measurement results for Samples 5-1 to 5-13.

[0116] As shown in Table 4, the impurity concentration in samples 4-1 to 4-13 was 9.0 × 10 17 / cm 3 Over 1.2 x 10 18 / cm 3 The dislocation density was 11 / cm 2 More than 16 pieces / cm 2 The average value of |Sr-St| was 4.6×10 -6 Over 5.2 x 10 -6 It was as follows.

[0117] For sample 4-1, whose center offset ratio was 0, the slicing yield was 90.8%. For samples whose center offset ratio was 1 or more (samples 4-11 to 4-13), the slicing yield was 91.6% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 4-2 to 4-10), the slicing yield was 93.2% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 4-4 to 4-8), the slicing yield was 96.9% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 4-5 to 4-7), the slicing yield was 98% or more.

[0118] As shown in Table 5, the impurity concentration in Samples 5-1 to 5-13 was 9.0 × 10 17 / cm 3 Over 1.2 x 10 18 / cm 3 The dislocation density was 11 / cm 2 More than 20 pieces / cm 2 The average value of |Sr-St| was 4.1×10 -6 Over 5.5 x 10 -6 It was as follows.

[0119] For sample 5-1, whose center offset ratio was 0, the slicing yield was 90.6%. For samples whose center offset ratio was 1 or more (samples 5-11 to 5-13), the slicing yield was 91.4% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 5-2 to 5-10), the slicing yield was 93% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 5-4 to 5-8), the slicing yield was 96.7% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 5-5 to 5-7), the slicing yield was 97.8% or more.

[0120] From the above, it was confirmed that even when the impurity is Zn or B, the slicing yield can be improved by keeping the center deviation rate between 0.1 and 0.9. [Example]

[0121] Next, the influence of the center offset rate on the slicing yield was investigated when the compound semiconductor substrate 100 was made of InP. First, compound semiconductor substrates 100 according to Samples 6-1 to 6-13 and 7-1 to 7-13 were prepared.

[0122] The compound semiconductor substrates 100 according to Samples 6-1 to 6-13 were prepared using the same method as the compound semiconductor substrates 100 according to Samples 1-1 to 1-13, except that the seed crystal 84 and the compound semiconductor material 85 were each formed of InP. The compound semiconductor substrates 100 according to Samples 7-1 to 7-13 were prepared using the same method as the compound semiconductor substrates 100 according to Samples 2-1 to 2-13, except that the seed crystal 84 and the compound semiconductor material 85 were each formed of InP.

[0123] In Samples 6-1 to 6-13 and 7-1 to 7-13, compound semiconductor substrate 100 was formed of InP. Compound semiconductor substrate 100 contained S as an impurity. In Samples 6-1 to 6-13, diameter D of first main surface 1 was 4 inches. In Samples 7-1 to 7-13, diameter D of first main surface 1 was 6 inches.

[0124] (Evaluation method) The impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured for all samples. The impurity concentration, average value of |Sr-St|, and slice yield were each measured using the methods described above.

[0125] In measuring the dislocation density of a compound semiconductor substrate 100 made of InP, a Huber etchant was prepared instead of molten potassium hydroxide. The Huber etchant contains phosphoric acid and hydrogen bromide. The mass ratio of phosphoric acid to hydrogen bromide in the Huber etchant was 2:1. The temperature of the Huber etchant was set to 20°C. The compound semiconductor substrate 100 was immersed in the Huber etchant for, for example, 2 minutes to 7 minutes. This resulted in the formation of etch pits on the first main surface 1.

[0126] (Evaluation results)

[0127] [Table 6]

[0128] [Table 7]

[0129] Table 6 shows the measurement results for Samples 6-1 to 6-13. Table 7 shows the measurement results for Samples 7-1 to 7-13.

[0130] As shown in Table 6, the impurity concentration in Samples 6-1 to 6-13 was 9.0 × 10 17 / cm 3 Over 1.2 x 10 18 / cm 3 The dislocation density was 10 / cm 2 More than 80 pieces / cm 2 The average value of |Sr-St| was 4.0×10 -6 Over 5.5 x 10 -6 It was as follows.

[0131] For sample 6-1, whose center offset ratio was 0, the slicing yield was 91%. For samples whose center offset ratio was 1 or more (samples 6-11 to 6-13), the slicing yield was 91.8% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 6-2 to 6-10), the slicing yield was 93.4% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 6-4 to 6-8), the slicing yield was 97.1% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 6-5 to 6-7), the slicing yield was 98.2% or more.

[0132] As shown in Table 7, the impurity concentration in samples 7-1 to 7-13 was 2.7 × 10 18 / cm 3 Over 3.3 x 10 18 / cm 3 The dislocation density was 20 / cm 2 More than 190 pieces / cm 2 The average value of |Sr-St| was 3.9×10 -6 Over 5.5 x 10 -6 It was as follows.

[0133] For sample 7-1, whose center offset ratio was 0, the slicing yield was 90.8%. For samples whose center offset ratio was 1 or more (samples 7-11 to 7-13), the slicing yield was 91.9% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 7-2 to 7-10), the slicing yield was 93.4% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 7-4 to 7-8), the slicing yield was 96.9% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 7-5 to 7-7), the slicing yield was 97.9% or more.

[0134] From the above, it has been confirmed that even when the compound semiconductor substrate 100 is made of InP, the slicing yield can be improved by setting the center deviation rate to 0.1 or more and 0.9 or less. [Example]

[0135] Next, the influence of the center offset rate on the slice yield was investigated when the compound semiconductor substrate 100 was made of InP and contained Sn or Zn as an impurity. First, the compound semiconductor substrates 100 of Samples 8-1 to 8-13 and 9-1 to 9-13 were prepared. The compound semiconductor substrates 100 of Samples 8-1 to 8-13 and 9-1 to 9-13 were prepared using the same method as the compound semiconductor substrates 100 of Samples 6-1 to 6-13, except that the impurity elements were different.

[0136] In Samples 8-1 to 8-13 and 9-1 to 9-13, compound semiconductor substrate 100 was formed of InP. Diameter D of first main surface 1 was 4 inches. In Samples 8-1 to 8-13, compound semiconductor substrate 100 contained Sn as an impurity. In Samples 9-1 to 9-13, compound semiconductor substrate 100 contained Zn as an impurity.

[0137] (Evaluation method) For all samples, the impurity concentration, dislocation density, average value of |Sr-St|, and slice yield were measured using the methods described above.

[0138] (Evaluation results)

[0139] [Table 8]

[0140] [Table 9]

[0141] Table 8 shows the measurement results for Samples 8-1 to 8-13. Table 9 shows the measurement results for Samples 9-1 to 9-13.

[0142] As shown in Table 8, the impurity concentration in samples 8-1 to 8-13 was 9.0 × 10 17 / cm 3 Over 1.2 x 10 18 / cm 3 The dislocation density was 400 / cm 2 More than 970 pieces / cm 2 The average value of |Sr-St| was 4.2×10 -6 Over 5.5 x 10 -6 It was as follows.

[0143] For sample 8-1, whose center offset ratio was 0, the slicing yield was 91.9%. For samples whose center offset ratio was 1 or more (samples 8-11 to 8-13), the slicing yield was 92% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 8-2 to 8-10), the slicing yield was 93.5% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 8-4 to 8-8), the slicing yield was 97% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 8-5 to 8-7), the slicing yield was 98% or more.

[0144] As shown in Table 9, the impurity concentration in Samples 9-1 to 9-13 was 1.5×10 17 / cm 3 Over 1.4 x 10 18 / cm 3 The dislocation density was 100 / cm 2 More than 200 pieces / cm 2 The average value of |Sr-St| was 3.9×10 -6 Over 5.6 x 10 -6 It was as follows.

[0145] For sample 9-1, whose center offset ratio was 0, the slicing yield was 91.8%. For samples whose center offset ratio was 1 or more (samples 9-11 to 9-13), the slicing yield was 91.9% or less. On the other hand, for samples whose center offset ratio was 0.1 to 0.9 (samples 9-2 to 9-10), the slicing yield was 93.4% or more. Furthermore, for samples whose center offset ratio was 0.3 to 0.7 (samples 9-4 to 9-8), the slicing yield was 96.9% or more. Furthermore, for samples whose center offset ratio was 0.4 to 0.6 (samples 9-5 to 9-7), the slicing yield was 97.9% or more.

[0146] From the above, it has been confirmed that even when the compound semiconductor substrate 100 is made of InP and the impurity is Sn or Zn, the slice yield can be improved by setting the center deviation rate to 0.1 or more and 0.9 or less.

[0147] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments and examples, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof. [Explanation of symbols]

[0148] 1 first main surface, 2 second main surface, 3 outer peripheral surface, 8 outer edge, 40 crucible, 41 seed crystal holder, 42 crystal growth section, 42a diameter increasing section, 42b straight body section, 48 heating section, 48a upper heating element, 48b lower heating element, 49 crucible holder, 50 heat insulating material, 84 seed crystal, 85 compound semiconductor raw material, 86 sealing material, 87 raw material melt, 88 liquid sealing material, 91 circle, 92 arc, 100 compound semiconductor substrate, 111 vertically upward direction, 112 vertically downward direction, 113 radial direction, 300 manufacturing apparatus, 400 compound semiconductor crystal, A center, C1 first central axis, C2 second central axis, D diameter, E1 first distance, E2 second distance, E3 third distance, P ripple-like pattern, R1 1st radius, R2 2nd radius, S solid-liquid interface, T apex, X wave source.

Claims

1. A compound semiconductor substrate having a main surface, Contains impurities, It is made of gallium arsenide or indium phosphide, a ripple-like pattern caused by the impurities is confirmed in an X-ray topography image of the main surface; The ripple-like pattern has a shape corresponding to a part of ripples spreading concentrically from a wave source, A compound semiconductor substrate, wherein a value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 or more and 0.9 or less.

2. 2. The compound semiconductor substrate according to claim 1, wherein a value obtained by dividing the distance between the center of said main surface and said wave source by the radius of said main surface is 0.3 or more and 0.7 or less.

3. 3. The compound semiconductor substrate according to claim 2, wherein a value obtained by dividing the distance between the center of said main surface and said wave source by the radius of said main surface is 0.4 or more and 0.6 or less.

4. 4. The compound semiconductor substrate according to claim 1, wherein the diameter of the main surface is 100 mm or more and 205 mm or less.

5. the compound semiconductor substrate is formed of gallium arsenide; 4. The compound semiconductor substrate according to claim 1, wherein the impurity includes at least one of silicon, boron, tellurium, and zinc.

6. the compound semiconductor substrate is formed of indium phosphide; 4. The compound semiconductor substrate according to claim 1, wherein the impurities include at least one of sulfur, tin, and zinc.

7. A method for manufacturing a compound semiconductor substrate using a vertical boat method, comprising: placing a seed crystal and a raw material inside a crucible; preparing a raw material melt by melting a portion of the seed crystal and the raw material; and growing a compound semiconductor crystal by solidifying the raw material melt, In the step of growing the compound semiconductor crystal, the solid-liquid interface is convex in the vertically upward direction, a value obtained by dividing a radial distance between a central axis of the crucible and an apex of the solid-liquid interface by half an inner diameter of the crucible is 0.1 or more and 0.9 or less.

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