Multilayer focus ring for plasma semiconductor processing.

Abstract

The present disclosure relates to plasma semiconductor processes, and related components and apparatus. In one embodiment, a focus ring includes a first and a second ring layer. The upper surface of the second ring layer is configured to support the first ring layer by the lower surface of the first ring layer contacting the upper surface. The lower and upper surfaces are periodic along the circumference and have the same periodic length. At least one of the lower and upper surfaces includes a first protruding radial line (PRL), a second PRL, and a recessed radial line (RRL) disposed between the first and second PRL. The periodic length is a length from the first PRL to the second PRL. The lower and / or upper surface from the first PRL to the RRL is continuous, and the lower and / or upper surface from the RRL to the second PRL is continuous. The second ring layer is rotatably movable relative to the first ring layer.

Description

[Background technology]

[0001] Plasma processes are widespread in the semiconductor industry. Plasma semiconductor processes have long been used for material etching, material deposition, and the like. Such plasma processes are known to improve the process quality or resulting properties of semiconductor substrates. For example, plasma-enhanced chemical vapor deposition (PECVD) is known to offer advantages over traditional chemical vapor deposition (CVD) processes, such as lower deposition temperatures, higher material purity, and improved step coverage. However, the introduction of plasma has presented various challenges. Summary of the Invention

[0002] One aspect of the present disclosure provides a component for semiconductor processing. The component includes a focus ring configured to surround a semiconductor substrate from the outside during a plasma semiconductor process. The focus ring includes a first ring layer having a lower surface and a second ring layer having an upper surface. The upper surface is configured to support the first ring layer by contacting the lower surface with the upper surface. The lower and upper surfaces are periodic around the circumference. The lower and upper surfaces have the same periodic length at the same first radial distance from the center of the focus ring. At least one of the lower and upper surfaces includes a first protrusion radius line, a first recess radius line, and a second protrusion radius line. The first recess radius line is horizontally disposed between the first protrusion radius line and the second protrusion radius line. The periodic length at the first radial distance is the length from the first protrusion radius line to the second protrusion radius line. At least one of the lower surface and the upper surface from the first protrusion radial line to the first recess radial line is continuous. At least one of the lower surface and the upper surface from the first recess radial line to the second protrusion radial line is continuous. The second ring layer is horizontally rotatable relative to the first ring layer while the upper surface supports the first ring layer.

[0003] Another aspect of the present disclosure provides a process apparatus for semiconductor processing. The process apparatus includes a chamber, a substrate support, and a focus ring rotation assembly. The chamber has an internal volume within the chamber. The substrate support is disposed within the internal volume of the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The substrate support includes a flange configured to support a focus ring that externally surrounds the support surface. The focus ring rotation assembly is disposed at least partially within the internal volume of the chamber. The focus ring rotation assembly is configured to horizontally rotate at least a portion of the focus ring about an axis perpendicular to the support surface. The focus ring rotation assembly includes a frame configured to horizontally rotate about an axis perpendicular to the support surface.

[0004] Another aspect of the present disclosure provides a method for semiconductor processing. The method includes adjusting the height of a focus ring. The focus ring is positioned to surround a semiconductor substrate from the outside within a chamber of a process apparatus. The focus ring includes a first ring layer and a second ring layer. Adjusting the height of the focus ring includes rotating the second ring layer relative to the first ring layer. The first ring layer has a lower surface. The second ring layer has an upper surface. The lower surface is disposed on and in contact with the upper surface. The lower and upper surfaces are periodic around a circumference. The lower and upper surfaces have the same periodic length at the same first radial distance from the center of the focus ring. At least one of the lower and upper surfaces includes a first protrusion radius line, a first recess radius line, and a second protrusion radius line. The first recess radius line is horizontally disposed between the first protrusion radius line and the second protrusion radius line. The periodic length at the first radial distance is the length from the first protrusion radius line to the second protrusion radius line. At least one of the lower surface and the upper surface from the first protrusion radius line to the first recess radius line is continuous. At least one of the lower surface and the upper surface from the first recess radius line to the second protrusion radius line is continuous. The method includes generating a plasma in a process volume of a chamber while a focus ring is positioned to surround the semiconductor substrate from the outside. The semiconductor substrate is exposed to the plasma.

[0005] Another aspect of the present disclosure provides a method for semiconductor processing. The method includes using a process apparatus to perform a plasma semiconductor process having first process conditions on a first plurality of substrates. The process apparatus includes a substrate support configured to support the substrate during the plasma semiconductor process. A focus ring is positioned to surround the substrate from the outside during the plasma semiconductor process. The focus ring has a first ring layer and a second ring layer supporting and in contact with the first ring layer. The height of the focus ring is adjustable by rotating the second ring layer relative to the first ring layer. The first process condition corresponds to a first amount of rotation of the second ring layer relative to the first ring layer to achieve a first height of the focus ring during the plasma semiconductor process. The method includes measuring a first characteristic of each of the first plurality of substrates near a center of each of the first plurality of substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates near an edge of each of the first plurality of substrates. The second characteristic is formed by a plasma semiconductor process. The method includes determining, by a processor-based system, second process conditions to be applied while performing the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to a second amount of rotation of the second ring layer relative to the first ring layer to achieve a second height of the focus ring during the plasma semiconductor process. The method includes performing the plasma semiconductor process having the second process conditions on the second plurality of substrates using the process apparatus.

[0006] The foregoing summary has outlined various features of embodiments of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of such embodiments are described below. The described embodiments may be readily utilized as a basis for modifying or designing other embodiments within the scope of the appended claims. [Brief explanation of the drawings]

[0007] For a more detailed understanding of the above features, reference is now made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] [Figure 1] 1 is a schematic diagram of a process apparatus for semiconductor processing according to some embodiments. [Figure 2A] FIG. 1 is a layout diagram of a focus ring according to some embodiments. [Figure 2B] FIG. 2B is a cross-sectional view of the focus ring of FIG. 2A in accordance with some embodiments. [Figure 2C] FIG. 2B is a cross-sectional view of the focus ring of FIG. 2A in accordance with some embodiments. [Figure 2D] FIG. 2D is a layout diagram of a cross-sectional portion of the focus ring of FIG. 2C in accordance with some embodiments. [Figure 3] 2A-2D illustrate height adjustment of the focus ring according to some embodiments. FIG. [Figure 4] 2A-2D illustrate height adjustment of the focus ring according to some embodiments. FIG. [Figure 5] FIG. 1 is a simplified cross-sectional view of a focus ring rotation assembly according to some embodiments. [Figure 6] FIG. 6 is a perspective view of the focus ring rotation assembly of FIG. 5 in accordance with some embodiments. [Figure 7A] FIG. 10 illustrates a layout of a focus ring on a flange of a substrate support in accordance with some embodiments. [Figure 7B] FIG. 1 is a first cross-sectional view of a focus ring on a flange of a substrate support in accordance with some embodiments. [Figure 7C] FIG. 10 is a second cross-sectional view of a focus ring on a flange of a substrate support in accordance with some embodiments. [Figure 8A] 10A-10C are layout diagrams of a focus ring on a flange of a substrate support, respectively, in accordance with some embodiments. [Figure 8B]FIG. 10 is a cross-sectional view of a focus ring on a flange of a substrate support in accordance with some embodiments. [Figure 9] FIG. 1 conceptually illustrates how focus ring height can affect plasma control in accordance with some embodiments. [Figure 10] FIG. 1 conceptually illustrates how focus ring height can affect plasma control in accordance with some embodiments. [Figure 11] FIG. 1 illustrates a processor-based system according to some embodiments. [Figure 12] 1 is a flowchart of a method of semiconductor processing according to some embodiments. [Figure 13] 1 is a flowchart of a method of semiconductor processing according to some embodiments. [Figure 14] 1A-1C are cross-sectional views of respective focus rings according to some embodiments. [Figure 15] 1A-1C are cross-sectional views of respective focus rings according to some embodiments. [Figure 16] 1A-1C are cross-sectional views of respective focus rings according to some embodiments. [Figure 17] 1A-1C are cross-sectional views of respective focus rings according to some embodiments. [Figure 18] 1A-1C are cross-sectional views of respective focus rings according to some embodiments.

[0009] The drawings and accompanying detailed description are provided to provide an understanding of the features of various embodiments and are not intended to limit the scope of the appended claims. The embodiments illustrated in the drawings and described in the accompanying detailed description may be readily utilized as a basis for modifying or designing other embodiments within the scope of the appended claims. Wherever possible, the same reference numbers may be used to designate identical elements common to the drawings. The figures are drawn to clearly illustrate associated elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0010] Various features are described below with reference to the figures. An embodiment may not have all aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment, even if not shown or explicitly described as such. Furthermore, while methods herein may be described with a particular order of operations, other methods according to other embodiments may be implemented in various other orders with more or fewer operations (e.g., including different sequential or parallel performance of various operations).

[0011] The present disclosure relates to plasma semiconductor processes, as well as components and process apparatus for plasma semiconductor processes. Some embodiments described herein include a focus ring including multiple layers. Generally, a first ring layer (e.g., an upper layer) of the focus ring has a lower surface, and a second ring layer (e.g., a lower layer) has an upper surface. The upper surface is configured to contact and support the lower surface of the first ring layer. The upper and lower surfaces are configured such that rotation of the second ring layer relative to the first ring layer adjusts the height of the focus ring. In some embodiments, continuous rotation of the second ring layer relative to the first ring layer produces periodic variations in the height of the focus ring without requiring a hard reset of the first or second ring layers for height adjustment.

[0012] Some embodiments described herein include a process apparatus in which such a focus ring may be used. The process apparatus includes a focus ring rotation assembly configured to rotate the second ring layer. The process apparatus may also include a substrate support including a mechanism for preventing over-rotation of the first ring layer when the second ring layer rotates. Such a mechanism may include a stop pin extending from the substrate support that engages with the first ring layer to prevent over-rotation of the first ring layer.

[0013] Other embodiments described herein include, for example, methods of semiconductor processing using such focus rings and process apparatus. Further embodiments include a method for semiconductor processing for determining the height of a focus ring to be implemented in subsequent processing of a semiconductor substrate based on results from a previous process in the semiconductor processing.

[0014] Additionally, in some embodiments, the focus ring may include an electrode to which a voltage, such as a radio frequency (RF) signal, may be applied. The process tool may include a component for applying the voltage across the focus ring electrode. The plasma semiconductor process may include applying the voltage across the electrode.

[0015] Plasma non-uniformity during semiconductor processing can result in defects in the integrated circuit (IC) die being fabricated. Plasma non-uniformity has been observed between the center of a semiconductor substrate (e.g., a wafer) and near the edge of the semiconductor substrate. Because a significant number of IC die are fabricated near the edge of the semiconductor substrate, plasma non-uniformity at the edge of the semiconductor substrate can result in significant yield loss.

[0016] Structural differences at the edge of a semiconductor substrate compared to the center of the semiconductor substrate can cause plasma non-uniformity between the center and the edge of the semiconductor substrate. For example, at the edge of a semiconductor substrate, the structure containing or defining the plasma may be different from that at the center of the semiconductor substrate. At the center, the plasma is contained or defined by a flat horizontal surface of the semiconductor substrate, while the vertical edge has structural differences from the flat horizontal surface. A focus ring surrounding the semiconductor substrate may be used to reduce such structural differences, but a gap may exist between the focus ring and the semiconductor substrate due to manufacturing tolerances. The plasma sheath of the plasma may bend toward the gap around the edge, which can cause ion bombardment of the semiconductor substrate near the edge at a different angle than at the center of the semiconductor substrate.

[0017] Additionally, the physical structure of the process tool may at least partially determine the electromagnetic field used to generate the plasma. The structure between the electrodes where the plasma is generated may determine the electromagnetic field. At the center of the electrode, the electromagnetic field may be modeled as emanating from an infinite plane with little or no edge effects. Near the edge of the electrode, edge effects become more pronounced, which may reduce and / or change the directionality of the electromagnetic field. As a result, the plasma density may differ between the center of the substrate and the edge of the semiconductor substrate. Furthermore, because the edge of the electrode is closer to the wall of the chamber of the process tool, low-resistance electromagnetic loops may be created, which may result in differences in plasma density and ion energy between the center and the edge.

[0018] Some embodiments can address and / or reduce these challenges associated with plasma semiconductor processing. By adjusting the height of the focus ring, the plasma sheath may be adjusted to provide a more consistent angle of ion impact at the edge relative to the center of the semiconductor substrate. Additionally, by applying voltages to the focus ring electrodes, the electromagnetic field can be controlled to provide a more consistent angle of ion impact at the edge relative to the center. Other advantages or benefits can be realized using various aspects described herein.

[0019] FIG. 1 is a schematic diagram of a process tool 100 for semiconductor processing according to some embodiments. FIG. 1 includes X, Y, and Z axes for simplified illustration of various directions, and such axes are reproduced according to the directions in other figures. The process tool 100 in FIG. 1 is depicted in a simplified manner so as not to obscure various aspects described herein. Those skilled in the art will readily appreciate other aspects of the process tool 100. In this embodiment, the process tool 100 is depicted as a capacitively coupled plasma (CCP) process tool. In other embodiments, the process tool 100 can be configured as an inductively coupled plasma (ICP) process tool, an electron cyclotron resonance (ECR) process tool, or another process tool. Those skilled in the art will readily appreciate that aspects described herein are applicable to such other process tools. The process apparatus 100 may be for performing plasma semiconductor processes such as sputtering, physical vapor deposition (PVD), modified double plasma (MDP), plasma enhanced chemical vapor deposition (PECVD), ion beam etching (IBE), reactive ion etching (RIE), and other semiconductor processes.

[0020] The process apparatus 100 includes a chamber 102. The chamber 102 has an interior volume 104 defined by the interior walls of the chamber 102. The process apparatus 100 includes a substrate support 106 disposed within the interior volume 104 of the chamber 102. The substrate support 106 includes an electrostatic chuck (ESC) 108, an intermediate plate 110, and a base plate 112. In the illustrated configuration, the intermediate plate 110 is disposed above and in contact with the base plate 112, and the ESC 108 is disposed above and in contact with the intermediate plate 110. The substrate support 106 is disposed on and supported by a pedestal 114. The base plate 112 is disposed above and in contact with the pedestal 114.

[0021] The substrate support 106 has a support surface 116 configured to support a semiconductor substrate 120 during semiconductor processing. During semiconductor processing, the semiconductor substrate 120 is positioned on the support surface 116 of the substrate support 106. In the illustrated embodiment, the support surface 116 is the top surface of the ESC 108. In the illustration of FIG. 1, the support surface 116 lies in the xy plane.

[0022] The ESC 108 includes a chuck electrode 122. The chuck electrode 122 is configured to have a direct current (DC) voltage applied thereto to chuck the semiconductor substrate 120 onto the support surface 116. The ESC 108 may include a dielectric material coating the chuck electrode 122 to electrically insulate the chuck electrode 122 from direct contact. The ESC 108 further includes a flange 126 at the outer periphery of the ESC 108. The flange 126 is configured to support a focus ring 130 that externally surrounds the semiconductor substrate 120 during plasma semiconductor processing. The flange 126 may be formed of a dielectric material coating the chuck electrode 122. The dielectric material may be or include any non-conductive material, such as aluminum oxide (Al2O3), yttrium oxide (YO3), silicon oxide (SiO2), or the like, or a combination thereof. In some embodiments, the ESC 108 may include a resistive heating element configured to allow an electrical current to flow therethrough, thereby generating thermal energy that is conducted to the semiconductor substrate 120 .

[0023] As described in more detail below, focus ring 130 includes a lower layer 130a and an upper layer 130b above lower layer 130a. Lower layer 130a is supported by flange 126 of ESC 108, and upper layer 130b is supported by lower layer 130a. Lower layer 130a is rotatable about a vertical axis (e.g., z-direction axis). During rotation, lower layer 130a slides or moves along the surface of flange 126 that supports focus ring 130. Upper layer 130b generally does not rotate excessively. As lower layer 130a rotates, upper layer 130b translates in the vertical direction (e.g., z-direction) due to the structure of the upper surface of lower layer 130a and the lower surface of upper layer 130b. The translation of upper layer 130b changes the height of focus ring 130 relative to semiconductor substrate 120.

[0024] The middle plate 110 includes an RF electrode 132. The RF electrode 132 may have a dielectric material thereon to electrically insulate the RF electrode 132 from direct contact with other components. In some embodiments, the middle plate 110 includes fluid channels configured to allow a fluid (e.g., a liquid) to flow therethrough to remove and dissipate thermal energy from the semiconductor substrate 120. The fluid channels may also be referred to as coolers.

[0025] The base plate 112 includes a bias electrode 136. The bias electrode 136 is configured to have a bias signal (e.g., an RF signal) applied thereto to facilitate operability of the RF electrode 132. The bias electrode 136 may have a dielectric material thereon to electrically insulate the bias electrode 136 from direct contact with other components.

[0026] The process apparatus 100 includes a focus ring rotation assembly. The focus ring rotation assembly includes a rotatable frame 138 and a rotation pin 140 that projects vertically from the rotatable frame 138. The rotatable frame 138 projects horizontally from the base 114. The rotation pin 140 is supported by the rotatable frame 138 and extends vertically from the rotatable frame 138. The rotation pin 140 extends through a slot through the flange 126 of the ESC 108 and mechanically couples to the focus ring 130 (e.g., the lower layer 130a). The rotatable frame 138 is rotatable about a vertical axis (e.g., a z-axis), and rotation of the rotatable frame 138 causes the lower layer 130a to rotate about the vertical axis. Additional details of the focus ring rotation assembly are described below.

[0027] The process apparatus 100 further includes a gas distribution plate 142 and a gas showerhead 144 disposed within the interior volume 104 of the chamber 102. The gas distribution plate 142 has an opening therethrough, and the gas showerhead 144 has an opening therethrough. The gas distribution plate 142 and the gas showerhead 144 are electrically connected to a ground node (e.g., electrically grounded). The chamber 102 has a gas inlet 146 fluidly connected to a gas supply system 148 and a gas outlet 150 fluidly connected to an exhaust system 152. The gas distribution plate 142 and the gas showerhead 144 are disposed within the interior volume 104 of the chamber 102 relative to the substrate support 106 such that, during semiconductor processing, gas flows from the gas supply system 148 through the gas inlet 146, through the openings through the gas distribution plate 142, and then through the openings through the gas showerhead 144 to a process volume 154 within the interior volume 104. The process volume 154 is located between the gas showerhead 144 and the substrate support 106 and is typically where a plasma is generated (using a flow of gas into the process volume 154) during semiconductor processing. A semiconductor substrate 120 disposed on the support surface 116 of the substrate support 106 is exposed to the plasma in the process volume 154 during semiconductor processing. The gases then flow through a gas outlet 150 to an exhaust system 152 where they can be exhausted from within the interior volume 104 of the chamber 102.

[0028] The process tool 100 includes a DC power supply 160 and an isolation filter 162. The DC power supply 160 is configured to generate and output a DC voltage. Output nodes (e.g., a positive output node and a negative output node) of the DC power supply 160 are electrically connected to input nodes of the isolation filter 162, and output nodes of the isolation filter 162 are electrically connected to the respective chuck electrodes 122. The isolation filter 162 may be, for example, a low-pass filter. The DC power supply 160 can be selectively turned on and off to chuck and release the semiconductor substrate 120.

[0029] The process apparatus 100 includes an RF power supply 164 and an RF signal control circuit 166. The RF power supply system 164 may include an RF generator and an RF matching network and is configured to generate and output an RF signal, which may be a continuous RF signal and / or a pulsed RF signal, at an output node of the RF power supply 164. The output node of the RF power supply 164 is electrically connected to an input node of the RF signal control circuit 166. The RF signal control circuit 166 is controllable to generate an regulated RF signal based on the RF signal received from the RF power supply 164. The regulated RF signal generated by the RF signal control circuit 166 may have an regulated amplitude of the received RF signal (e.g., a magnitude greater than, equal to, or less than 1, depending on the gain of the RF signal control circuit 166) and / or may have a phase offset from the received RF signal. The gain and / or phase offset may be selectable from a range of gains and / or phase offsets, respectively, that the RF signal control circuit 166 is configured to implement. The RF signal control circuit 166 has an output node electrically connected to the RF electrode 132 of the middle plate 110. The RF signal control circuit 166 is configured to output a regulated RF signal at an output node such that the regulated RF signal can be applied to the RF electrode 132. The RF signal output by the RF signal control circuit 166 can be used to generate and / or control a plasma in the process volume 154.

[0030] The process tool 100 includes an RF power supply 168 and an RF bias control circuit 172. The RF power supply system 168 may include an RF generator and an RF matching network and is configured to generate and output an RF signal, which may be a continuous RF signal and / or a pulsed RF signal, at an output node of the RF power supply 168. The output node of the RF power supply 168 is electrically connected to an input node of the RF bias control circuit 172. Similar to the RF signal control circuit 166, the RF bias control circuit 172 RF power supply 168The RF bias control circuit 172 may be controllable to generate an conditioned RF signal based on the RF signal received from the RF bias control circuit 172. The conditioned RF signal generated by the RF bias control circuit 172 may have an conditioned amplitude of the received RF signal (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the RF bias control circuit 172) and / or may have a phase offset from the received RF signal. The gain and / or phase offset may be selectable from a range of gains and / or phase offsets, respectively, that the RF bias control circuit 172 is configured to implement. The RF bias control circuit 172 has an output node electrically connected to the bias electrode 136 of the base plate 112.

[0031] The base plate 112 may be strongly capacitively coupled to the RF electrode 132 in the middle plate 110 in this embodiment. Therefore, according to some embodiments, the base plate 112 is biased by an RF signal output by an RF bias control circuit 172 to improve the operability of the RF electrode 132 to generate plasma. During operation, the RF bias control circuit 172 outputs an RF signal having a target amplitude and a target phase offset relative to the RF signal applied to the RF electrode 132. Applying such an RF signal to the bias electrode 136 of the base plate 112 can improve the operability of the RF electrode 132 to generate and control plasma.

[0032] The process tool 100 includes an RF power supply 180 and an RF signal control circuit 182. The RF power supply system 180 may include an RF generator and an RF matching network and is configured to generate and output an RF signal, which may be a continuous RF signal and / or a pulsed RF signal, at an output node of the RF power supply 180. The output node of the RF power supply 180 is electrically connected to an input node of the RF signal control circuit 182. The RF signal control circuit 182 is controllable to generate a conditioned RF signal based on the RF signal received from the RF power supply 180. The conditioned RF signal generated by the RF signal control circuit 182 may have an conditioned amplitude of the received RF signal (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the RF signal control circuit 182) and / or may have a phase offset from the received RF signal. The gain and / or phase offset may be selectable from a range of gains and / or phase offsets, respectively, that the RF signal control circuit 182 is configured to implement. RF signal control circuitry 182 has an output node electrically connected to an external electrical connector 186 on lower layer 130a of focus ring 130. RF signal control circuitry 182 is configured to output a regulated RF signal at the output node such that the regulated RF signal can be applied to lower layer 130a. The RF signal output by RF signal control circuitry 182 can be used to control a plasma in process volume 154 near the edge of semiconductor substrate 120.

[0033] The process tool 100 includes a controller 190. The controller 190 may be or include any processor-based system that is or can be a hardened processor architecture, a soft processor (e.g., implemented on the programmable fabric of a Field Programmable Gate Array (FPGA)), or a combination thereof. For example, the controller 190 may be or include a computer, a server, a programmable logic controller (PLC), or the like, or a combination thereof. The controller 190 may control the operation of the process tool 100 and may be programmed to perform the operations of the process tool 100 as described herein. Among other things, the controller 190 is communicatively coupled to the RF signal control circuit 166, the RF bias control circuit 172, and the RF signal control circuit 182. The controller 190 may be programmed to implement various settings for controlling the RF signal control circuit 166, the RF bias control circuit 172, and the RF signal control circuit 182. The setpoints may be implemented in the RF signal control circuits 166, 182 and the RF bias control circuit 172 to implement and / or selectively configure the respective control circuits to achieve the corresponding gain and / or phase offset.

[0034] 1 as being implemented to control a plasma in chamber 102, focus ring 130 may also be implemented in other process tools, such as an ICP process tool. The aspects described herein may be applied to other devices and configurations for controlling a plasma.

[0035] Figure 2A is a layout diagram of focus ring 130 according to some embodiments, showing cross section 2B-2B in the x-z plane shown in Figure 2B, and cross section 2C-2C (approximately in the y-z plane) contoured to coincide with the outer periphery of focus ring 130 shown in Figure 2C.

[0036] Referring to FIG. 2B , the upper layer 130b is above and supported by the lower layer 130a. The lower layer 130a includes an electrode 202. The electrode 202 is electrically connected to an external electrical connector 186, which is configured to be electrically connected to the RF signal control circuitry 182. A dielectric material 204 covers the electrode 202 and also forms a flange 206 that protrudes vertically (e.g., in the z-direction) along the outer edge of the lower layer 130a and limits movement of the upper layer 130b. The dielectric material 204 can electrically insulate the electrode 202 from direct electrical contact with other components. The flange 206 of the lower layer 130a can externally limit the upper layer 130b relative to the lower layer 130a. As generally described above, the lower layer 130a may rotate relative to the upper layer 130b. When such rotation occurs, the flanges 206 may externally confine the upper layer 130b within the outer boundary of the lower layer 130a to facilitate proper engagement between the lower layer 130a and the upper layer 130b.

[0037] Upper layer 130b may be formed of dielectric material 208 or any other material that is resistant to plasma semiconductor processes (e.g., etching processes) to which focus ring 130 will be exposed. Dielectric materials 204, 208 in embodiments for lower layer 130a and upper layer 130b include any non-conductive material, such as aluminum oxide (Al2O3), yttrium oxide (YO3), silicon oxide (SiO2), etc., or combinations thereof. Electrode 202 may be formed of any conductive material (e.g., a metal), such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc., or combinations thereof.

[0038] Lower layer 130a has inner vertical sidewall 212, and upper layer 130b has inner vertical sidewall 214. Radial distance 216 is from inner vertical sidewall 212 of lower layer 130a to center 210 of focus ring 130. Radial distance 218 is from inner vertical sidewall 214 of upper layer 130b to center 210 of focus ring 130. Radial distance 218 is less than radial distance 216. Upper layer 130b extends further inward toward center 210 of focus ring 130 than lower layer 130a. This further inward extension of upper layer 130b enables the formation of particle traps 220 below the inward extension of upper layer 130b along inner vertical sidewall 212 of lower layer 130a. Particle traps 220 may be areas where particles accumulate. Particles that accumulate in particle trap 220 may originate from the surfaces of lower layer 130a and upper layer 130b rubbing against each other during relative rotation of lower layer 130a. Particle trap 220 may prevent particles from contaminating the plasma semiconductor process.

[0039] Lower layer 130a has an upper surface 230a, and upper layer 130b has a lower surface 230b. Lower surface 230b of upper layer 130b is disposed on, contacts, and is supported by upper surface 230a of lower layer 130a. Cross section 2C-2C intersects upper surface 230a and lower surface 230b. FIG. 2C shows cross section 2C-2C, which is a circumferential cross section of a portion of focus ring 130. In the embodiment illustrated in FIG. 2C, upper surface 230a and lower surface 230b are complementary, and in other embodiments, the upper and lower surfaces may not be complementary, as shown in subsequent figures.

[0040] Upper surface 230a and lower surface 230b are circumferentially periodic around focus ring 130 and have the same periodic length at a given radial distance 260 ( FIG. 2A ) from center 210 of focus ring 130. Protrusion / recess radius line 240, recess / protrusion radius line 242, and protrusion / recess radius line 244 of upper surface 230a and lower surface 230b are shown within periodic length 250 at radial distance 260. Protrusion / recess radius line 240, recess / protrusion radius line 242, and protrusion / recess radius line 244 are protrusion radius line, recess radius line, and protrusion radius line, respectively, for upper surface 230a, and are recess radius line, protrusion radius line, and recess radius line, respectively, for lower surface 230b. Periodic length 250 is shown between protrusion / recess radius lines 240 and 244. The period length 250 is symmetrical about a center line of the period length 250 (eg, recess / protrusion radius line 242).

[0041] Protrusion / recess radius line 240, recess / protrusion radius line 242, and protrusion / recess radius line 244 are shown in FIG. 2D along a layout diagram of the corresponding portion of focus ring 130. The layout diagram in FIG. 2D illustrates the radial nature of radius lines 240, 242, and 244. Additionally, the period of focus ring 130 generally reflects the radial nature. For example, the period length along the outer periphery of focus ring 130 for a given period is longer than the period length along the inner periphery of focus ring 130 for the same given period.

[0042] Upper surface 230a and lower surface 230b are continuous surfaces between adjacent pairs of protrusion and recess radii. For example, upper surface 230a is continuous from protrusion / recess radius line 240 to recess / protrusion radius line 242, and upper surface 230a is continuous from recess / protrusion radius line 242 to protrusion / recess radius line 244. Furthermore, lower surface 230b is continuous from protrusion / recess radius line 240 to recess / protrusion radius line 242, and lower surface 230b is continuous from recess / protrusion radius line 242 to protrusion / recess radius line 244. In the illustrated embodiment, both the upper surface 230a and the lower surface 230b are continuous surfaces between adjacent pairs of protrusion and recess radius lines, and in other embodiments, as shown in later figures, one of the upper and lower surfaces is a continuous surface between adjacent pairs of protrusion and recess radius lines.

[0043] In the illustrated embodiment, the upper surface 230a and the lower surface 230b are continuous at the protrusion and recess radius lines (e.g., at the protrusion / recess radius line 240, the recess / protrusion radius line 242, and the protrusion / recess radius line 240), but in other embodiments, the upper surface 230a and the lower surface 230b may be discontinuous at the protrusion and recess radius lines. For example, the upper surface 230a and / or the lower surface 230b may be discontinuous at a vertex line (e.g., of a triangular prism), as described below.

[0044] In the illustrated embodiment, the upper and lower surfaces 230a, 230b are sinusoidal surfaces, although other continuous surfaces having periodic structures are contemplated in other embodiments. In further embodiments, the upper and lower surfaces 230a, 230b repeat triangular or other discontinuous surfaces at the protrusion and recess radius lines.

[0045] 3 and 4 illustrate height adjustment of focus ring 130 according to some embodiments. Referring to FIG. 3, focus ring 130 has height 302. Height 302 is the minimum height that focus ring 130 can have. For ease of reference, height 302 is designated height h0. At height h0, the protrusion radius line of upper surface 230a meets the respective recess radius line of lower surface 230b, and similarly, the recess radius line of upper surface 230a meets the respective protrusion radius line of lower surface 230b. In the arrangement of FIG. 3, protrusion radius line 304 of upper surface 230a and protrusion radius line 306 of lower surface 230b are shown for reference.

[0046] In FIG. 4 , focus ring 130 has height 402. Height 402 is the maximum height that focus ring 130 can have. Height 402 is height h0 plus twice the amplitude of the periodic structures on upper surface 230a and lower surface 230b. At height 402, the protrusion radius lines on upper surface 230a contact the respective protrusion radius lines on lower surface 230b. Protrusion radius lines 304 on upper surface 230a and protrusion radius lines 306 on lower surface 230b are also shown in the arrangement of FIG. 4 for reference.

[0047] Rotation 404 of lower layer 130a is half the period length of upper surface 230a and lower surface 230b relative to the position of upper layer 130b. Continuing to rotate lower layer 130a relative to upper layer 130b through a full period returns the focus ring to height 302 of FIG. 3. Continuing to rotate lower layer 130a relative to upper layer 130b results in periodic variation of the height of focus ring 130 between heights 302 and 402 without hard resetting lower layer 130a or upper layer 130b to adjust the height.

[0048] FIG. 5 is a simplified cross-sectional view of a focus ring rotation assembly, and FIG. 6 is a perspective view of the focus ring rotation assembly, according to some embodiments. Semiconductor substrate 120 and focus ring 130 are shown in FIGS. 5 and 6 for context, as are substrate support 106, pedestal 114, and controller 190 in FIG. 5 . The focus ring rotation assembly further includes a motor 502 having a drive shaft 504. In some embodiments, motor 502 is a stepper motor, and in other embodiments, motor 502 can be another type of motor. Motor 502 is configured to rotate 506 drive shaft 504 about a vertical axis 508 (e.g., the z-direction) perpendicular to the top surface of semiconductor substrate 120 and / or support surface 116. Rotatable frame 138 is mechanically attached to and supported by drive shaft 504. As previously mentioned, rotation pins 140 are supported by and extend vertically from rotatable frame 138. Rotation pins 140 extend through respective slots through flange 126 of ESC 108 and engage lower layer 130a of focus ring 130. Motor 502 is communicatively coupled to controller 190, and controller 190 is configured to control operation of motor 502.

[0049] In operation, motor 502 rotates 506 drive shaft 504 about vertical axis 508, which in this embodiment corresponds to the axis of drive shaft 504. Rotation 506 of drive shaft 504 causes rotatable frame 138 to rotate about vertical axis 508. Due to the mechanical connection between rotatable frame 138 and lower layer 130a of focus ring 130 by rotation pin 140, as rotatable frame 138 rotates about vertical axis 508, lower layer 130a rotates about vertical axis 508.

[0050] Substrate support 106 (e.g., ESC 108) supporting focus ring 130 further includes a stop mechanism that prevents rotation of upper layer 130b of focus ring 130 when lower layer 130a of focus ring 130 rotates. In some embodiments, the stop mechanism includes a pin extending horizontally from a sidewall of substrate support 106 (e.g., ESC 108) into upper layer 130b. In some embodiments, the stop mechanism includes a pin extending vertically from an upper surface of substrate support 106 (e.g., ESC 108) supporting focus ring 130.

[0051] FIG. 7A is a layout diagram of focus ring 130 on flange 126 of ESC 108, according to some embodiments. In this embodiment, the stop mechanism includes stop pins 702 extending horizontally from a vertical sidewall of substrate support 106 (e.g., ESC 108) into respective slots 704 in upper layer 130b. The embodiment of FIG. 7A includes three stop pins 702, although other numbers of stop pins may be used. FIG. 7A also shows rotation pins 140 extending vertically through respective circumferential slots 710 through flange 126 of ESC 108 and engaging respective recesses 712 in lower layer 130a of focus ring 130. The embodiment of FIG. 7A includes three rotation pins 140, although other numbers of pins may be used (e.g., as shown in previous figures). FIG. 7A also shows cross section 7B through stop pin 702 and cross section 7C through rotation pin 140. FIG. 7B shows cross section 7B in more detail, and FIG. 7C shows cross section 7C in more detail.

[0052] 7A-7C, as previously described, semiconductor substrate 120 is disposed on and supported by support surface 116 of substrate support 106 (e.g., ESC 108), and ESC 108 includes flange 126 on which focus ring 130 is disposed. Focus ring 130, including lower layer 130a and upper layer 130b, is disposed to externally surround semiconductor substrate 120.

[0053] 7A and 7B, ESC 108 includes, for each stop pin 702, an actuator 706 on a side of ESC 108 extending from the top of flange 126. Actuator 706 is mechanically coupled to stop pin 702 to push and retract stop pin 702. In the retracted position, stop pin 702 does not engage slot 704 in top layer 130b of focus ring 130. In the pushed-out position, stop pin 702 engages slot 704, as shown in FIG. 7B. Slot 704 has a horizontal depth (e.g., along the y-direction in FIG. 7B ) from the inner sidewall of top layer 130b of focus ring 130 sufficient to accommodate stop pin 702 in the pushed-out position. The horizontal depth is measured along a radial direction intersecting slot 704 from the center of focus ring 130 to the edge of focus ring 130. Slot 704 has a horizontal width (e.g., along the x-direction in FIG. 7B ) that is generally the corresponding horizontal width of stop pin 702 (e.g., plus any tolerances). The horizontal width lies in a plane parallel to support surface 116 and is perpendicular to a radial direction from the center of focus ring 130 to the edge of focus ring 130 that intersects slot 704. Slot 704 has a vertical length (e.g., along the z-direction in FIG. 7B ) that generally corresponds to a vertical travel distance that upper layer 130b may translate vertically as a result of rotation of lower layer 130a. The vertical length lies in a plane perpendicular to support surface 116 and is perpendicular to a radial direction from the center of focus ring 130 to the edge of focus ring 130 that intersects slot 704.

[0054] 7A and 7C , for each rotation pin 140, the rotation pin 140 extends vertically through a respective circumferential slot 710 through flange 126 and engages a respective recess 712 in the bottom surface of lower layer 130a of focus ring 130. Circumferential slot 710 has a horizontal circumferential length (e.g., in the x-y plane) corresponding to the allowable rotational travel of rotation pin 140 and lower layer 130a. The horizontal circumferential length is along an arc perpendicular to the respective radial direction that intersects the arc. Circumferential slot 710 has a horizontal width (e.g., along the radial direction) that is generally the corresponding horizontal width of rotation pin 140 (e.g., plus any tolerances). Recess 712 has a vertical depth (e.g., in the z-direction) from the bottom surface of lower layer 130a. The bottom surface of lower layer 130a contacts and is supported by the upper surface of flange 126. The vertical depth of the recess 712 is, for example, deep enough to accommodate a rotation pin 140 engaging the recess 712 without the rotation pin 140 vertically supporting the lower layer 130a. The recess 712 has horizontal dimensions (e.g., in the x-direction and in the y-direction) that are generally the corresponding horizontal dimensions (e.g., plus any tolerances) of the rotation pin 140.

[0055] In operation, rotation of the rotatable frame 138 (as described above) causes the rotation pin 140 to translate circumferentially within the circumferential slot 710. This translation of the rotation pin 140, which engages with the recess 712 in the lower layer 130a, causes the lower layer 130a to rotate about the rotation axis of the rotatable frame 138, which may correspond to the center of the support surface 116. With the stop pin 702 in the pushed-out position and engaged in the slot 704, the upper layer 130b is prevented from over-rotating by the lower layer 130a, and therefore the lower layer 130a rotates relative to the upper layer 130b (and the ESC 108). Rotation of the lower layer 130a relative to the upper layer 130b may cause the upper layer 130b to translate vertically, allowing the stop pin 702 to move vertically within the slot 704. As described with respect to FIGS. 3 and 4, the height of focus ring 130 can be varied by relative rotation of lower layer 130a and vertical movement of upper layer 130b.

[0056] FIG. 8A is a layout diagram of the focus ring 130 on the flange 126 of the ESC 108, according to some embodiments. In this embodiment, the stop mechanism includes stop pins 802 extending vertically from the upper surface of the flange 126 through respective circumferential slots 804 through the lower layer 130a into respective recesses 806 in the upper layer 130b. The embodiment of FIG. 8A includes three stop pins 802, although other numbers of stop pins may be used. FIG. 8A also illustrates the rotation pin 140, as in FIG. 7A. FIG. 8A illustrates cross section 8B through the stop pin 802 and cross section 7C through the rotation pin 140. FIG. 8B illustrates cross section 8B in more detail, and FIG. 7C illustrates cross section 7C as previously described. Descriptions of features in FIGS. 8A and 8B that are similar to those discussed above with respect to FIGS. 7A–7C are omitted for brevity.

[0057] 8A and 8B, stop pin 802 extends vertically from the upper surface of flange 126, which contacts and supports focus ring 130 (e.g., lower layer 130a). Stop pin 802 may be fixed in the embodiment of FIGS. 8A and 8B. Circumferential slot 804 has a horizontal circumferential length (e.g., in the x-y plane) corresponding to the allowable horizontal rotational movement of lower layer 130a relative to flange 126. The horizontal circumferential length is along an arc perpendicular to each radial direction that intersects the arc. Circumferential slot 804 has a horizontal width (e.g., along the radial direction) that is generally the corresponding horizontal width (e.g., plus any tolerances) of stop pin 802. Recess 806 has a vertical depth (e.g., in the z-direction) from lower surface 230b of upper layer 130b. The vertical depth of recess 806 is sufficient to accommodate stop pin 802, which engages in recess 806, as upper layer 130b translates vertically at different heights of focus ring 130. Furthermore, stop pin 802 has a vertical height sufficient to extend through circumferential slot 804 in lower layer 130a and engage recess 806 in upper layer 130b at each height that focus ring 130 can achieve (which may be limited, for example, by the travel distance of rotation pin 140 in conjunction with the structure of upper surface 230a and lower surface 230b). Recess 806 has horizontal dimensions (e.g., in the x-direction and the y-direction) that are generally the corresponding horizontal dimensions of stop pin 802 (e.g., plus any tolerances).

[0058] In operation, rotation of the rotatable frame 138 (as described above) causes the rotation pin 140 to translate circumferentially within the circumferential slot 710. This translation of the rotation pin 140, which engages with the recess 712 in the lower layer 130a, causes the lower layer 130a to rotate about the axis of rotation of the rotatable frame 138, which may correspond to the center of the support surface 116. When the stop pin 802 engages the recess 806, the upper layer 130b is prevented from over-rotating by the lower layer 130a, and therefore the lower layer 130a rotates relative to the upper layer 130b (and the flange 126 of the ESC 108). Rotation of the lower layer 130a relative to the upper layer 130b may cause the upper layer 130b to translate vertically, such that the recess 806 is translated vertically relative to the stop pin 802. As described with respect to FIGS. 3 and 4, the height of focus ring 130 can be varied by relative rotation of lower layer 130a and vertical movement of upper layer 130b.

[0059] 9 and 10 conceptually illustrate how the height of focus ring 130 can affect plasma control in some embodiments. FIGS. 9 and 10 are cross-sectional views of semiconductor substrate 120 and focus ring 130 (as disposed in process tool 100 of FIG. 1). For example, in FIG. 9 , focus ring 130 has height 302 of FIG. 3 , and in FIG. 10 , focus ring 130 has height 402 of FIG. 4 . Referring to FIG. 9 , plasma sheath 902 descends toward the gap between the edge of semiconductor substrate 120 and focus ring 130. Because plasma sheath 902 is generally flat at the center of semiconductor substrate 120, ion bombardment 904 from the plasma at the center of semiconductor substrate 120 can be generally perpendicular to the top surface of semiconductor substrate 120. At the edge of semiconductor substrate 120, plasma sheath 902 curves as the plasma sheath descends toward the gap, so that ion impacts 906 from the plasma at the edge of semiconductor substrate 120 may not generally be perpendicular to the top surface of semiconductor substrate 120 (e.g., at a slight angle from vertical). Referring to FIG. 10 , increasing the height of focus ring 130 can provide a flatter extension of plasma sheath 1002 beyond the edge of semiconductor substrate 120. Thus, both ion impacts 1004 at the center of semiconductor substrate 120 and ion impacts 1006 at the edge of semiconductor substrate 120 may be generally perpendicular to the top surface of semiconductor substrate 120.

[0060] 11 illustrates a processor-based system 1100 according to some embodiments. The processor-based system 1100 may be or include a computer, a server, a PLC, etc., or a combination thereof. The processor-based system 1100 may be implemented as a controller 190 or any other processor-based system that performs any of the operations described herein. The processor-based system 1100 includes one or more processors 1102, a memory system 1112, a communication bus 1122, one or more input / output (I / O) interfaces 1132, and a network interface 1142.

[0061] Each processor 1102 may include one or more processor cores 1104. Each processor 1102 and / or processor core 1104 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an enhanced processor such as an application specific integrated circuit (ASIC), or a combination thereof, or a soft processor implemented in programmable logic such as an FPGA.

[0062] The memory system 1112 includes one or more memory controllers 1114 and memories 1116. The memory controller 1114 is configured to control read and / or write access to a particular memory 1116 or a subset of the memories 1116. The memory 1116 may include main memory, disk storage, or any suitable combination thereof. The memory 1116 may include any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage, etc. The memory 1116 is a non-transitory machine-readable storage medium. Instructions 1118 are stored in the memory 1116. The instructions 1118 may be machine-executable code (e.g., machine code) and may include firmware, software, programs, applications, or other machine-executable code. The instructions 1118 may embody, for example, software modules 1120, which, when executed by the one or more processors 1102, perform various functions and operations described herein.

[0063] The one or more I / O interfaces 1132 are configured to be electrically and / or communicatively coupled to one or more I / O devices 1134. The I / O devices 1134 include the RF signal control circuit 166, the RF bias control circuit 172, the RF signal control circuit 182, and the motor 502. The RF signal control circuit 166, the RF bias control circuit 172, the RF signal control circuit 182, and the motor 502 can receive their respective setting values via the I / O interface 1132. In other embodiments, the I / O devices 1134 include a keyboard, a mouse, a display device, a printer, etc. The one or more I / O interfaces 1132 may include connectors or coupling circuits such as an industrial application connection, a Universal Serial Bus (USB) connection, a High-Definition Multimedia Interface (HDMI®) connection, a Bluetooth® circuit, etc.

[0064] The network interface 1142 is configured to be communicatively coupled to a network 1144. The network interface 1142 can include circuitry for wired communication, such as an Ethernet connection, and / or can include circuitry for wireless communication, such as circuitry for Wi-Fi® communication. For example, one or more computers and / or servers communicatively coupled to the network 1144 may communicate recipes, process conditions, etc. to the processor-based system 1100 via the network 1144 and the network interface 1142.

[0065] The communication bus 1122 is communicatively coupled to one or more processors 1102, the memory system 1112, one or more I / O interfaces 1132, and the network interface 1142. The various components may communicate with one another via the communication bus 1122. The communication bus 1122 may control the flow of communication, such as by including an arbiter that arbitrates communications.

[0066] 12 is a flowchart of a method 1200 of semiconductor processing according to some embodiments. Method 1200 can be implemented using the process tool 100 described above. Operation of method 1200 can be initiated and / or controlled by controller 190 (e.g., by execution of instructions 1118 by one or more processors 1102). At block 1202, a semiconductor substrate 120 is transferred into chamber 102 of process tool 100 and placed on a substrate support 106 (e.g., ESC 108) within chamber 102. Concurrently with the transfer of semiconductor substrate 120 into chamber 102, focus ring 130 can be positioned on flange 126 of ESC 108. Focus ring 130 can have a minimum height h0. Semiconductor substrate 120 can be secured to ESC 108 by applying a DC voltage to chuck electrode 122 (e.g., to chuck semiconductor substrate 120). A DC voltage may be generated by a DC power supply 160 and applied to chuck electrode 122. After semiconductor substrate 120 is transferred into chamber 102 and placed on support surface 116, focus ring 130 is positioned to surround semiconductor substrate 120 from the outside.

[0067] In block 1204, the height of focus ring 130 is adjusted. The height can be adjusted to a desired height for targeted plasma control. The height can be adjusted by rotating lower layer 130a relative to upper layer 130b, as described above. Controller 190 can cause motor 502 to rotate rotatable frame 138, which rotates lower layer 130a relative to upper layer 130b. This adjusts the height of focus ring 130.

[0068] In block 1206, a plasma semiconductor process is performed in the chamber 102 of the process tool 100. The plasma semiconductor process can be, for example, an etching process, a deposition process, or any other applicable process. Plasma semiconductor processes in embodiments include sputtering, PVD, MDP, PECVD, IBE, and RIE. Block 1206 includes, in block 1208, generating a plasma in the process volume 154 of the chamber 102. The semiconductor substrate 120 can be exposed to the plasma in the process volume 154. The plasma can be generated by flowing gas into the chamber 102 (e.g., from the gas supply system 148 through the gas inlet 146, the gas distribution plate 142, and the gas showerhead 144) and applying an RF signal to the RF electrode 132. The plasma can be generated as a result of the RF signal when the RF electrode 132 and the gas showerhead 144 are grounded. Block 1206 further includes, in block 1210, controlling the plasma at the periphery of the semiconductor substrate 120. Although described separately for simplicity, blocks 1208 and 1210 can be implemented by the same operations. The plasma can be controlled by applying an RF signal to RF electrode 132. The plasma can be controlled at the periphery using focus ring 130 based on the height of the focus ring, as described with respect to FIGS. 9 and 10 . Additionally, an RF signal can be applied to electrode 202 in lower layer 130 a of focus ring 130 to control the plasma at the periphery of semiconductor substrate 120. RF power supply 180 can generate an RF signal that is output to RF signal control circuitry 182, which may adjust the RF signal (to an adjusted amplitude and / or phase) to output the adjusted RF signal. The RF signal output by RF signal control circuitry 182 is applied to electrode 202 in lower layer 130 a. The RF signal to electrode 202 can partially control the electromagnetic field at the periphery of semiconductor substrate 120 to control the plasma at the periphery. Additionally, biasing of the bias electrode 136 can be performed during blocks 1208 and 1210 .Biasing may include applying an RF bias signal to the bias electrode 136 .

[0069] In block 1212, the plasma semiconductor process is terminated, and semiconductor substrate 120 is transferred from chamber 102 of process tool 100 to its exit. Upon termination of the plasma semiconductor process, RF signals can be deactivated to RF electrode 132 and electrode 202 of focus ring 130 (e.g., RF power systems 164, 180 are turned off), and gas can be deactivated and evacuated from chamber 102 to its exit. Additionally, RF bias signals can be deactivated to bias electrode 136. Focus ring 130 can then be adjusted back to its minimum height h0. The DC voltage can also be deactivated (e.g., by turning off DC power supply 160) to release semiconductor substrate 120 from ESC 108. Semiconductor substrate 120 can then be transferred from chamber 102 to its exit.

[0070] FIG. 13 is a flowchart of a method 1300 for semiconductor processing according to some embodiments. At block 1302, a plasma semiconductor process, such as that described with respect to FIG. 12, is performed on a first plurality of semiconductor substrates (e.g., one or more lots of semiconductor substrates) using process tool 100. The plasma semiconductor process is performed under first process conditions. The first process conditions include settings for RF signal control circuitry 182 and motor 502. Based on these settings, an RF signal is applied to electrode 202 of focus ring 130 during the plasma semiconductor process, and the height of focus ring 130 is set for the plasma semiconductor process.

[0071] At block 1304, a first property of each of the first plurality of semiconductor substrates near a center of each of the first plurality of substrates is measured, and at block 1306, a second property of each of the first plurality of semiconductor substrates near an edge of each of the first plurality of substrates is measured. The first property and the second property may be the same feature or component, and "first" and "second" are used for ease of reference. The measurements may be performed by a metrology device. In some embodiments, the first and second properties may be or include a profile angle of a recess etched by the plasma semiconductor process. In some embodiments, the first and second properties may be or include a depth of a recess etched by the plasma semiconductor process. In some embodiments, the first and second properties may be or include a thickness of a film deposited by the plasma semiconductor process. Other properties may be measured. Variation between the first property and the second property may indicate non-uniformity of the plasma during the plasma semiconductor process as the first plurality of substrates are processed.

[0072] At block 1308, one or more processor-based systems are used to determine second process conditions to be applied in the process tool while the plasma semiconductor process is performed on the second plurality of semiconductor substrates. The second process conditions are determined based on the first and second characteristics measured in blocks 1304 and 1306, such as a difference between the first and second characteristics. The second process conditions are of the same type as the first process conditions, but the values or data of the first and second process conditions may be different. In one embodiment, a processor-based system running an Advanced Process Control (APC) algorithm may determine the RF signal (including amplitude and phase) applied to electrode 202 of focus ring 130 and may determine the height of focus ring 130. The processor-based system running the APC algorithm may then determine setpoints for setting RF signal control circuitry 182 and motor 502.

[0073] In block 1310, second process conditions are applied to a process tool for a plasma semiconductor process. For example, a processor-based system running an APC algorithm may communicate the second process conditions to controller 190 (e.g., via network 1144). Controller 190 may reset a recipe for the plasma semiconductor process to have the second process conditions, communicate the second process conditions (e.g., setpoints) to RF signal control circuitry 182, which may selectively configure RF signal control circuitry 182 based on the second process conditions, and communicate the second process conditions to motor 502, which may cause motor 502 to adjust the height of focus ring 130.

[0074] At block 1312, a plasma semiconductor process is performed on a second plurality of semiconductor substrates using process tool 100. The plasma semiconductor process is performed under second process conditions. Based on the setpoints of the second process conditions, motor 502 rotates lower layer 130a relative to upper layer 130b to achieve the height of focus ring 130, and an RF signal is applied to electrode 202 during the plasma semiconductor process.

[0075] Figures 14, 15, 16, 17, and 18 are cross-sectional views of focus rings 1430, 1530, 1630, 1730, and 1830, respectively, according to some embodiments. The cross sections in these figures are taken along section 2C-2C in Figure 2A. Focus rings 1430, 1530, 1630, 1730, and 1830 may be similar to focus ring 130 described above, except for the upper surface of the lower layer and / or the lower surface of the upper layer of each focus ring 1430, 1530, 1630, 1730, and 1830.

[0076] Referring to FIG. 14 , lower layer 1430a of focus ring 1430 has upper surface 1440a, and upper layer 1430b of focus ring 1430 has lower surface 1440b. Lower surface 1440b of upper layer 1430b is disposed on, in contact with, and supported by upper surface 1440a of lower layer 1430a. Upper surface 1440a and lower surface 1440b are complementary to one another. Upper surface 1440a and lower surface 1440b are circumferentially periodic around focus ring 1430 and have the same periodic length at a given radial distance from the center of focus ring 1430. Protrusion / recess radius line 1450, recess / protrusion radius line 1452, and protrusion / recess radius line 1454 of upper surface 1440a and lower surface 1440b are shown with a periodic length 1460 at a given radial distance from the center of focus ring 1430. Protrusion / recess radius line 1450, recess / protrusion radius line 1452, and protrusion / recess radius line 1454 are protrusion, recess, and protrusion radius lines, respectively, for upper surface 1440a, and recess, protrusion, and recess radius lines, respectively, for lower surface 1440b. Periodic length 1460 is shown between protrusion / recess radius lines 1450 and 1454. Periodic length 1460 is symmetrical about a center line of periodic length 1460 (e.g., recess / protrusion radius line 1452).

[0077] The upper surface 1440a and the lower surface 1440b are continuous surfaces between adjacent pairs of protrusion and recess radii. For example, the upper surface 1440a is continuous from the protrusion / recess radius line 1450 to the recess / protrusion radius line 1452, and the upper surface 1440a is continuous from the recess / protrusion radius line 1452 to the protrusion / recess radius line 1454. Furthermore, the lower surface 1440b is continuous from the protrusion / recess radius line 1450 to the recess / protrusion radius line 1452, and the lower surface 1440b is continuous from the recess / protrusion radius line 1452 to the protrusion / recess radius line 1454.

[0078] In the illustrated embodiment, the upper surface 1440a and the lower surface 1440b are discontinuous surfaces at the protrusion and recess radius lines (e.g., at the protrusion / recess radius line 1450, the recess / protrusion radius line 1452, and the protrusion / recess radius line 1450). In the illustrated embodiment, the upper surface 1440a and the lower surface 1440b are surfaces that repeat a triangular prism.

[0079] Referring to FIG. 15 , focus ring 1530 has lower layer 130a with upper surface 230a, as previously described. Upper layer 1530b has lower surface 1540b. Lower surface 1540b of upper layer 1530b is disposed on, in contact with, and supported by upper surface 230a of lower layer 130a. Lower surface 1540b is generally flat with protrusions 1542 extending from the flat surface. Lower surface 1540b does not complement upper surface 230a. Upper surface 230a of lower layer 130a is periodic and has protrusion radius line 1550, recess radius line 1552, and protrusion radius line 1554 at a given radial distance from the center of focus ring 1530 within period length 1560. The protrusions 1542 on the lower surface 1540b of the upper layer 1530b are arranged circumferentially around the focus ring 1530 at the same periodic length 1560 at a given radial distance from the center of the focus ring 1530. The periodic length 1560 of the lower surface 1540b is symmetrical about a radial line intersecting each of the protrusions 1542. In this embodiment, the lower surface 1540b is discontinuous between adjacent pairs of protrusion and recess radial lines (e.g., for a single recess radial line arbitrarily placed on a flat surface, the lower surface 1540b is not continuous to both of the neighboring protrusion radial lines on either side of the recess radial line).

[0080] Referring to FIG. 16 , focus ring 1630 has upper layer 130b with lower surface 230b, as previously described. Lower layer 1630a has upper surface 1640a. Lower surface 230b of upper layer 130b is disposed on, in contact with, and supported by upper surface 1640a of lower layer 1630a. Upper surface 1640a is generally a flat surface with protrusions 1642 extending from the flat surface. Upper surface 1640a does not complement lower surface 230b. Lower surface 230b of upper layer 130b is periodic and, within period length 1660, extends beyond the focus ring. 1630 At a given radial distance from the center of focus ring 1630, protrusion radius line 1650, recess radius line 1652, and protrusion radius line 1654. Protrusion 1642 on upper surface 1640a of lower layer 1630a extends circumferentially around focus ring 1630. 1630 At a given radial distance from the center of the projections 1642, the projections 1642 are arranged with the same periodic length 1660. The periodic length 1660 of the upper surface 1640a is symmetrical about a radial line intersecting each of the projections 1642. In this embodiment, the upper surface 1640a is discontinuous between adjacent pairs of projection and recess radius lines (e.g., for a single recess radius line arbitrarily placed on a flat surface, the upper surface 1640a is not continuous to both of the neighboring projection radius lines on either side of the recess radius line).

[0081] Referring to FIG. 17 , focus ring 1730 has lower layer 1430a with upper surface 1440a, as previously described. Upper layer 1730b has lower surface 1740b. Lower surface 1740b of upper layer 1730b is disposed on, in contact with, and supported by upper surface 1440a of lower layer 1430a. Lower surface 1740b is generally a flat surface with protrusions 1742 extending from the flat surface. Lower surface 1740b does not complement upper surface 1440a. Upper surface 1440a of lower layer 1430a is periodic and within period length 1760, the focus ring 1730At a given radial distance from the center of focus ring 1730, protrusion radius line 1750, recess radius line 1752, and protrusion radius line 1754. Protrusion 1742 on lower surface 1740b of upper layer 1730b extends circumferentially around focus ring 1730. 1730 At a given radial distance from the center of the projection 1742, the projections 1742 are arranged with the same periodic length 1760. The periodic length 1760 of the lower surface 1740b is symmetrical about the radial line that intersects each of the projections 1742. In this embodiment, the lower surface 1740b is discontinuous between adjacent pairs of projection and recess radial lines (e.g., for one recess radial line arbitrarily placed on a flat surface, the lower surface 1740b is not continuous to both of the neighboring projection radial lines on either side of the recess radial line).

[0082] Referring to FIG. 18 , focus ring 1830 has an upper layer 1430b with a lower surface 1440b, as previously described. Lower layer 1830a has an upper surface 1840a. Lower surface 1440b of upper layer 1430b is disposed on, in contact with, and supported by upper surface 1840a of lower layer 1830a. Upper surface 1840a is generally a flat surface with protrusions 1842 extending from the flat surface. Upper surface 1840a is not complementary to lower surface 1440b. Lower surface 1440b of upper layer 1430b is periodic and within period length 1860, the focus ring 1830 At a given radial distance from the center of focus ring 1830, protrusion radius line 1850, recess radius line 1852, and protrusion radius line 1854. Protrusion 1842 on upper surface 1840a of lower layer 1830a extends circumferentially around focus ring 1830. 1830 At a given radial distance from the center of the projections 1842, the projections 1842 are arranged with the same periodic length 1860. The periodic length 1860 of the upper surface 1840a is symmetrical about a radial line that intersects each of the projections 1842. In this embodiment, the upper surface 1840a is discontinuous between adjacent pairs of projection and recess radius lines (e.g., for a single recess radius line arbitrarily placed on a flat surface, the upper surface 1840a is not continuous to both of the neighboring projection radius lines on either side of the recess radius line).

[0083] Various upper and lower surfaces of the lower and upper focus ring layers have been provided as examples. Other modifications and arrangements of the upper and lower surfaces of the lower and upper focus ring layers can be implemented according to other embodiments.

[0084] A first embodiment is a component for semiconductor processing. The component includes a focus ring configured to surround a semiconductor substrate from the outside during plasma semiconductor processing. The focus ring includes a first ring layer having a lower surface and a second ring layer having an upper surface. The upper surface is configured to support the first ring layer by contacting the lower surface with the upper surface. The lower and upper surfaces are periodic around the circumference. The lower and upper surfaces have the same periodic length at the same first radial distance from the center of the focus ring. At least one of the lower and upper surfaces includes a first protrusion radius line, a first recess radius line, and a second protrusion radius line. The first recess radius line is horizontally disposed between the first protrusion radius line and the second protrusion radius line. The periodic length at the first radial distance is the length from the first protrusion radius line to the second protrusion radius line. At least one of the lower surface and the upper surface from the first protrusion radial line to the first recess radial line is continuous. At least one of the lower surface and the upper surface from the first recess radial line to the second protrusion radial line is continuous. The second ring layer is horizontally rotatable relative to the first ring layer while the upper surface supports the first ring layer.

[0085] In a first embodiment, at least one of the lower surface and the upper surface may be continuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

[0086] In a first embodiment, at least one of the lower surface and the upper surface may be discontinuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

[0087] In the first embodiment, the periodic length at the first radial distance from the first protrusion radial line to the second protrusion radial line may be symmetrical about the first recess radial line.

[0088] In a first embodiment, at least one of the lower surface and the upper surface may be a sinusoidal surface, and each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line may lie within the sinusoidal surface.

[0089] In the first embodiment, the other of the lower surface and the upper surface may include a second recess radius line, a third protrusion radius line, and a third recess radius line. The third protrusion radius line may be horizontally disposed between the second recess radius line and the third recess radius line. The periodic length at the first radial distance may be the length from the second recess radius line to the third recess radius line. The other of the lower surface and the upper surface may be continuous from the second recess radius line to the third protrusion radius line. The other of the lower surface and the upper surface may be continuous from the third protrusion radius line to the third recess radius line. Furthermore, in the component, the other of the lower surface and the upper surface may be continuous at each of the second recess radius line, the third protrusion radius line, and the third recess radius line. Additionally, in the component, the other of the lower surface and the upper surface may be discontinuous at each of the second recess radius line, the third protrusion radius line, and the third recess radius line.

[0090] In a first embodiment, the lower and upper surfaces may each be sinusoidal surfaces. The upper surface may be complementary to the lower surface.

[0091] In a first embodiment, the first ring layer may be a non-conductive material.

[0092] In a first embodiment, the second ring layer may include a conductive electrode.

[0093] In a first embodiment, the second ring layer may include a vertically protruding flange, which may be configured to externally restrain the first ring layer.

[0094] In a first embodiment, the inner vertical surface of the first ring layer may be at a second radial distance from the center of the focus ring. The inner vertical surface of the second ring layer may be at a third radial distance from the center of the focus ring. The inner vertical surface of the second ring layer may be configured to underlie the first ring layer while the lower surface supports the first ring layer. The second radial distance may be shorter than the third radial distance.

[0095] In a first embodiment, the second ring layer may have a bottom surface and the recesses may be in the second ring layer from the bottom surface. The recesses may be configured so that the respective pins engage with the recesses.

[0096] In a first embodiment, the first ring layer may have an inner sidewall. The slots may be in the first ring layer from the inner sidewall to a depth of the first ring layer. The slots may be configured to allow each pin to engage with the slot. The slots may be further configured to allow each pin to move vertically within the slot relative to the first ring layer.

[0097] In the first embodiment, the second ring layer may have a slot therethrough. The slot may be further configured to allow each pin to move horizontally within the slot relative to the second ring layer. The first ring layer may have a recess from a lower surface within the first ring layer. The recess may be configured to engage with each pin. The recess may be further configured to allow each pin to move vertically within the recess relative to the first ring layer.

[0098] A second embodiment is a process apparatus for semiconductor processing. The process apparatus includes a chamber, a substrate support, and a focus ring rotation assembly. The chamber has an internal volume within the chamber. The substrate support is disposed within the internal volume of the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The substrate support includes a flange configured to support a focus ring that externally surrounds the support surface. The focus ring rotation assembly is disposed at least partially within the internal volume of the chamber. The focus ring rotation assembly is configured to horizontally rotate at least a portion of the focus ring about an axis perpendicular to the support surface. The focus ring rotation assembly includes a frame configured to horizontally rotate about an axis perpendicular to the support surface.

[0099] In a second embodiment, the substrate support may include stop pins on a vertical sidewall of the substrate support above the flange. The stop pins may extend horizontally from the vertical sidewall in an extended position. The stop pins may be retractable. The stop pins may be configured to engage respective slots in an inner sidewall of the focus ring. Additionally, the substrate support may include actuators configured to retract and extend each of the stop pins.

[0100] In a second embodiment, the substrate support may include stop pins extending vertically from the flange. The stop pins may be configured to engage respective recesses in the lower surface of the focus ring. Further, the stop pins may be fixed.

[0101] In a second embodiment, the focus ring rotation assembly may further include rotation pins that may be mechanically coupled to and protrude from the frame, that may extend through respective slots through the flange, and that may protrude vertically above the flange configured to engage respective recesses in the bottom surface of the focus ring.

[0102] In a second embodiment, the focus ring rotation assembly may further include a motor mechanically coupled to the frame and configured to rotate the frame horizontally.

[0103] The second embodiment may further include an electrical connector configured to be electrically connected to the focus ring.

[0104] The second embodiment may further include a power supply and a control circuit. The power supply may be configured to output a voltage at an output node of the power supply. The control circuit may have an input node electrically connected to the output node of the power supply and may have an output node configured to be electrically connected to the focus ring. The control circuit may be controllable to adjust the amplitude, phase, or a combination thereof of the voltage and output a corresponding adjusted voltage at the output node of the control circuit. Additionally, the process device may further include a controller. The controller may include one or more processors and non-transitory memory. The non-transitory memory may include stored instructions that, when executed by the one or more processors, may cause the one or more processors to control the control circuit to adjust the amplitude, phase, or a combination thereof.

[0105] A third embodiment is a method for semiconductor processing. The method includes adjusting the height of a focus ring. The focus ring is positioned in a chamber of a process apparatus to surround a semiconductor substrate from the outside. The focus ring includes a first ring layer and a second ring layer. Adjusting the height of the focus ring includes rotating the second ring layer relative to the first ring layer. The first ring layer has a lower surface. The second ring layer has an upper surface. The lower surface is disposed on and in contact with the upper surface. The lower and upper surfaces are periodic around a circumference. The lower and upper surfaces have the same periodic length at the same first radial distance from the center of the focus ring. At least one of the lower and upper surfaces includes a first protrusion radius line, a first recess radius line, and a second protrusion radius line. The first recess radius line is horizontally disposed between the first protrusion radius line and the second protrusion radius line. The periodic length at the first radial distance is the length from the first protrusion radius line to the second protrusion radius line. At least one of the lower surface and the upper surface from the first protrusion radius line to the first recess radius line is continuous. At least one of the lower surface and the upper surface from the first recess radius line to the second protrusion radius line is continuous. The method includes generating a plasma in a process volume of a chamber while a focus ring is positioned to surround the semiconductor substrate from the outside. The semiconductor substrate is exposed to the plasma.

[0106] In a third embodiment, at least one of the lower surface and the upper surface may be continuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

[0107] In a third embodiment, at least one of the lower surface and the upper surface may be discontinuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

[0108] In a third embodiment, the periodic length at the first radial distance from the first protrusion radial line to the second protrusion radial line may be symmetrical about the first recess radial line.

[0109] In a third embodiment, at least one of the lower surface and the upper surface may be a sinusoidal surface, and each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line may lie within the sinusoidal surface.

[0110] In a third embodiment, the other of the lower surface and the upper surface may include a second recess radius line, a third protrusion radius line, and a third recess radius line. The third protrusion radius line may be horizontally disposed between the second recess radius line and the third recess radius line. The periodic length at the first radial distance may be the length from the second recess radius line to the third recess radius line. The other of the lower surface and the upper surface may be continuous from the second recess radius line to the third protrusion radius line. The other of the lower surface and the upper surface may be continuous from the third protrusion radius line to the third recess radius line. The other of the lower surface and the upper surface may be continuous at each of the second recess radius line, the third protrusion radius line, and the third recess radius line. In this method, the other of the lower surface and the upper surface may be discontinuous at each of the second recess radius line, the third protrusion radius line, and the third recess radius line.

[0111] In a third embodiment, the lower and upper surfaces may each be sinusoidal surfaces. The upper surface may be complementary to the lower surface.

[0112] In a third embodiment, the first ring layer may be a non-conductive material.

[0113] In a third embodiment, the second ring layer may include a conductive electrode. Additionally, the method may further include applying a voltage to the conductive electrode while the plasma is in the process volume.

[0114] In a third embodiment, the second ring layer may include a vertically protruding flange configured to externally restrain the first ring layer.

[0115] In a third embodiment, the inner vertical surface of the first ring layer can be at a second radial distance from the center of the focus ring, and the inner vertical surface of the second ring layer can be at a third radial distance from the center of the focus ring. The inner vertical surface of the second ring layer can be configured to underlie the first ring layer while the lower surface supports the first ring layer. The second radial distance can be less than the third radial distance.

[0116] In a third embodiment, a semiconductor substrate may be disposed on a substrate support in a chamber of a process apparatus. The substrate support may include a flange. A focus ring may be disposed on the flange. A focus ring rotation assembly may rotate the second ring layer relative to the first ring layer. Further, the focus ring rotation assembly may include a frame and a rotation pin mechanically coupled to the frame and protruding from the frame. The rotation pins may extend through respective slots through the flange and engage respective recesses in a bottom surface of the focus ring. Rotating the second ring layer relative to the first ring layer may include rotating the frame. Further, the focus ring rotation assembly may include a motor, and the motor may rotate the frame.

[0117] The substrate support may include stop pins on a vertical sidewall of the substrate support above the flange. Rotating the second ring layer relative to the first ring layer may include engaging the stop pins in respective slots in an inner sidewall of the first ring layer. Additionally, in this method, the stop pins may be retractable.

[0118] The substrate support may include stop pins extending vertically from the flange. Rotating the second ring layer relative to the first ring layer may include extending the stop pins through respective slots through the second ring layer and engaging the stop pins within respective recesses in the lower surface of the first ring layer. Additionally, the stop pins may be fixed.

[0119] A fourth embodiment is a method for semiconductor processing. The method includes using a process apparatus to perform a plasma semiconductor process having first process conditions on a first plurality of substrates. The process apparatus includes a substrate support configured to support the substrate during the plasma semiconductor process. A focus ring is positioned to surround the substrate from the outside during the plasma semiconductor process. The focus ring has a first ring layer and a second ring layer supporting and in contact with the first ring layer. The height of the focus ring is adjustable by rotating the second ring layer relative to the first ring layer. The first process condition corresponds to a first amount of rotation of the second ring layer relative to the first ring layer to achieve a first height of the focus ring during the plasma semiconductor process. The method includes measuring a first characteristic of each of the first plurality of substrates near a center of each of the first plurality of substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates near an edge of each of the first plurality of substrates. The second characteristic is formed by a plasma semiconductor process. The method includes determining, by a processor-based system, second process conditions to be applied while performing the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to a second amount of rotation of the second ring layer relative to the first ring layer to achieve a second height of the focus ring during the plasma semiconductor process. The method includes performing the plasma semiconductor process having the second process conditions on the second plurality of substrates using the process apparatus.

[0120] In a fourth embodiment, the first characteristic may include a first contour angle of a recess etched into each substrate of the first plurality of substrates near a center of each of the respective substrates, and the second characteristic may include a second contour angle of a recess etched into each substrate of the first plurality of substrates near an edge of each of the respective substrates.

[0121] In a fourth embodiment, the first characteristic may include a first depth of a recess to be etched into each substrate of the first plurality of substrates near a center of each of the respective substrates, and the second characteristic may include a second depth of a recess to be etched into each substrate of the first plurality of substrates near an edge of each of the respective substrates.

[0122] In a fourth embodiment, the first characteristic may include a first thickness of a film deposited on each substrate of the first plurality of substrates near a center of each of the respective substrates, and the second characteristic may include a second thickness of a film deposited on each substrate of the first plurality of substrates near an edge of each of the respective substrates.

[0123] In a fourth embodiment, performing a plasma semiconductor process having first process conditions on the first plurality of substrates may further include a third process condition. The third process condition may correspond to a first amplitude and a first phase of a signal applied to a focus ring electrode during the plasma semiconductor process. Determining second process conditions may further include determining fourth process conditions to be applied while performing the plasma semiconductor process on the second plurality of substrates based on the first characteristic and the second characteristic. The fourth process condition may correspond to a second amplitude and a second phase of a signal applied to the focus ring electrode during the plasma semiconductor process. Performing a plasma semiconductor process having second process conditions on the second plurality of substrates may further include the fourth process condition.

[0124] Although various embodiments have been described in detail, it should be understood that various changes, substitutions, and alterations can be made thereto without departing from the scope defined by the appended claims.

Claims

1. 1. A component for semiconductor processing, the component including a focus ring configured to outwardly surround a semiconductor substrate during plasma semiconductor processing, the focus ring comprising: a first ring layer having a lower surface; a second ring layer having an upper surface configured to support the first ring layer by the lower surface contacting the upper surface; the lower surface and the upper surface each have a surface shape that is periodic along the circumference; the lower surface and the upper surface have the same periodic length at the same first radial distance from the center of the focus ring; at least one of the lower surface and the upper surface includes a first protrusion radius line, a first recess radius line, and a second protrusion radius line, the first recess radius line being horizontally disposed between the first protrusion radius line and the second protrusion radius line; the periodic length at the first radial distance is a length from the first protrusion radial line to the second protrusion radial line, the at least one of the lower surface and the upper surface is continuous from the first protrusion radial line to the first recess radial line; the at least one of the lower surface and the upper surface from the first recessed radial line to the second protruding radial line is continuous; the second ring layer is horizontally rotatable relative to the first ring layer while the upper surface supports the first ring layer; Component.

2. 2. The component of claim 1, wherein the at least one of the lower surface and the upper surface is continuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

3. 2. The component of claim 1, wherein the at least one of the lower surface and the upper surface is discontinuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

4. 2. The component of claim 1, wherein the periodic length at the first radial distance from the first protrusion radius line to the second protrusion radius line is symmetric about the first recess radius line.

5. 2. The component of claim 1, wherein the at least one of the lower surface and the upper surface is a sinusoidal surface, and wherein each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line lies on the sinusoidal wave.

6. the other of the lower surface and the upper surface includes a second recess radius line, a third protrusion radius line, and a third recess radius line, the third protrusion radius line being horizontally disposed between the second recess radius line and the third recess radius line; the periodic length at the first radial distance is a length from the second recess radial line to the third recess radial line, the other of the lower surface and the upper surface from the second recess radial line to the third protrusion radial line is continuous; the other of the lower surface and the upper surface from the third protrusion radial line to the third recess radial line is continuous; 10. The component of claim 1.

7. 7. The component of claim 6, wherein said other of said lower surface and said upper surface is continuous at each of said second recess radius line, said third protrusion radius line, and said third recess radius line.

8. The component of claim 6 , wherein said other of said lower surface and said upper surface is discontinuous at each of said second recess radius line, said third protrusion radius line, and said third recess radius line.

9. The component of claim 1 , wherein each of the lower surface and the upper surface is a sinusoidal surface, the upper surface being complementary to the lower surface.

10. The component of claim 1 , wherein the first ring layer is a non-conductive material.

11. The component of claim 1 , wherein the second ring layer comprises a conductive electrode.

12. The component of claim 1 , wherein the second ring layer includes a vertically protruding flange, the flange configured to externally restrain the first ring layer.

13. an inner vertical surface of the first ring layer at a second radial distance from the center of the focus ring; an inner vertical surface of the second ring layer at a third radial distance from the center of the focus ring, the inner vertical surface of the second ring layer configured to underlie the first ring layer while the lower surface supports the first ring layer; the second radial distance is less than the third radial distance; 10. The component of claim 1.

14. 2. The component of claim 1, wherein the second ring layer has a bottom surface and recesses extending from the bottom surface into the second ring layer, the recesses configured to engage respective pins on a frame, and wherein rotation of the frame rotates the second ring layer about an axis.

15. 2. The component of claim 1, wherein the first ring layer has an inner sidewall and a slot in the first ring layer from the inner sidewall to a depth in the first ring layer, the slots configured to engage respective pins provided on a substrate support that supports the semiconductor substrate, the slots further configured to allow the respective pins to move vertically within the slot relative to the first ring layer.

16. the second ring layer has slots therethrough configured to allow respective pins on a flange supporting the second ring layer to move horizontally within the slots relative to the second ring layer; 2. The component of claim 1, wherein the first ring layer has a recess from the lower surface into the first ring layer, the recess configured to engage the respective pin, the recess further configured to allow the respective pin to move vertically within the recess relative to the first ring layer.

17. A process apparatus for semiconductor processing, the process apparatus comprising: a chamber having an interior volume within the chamber; a substrate support disposed within the chamber, the substrate support having a support surface configured to support a semiconductor substrate, the substrate support including a flange configured to support a focus ring externally surrounding the support surface; a focus ring rotation assembly disposed at least partially within the chamber, the focus ring rotation assembly configured to horizontally rotate at least a portion of the focus ring about an axis perpendicular to the support surface, the focus ring rotation assembly including a frame disposed below the flange, the focus ring rotation assembly configured to horizontally rotate about the axis perpendicular to the support surface; 1. A process device comprising:

18. 20. The process apparatus of claim 17, wherein the substrate support includes stop pins on a vertical sidewall of the substrate support above the flange, the stop pins extending horizontally from the vertical sidewall in an extended position, the stop pins being retractable, and the stop pins configured to engage respective slots in an inner sidewall of the focus ring.

19. 20. The process apparatus of claim 18, wherein the substrate support includes actuators respectively configured to retract and push out respective ones of the stop pins.

20. 20. The process apparatus of claim 17, wherein the substrate support includes stop pins extending perpendicularly from the flange, the stop pins configured to engage respective recesses in a lower surface of the focus ring.

21. 21. The process device of claim 20, wherein the stop pin is fixed.

22. 18. The process apparatus of claim 17, wherein the focus ring rotation assembly further includes rotation pins mechanically coupled to and protruding from the frame, the rotation pins extending through respective slots through the flange and protruding vertically above the flange configured to engage respective recesses in a bottom surface of the focus ring.

23. 20. The process apparatus of claim 17, wherein the focus ring rotation assembly further comprises a motor mechanically coupled to the frame and configured to rotate the frame horizontally.

24. 20. The process apparatus of claim 17, further comprising an electrical connector configured to be electrically connected to the focus ring.

25. a power supply configured to output a voltage at an output node of the power supply; a control circuit having an input node electrically connected to the output node of the power supply and having an output node configured to be electrically connected to the focus ring, the control circuit being controllable to adjust an amplitude, a phase, or a combination thereof, of the voltage to output a corresponding adjusted voltage at the output node of the control circuit; 20. The process device of claim 17, further comprising:

26. a controller, one or more processors; a non-transitory memory containing stored instructions that, when executed by the one or more processors, cause the one or more processors to control the control circuitry to adjust the amplitude, the phase, or a combination thereof; further comprising a controller; 26. The process device of claim 25.

27. 1. A method for semiconductor processing, the method comprising: adjusting a height of a focus ring, the focus ring being disposed in a chamber of a process apparatus so as to surround a semiconductor substrate from the outside, the focus ring including a first ring layer and a second ring layer; generating a plasma in the chamber while the focus ring is disposed to surround the semiconductor substrate from outside, the semiconductor substrate being exposed to the plasma; adjusting the height of the focus ring includes rotating the second ring layer relative to the first ring layer; the first ring layer has a lower surface; the second ring layer has an upper surface, the lower surface is disposed on and in contact with the upper surface; the lower surface and the upper surface each have a surface shape that is periodic along the circumference; the lower surface and the upper surface have the same periodic length at the same first radial distance from the center of the focus ring; at least one of the lower surface and the upper surface includes a first protrusion radius line, a first recess radius line, and a second protrusion radius line, the first recess radius line being horizontally disposed between the first protrusion radius line and the second protrusion radius line; the periodic length at the first radial distance is a length from the first protrusion radial line to the second protrusion radial line, the at least one of the lower surface and the upper surface is continuous from the first protrusion radial line to the first recess radial line; the at least one of the lower surface and the upper surface from the first recess radial line to the second protrusion radial line is continuous; method.

28. 28. The method of claim 27, wherein the at least one of the lower surface and the upper surface is continuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

29. 28. The method of claim 27, wherein the at least one of the lower surface and the upper surface is discontinuous at each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line.

30. 28. The method of claim 27, wherein the periodic length at the first radial distance from the first protrusion radius line to the second protrusion radius line is symmetric about the first recess radius line.

31. 28. The method of claim 27, wherein the at least one of the lower surface and the upper surface is a sinusoidal surface, and wherein each of the first protrusion radius line, the first recess radius line, and the second protrusion radius line lies within the sinusoidal wave.

32. the other of the lower surface and the upper surface includes a second recess radius line, a third protrusion radius line, and a third recess radius line, the third protrusion radius line being horizontally disposed between the second recess radius line and the third recess radius line; the periodic length at the first radial distance is a length from the second recess radial line to the third recess radial line, the other of the lower surface and the upper surface from the second recess radial line to the third protrusion radial line is continuous; the other of the lower surface and the upper surface from the third protrusion radial line to the third recess radial line is continuous; 28. The method of claim 27.

33. 33. The method of claim 32, wherein the other of the lower surface and the upper surface is continuous at each of the second recess radius line, the third protrusion radius line, and the third recess radius line.

34. 33. The method of claim 32, wherein the other of the lower surface and the upper surface is discontinuous at each of the second recess radius line, the third protrusion radius line, and the third recess radius line.

35. 28. The method of claim 27, wherein each of the lower surface and the upper surface is a sinusoidal surface, the upper surface being complementary to the lower surface.

36. 28. The method of claim 27, wherein the first ring layer is a non-conductive material.

37. 28. The method of claim 27, wherein the second ring layer comprises a conductive electrode.

38. 38. The method of claim 37, further comprising applying a voltage to the conductive electrode while the plasma is in the chamber.

39. 28. The method of claim 27, wherein the second ring layer includes a vertically protruding flange, the flange configured to externally confine the first ring layer.

40. an inner vertical surface of the first ring layer at a second radial distance from the center of the focus ring; an inner vertical surface of the second ring layer at a third radial distance from the center of the focus ring, the inner vertical surface of the second ring layer configured to underlie the first ring layer while the lower surface supports the first ring layer; the second radial distance is less than the third radial distance; 28. The method of claim 27.

41. the semiconductor substrate is positioned on a substrate support within the chamber of the process apparatus; the substrate support includes a flange, the focus ring being disposed on the flange; a focus ring rotation assembly for rotating the second ring layer relative to the first ring layer; 28. The method of claim 27.

42. the focus ring rotation assembly includes a frame and a rotation pin mechanically coupled to the frame and protruding from the frame; the rotation pins extend through respective slots through the flange and engage respective recesses in a bottom surface of the focus ring; rotating the second ring layer relative to the first ring layer includes rotating the frame.

42. The method of claim 41.

43. 43. The method of claim 42, wherein the focus ring rotation assembly includes a motor, the motor rotating the frame.

44. the substrate support includes a stop pin on a vertical sidewall of the substrate support above the flange; rotating the second ring layer relative to the first ring layer includes engaging the stop pins within respective slots in an inner sidewall of the first ring layer.

42. The method of claim 41.

45. 45. The method of claim 44, wherein the stop pin is retractable.

46. the substrate support includes a stop pin extending perpendicularly from the flange; Rotating the second ring layer relative to the first ring layer includes: extending the stop pins through respective slots through the second ring layer; and engaging the stop pins within respective recesses in the lower surface of the first ring layer.

42. The method of claim 41.

47. 47. The method of claim 46, wherein the stop pin is fixed.

48. 1. A method for semiconductor processing, the method comprising: performing a plasma semiconductor process having first process conditions on a first plurality of substrates using a process apparatus, the process apparatus including: a substrate support configured to support the substrates during the plasma semiconductor process; and a focus ring positioned to outer surround the substrates during the plasma semiconductor process, the focus ring having a first ring layer and a second ring layer supporting and in contact with the first ring layer, the focus ring having a height that is adjustable by rotating the second ring layer relative to the first ring layer, the first process condition corresponding to a first amount of rotation of the second ring layer relative to the first ring layer to achieve a first height of the focus ring during the plasma semiconductor process; measuring a first property of each of the first plurality of substrates near a center of each of the first plurality of substrates, the first property being formed by the plasma semiconductor process; measuring a second property of each of the first plurality of substrates near an edge of each of the first plurality of substrates, the second property being formed by the plasma semiconductor process; determining second process conditions to be applied during performing the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic, the second process conditions corresponding to a second amount of rotation of the second ring layer relative to the first ring layer to achieve a second height of the focus ring during the plasma semiconductor process; performing the plasma semiconductor process having the second process conditions on the second plurality of substrates using the process apparatus; method.

49. the first characteristic includes, for each substrate of the first plurality of substrates, a first contour angle of a recess etched into the respective substrate near a center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second profile angle of a recess etched into the respective substrate near an edge of the respective substrate; 49. The method of claim 48.

50. the first characteristic includes, for each substrate of the first plurality of substrates, a first depth of a recess etched into the respective substrate near a center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second depth of a recess etched into the respective substrate near the respective edge of the respective substrate; 49. The method of claim 48.

51. the first characteristic includes, for each substrate of the first plurality of substrates, a first thickness of a film deposited on the respective substrate near a center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second thickness of the film near an edge of each of the respective substrates; 49. The method of claim 48.

52. performing the plasma semiconductor process having first process conditions on the first plurality of substrates further comprises a third process condition; the third process condition corresponds to a first amplitude and a first phase of a signal applied to an electrode of the focus ring during the plasma semiconductor process; determining the second process conditions further includes determining fourth process conditions to be applied during performing the plasma semiconductor process on the second plurality of substrates based on the first characteristic and the second characteristic; the fourth process condition corresponds to a second amplitude and a second phase of a signal applied to the electrode of the focus ring during the plasma semiconductor process; performing the plasma semiconductor process having the second process conditions on the second plurality of substrates further comprises the fourth process conditions; 49. The method of claim 48.

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