Optical integrated chip structure and manufacturing method thereof

Abstract

The present invention provides an optical integrated chip structure and a method for manufacturing the same, which effectively achieves P / N electrical isolation between each separate device in an integrated chip, thereby enabling P / N bilateral RF drive for each device. The optical integrated chip structure includes a substrate (10), a buffer layer (20) formed on the substrate, a bottom conductive layer formed on the buffer layer, a core layer formed on the bottom conductive layer, and a top conductive layer formed on the core layer. The top conductive layer is formed on the core layer and includes a plurality of top conductive regions, each of which corresponds one-to-one to a core region, and a top isolation region (53) is provided between two adjacent top conductive regions. The top isolation of the first sub-device (100) and the second sub-device (200) is achieved by deeply etching a specific region to remove the top conductive region, or by methods such as ion implantation and diffusion.

Description

[Technical Field]

[0001] The present invention belongs to the field of semiconductor laser technology, and more particularly to an optical integrated chip structure and its manufacturing method. [Background technology]

[0002] An optical integrated chip is a device structure in which multiple independent optical subdevices are integrated on the same substrate. Typically, it integrates one or more of lasers, modulators, optical amplifiers, and detectors on a semiconductor III-V material or Si substrate. Most conventional optical integrated chips are based on N-type substrate materials, and all devices share a common N pole. Therefore, although these optical integrated chips can provide P isolation for individual optical subdevices, they cannot achieve N isolation, resulting in only single-ended RF drive for each device. If it were possible to simultaneously electrically isolate the P and N electrodes of each device within an optical integrated chip, crosstalk between devices could be significantly reduced, enabling P / N double-sided RF drive in optical chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Chinese Patent Publication No. CN111580215A Summary of the Invention [Problem to be solved by the invention]

[0004] A common electrical isolation method for optical integrated chips is the deep-etched structure. This method significantly improves the P-isolation resistance between devices by completely or partially etching the P-type material between two devices, thereby blocking crosstalk between the P-electrodes of the devices. However, while N-isolation can also be achieved by etching the N-type material on the side of the substrate, because each optical device on an integrated chip generally dissipates heat through the substrate, etching the N-type material on the substrate side significantly increases the thermal resistance and significantly increases the junction temperature of the optical device. This limits the operating current of the optical device and significantly increases the device reliability risk.

[0005] Electrical isolation between chips can also be achieved by ion implantation and diffusion. To avoid the influence of implanted particles and diffused elements on the extended growth, these steps must be performed after the extended growth is complete. In this case, the implantation depth is very deep, requiring high implantation energy. This not only results in expensive equipment, but also makes it difficult to control the effects of high-energy particles on the optical properties of the extended material. Furthermore, diffusion methods, especially those involving material type inversion, require relatively deep diffusion depths and high diffusion concentrations to achieve electrical isolation. This prolongs the diffusion time, and the large amount of diffused elements increases the loss of the optical waveguide. These diffused elements can also cause instability in subsequent steps, potentially adversely affecting device reliability. [Means for solving the problem]

[0006] The present invention discloses an optical integrated chip structure and its manufacturing method, which effectively realizes P / N electrical isolation between each separate device in the integrated chip, thereby enabling P / N bilateral RF drive for each device.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions. The present invention discloses an optical integrated chip structure comprising: a substrate; a buffer layer formed on the substrate; a bottom conductive layer formed on the buffer layer; a core layer formed on the bottom conductive layer; and a top conductive layer formed on the core layer; the bottom conductive layer includes a plurality of bottom conductive regions, and a bottom isolation region is provided between two adjacent bottom conductive regions, the bottom isolation region being used to isolate the two adjacent bottom conductive regions, and the type of impurity doped in the bottom isolation region is opposite to the type of impurity doped in the adjacent bottom conductive region; the core layer includes a plurality of core regions, each of which corresponds one-to-one with the bottom conductive region, and an optical transmission region is provided between the two adjacent core regions; the top conductive layer includes a plurality of top conductive regions, each of which corresponds one-to-one with the core region, and a top isolation region is provided between the two adjacent top conductive regions.

[0008] Furthermore, a light transmission region (light transmitting region) is provided between two adjacent core regions.

[0009] Furthermore, the type of impurity doped into the bottom conductive region is opposite (reciprocal) to the type of impurity doped into the buffer layer, and the substrate is P-type, N-type, or semi-insulating.

[0010] Furthermore, the top isolation region is formed by an etching process or a doping process, the width of the top isolation region is greater than the width of the optical transmission region, and the distance from the left end of the top isolation region to the left end of the optical transmission region and the distance from the right end of the top isolation region to the right end of the optical transmission region are both 1 μm or more.

[0011] Furthermore, the bottom isolation region is a P-type doped or N-type doped semiconductor layer.

[0012] Furthermore, the thickness of the bottom conductive region is 500 nm or more, the difference in thickness between the bottom isolation region and the bottom conductive region is less than 300 nm, and the distance from the left end of the bottom isolation region to the left end of the optical transmission region and the distance from the right end of the bottom isolation region to the right end of the optical transmission region are both 10 μm or less.

[0013] Furthermore, the material of the light-transmitting region is a multi-component semiconductor compound.

[0014] Furthermore, the present invention discloses a method for manufacturing the optical integrated chip structure, including the steps of: forming a buffer layer on a substrate; forming a bottom isolation region on the buffer layer and forming bottom conductive regions on both sides of the bottom isolation region; forming a corresponding core region on the bottom conductive region and forming an optical transmission region between two adjacent core regions; and forming a corresponding top conductive region on the core region and forming a top isolation region between two adjacent top conductive regions.

[0015] Furthermore, the step of forming a bottom isolation region on the buffer layer and forming bottom conductive regions on both sides of the bottom isolation region specifically includes the steps of forming a bottom isolation layer on the buffer layer and subjecting the bottom isolation layer to an etching process to obtain the bottom isolation region; and epitaxially growing the bottom conductive regions on the buffer layer in regions located on both sides of the bottom isolation region. [Effects of the Invention]

[0016] The beneficial effects of the present invention are as follows: the optical integrated chip structure disclosed in the present invention provides a bottom isolation region between two adjacent bottom conductive regions, and the type of impurity doped in the bottom isolation region is opposite to that of the adjacent bottom conductive region, forming an inversion-blocking junction, thereby achieving bottom electrical isolation; and a top isolation region between two adjacent top conductive regions, providing electrical isolation (electrical isolation). This structure achieves P / N electrical isolation between each separate device in the integrated chip, allowing the device to be RF-driven on both sides of the P / N, without crosstalk between other devices. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a schematic cross-sectional view of an optical integrated chip structure according to an embodiment of the present invention; [Figure 2] 2 is a schematic diagram of the structure of an extended buffer layer and a bottom isolation layer formed on a substrate according to an embodiment of the present invention; [Figure 3] FIG. 10 is a schematic diagram of the structure after depositing a mask on the bottom isolation layer and completing photolithography and etching according to an embodiment of the present invention. [Figure 4] FIG. 10 is a schematic diagram of the structure after the bottom conductive region of the extended sub-device according to an embodiment of the present invention. [Figure 5] FIG. 2 is a schematic diagram of the structure after the first core layer of the extended first sub-device according to an embodiment of the present invention. [Figure 6] FIG. 10 is a schematic diagram of a structure after the second core region of the extended second sub-device according to an embodiment of the present invention. [Figure 7] 1 is a schematic diagram of the structure of the outer optical transmission region after selective etching is performed at the core region connection portion of the first sub-device and the second sub-device according to an embodiment of the present invention. FIG. [Figure 8] FIG. 10 is a schematic diagram of a structure after extending the top conductive regions of the first and second sub-devices according to an embodiment of the present invention. [Figure 9]FIG. 1 is a schematic diagram of a structure after forming a top isolation region according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described in detail below based on examples, but the present invention is not limited to these examples.

[0019] An embodiment of the present invention discloses an optical integrated chip structure. As shown in Figure 1, the structure includes a substrate 10, a buffer layer 20, a bottom conductive layer, and a core layer.

[0020] The substrate 10 can be configured as a P-type, N-type, or semi-insulating semiconductor, where the P-type dopant can be Zn, the N-type dopant can be S or Si, and the semi-insulating dopant can be Fe. The material of the substrate 10 can be InP or GaAs, but is not limited to these in embodiments of the present invention.

[0021] A buffer layer 20 is formed on the substrate 10. This buffer layer 20 may be configured as a P-type, N-type, undoped, or semi-insulating semiconductor to provide isolation between devices formed thereon and the substrate 10. The P-type dopant may be Zn, the N-type dopant may be S or Si, and the semi-insulating dopant may be Fe.

[0022] The material of the buffer layer 20 may be InP or GaAs, but is not limited to these in the embodiments of the present invention.

[0023] The bottom conductive layer formed on the buffer layer 20 includes a plurality of bottom conductive regions, and a bottom isolation region 33 is provided between two adjacent bottom conductive regions, whereby the bottom isolation region 33 is used to isolate the adjacent bottom conductive regions, and the bottom isolation region 33 is of an impurity type opposite to that doped in the adjacent bottom conductive region.

[0024] The bottom isolation region 33 is a P-type or N-type doped semiconductor layer, and the type of impurity doped in the bottom conductive region is opposite to the type of impurity doped in the buffer layer 20. The thickness of the bottom conductive region is typically 500 nm or more, and the thickness difference between the bottom isolation region 33 and the bottom conductive region is less than 300 nm.

[0025] The embodiment of the present invention will be described by taking the example of forming two sub-devices on a buffer layer 20. The two sub-devices are respectively designated as a first sub-device 100 and a second sub-device 200. The first sub-device 100 and the second sub-device 200 may be a laser, a modulator, or an optical amplifier.

[0026] Taking two sub-devices as an example, two bottom conductive regions are formed on the buffer layer 20, designated as a first bottom conductive region 31 and a second bottom conductive region 32. The first bottom conductive region 31 and the second bottom conductive region 32 can be P-type or N-type doped semiconductors, and the bottom isolation region 33 between the first bottom conductive region 31 and the second bottom conductive region 32 can be N-type or P-type doped semiconductor. The bottom isolation region 33 has a different polarity from the bottom conductive regions, forming an inversion blocking junction to achieve bottom electrical isolation.

[0027] In actual manufacturing steps, SiOx or SiNx is deposited on the surface of the bottom isolation layer 34 and used as a mask to selectively etch other areas to form the bottom isolation region 33, and then the first bottom conductive region 31 and the second bottom conductive region 32 are grown on both sides of the bottom isolation region 33. The etching of the bottom isolation layer 34 can be performed by dry etching or wet etching.

[0028] The core layer formed on the bottom conductive layer includes a plurality of core regions, each of which corresponds one-to-one with a bottom conductive region.

[0029] Taking two sub-devices as an example, two core regions, designated as the first core region 41 and the second core region 42, are formed on the bottom conductive layer. These core regions may be directly connected, or an optical transmission region 43 made of another material may be formed between them. The relative positions of the optical transmission region 43 and the bottom isolation region 33 are not fixed. The left end face of the optical transmission region 43 may be located on the left, center, or right side of the bottom isolation region 33. Preferably, the distance from the left edge of the bottom isolation region 33 to the left edge of the optical transmission region 43 or the distance from the right edge of the bottom isolation region 33 to the right edge of the optical transmission region 43 is 10 μm or less.

[0030] The material of the light-transmitting region 43 may be a multi-component semiconductor compound. The first core region 41 and the second core region 42 may use the same or different outer materials.

[0031] The first core region 41 and the second core region 42 include structures formed from bottom to top, such as a transition layer, a lower limiting layer, an active layer, and an upper limiting layer. The material of the active layer may be a multiple quantum well of InGaAsP or InGaAlAs.

[0032] By extending the optical transmission region 43 made of another material between the first core region 41 and the second core region 42, it is possible to block current crosstalk between the weakly doped confinement layers below the core regions, further improving the isolation effect.

[0033] After the core region of the first sub-device 100 is epitaxially grown, a portion of the core region is selectively removed by a dry etching or wet etching process (wet etching), and the core region of the second sub-device 200 is then epitaxially grown. After that, the connection portion between the core regions of the first sub-device 100 and the second sub-device 200 is selectively etched, and the optical transmission region 43 is epitaxially grown.

[0034] The top conductive layer is formed on the core layer and includes a plurality of top conductive regions, each of which corresponds to a core region one-to-one, and a top isolation region 53 is provided between two adjacent top conductive regions.

[0035] The top isolation region 53 is formed by an etching process or a doping process. Specifically, the top isolation of the first sub-device 100 and the second sub-device 200 is achieved by deeply etching certain areas to remove the top conductive region, or by methods such as ion implantation and diffusion.

[0036] More preferably, the width of the top isolation region 53 is greater than the width of the optical transmission region 43, and the distance from the left end of the top isolation region 53 to the left end of the optical transmission region 43 and the distance from the right end of the top isolation region 53 to the right end of the optical transmission region 43 are both 1 μm or more.

[0037] Taking two sub-devices as an example, two top conductive regions are formed on the core layer, which are respectively called a first top conductive region 51 and a second top conductive region 52. The materials of the first top conductive region 51 and the second top conductive region 52 are InGaAs or InAlAs, and the materials of the first top conductive region 51 and the second top conductive region 52 can be the same or different.

[0038] In practical applications, the electrodes connected to the bottom conductive regions of the first sub-device 100 and the second sub-device 200 metallize their respective bottom conductive regions and extend to the top surface, forming a coplanar electrode structure with the top electrode.

[0039] The optical integrated chip structure disclosed in the present invention may form a pnp or npn anti-junction isolation on the bottom conductive layer. Based on the extended isolation method, the present invention can significantly reduce the concentration of doping elements and minimize the impact of impurity atoms on device performance and reliability.

[0040] Another embodiment of the present invention discloses a method for manufacturing any of the above-mentioned optical integrated chip structures, which includes the following steps S1 to S4.

[0041] Step S1 forms a buffer layer 20 on a substrate 10.

[0042] Step S2 forms a bottom isolation region 33 on the buffer layer 20 and forms bottom conductive regions on both sides of the bottom isolation region 33.

[0043] Step S3 forms a corresponding core region on the bottom conductive region.

[0044] Step S4 forms corresponding top conductive regions on the core regions, and forms top isolation regions 53 between two adjacent top conductive regions.

[0045] Further, the method includes forming a corresponding core region on the bottom conductive region, and then forming a light-transmitting region 43 between two adjacent core regions.

[0046] In an embodiment of the present invention, the method for forming the bottom isolation region 33 on the buffer layer 20 and the bottom conductive regions on both sides of the bottom isolation region 33 specifically includes the steps of first forming a bottom isolation layer 34 on the buffer layer 20 and etching the bottom isolation layer 34 to obtain the bottom isolation region 33, and then performing extensional growth on the buffer layer 20 in regions located on both sides of the bottom isolation region 33 to form the bottom conductive regions.

[0047] Another embodiment of the present invention provides a specific method for manufacturing an optical integrated chip structure, which includes the following steps (1) to (8):

[0048] Step (1) comprises overgrowing a buffer layer 20 and a bottom isolation layer 34 on a substrate 10 .

[0049] At this stage, as shown in FIG. 2, a semi-insulating semiconductor may be selected as the substrate 10, or may be replaced by an N-type doped or P-type doped semiconductor.

[0050] The buffer layer 20 is formed of P-type InP (e.g., Zn-doped, doping concentration >1E15 cm-3) that is the opposite type to the bottom conductive layer, N-type InP (e.g., S-doped and Si-doped, doping concentration >1E15 cm-3), or undoped semi-insulating InP (e.g., Fe-doped, doping concentration >1E15 cm-3), and provides isolation between the two sub-devices and the substrate 10.

[0051] The bottom isolation layer 34 may be a P-type doped or N-type doped semiconductor (doping concentration >1E15 cm-3).

[0052] MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Flux Epitaxy) may be used as the extension method.

[0053] Step (2) is to deposit a mask on the bottom isolation layer 34 and perform photolithography and etching.

[0054] As shown in Figure 3, the mask material used in this step can be SiOx or SiNx, which has a lattice constant mismatch with the III-V binary or multi-compound semiconductor, so that the corresponding material will not grow in the subsequent extension process, thereby realizing selective area growth.

[0055] In this step, first, photolithography is performed using a first mask 61 (SiOx or SiNx), and then a graphical photoresist is used as a second mask to selectively etch the first mask 61 using ICP (inductively coupled plasma etching) or RIE (reactive ion etching). After this step is completed, the second mask is removed, and only the bottom isolation region 33 in a specific region and the first mask 61 remain on the buffer layer 20.

[0056] Step (3) extends and grows the first bottom conductive region 31 of the first sub-device 100 and the second bottom conductive region 32 of the second sub-device 200 .

[0057] 4, at this stage, the extended bottom conductive region is an N-type or P-type semiconductor (e.g., N-InP or P-InP with a doping concentration of 1E18 cm-3 or more) and is grown to a certain thickness on the buffer layer 20 not covered by the first mask 61. After the extended growth, the remaining first mask 61 may be removed by a dry or wet etching process to form lateral npn or pnp inverted junction isolation.

[0058] A typical thickness of the bottom conductive region is greater than 500 nm, and the thickness of the bottom isolation region 33 may be equal to or different from the bottom conductive region.

[0059] Step (4) involves extending and growing the first core layer 44 of the first sub-device 100 .

[0060] 5, the first core layer 44 includes a transition layer, a lower limiting layer, an active layer, an upper limiting layer, etc. The gain medium of the active layer is formed of a multi-component compound semiconductor such as InGaAsP or InGaAlAs, and has a stressed multiple quantum well (MQW) structure. The thickness of the MQW structure is 10 nm or more.

[0061] In step (5), a portion of the first core layer 44 of the first sub-device 100 is selectively etched, and then the second core region 42 of the second sub-device 200 is grown by extension.

[0062] As shown in FIG. 6, the second core region 42 of the second subdevice 200 is similar to the first core region 41 of the first subdevice 100, and its material composition and thickness may be the same as or different from the first core region 41 of the first subdevice 100.

[0063] 5 is first subjected to a photolithography process to protect the first core layer 44 (first core region 41) of the part of the first sub-device 100 that needs to be retained, and then a dry etching or wet etching process is performed to remove the region of the first core layer 44 that corresponds to the second core region 42 of the second sub-device 200. Furthermore, the second core region 42 of the second sub-device 200 is grown over the etched region.

[0064] In step (6), the connection portion between the first sub-device 100 and the second sub-device 200 is selectively etched, and then the optical transmission region 43 is grown over the connection portion.

[0065] As shown in Figure 7, the material of the optical transmission region 43 is a multi-component semiconductor compound, such as InGaAsP, which is used to improve the optical coupling efficiency between the two sub-devices. In this step, optical lithography is first performed to protect a portion of the first core region 41 of the first sub-device 100 and the second core region 42 of the second sub-device 200, and then a dry or wet etching process is used to remove the unprotected core regions at the connection between them. The optical transmission region 43 may then be overgrown in the etched region.

[0066] The thickness of the optical transmission region 43 may be greater than, less than, or equal to the thickness of the first core region 41 provided in the first sub-device 100 and the second core region 42 provided in the second sub-device 200.

[0067] Furthermore, the relative positions of the light-transmitting region 43 and the bottom isolation region 33 are not fixed, that is, the left end face of the light-transmitting region 43 may be located to the left, middle, or right of the bottom isolation region 33 .

[0068] Step (7) extends and grows the top conductive regions of the first sub-device 100 and the second sub-device 200 .

[0069] The top conductive regions of the first sub-device 100 and the second sub-device 200 may use the same or different extending materials, and may be formed by primary extending or secondary extending in a corresponding manner. However, if the top conductive regions of the first sub-device 100 and the second sub-device 200 use the same extending material, primary extending is used, i.e., the first conductive layer 54 is extended on the core layer, as shown in FIG. 8 .

[0070] Step (8) selectively etches or ions implants the top conductive region at the connection between the first sub-device 100 and the second sub-device 200 to form the top isolation region 53 .

[0071] As shown in FIG. 9, the top isolation region 53 provides top electrical isolation between the first sub-device 100 and the second sub-device 200 .

[0072] The relative positions of the light-transmitting region 43 and the top isolation region 53 are not fixed. The left end face of the light-transmitting region 43 may be located to the left, center, or right of the top isolation region 53.

[0073] Thus, the first bottom conductive region 31, the first core region 41, and the first top conductive region 51 constitute the first sub-device 100, and the second bottom conductive region 32, the second core region 42, and the second top conductive region 52 constitute the second sub-device 200. The first sub-device 100 and the second sub-device 200 achieve bottom electrical isolation via the bottom isolation region 33, and achieve top electrical isolation via the top isolation region 53.

[0074] The present invention provides a bottom isolation region 33 between two adjacent bottom conductive regions, and the type of impurity doped in the bottom isolation region 33 is opposite to that of the adjacent bottom conductive region, forming an inversion blocking junction and achieving bottom electrical isolation. Furthermore, a top isolation region 53 is provided between two adjacent top conductive regions to achieve electrical isolation, thereby achieving P / N electrical isolation between each isolated device within an integrated chip, and enabling P / N bilateral RF drive without crosstalk with other devices.

[0075] The above-described contents are merely some examples of the present application and do not limit the present application in any way. Even if the present application is disclosed with preferred embodiments, the present application is not limited thereby, and those skilled in the art can make slight changes or modifications using the above disclosure without departing from the technical scope of the present application, and these are all considered as equivalent embodiments and are included in the technical scope of the present application. [Explanation of symbols]

[0076] 100, first subdevice 200, second subdevice 10. Circuit board 20. Buffer layer 31, 1st bottom conductive area 32, second bottom conductive area 33, bottom isolation area 34, bottom separation layer 41. First Core Area 42. Second Core Area 43. Optical transmission area 44. First core layer 51, first top conductive region 52, second top conductive region 53. Top separation area 54. First conductive layer 61. First Mask

Claims

1. An optical integrated chip structure that integrates one or more of a laser, a modulator, an optical amplifier, a detector, etc., A substrate; a buffer layer formed on the substrate; a bottom conductive layer formed on the buffer layer; a core layer formed on the bottom conductive layer; a top conductive layer formed on the core layer, the bottom conductive layer includes a plurality of bottom conductive regions, and a bottom isolation region is provided between two adjacent bottom conductive regions, the bottom isolation region is used to isolate the two adjacent bottom conductive regions, and the type of impurity doped in the bottom isolation region is opposite to the type of impurity doped in the adjacent bottom conductive region; the core layer includes a plurality of core regions, each of which corresponds to one of the bottom conductive regions, and an optical transmission region is provided between two adjacent core regions; the top conductive layer includes a plurality of top conductive regions, each of which corresponds to one of the core regions, and a top isolation region is provided between two adjacent top conductive regions; a distance from a left end of the bottom isolation region to a left end of the optical transmission region and a distance from a right end of the bottom isolation region to a right end of the optical transmission region are both 10 μm or less; 1. An optical integrated chip structure comprising: a bottom isolation region; a PN junction region doped with an impurity type opposite to that of the bottom conductive region; and the PN junction forming an inversion blocking junction under reverse bias to provide electrical isolation between adjacent bottom conductive regions.

2. the bottom conductive region is doped with an impurity of a type opposite to the type of impurity doped in the buffer layer; 2. The optical integrated chip structure according to claim 1, wherein the substrate is P-type, N-type or semi-insulating.

3. the top isolation region is formed by an etching process or a doping process; the width of the top isolation region is greater than the width of the light-transmitting region; 2. The optical integrated chip structure according to claim 1, wherein the distance from the left end of the top isolation region to the left end of the optical transmission region and the distance from the right end of the top isolation region to the right end of the optical transmission region are both 1 μm or more.

4. 2. The optical integrated chip structure of claim 1, wherein the bottom isolation region is a P-type doped or N-type doped semiconductor layer.

5. the bottom conductive region has a thickness of 500 nm or greater; and 2. The optical integrated chip structure according to claim 1, wherein the thickness difference between the bottom isolation region and the bottom conductive region is less than 300 nm.

6. 2. The optical integrated chip structure according to claim 1, wherein the material of the optical transmission region is a multi-component semiconductor compound.

7. forming a buffer layer on a substrate; forming a bottom isolation region on the buffer layer and bottom conductive regions on either side of the bottom isolation region; forming corresponding core regions on the bottom conductive regions and forming an optical transmission region between two adjacent core regions; forming a corresponding top conductive region on the core region and a top isolation region between two adjacent top conductive regions; 7. A method for manufacturing an optical integrated chip structure according to claim 1, comprising:

8. The step of forming the bottom isolation region on the buffer layer and forming the bottom conductive region on both sides of the bottom isolation region specifically includes: forming a bottom isolation layer on the buffer layer, and subjecting the bottom isolation layer to an etching process to obtain the bottom isolation region; 8. The method of claim 7, further comprising epitaxially growing the bottom conductive region on the buffer layer in regions on both sides of the bottom isolation region.

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