Semiconductor Devices

Abstract

To provide a semiconductor device capable of miniaturization or high integration.SOLUTION: A semiconductor device has a first oxide, an insulator on the first oxide, a first conductor on the insulator, a second conductor electrically connected to the first oxide, and a second oxide provided between the first oxide and the second conductor. A contact area between the second oxide and the second conductor is larger than a contact area between the second oxide and the first oxide.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device, or to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are examples of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, semiconductor devices have been developed and are now used in LSIs, CPUs, memories, etc. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely low leakage current in a non-conducting state. For example, a low-power CPU that utilizes the low leakage current property of a transistor using an oxide semiconductor has been disclosed (see Patent Document 1).

[0008] In addition, a method for manufacturing a transistor including an oxide semiconductor in which a gate electrode is embedded in an opening has been disclosed (see Patent Document 2).

[0009] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for integrated circuits in which transistors and other components are densely integrated, and there is also a demand for improved productivity in semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-050530 Summary of the Invention [Problem to be solved by the invention]

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device having good frequency characteristics.An object of one embodiment of the present invention is to provide a semiconductor device with high reliability.An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.An object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed.An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0014] One embodiment of the present invention is a semiconductor device having a first oxide, an insulator on the first oxide, a first conductor on the insulator, a second conductor electrically connected to the first oxide, and a second oxide provided between the first oxide and the second conductor, wherein the contact area between the second oxide and the second conductor is larger than the contact area between the second oxide and the first oxide.

[0015] One embodiment of the present invention is a semiconductor device having a first oxide having a recess, a first insulator on the first oxide, a first conductor on the first insulator, a second insulator on the first insulator and on the first conductor, a second conductor electrically connected to the first oxide, and a second oxide provided between the first oxide and the second conductor, wherein the first insulator, the first conductor, and the second insulator are provided in the recess, and the second oxide has a region overlapping with the second insulator.

[0016] In the above, the first oxide preferably contains indium, an element M (M is aluminum, gallium, yttrium, or tin), and zinc.

[0017] In the above, the second oxide preferably contains indium, an element M (M is aluminum, gallium, yttrium, or tin), and zinc.

[0018] In the above, the second oxide preferably has the same material as the first oxide.

[0019] In the above, the second oxide preferably contacts the bottom and side surfaces of the second conductor.

[0020] In the above, the second conductor is preferably provided above the first conductor.

[0021] In the above, the semiconductor device may have an interlayer film on the first oxide, the interlayer film having an opening, the second oxide and the second conductor being provided inside the opening, and it is preferable that the contact area between the second oxide and the second conductor is larger than the area of ​​the opening.

[0022] In the above, the semiconductor device may include a capacitor, and the capacitor is preferably electrically connected to the second conductor. [Effects of the Invention]

[0023] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having good frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with good reliability can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0024] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with high design freedom can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0026] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] 2A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 2B to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 3A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 3B to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4]4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14]14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 20] 20A and 20B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A to 21C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 22] FIG. 22 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 23] FIG. 23 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 24 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A and 25B are cross-sectional and circuit diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 26]FIG. 26 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 29] 29A and 29B are block diagrams illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. [Figure 30] 30A and 30B are diagrams illustrating an example of an electronic component. [Figure 31] 31A to 31E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 32] 32A to 32H are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0028] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbol may be assigned.

[0029] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0030] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0031] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0032] For example, when it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in figures or text, and connection relationships other than those shown in figures or text are also assumed to be disclosed in figures or text.

[0033] Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0034] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0035] In this specification and the like, depending on the structure of a transistor, the channel length in a region where a channel is actually formed (hereinafter also referred to as an "effective channel length") may differ from the channel length shown in a top view of the transistor (hereinafter also referred to as an "apparent channel length"). For example, when a semiconductor has a recess and a gate electrode is provided so as to be embedded in the recess, the effective channel length may be longer than the apparent channel length, and the influence thereof may become unnegligible. For example, in a miniaturized transistor in which the semiconductor covers the side surfaces of the gate electrode, the proportion of the channel formation region formed on the side surfaces of the gate electrode may be large. In such a case, the effective channel length is longer than the apparent channel length.

[0036] In such cases, it may be difficult to estimate the effective channel length by actual measurement. For example, in order to estimate the effective channel length from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel length.

[0037] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0038] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0039] Furthermore, in this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, in this specification, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0040] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the density of states (DOS) of the semiconductor or reduce its crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor's characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water can also function as an impurity. In addition, in the case of an oxide semiconductor, for example, the inclusion of impurities can form oxygen vacancies. In addition, when the semiconductor is silicon, impurities that change the semiconductor's characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements excluding oxygen and hydrogen.

[0041] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0042] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" or "orthogonal" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "substantially orthogonal" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0043] In this specification, "having barrier properties" means having a function of suppressing the permeation of impurities such as hydrogen and oxygen, and an insulating film having barrier properties may be called an insulating barrier film, a barrier insulating film, or a barrier insulator. Also, a conductive film having barrier properties may be called a conductive barrier film.

[0044] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, the term "OS FET" or "OS transistor" can be rephrased as a transistor including an oxide or an oxide semiconductor.

[0045] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0046] (Embodiment 1) An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0047] <Configuration example of semiconductor device> 1A to 1D are a top view and a cross-sectional view of a semiconductor device and the periphery of the semiconductor device according to one embodiment of the present invention.

[0048] FIG. 1A is a top view of a semiconductor device. FIGS. 1B, 1C, and 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the channel length direction of transistor 200. FIG. 1C is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 1A, and is a cross-sectional view of the channel formation region in the direction in which conductor 260 extends. FIG. 1C represents a cross-section of transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by the dashed-dotted line A5-A6 in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for clarity.

[0049] A semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator 211, an insulator 212, an insulator 214, an insulator 280, and an insulator 281 which function as interlayer films. The semiconductor device also includes an oxide 243 (oxide 243a, oxide 243b, and oxide 243c) and a conductor 240 (conductor 240a, conductor 240b, and conductor 240c) which are electrically connected to the transistor 200 and function as a plug.

[0050] The transistor 200 includes two conductors 260 functioning as gate electrodes in one semiconductor layer. That is, the transistor 200 can be described as having a structure including transistors 200a and 200b in one semiconductor layer. One of the source and drain of the transistor 200a is shared with one of the source and drain of the transistor 200b. Therefore, compared with the case where the transistor 200a and the transistor 200b are formed separately, the number of plugs and the like connected to the transistor 200 can be reduced, and the area of ​​the transistor 200 can be reduced. One of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b are electrically connected to the conductor 240a through an oxide 243a. The other of the source and drain of the transistor 200a is electrically connected to the conductor 240b through an oxide 243b, and the other of the source and drain of the transistor 200b is electrically connected to the conductor 240c through an oxide 243c.

[0051] In this embodiment, the detailed description of the transistor 200 may focus on one of the transistors 200a and 200b, but unless otherwise specified, the transistors 200a and 200b have the same configuration, and therefore the description of the other of the transistors 200a and 200b will be omitted. Furthermore, in this specification, the transistor 200 may refer to either or both of the transistors 200a and 200b.

[0052] The conductor 260 (conductor 260a and conductor 260b) functioning as a gate electrode or word line of the transistor 200 is formed so as to be embedded in a recess provided in the oxide 230a functioning as a semiconductor layer of the transistor 200. The conductor 260 is formed so that its top surface is lower than the top surface of the oxide 230a, and an insulator 262 is provided on the conductor 260 at least in the recess. The insulator 262 has the function of preventing electrical connection between the conductor 260 and the oxide 243 and between the conductor 260 and the conductor 240.

[0053] At this time, it is preferable that the upper surface of the insulator 250 is also formed to be lower than the upper surface of the oxide 230a, and it is preferable that the insulator 262 is also provided on the insulator 250, at least within the recess. It is also preferable that the upper surface of the oxide 230b is also formed to be lower than the upper surface of the oxide 230a, and it is preferable that the insulator 262 is also provided on the oxide 230b, at least within the recess.

[0054] The oxide 243 is provided so as to contact the upper surface of the oxide 230a, and the conductor 240 is electrically connected to the oxide 230a via the oxide 243, so the oxide 243 and the conductor 240 are provided above the oxide 230a. In addition, the oxide 243 and the conductor 240 are provided above the conductor 260.

[0055] Furthermore, it is preferable to provide an insulator 272 so as to cover a portion of the upper surface and the side surfaces of the oxide 230a. An insulator 241 (insulators 241a, 241b, and 241c) may be provided in contact with the inner walls of the openings of the insulators 272, 280, and 281. In this case, the oxide 243 is provided in contact with the inner walls of the openings of the insulators 272, 280, and 281, via the insulator 241. The oxide 243 is formed in contact with the insulator 241, and the first conductor of the conductor 240 is formed inside the oxide 243, and the second conductor of the conductor 240 is formed further inside.

[0056] The insulator 241 is expected to suppress absorption of oxygen contained in the insulator 280 and the insulator 281 by at least one of the oxide 243 and the conductor 240. As a result, the characteristics and reliability of the semiconductor device can be improved, but the insulator 241 is not necessarily provided. That is, the oxide 243 may be provided in contact with the inner walls of the openings of the insulators 272, 280, and 281. Note that, although the transistor 200 shows a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish the structures.

[0057] Consider a case where misalignment occurs with respect to the desired position of the oxide 230a during the lithography process for forming openings in the insulators 272, 280, and 281. If misalignment occurs, the openings may overlap the conductor 260. However, according to one embodiment of the present invention, the insulator 262 is provided on the conductor 260 in the recess of the oxide 230a. This prevents electrical connection, i.e., short-circuiting, between the conductor 260 and the oxide 243 or conductor 240 formed in a later process. Furthermore, the openings can be designed to be larger than the desired region of the oxide 230a. By forming the openings larger than the desired region of the oxide 230a, connection between the desired region of the oxide 230a and the oxide 243 is possible even if the openings are misaligned with respect to the desired position of the oxide 230a.

[0058] If a misalignment occurs during the formation of the above opening, or if the size of the opening is designed to be larger than the width of oxide 230a in the A5-A6 direction shown in Figure 1D, the lower surface of oxide 243 or the lower surface of conductor 240 may be positioned lower than the upper surface of oxide 230a.

[0059] By using the semiconductor device of one embodiment of the present invention and the manufacturing method thereof, the margin for alignment in forming an opening is increased, and a semiconductor device having favorable characteristics can be realized even if the semiconductor device is miniaturized.

[0060] The conductor 240 electrically connects to the source and drain regions of the oxide 230a of the transistor 200 within the openings of the insulators 272, 280, and 281. If the conductor 240 is made of a metal and directly connects to the oxide 230a, which functions as a semiconductor, there is a concern that the contact resistance between the metal and the semiconductor will be high. Furthermore, if the contact is only made inside the contact, the contact area between the conductor 240 and the oxide 230a will be small, which could result in even higher contact resistance. A semiconductor device fabricated in this manner may have difficulty achieving good electrical characteristics.

[0061] In one embodiment of the present invention, an oxide 243 is provided on the bottom and side surfaces of the conductor 240, and the conductor 240 is electrically connected to the oxide 230a through the oxide 243. The oxide 243 is in direct contact with not only the bottom surface of the conductor 240 but also the side surfaces of the conductor 240, thereby increasing the contact area compared to when the oxide 243 is in direct contact with only the bottom surface of the conductor 240. Even when the conductor 240 is made of a metal, the contact area between the conductor 240 and the oxide 243 is sufficiently large, thereby suppressing an increase in contact resistance due to dissimilar materials. Furthermore, because the oxide 230a is connected to the oxide 243 within the opening, there is no concern about an increase in resistance due to the material. Therefore, the conductor 240 can achieve good electrical connection with the oxide 230a through the oxide 243.

[0062] When the oxide 230a and the conductor 240 are electrically connected using the above configuration, the contact area between the oxide 243 and the conductor 240 is larger than the contact area between the oxide 243 and the oxide 230a. The contact area between the oxide 243 and the conductor 240 is also larger than the area of ​​the openings formed in the insulators 272, 280, and 281. By forming deeper openings in the insulators 272, 280, and 281, the heights of the oxide 243 and the conductor 240 are increased, thereby suppressing an increase in contact resistance. The depth of the openings can be controlled, for example, by the film thickness of the insulator 281. The thickness of the insulator 281 can be set to 50 nm or more and 400 nm or less, preferably 100 nm or more and 250 nm or less.

[0063] The conductor 240a, the conductor 240b, and the conductor 240c can be electrically connected to wiring or elements such as transistors and capacitors. For example, the conductor 240a may be electrically connected to a wiring that functions as a bit line, and the conductor 240b and the conductor 240c may be electrically connected to different capacitors, thereby configuring a semiconductor device that functions as a memory device.

[0064] [Transistor 200] As shown in FIGS. 1A to 1D, the transistor 200 includes an insulator 211 disposed on a substrate (not shown), an insulator 212 disposed on the insulator 211, an insulator 214 disposed on the insulator 212, an insulator 216 disposed on the insulator 214, conductors 205 (conductors 205a and 205b) disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, an insulator 224 disposed on the insulator 222, and a recessed portion on the insulator 224. the oxide 230a arranged in the recess of the oxide 230a, an oxide 230b provided in contact with the bottom and side surfaces of the oxide 230a in a recess of the oxide 230a, an insulator 250 provided inside the oxide 230b, a conductor 260a provided inside the insulator 250, a conductor 260b provided so as to be embedded inside the conductor 260a, an insulator 262 on the oxide 230b, the insulator 250, the conductor 260a, and the conductor 260b in the recess, an insulator 224, and an insulator 272 on the oxide 230a.

[0065] In addition, insulator 280 is provided on insulator 272, insulator 281 is provided on insulators 262, 272, and 280, openings are provided in insulators 281, 280, and 272, insulator 241 is provided on the side of the opening, oxide 243 is provided inside the opening in which insulator 241 is provided, and conductor 240 is provided inside oxide 243.

[0066] Although the transistor 200 has a structure in which the oxide 230a is provided on and in contact with the insulator 224 and the top surface of the oxide 230a is in contact with the oxide 243, the present invention is not limited to this. For example, the oxide 230a may have a stacked structure of two or more layers. When the oxide 230a has a stacked structure, the layer in contact with the oxide 243 (upper layer) is preferably made of a material that has lower resistance or is easily reduced in resistance compared to the layer in contact with the insulator 224 (lower layer). Furthermore, the lower layer of the oxide 230a is preferably made of a material that allows oxygen to diffuse more easily than the upper layer. Oxygen diffusion compensates for oxygen vacancies in the oxide 230a, thereby reducing the oxygen vacancies. Using the oxide 230a with reduced oxygen vacancies in the channel formation region can realize a transistor with extremely low leakage current in a non-conducting state. Furthermore, although the transistor 200 has a two-layer structure in which the conductor 260 is made of the conductor 260a and the conductor 260b, the present invention is not limited to this structure. For example, the conductor 260 may have a single layer structure or a laminated structure of three or more layers.

[0067] Here, the conductor 260 functions as the gate electrode of the transistor. As described above, the conductor 260 is formed so as to be embedded in the recess of the oxide 230a via the oxide 230b, the insulator 250, etc. Here, the arrangement of the conductor 260 is selected in a self-aligned manner with respect to the recess of the oxide 230a. Therefore, the conductor 260 can be formed without providing an alignment margin, which allows the area occupied by the transistor 200 to be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0068] Furthermore, since an insulator 262 is provided on the conductor 260 within the recess of the oxide 230a, even if there is an overlapping area between the conductor 260 and the oxide 243 or the conductor 240, it is possible to prevent a short circuit between the conductor 260 and the oxide 243 or the conductor 240.

[0069] In the transistor 200, the oxide 230 including the channel formation region (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor).

[0070] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely small leakage current in an off-state, and therefore can provide a semiconductor device with low power consumption. Furthermore, an oxide semiconductor can be deposited by a sputtering method, an atomic layer deposition (ALD) method, or the like, and therefore can be used for the transistor 200 that constitutes a highly integrated semiconductor device.

[0071] For example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. In particular, it is preferable that in addition to indium and zinc, aluminum, gallium, yttrium, or tin is contained. Alternatively, In-Ga oxide or In-Zn oxide may be used as oxide 230.

[0072] The oxide 230a preferably has a crystalline structure. For example, the oxide 230a preferably has a c-axis aligned crystalline oxide semiconductor (CAAC-OS) or a nanocrystalline oxide semiconductor (nc-OS), as will be described in detail later. When the oxide 230a has a crystalline structure, the transistor 200 can have high field-effect mobility. Furthermore, the transistor can have high reliability.

[0073] In particular, when the oxide 230a includes a CAAC-OS, it is difficult to identify clear grain boundaries in the CAAC-OS, and therefore a decrease in electron mobility due to the grain boundaries is unlikely to occur. Therefore, the transistor 200 can have high field-effect mobility. Furthermore, the CAAC-OS has high crystallinity, which reduces the amount of impurities and defects, resulting in stable physical properties, and therefore the transistor 200 can have high reliability.

[0074] On the other hand, when the oxide 230a contains an nc-OS, no crystalline orientation is observed throughout the oxide 230a. This means that the film characteristics of the oxide 230a are constant regardless of the direction of carriers flowing through the oxide 230a, resulting in stable electrical characteristics of the transistor 200. As shown in this embodiment, when the transistor 200 has a U-shaped channel formation region, carriers flow in two or more directions, namely, perpendicular or substantially perpendicular to the normal direction of the formation surface of the oxide 230a, and parallel or substantially parallel to the normal direction. Therefore, it is preferable to use an nc-OS, which does not exhibit crystalline orientation throughout the film, for the oxide 230a.

[0075] Note that by using a CAAC-OS or an nc-OS as the oxide 230b, the transistor 200 can have high field-effect mobility and high reliability.

[0076] Here, the presence of impurities such as hydrogen, nitrogen, or metal elements in the oxide 230 may increase the carrier density and lower the resistance. Also, a decrease in the oxygen concentration in the oxide 230 may increase the carrier density and lower the resistance.

[0077] Furthermore, the oxide 243 that functions as a part of the plug can be made of a metal oxide similar to the oxide 230 .

[0078] When a conductor provided in contact with an oxide has the function of absorbing oxygen from the oxide or the function of supplying impurities such as hydrogen, nitrogen, or metal elements to the oxide, a low resistance region may be formed in the oxide or at least in part of the oxide.

[0079] As shown in FIGS. 1B and 1D , the oxide 243 is provided so as to contact the bottom and side surfaces of the conductor 240, whereby the oxide 243 functions as a low-resistance region. A portion of the oxide 230a in contact with the oxide 243 may also function as a low-resistance region. The channel formation region of the transistor 200 is formed in the oxide 230a along a recess provided in the oxide 230a and is electrically connected to the conductor 240 via the oxide 243. Therefore, the transistor 200 can also be considered a transistor having a U-shaped channel formation region. In this case, the oxide 230b, or at least a portion of the oxide 230b, may also function as the channel formation region of the transistor 200. In such a transistor having a U-shaped channel formation region, carriers flow in a direction perpendicular or approximately perpendicular to the normal direction of the top surface of the insulator 222, and in a direction parallel or approximately parallel to the normal direction.

[0080] The conductor 240a functions as one of a source electrode and a drain electrode electrically connected to the transistor 200a, and the conductor 240b functions as the other of a source electrode and a drain electrode electrically connected to the transistor 200a. In this case, the conductor 240a functions as one of a source electrode and a drain electrode electrically connected to the transistor 200b, and the conductor 240c functions as the other of a source electrode and a drain electrode electrically connected to the transistor 200b. Note that the source electrode or the drain electrode may include not only the conductor 240 but also the oxide 243.

[0081] The oxide 243 and a part of the oxide 230a whose resistance is reduced by the conductor 240 can be referred to as a source region or a drain region. The source region and the drain region are regions with a lower oxygen concentration or a higher content of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, resulting in an increased carrier concentration and reduced resistance. That is, the source region and the drain region are regions with a higher carrier density and lower resistance than the channel formation region. The channel formation region is a high-resistance region with a lower carrier density because it has a higher oxygen concentration or a lower impurity concentration than the source region and the drain region.

[0082] In addition, when the low resistance region contains a metal element, it is preferable that the region contains, in addition to the metal element contained in oxide 243 or oxide 230, one or more metal elements selected from metal elements such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum.

[0083] Furthermore, it may be difficult to clearly detect the boundary between the low-resistance region and the channel-forming region in the oxide 230a. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously (also called gradation) within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel-forming region.

[0084] To reduce the resistance of at least a portion of the oxide 243 and the oxide 230, it is preferable to use a material containing at least one of a metal element that enhances conductivity, such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, and an impurity, as the conductor 240. Alternatively, in forming the conductive film 240A that becomes the conductor 240, a material or film formation method may be used in which impurities, such as elements that form oxygen vacancies or elements that are captured by oxygen vacancies, are implanted into the oxide 243 and the oxide 230. Examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon.

[0085] Here, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics of a transistor using an oxide semiconductor may fluctuate, resulting in poor reliability. Furthermore, if oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable to reduce oxygen vacancies in the region where a channel is formed in the oxide 230 as much as possible.

[0086] To prevent the transistor from becoming normally on, the insulator 224 adjacent to the oxide 230 preferably contains more oxygen (also referred to as excess oxygen) than the amount of oxygen required for the stoichiometric composition. The oxygen in the insulator 224 diffuses into the oxide 230, reduces oxygen vacancies in the oxide 230, and prevents the transistor from becoming normally on.

[0087] In other words, oxygen contained in the insulator 224 diffuses into the oxide 230, thereby reducing oxygen vacancies in the channel formation region of the oxide 230.

[0088] Furthermore, insulators 211, 212, 214, 222, 272, and 262 are preferably provided to prevent oxygen in the oxide 230 and the insulator 224 from diffusing outward from the transistor 200. These insulators are preferably made of a material that is impermeable to oxygen. For example, an oxide containing aluminum or hafnium, or a nitride of silicon, can be used. Alternatively, a metal oxide such as indium-gallium-zinc oxide with a reduced concentration of In or a metal oxide that does not contain In can be used. Furthermore, these insulating films are preferably made of a material that is impermeable to impurities such as hydrogen, water, nitrogen, and metal elements. Using such a material can prevent impurities from entering the transistor 200 from the outside.

[0089] In addition, oxide semiconductors can be used for transistors that form highly integrated semiconductor devices because they can be formed by sputtering, ALD, etc. Furthermore, transistors that use oxide semiconductors in their channel formation regions have extremely low leakage current (off-state current) in a non-conducting state, and therefore can provide semiconductor devices with low power consumption.

[0090] As described above, a semiconductor device including a transistor with high on-state current, a semiconductor device including a transistor with low off-state current, or a semiconductor device in which fluctuations in electrical characteristics are suppressed, which has stable electrical characteristics and improved reliability can be provided.

[0091] A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0092] 1A and 1C, the conductor 205 extends in the channel width direction and is arranged so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 216.

[0093] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. By providing the second gate electrode, an electric field can be applied from the conductor 205 to at least a region of the oxide 230a where the conductor 205 and the conductor 260 overlap. In this case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0094] 1A to 1C, the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. In particular, as shown in FIG. 1C, it is preferable that the conductor 205 also extends in a region outside the end of the oxide 230 that intersects with the channel width direction. In other words, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator on the outside of the side surface of the oxide 230 in the channel width direction.

[0095] With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and at least a portion of the channel formation region formed in the oxide 230 can be covered.

[0096] That is, at least a part of the channel formation region can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0097] As will be described in detail later, the conductor 205 has a conductor 205a formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205b formed inside the conductor 205a. Here, the height of the top surfaces of the conductors 205a and 205b can be made approximately the same as the height of the top surface of the insulator 216. Note that, although the transistor 200 shows a structure in which the conductors 205a and 205b are stacked, the present invention is not limited to this. For example, the conductor 205 may be configured as a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0098] Here, it is preferable to use a conductive barrier film as the conductor 205a. For example, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., the impurities are less likely to permeate). Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0099] The conductor 205a has the function of suppressing oxygen diffusion, thereby suppressing oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that suppress oxygen diffusion include, for example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed using a conductive material selected from the above. This can suppress the diffusion of impurities such as hydrogen and water to the transistor 200 through the conductor 205. The conductor 205a may also have a stacked structure of two or more layers using a material selected from the above materials. For example, the conductor 205a may be a conductor with a stacked structure including tantalum nitride and titanium nitride on the tantalum nitride.

[0100] Furthermore, the conductor 205b is preferably made of a material having higher conductivity than the conductor 205a, and is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component.

[0101] The insulators 211, 212, and 214 preferably function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulators 211, 212, and 214 are preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., the impurities are less likely to permeate through the material). Alternatively, the insulators 211, 212, and 214 are preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through the material).

[0102] Aluminum oxide, hafnium oxide, silicon nitride, or the like can be used for the insulators 211, 212, and 214. Alternatively, a metal oxide such as indium-gallium-zinc oxide with a reduced In concentration or a metal oxide that does not contain In can be used. For example, it is preferable to use silicon nitride or the like for the insulators 211 and 212 and aluminum oxide or the like for the insulator 214. This can prevent impurities such as hydrogen and water from diffusing from the substrate side of the insulators 211, 212, and 214 toward the transistor 200. Alternatively, it can prevent oxygen contained in the insulator 216 or the insulator 224 from diffusing toward the substrate side of the insulators 211, 212, and 214.

[0103] Furthermore, it is preferable that the insulators 216, 280, and 281, which function as interlayer films, have a lower dielectric constant than the insulators 211, 212, and 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0104] For example, insulators 216, 280, and 281 can be formed of a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0105] The insulators 222, 224, and 250 function as gate insulators.

[0106] Here, the insulator 224 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230a, oxygen vacancies in the oxide 230a can be reduced, and the reliability of the transistor 200 can be improved.

[0107] Specifically, it is preferable to use an insulator that has an excess oxygen region, from which a portion of oxygen is desorbed by heating. An insulator that desorbs oxygen by heating is an insulator that has a thermal desorption spectroscopy (TDS) analysis in which the amount of desorbed oxygen molecules is 1.0 × 10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0108] For example, the insulator 224 may be a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). Alternatively, these insulators may be doped with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0109] Furthermore, when the insulator 224 has an excess oxygen region, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0110] The insulator 222 preferably has a function of suppressing the diffusion of oxygen and impurities, so that the oxygen contained in the oxide 230 does not diffuse toward the insulator 216. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0111] The insulator 222 is preferably a single layer or multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0112] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., the oxygen is less likely to permeate). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230a and the intrusion of impurities such as hydrogen into the oxide 230a from the periphery of the transistor 200.

[0113] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0114] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0115] The oxide 230 includes an oxide 230a and an oxide 230b on the oxide 230a. When the oxide 230a is in contact with the insulator 224, oxygen contained in the insulator 224 is supplied to the oxide 230a. If the oxide 230a has oxygen vacancies, the oxygen vacancies in the oxide 230a can be compensated for and reduced by supplying oxygen. By using the oxide 230a with reduced oxygen vacancies in the channel formation region, a transistor with extremely low leakage current in the non-conducting state can be realized.

[0116] The oxide 230a may have a stacked structure of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, when the oxide 230a has a stacked structure, the atomic ratio of the element M among the constituent elements in the metal oxide used for the upper layer of the oxide 230a is preferably smaller than the atomic ratio of the element M among the constituent elements in the metal oxide used for the lower layer of the oxide 230a. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the upper layer of the oxide 230a is preferably smaller than the atomic ratio of the element M to In in the metal oxide used for the lower layer of the oxide 230a. Furthermore, the atomic ratio of In to M in the metal oxide used for the upper layer of the oxide 230a is preferably larger than the atomic ratio of In to M in the metal oxide used for the lower layer of the oxide 230a. Furthermore, a conductive metal oxide may be used for the upper layer of the oxide 230a. With this configuration, the lower layer of the oxide 230a has a higher resistance than the upper layer, and the upper layer of the oxide 230a has a lower resistance than the lower layer. Therefore, the lower layer of the oxide 230a can be used as a channel formation region, and the upper layer of the oxide 230a can be used as a source region or a drain region. When the oxide 230a has a stacked structure, it is preferable that the upper surface of the lower layer of the oxide 230a is located higher than the lower surface of the oxide 230b and lower than the lower surface of the oxide 243. It is also preferable that the upper surface of the lower layer of the oxide 230a roughly coincides with the upper surface of the conductor 260.

[0117] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, an atomic ratio of In:Ga:Zn=5:1:6 or thereabouts, an atomic ratio of In:Ga:Zn=5:1:3 or thereabouts, an atomic ratio of In:Ga:Zn=10:1:3 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts, or a metal oxide such as In-Zn oxide or indium oxide. When the oxide 230a has a stacked structure and a conductive metal oxide is used as the upper layer of the oxide 230a, the conductive metal oxide may be indium tin oxide, zinc oxide, indium oxide, or the like. The oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, an atomic ratio of In:Ga:Zn=4:2:3, an atomic ratio of Ga:Zn=2:1, or an atomic ratio of Ga:Zn=2:5. In addition, the oxide 230b may have a layered structure, and specific examples of the oxide 230b having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0118] In this case, the main carrier path is the region of the oxide 230a near the oxide 230b. The above-described structure of the oxide 230b reduces the defect state density at the interface between the oxide 230a and the oxide 230b. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200 to achieve a high on-state current and high frequency characteristics. Note that, when the oxide 230b has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the oxide 230a and the oxide 230b, it is expected to suppress the diffusion of constituent elements of the oxide 230b toward the insulator 250. More specifically, by forming the oxide 230b into a stacked structure and positioning an oxide that does not contain In or has a reduced In concentration above the stacked structure, it is possible to suppress In that may diffuse toward the insulator 250. Because the insulator 250 functions as a gate insulator, the diffusion of In leads to poor transistor characteristics. Therefore, by forming the oxide 230b into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0119] Furthermore, by forming the oxide 230b in a stacked structure, the main path of carriers may be the interface between the oxide 230a and the lower layer of the oxide 230b or the vicinity thereof.

[0120] 1C, the oxide 230b is in contact with the insulator 224, and therefore oxygen contained in the insulator 224 can be supplied to the channel formation region of the transistor 200 through the oxide 230b. When the oxide 230b has a stacked structure, it is preferable to use a material that is easily permeable to oxygen for the lower layer of the oxide 230b and a material that is less permeable to oxygen for the upper layer of the oxide 230b. Using the above-mentioned material can prevent oxygen contained in the insulator 224 from permeating the oxide 230b and being absorbed by the insulator 250 or the conductor 260, thereby enabling efficient supply of oxygen to the channel formation region.

[0121] As described above, the oxygen contained in the insulator 224 may be supplied to the channel formation region by passing through the interface between the insulator 224 and the oxide 230a, or may be supplied to the channel formation region via the oxide 230b.

[0122] That is, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements in accordance with the circuit design.

[0123] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). For example, as an oxide that functions as a channel formation region, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more, is preferably used. By using such a metal oxide with a wide band gap, the off-state current of the transistor 200 can be reduced.

[0124] A transistor including an oxide semiconductor has an extremely small leakage current in an off-state, and therefore a semiconductor device with low power consumption can be provided. In addition, an oxide semiconductor can be formed into a film by a sputtering method or the like, and therefore can be used for a transistor included in a highly integrated semiconductor device.

[0125] The insulator 272 is provided to cover the oxide 230a and to be in contact with the insulator 224. By providing the insulator 272, it is possible to suppress the diffusion of oxygen contained in the insulator 224 into the insulator 280. It is also possible to suppress the supply of oxygen contained in the insulators 280 and 281 to the oxide 230a. By providing the insulator 272, it is possible to efficiently supply the oxygen contained in the insulator 224 to the oxide 230a, and it is possible to suppress the oxygen contained in the insulators 280 and 281 from increasing the resistance of the upper layer of the oxide 230a, particularly the region in contact with the oxide 243, due to the oxygen.

[0126] A metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. may be used as the insulator 272. Alternatively, a metal oxide in which the atomic ratio of In among the constituent elements in the metal oxide is smaller than the atomic ratio of element M, such as indium-gallium-zinc oxide in which the concentration of In is smaller than the concentration of Ga, or a metal oxide that does not contain In may be used as the insulator 272.

[0127] In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than hafnium oxide film, and is therefore preferable because it is less likely to crystallize during heat treatment in a later process.

[0128] The insulator 272 may have a laminated structure of two or more layers. In this case, the layers included in the insulator 272 may be made of different materials. Furthermore, the layers included in the insulator 272 may be formed by different methods. For example, the lower layer of the insulator 272 may be made of aluminum oxide formed by a sputtering method, and the upper layer of the insulator 272 may be made of aluminum oxide formed by an ALD method.

[0129] An insulator 280 is provided on the insulator 272. The insulator 280 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. It is preferable to use an insulator with a reduced oxygen concentration as the insulator 280. For example, the oxygen concentration of the insulator 280 is preferably lower than the oxygen concentration of the insulator 224.

[0130] The insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen. The insulator 280 may have a stacked structure of two or more layers. The top surface of the insulator 280 may be flattened. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using the same material as the insulator 216, for example.

[0131] 1B and 1C, the oxide 230b is provided so as to be in contact with the upper surface of the oxide 230a, the side surface of the oxide 230a, and the side surface of the insulator 224. Note that, although FIG. 1C shows an example in which the oxide 230b has a region in contact with the insulator 222, the present embodiment is not limited to this. When the insulator 224 is provided on the upper surface of the insulator 222, the oxide 230b is provided so as to be in contact with the upper surface of the insulator 224.

[0132] The insulator 250 functions as a gate insulator and is preferably disposed in contact with the inside (top and side surfaces) of the oxide 230b.

[0133] Specifically, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies can be used as the insulator 250. Silicon oxide and silicon oxynitride are particularly preferable because they are stable against heat.

[0134] Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0135] 1B and 1C, the conductor 260 functioning as the first gate electrode is shown as having a two-layer structure, but may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 260 has a two-layer structure, the conductor 260a, like the conductor 205a, is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0136] Conductor 260a has the function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of conductor 260b caused by oxygen contained in insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide.

[0137] Furthermore, it is preferable that the conductor 260b be made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 260 also functions as wiring, it is preferable that a conductor with high conductivity be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0138] 1C, when the conductor 205 extends in a region outside the end of the oxide 230a that intersects with the channel width direction, the conductor 260 preferably overlaps the oxide 230b and the insulator 250 in that region. In other words, outside the side surface of the oxide 230a, the conductor 205, the oxide 230b, the insulator 250, and the conductor 260 preferably form a stacked structure.

[0139] With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and the channel formation region formed in the oxide 230 can be covered.

[0140] That is, the channel formation region can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.

[0141] The insulator 262 is provided at least on the conductor 260. Preferably, the insulator 262 is also provided on the insulator 250. While FIG. 1B illustrates an example in which the insulator 262 is provided on the conductor 260, the insulator 250, and the oxide 230b and is provided so as to contact the side surface of the oxide 230a, this embodiment is not limited to this. The oxide 230b may be provided so that the height of the upper surface of the oxide 230b is approximately the same as the height of the upper surface of the oxide 230a or the height of the upper surface of the insulator 272. In this case, the insulator 262 is provided so as to contact the upper surface of the conductor 260, the upper surface of the insulator 250, and the side surface of the oxide 230b. FIG. 1B illustrates the insulator 262 provided in a recess formed in the oxide 230a. On the other hand, as shown in FIGS. 1A and 1C, the insulator 262 is provided in a recess provided in the insulator 280 in the region where it does not overlap with the oxide 230a.

[0142] The insulator 262 is preferably formed using an insulating barrier film. The insulator 262 has barrier properties against impurities such as hydrogen and oxygen, which can suppress the diffusion of impurities such as hydrogen contained in the insulator 281 and the like into the oxide 230a. Furthermore, the insulator 262 can suppress the diffusion of oxygen contained in the insulator 281 and the like into the oxide 230a, thereby suppressing an increase in the resistance of the oxide 230a. Furthermore, the insulator 262 can suppress the diffusion of oxygen contained in the insulator 281 and the like into the conductor 260, thereby suppressing an increase in the resistance of the conductor 260.

[0143] It is preferable to use a material for the insulator 262 that does not disappear when processing the insulator 272. For example, hafnium oxide, silicon nitride, or the like can be used for the insulator 262. Alternatively, aluminum oxide may be used for the insulator 262.

[0144] It is preferable that an insulator 281 functioning as an interlayer film be provided over the insulators 272, 280, and 262. The insulator 281 can be made of a material similar to that of the insulator 280. It is preferable that the insulator 281 have a reduced concentration of impurities such as water or hydrogen.

[0145] Furthermore, an oxide 243 electrically connected to the oxide 230a and a conductor 240 are disposed in openings formed in the insulators 281, 280, and 272. In this case, an insulator 241 is preferably provided on the side surfaces of the openings. The insulator 241 preferably has a function of suppressing the permeation of impurities such as hydrogen and oxygen. The insulator 241 can be made of a material similar to that of the insulators 211, 212, 214, 222, and 272. By providing the insulator 241, oxygen absorption by the oxide 243 and the conductor 240 can be suppressed. By suppressing oxygen absorption by the oxide 243, a decrease in the carrier density of the oxide 243 can be suppressed, and an increase in resistivity can be suppressed. Furthermore, by suppressing oxygen absorption by the conductor 240, an increase in resistivity due to oxidation of the conductor 240 can be suppressed. However, if the insulators 280 and 281 are not insulators that release oxygen at room temperature or when heated, it is not necessary to provide the insulator 241. Furthermore, by providing the insulator 241, it is possible to prevent hydrogen contained in the insulators 280 and 281 from diffusing into the oxide 230 via the conductor 240.

[0146] The conductor 240 functions as a plug that electrically connects the transistor 200 to wiring or to an element such as a capacitor or a transistor other than the transistor 200. Furthermore, an oxide 243 is provided on the bottom and side surfaces of the conductor 240 to reduce contact resistance with the transistor 200. Therefore, the oxide 243 and the conductor 240 can be collectively referred to as a plug. The conductor 240 can be referred to as a source electrode or a drain electrode based on its functional characteristics. The oxide 243 can be referred to as a low-resistance region based on its functional characteristics. The low-resistance region is a region that has a lower resistance than the channel formation region and a higher resistance than conductors that can be used for the conductors 205, 260, and 240. The low-resistance region may also be referred to as a source region or a drain region.

[0147] The conductor 240 may have a layered structure consisting of a first conductor and a second conductor. In this case, the first conductor is provided inside the oxide 243, and the second conductor is provided on the first conductor. In addition, it is preferable that the first conductor is provided so as to cover the side surface of the second conductor.

[0148] FIG. 1D shows a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 1A. As shown in FIG. 1D, oxide 243a and conductor 240 contact the upper surface of oxide 230a that is not covered by insulator 272. The area of ​​oxide 230a near the area in contact with oxide 243a may have a high carrier density and low resistance. That is, oxide 230a shown in FIG. 1D may have a region that functions as a channel formation region and a region that functions as a source region or drain region above the channel formation region.

[0149] A conductive material containing tungsten, copper, or aluminum as a main component is preferably used for the conductor 240. The conductor 240 may be a single layer or may have a laminated structure of three or more layers.

[0150] Furthermore, when the conductor 240 has a layered structure including a first conductor and a second conductor on the first conductor, it is preferable to use a conductive material for the first conductor that has the function of suppressing the permeation of impurities such as water or hydrogen, similar to the conductor 205a. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using such a conductive material, it is possible to suppress the intrusion of impurities such as hydrogen and water from layers above the insulator 281 into the oxide 230 through the conductor 240. Furthermore, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum as the second conductor provided on the first conductor.

[0151] Since the oxide 243 is provided so as to contact the bottom and side surfaces of the conductor 240, the contact area between them is sufficiently large, and the influence of an increase in contact resistance due to contact between a metal and a semiconductor can be reduced. The conductor 240 is electrically connected to the oxide 230 via the oxide 243, and therefore a good electrical connection can be achieved.

[0152] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0153] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon, germanium, or other materials, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0154] A flexible substrate may also be used as the substrate. A method for providing a transistor on a flexible substrate includes fabricating a transistor on a non-flexible substrate, peeling the transistor, and transferring the transistor to a flexible substrate. In this case, a peeling layer may be provided between the non-flexible substrate and the transistor. The substrate may be stretchable. The substrate may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. The substrate may have a region with a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. Thinning the substrate can reduce the weight of a semiconductor device including a transistor. Thinning the substrate may also provide stretchability, even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

[0155] As the flexible substrate, for example, metal, alloy, resin, glass, or fibers thereof can be used. Furthermore, a sheet, film, or foil containing woven fibers may also be used as the substrate. The lower the linear expansion coefficient of the flexible substrate, the more preferable it is, since deformation due to the environment is suppressed. As the flexible substrate, for example, a substrate having a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid, in particular, has a low linear expansion coefficient and is therefore suitable for flexible substrates.

[0156] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0157] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0158] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0159] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0160] In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining them with a resin, a thermally stable laminate structure with a low dielectric constant can be formed. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Furthermore, for example, by combining silicon oxide and silicon oxynitride with an insulator with a high dielectric constant, a thermally stable laminate structure with a high dielectric constant can be formed.

[0161] Furthermore, when a transistor including an oxide semiconductor is surrounded by an insulator that has a function of suppressing permeation of oxygen and impurities such as hydrogen and water, the electrical characteristics of the transistor can be stabilized.

[0162] Examples of insulators that can suppress the permeation of impurities such as hydrogen and water and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, phosphorus, chlorine, argon, silicon, aluminum, hafnium, magnesium, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, tungsten, titanium, tantalum, and nickel, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tungsten oxide, titanium oxide, tantalum oxide, and nickel oxide, and silicon nitrides such as silicon nitride oxide and silicon nitride.

[0163] For example, the insulator 224 functioning as a gate insulator is preferably an insulator containing oxygen. For example, by using a structure in which silicon oxide or silicon oxynitride containing oxygen is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0164] Furthermore, for example, the insulator 222 that functions as part of the gate insulator can be an insulator containing one or more oxides of aluminum, hafnium, and gallium. In particular, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as an insulator containing one or both of aluminum and hafnium oxides.

[0165] The above stacked structure can improve the on-state current without weakening the influence of the electric field from the gate electrode. Furthermore, the physical thickness of the gate insulator can maintain a distance between the gate electrode and the channel formation region, thereby suppressing leakage current between the gate electrode and the channel formation region. Furthermore, the release of oxygen from the insulator 224 toward the insulator 216 can be suppressed.

[0166] The insulators 216, 280, and 281 preferably have a single layer or a stack of insulators with a low dielectric constant. For example, the insulators 216, 280, and 281 preferably have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having pores, or resin. Alternatively, the insulators 216, 280, and 281 preferably have a stack structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having pores, and a resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore, by combining them with a resin, a thermally stable stack structure with a low dielectric constant can be achieved. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0167] Insulators 211, 212, 214, 272, and 241 may be insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen and water. Metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tungsten oxide, titanium oxide, tantalum oxide, and nickel oxide, silicon nitride oxide, or silicon nitride may be used for insulators 211, 212, 214, 272, and 241. Metal oxides such as indium-gallium-zinc oxide with a reduced In concentration or metal oxides that do not contain In may also be used for the insulators.

[0168] <<Conductors>> The conductor may be a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0169] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0170] Conductor 260, conductor 205, and conductor 240 are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above metal elements or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are also preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0171] <<Metal oxides>> A metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used as the oxide 230 and the oxide 243. Metal oxides that can be used as the oxide 230 and the oxide 243 according to the present invention will be described below.

[0172] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like.

[0173] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M may be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0174] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0175] [Metal oxide composition] The structure of a cloud-aligned composite (CAC)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

[0176] In this specification, etc., they may be referred to as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0177] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the semiconductor layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0178] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0179] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0180] Furthermore, the CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0181] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0182] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0183] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0184] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS can be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0185] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0186] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, since the crystallinity of metal oxides can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS is unlikely to have impurities or defects (oxygen vacancies (V OIt can also be said that these metal oxides have low oxygen vacancies. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0187] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0188] Indium-gallium-zinc oxide (IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, because IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable when made into small crystals (such as the above-mentioned nanocrystals) than large crystals (here, crystals of a few millimeters or a few centimeters).

[0189] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0190] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0191] [Transistors with metal oxides] Next, a case where the above metal oxide is used for a channel formation region of a transistor will be described.

[0192] By using the metal oxide for a channel formation region of a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0193] Furthermore, it is preferable to use a metal oxide with a low carrier density for the channel formation region of a transistor. In order to reduce the carrier density of a metal oxide film, the impurity concentration in the metal oxide film may be reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, a metal oxide having a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0194] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect state density, and therefore may also have a low trap state density.

[0195] In addition, charges trapped in the trap states of a metal oxide take a long time to dissipate and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap states may have unstable electrical characteristics.

[0196] Therefore, to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the metal oxide. Furthermore, to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0197] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0198] When a metal oxide contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon near the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0199] Furthermore, when a metal oxide contains an alkali metal or alkaline earth metal, defect levels may be formed, generating carriers. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal in a channel formation region is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is reduced to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0200] Furthermore, when nitrogen is contained in a metal oxide, electrons serving as carriers are generated, the carrier density increases, and the metal oxide is easily made n-type. As a result, a transistor using a metal oxide containing nitrogen in the channel formation region is likely to have normally-on characteristics. Therefore, it is preferable that the nitrogen in the channel formation region of the metal oxide is reduced as much as possible. For example, the nitrogen concentration in the metal oxide is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0201] Furthermore, hydrogen contained in metal oxides may react with oxygen bonded to metal atoms to form water, forming oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons, which act as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which act as carriers. Therefore, transistors using metal oxides containing hydrogen tend to exhibit normally-on characteristics.

[0202] Furthermore, hydrogen contained in metal oxides can form shallow defect levels (sDOS: shallow level density of states) in the metal oxide. Shallow defect levels refer to interface states located near the bottom of the conduction band. Shallow defect levels are presumed to exist near the boundary between high-density and low-density regions in the metal oxide. Here, high-density and low-density regions in a metal oxide are distinguished by the amount of hydrogen contained in the region. In other words, high-density regions are regions that contain more hydrogen than low-density regions. Microcracks are likely to occur near the boundary between high-density and low-density regions in a metal oxide due to stress and strain between the two regions. Oxygen vacancies and indium dangling bonds are generated near the cracks, and it is presumed that the localization of impurities such as hydrogen or water here leads to the formation of shallow defect levels.

[0203] Furthermore, the high-density region in the metal oxide may have higher crystallinity than the low-density region. Furthermore, the high-density region in the metal oxide may have higher film density than the low-density region. Furthermore, when the metal oxide has a composition containing indium, gallium, and zinc, the high-density region may contain indium, gallium, and zinc, and the low-density region may contain indium and zinc. In other words, the low-density region may have a lower proportion of gallium than the high-density region.

[0204] The shallow defect levels are presumed to be caused by oxygen vacancies. It is presumed that as the oxygen vacancies in a metal oxide increase, the density of shallow defect levels as well as the density of deep defect levels (dDOS) also increases. This is because the deep defect levels are also thought to be caused by oxygen vacancies. The deep defect levels refer to defect levels located near the center of the band gap.

[0205] Therefore, by suppressing oxygen vacancies in the metal oxide, it is possible to reduce the density of both shallow and deep defect levels. Furthermore, the shallow defect level may be controlled to some extent by adjusting the temperature during the deposition of the metal oxide. Specifically, the density of shallow defect levels can be reduced by setting the temperature during the deposition of the metal oxide at or near 170°C, preferably at or near 130°C, and more preferably at room temperature.

[0206] Furthermore, shallow defect levels in metal oxides affect the electrical characteristics of transistors that use metal oxides as semiconductor layers. That is, shallow defect levels cause a gradual change in the drain current Id relative to the gate voltage Vg in the drain current-gate voltage (Id-Vg) characteristics of a transistor, deteriorating the S value (also known as subthreshold swing, SS), which is one of the indicators of the quality of the transition characteristics from the off state to the on state of a transistor. This is thought to be due to electrons being trapped in the shallow defect levels.

[0207] For this reason, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by SIMS is reduced to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0208] <Method for manufacturing semiconductor device> Next, a manufacturing method of a semiconductor device including a transistor 200 according to the present invention will be described with reference to FIGS. 2A to 18D. In FIGS. 2A to 18D, A in each figure is a top view. B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A of each figure. C in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A of each figure. D in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A of each figure.

[0209] First, a substrate (not shown) is prepared, and then an insulator 211 and an insulator 212 are formed on the substrate. The insulator 212 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0210] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0211] In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios, etc. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0212] In this embodiment, silicon nitride is deposited as the insulator 211 by sputtering, CVD, or ALD. Silicon nitride is deposited as the insulator 212 by sputtering, CVD, or ALD. It is preferable that the insulators 211 and 212 are deposited by different methods. For example, silicon nitride is deposited as the insulator 211 by CVD, and silicon nitride is deposited as the insulator 212 by sputtering.

[0213] Next, the insulator 214 is formed on the insulator 212. The insulator 214 is formed by forming an aluminum oxide film by sputtering. The insulator 214 may also have a multilayer structure. For example, the insulator 214 may have a structure in which an aluminum oxide film is formed by sputtering, and then another aluminum oxide film is formed on the aluminum oxide by ALD. Alternatively, the insulator 214 may have a structure in which an aluminum oxide film is formed by ALD, and then another aluminum oxide film is formed on the aluminum oxide by sputtering.

[0214] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is deposited as the insulator 216 by a CVD method.

[0215] Next, an opening is formed in the insulator 216. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. A wet etching method may be used to form the opening, but dry etching is preferable for fine processing. Furthermore, it is preferable to select an insulator for the insulator 214 that functions as an etching stopper when the insulator 216 is etched to form the opening. For example, if silicon oxide is used for the insulator 216 in which the opening is formed, aluminum oxide, hafnium oxide, or silicon nitride may be used for the insulator 214 as an insulator that functions as an etching stopper.

[0216] After the openings are formed, a conductive film that will become the conductor 205a is formed. The conductive film preferably contains a conductive material that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that will become the conductor 205a can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0217] In this embodiment, a titanium nitride film is formed by CVD as the conductive film that becomes the conductor 205a.

[0218] The conductor 205a may have a laminated structure, and may be formed by depositing a tantalum nitride film by sputtering, and then depositing a titanium nitride film by CVD.

[0219] Next, a conductive film that will become the conductor 205b is formed on the conductive film that will become the conductor 205a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0220] In this embodiment, a tungsten film is formed by CVD as the conductive film that becomes the conductor 205b.

[0221] Next, chemical mechanical polishing (CMP) is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductive film that will become the conductor 205a and the conductor 205b remains only in the openings. This allows the formation of a conductor 205 that includes the conductor 205a and the conductor 205b and has a flat upper surface (see FIGS. 2A to 2D). Note that the CMP process may remove a portion of the insulator 216.

[0222] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0223] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or other methods. Films formed by ALD have good coverage. On the other hand, sputtering is preferable because it can form films with a lower hydrogen concentration than other methods. The method should be selected based on the characteristics required for the device.

[0224] Next, the insulator 224 is deposited over the insulator 222. The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is deposited as the insulator 224 by a sputtering method. Alternatively, a silicon oxide film or a silicon oxynitride film may be deposited by a CVD method.

[0225] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by another heat treatment in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0226] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the formation of the insulator 224. By this heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed.

[0227] Alternatively, the heat treatment can be performed after the formation of the insulator 222. The heat treatment can be performed under the above-described heat treatment conditions.

[0228] Here, to incorporate a large amount of oxygen into the insulator 224, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use, for example, an apparatus having a power supply that generates high-density plasma using microwaves. Alternatively, a power supply that applies RF (radio frequency) to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not necessary.

[0229] Next, an oxide film 230A is formed on the insulator 224 (see FIGS. 2A to 2D).

[0230] The oxide film 230A can be formed by sputtering, CVD, MBE, PLD, ALD, etc. The thickness of the oxide film 230A is 40 nm to 400 nm, preferably 60 nm to 200 nm, and more preferably 75 nm to 160 nm.

[0231] For example, when the oxide film 230A is formed by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. When the oxide film 230A is formed by sputtering, for example, an In-M-Zn oxide target can be used.

[0232] In particular, it is preferable that the oxide film 230A contains as much oxygen as possible. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A should be 70% or more, preferably 80% or more, and more preferably 100%.

[0233] On the other hand, when the oxide film 230A is an oxygen-deficient oxide semiconductor, the oxide film 230A may be formed by setting the ratio of oxygen contained in the sputtering gas to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can achieve relatively high field-effect mobility.

[0234] Furthermore, when the oxide film 230A is formed by the ALD method, a precursor containing In, a precursor containing M, and a precursor containing Zn can be used. Alternatively, a precursor containing two or more of In, M, and Zn may be used. The oxide film 230A may be formed by sequentially or simultaneously introducing the precursors into a reaction chamber containing a substrate, followed by repeating the step of introducing an oxidizing agent, or by repeating the step of alternately introducing each precursor and the oxidizing agent.

[0235] In this embodiment, the oxide film 230A can be formed by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1, 5:1:6, 5:1:3, 10:1:3, or 1:1:1 (all atomic ratios), or a target such as In-Zn oxide or indium oxide. Each oxide film can be formed according to the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0236] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as hydrogen and water from the oxide film 230A. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for 1 hour, followed by another heat treatment in an oxygen atmosphere at 400°C for 1 hour.

[0237] Next, masks 232 (mask 232a and mask 232b) are formed on the oxide film 230A (see FIGS. 2A to 2D). Mask 232a is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining the above metal elements. For example, mask 232a is preferably made of tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Mask 232a can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0238] Alternatively, the mask 232a may be an insulator containing carbon, or may have a layered structure including a material containing the metal element and an insulator containing carbon on the material containing the metal element.

[0239] A resist mask can be used as the mask 232b.

[0240] The mask 232a and the mask 232b may be formed by lithography.

[0241] In the lithography method, first, a resist is formed on a film containing a material that will become the mask 232a, and the resist is exposed through the mask. Next, the exposed region is removed or left using a developer to form the mask 232b, which is a resist mask. Next, the film containing the material that will become the mask 232a is etched through the mask 232b to form the mask 232a. Dry etching or wet etching can be used to form the mask 232a. Dry etching is suitable for microfabrication. The mask 232b can be formed by exposing the resist to, for example, KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Instead of the light described above, an electron beam or ion beam can also be used. When using an electron beam or ion beam, writing is performed directly on the resist, eliminating the need for the resist exposure mask described above. The mask 232b can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0242] Next, the oxide film 230A is etched using the mask 232 to form the oxide 230B (see FIGS. 3A to 3D). The oxide 230B may be formed after removing the mask 232b, or may be formed while leaving the mask 232b in place. In the latter case, the mask 232b may be lost during etching. Also, part of the insulator 224 may be removed during this processing. After etching the oxide film 230A, the mask 232a is removed by etching.

[0243] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high density plasma source.

[0244] Here, the oxide 230B is formed so that at least a portion thereof overlaps the conductor 205. In addition, it is preferable that the side surface of the oxide 230B has a tapered shape with respect to the upper surface of the insulator 222 or the upper surface of the substrate. By having the side surface of the oxide 230B have a tapered shape with respect to the upper surface of the insulator 222 or the upper surface of the substrate, it is possible to easily form a film on the side surface of the oxide 230B or remove a film formed on the side surface in a later process.

[0245] Furthermore, the oxide 230B has a curved surface between its side surface and top surface. In other words, the edges of the side surface and the top surface are preferably curved (hereinafter also referred to as rounded). The curved surface has a radius of curvature of, for example, 3 nm to 10 nm, preferably 5 nm to 6 nm, at the edge of the oxide 230B. The lack of corners at the edge improves film coverage in the subsequent film formation process.

[0246] The oxide film 230A can be processed by dry etching or wet etching using the mask 232. Dry etching is suitable for fine processing.

[0247] Furthermore, by performing the above-mentioned dry etching or other processes, impurities resulting from the etching gas or the like may adhere to or diffuse into the side surfaces or interior of the oxide 230B, etc. Examples of impurities include fluorine and chlorine.

[0248] Cleaning is performed to remove the above-mentioned impurities, etc. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0249] As the wet cleaning, cleaning treatment may be performed using an aqueous solution of oxalic acid, phosphoric acid, hydrogen peroxide, or hydrofluoric acid diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning may be performed using the above aqueous solution, pure water, or carbonated water. In this embodiment, ultrasonic cleaning is performed using an aqueous solution of hydrofluoric acid diluted with pure water.

[0250] Subsequently, a heat treatment may be carried out under the conditions described above.

[0251] Next, the insulator 272 is formed on the insulator 224 and the oxide 230B (see FIGS. 4A to 4D). The insulator 272 preferably has barrier properties, and may be formed using an insulator containing a metal oxide such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tungsten oxide, titanium oxide, tantalum oxide, or nickel oxide, or silicon nitride oxide or silicon nitride. An oxide containing aluminum and hafnium (hafnium aluminate) may be used as an insulator containing both aluminum and hafnium. Alternatively, a metal oxide such as indium-gallium-zinc oxide with a reduced In concentration or a metal oxide not containing In may be used. The insulator 272 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0252] The insulator 272 may also have a laminated structure of two or more layers. In this case, each layer of the insulator 272 may be made of a different material. The layers of the insulator 272 may also be formed by different methods. For example, the lower layer of the insulator 272 may be made of aluminum oxide formed by a sputtering method, and the upper layer of the insulator 272 may be made of aluminum oxide formed by an ALD method.

[0253] Next, the insulator 280 is formed on the insulator 272 (see FIGS. 5A to 5D). The insulator 280 preferably has a low dielectric constant. For example, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resin. Silicon oxide and silicon oxynitride are also preferable because they are thermally stable. The insulator 280 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Alternatively, it can be formed by spin coating, dipping, droplet discharging (such as inkjet printing), printing (such as screen printing or offset printing), doctor knife, roll coater, or curtain coater.

[0254] The insulator 280 may have a laminated structure of two or more layers. In this case, the layers of the insulator 280 may be made of different materials. The layers of the insulator 280 may be formed by different methods.

[0255] In this embodiment, a silicon oxide film is formed by sputtering as the lower layer of the insulator 280, and a silicon oxynitride film is formed by CVD as the upper layer of the insulator 280. Using a sputtering method to form the lower layer of the insulator 280 is preferable because it can reduce the hydrogen concentration in the insulator 280. Also, using a CVD method to form the upper layer of the insulator 280 is preferable because it can form the insulator 280 with good coverage.

[0256] It is preferable that the insulator 280 be formed so that its upper surface is flat. For example, the insulator 280 may have a flat upper surface immediately after deposition. Alternatively, for example, the insulator 280 may be made flat by removing the insulator or the like from its upper surface after deposition so that it is parallel to a reference plane such as the rear surface of the substrate. This type of process is called a planarization process, and the resulting film may be called a planarized film. Examples of planarization processes include CMP and dry etching. In this embodiment, CMP is used as the planarization process. However, the upper surface of the insulator 280 does not necessarily have to be flat.

[0257] Next, the insulator 280 is processed to form an opening 245 so as to have at least a region overlapping with the conductor 205 (see FIGS. 6A to 6D). To form the opening, a resist mask or a hard mask can be used, and wet etching or dry etching can be used. However, dry etching is preferable because it allows for fine processing and allows the side surface of the insulator 280 to be processed approximately vertically. Furthermore, in processing the insulator 280, it is preferable that the insulator 272 functions as an etching stopper.

[0258] Next, processing is performed on the insulator 272 in the opening 245 (see FIGS. 7A to 7D). Since the insulator 272 on the side surface of the oxide 230B needs to be removed during this processing, it is preferable to use wet etching or plasma etching, which allows isotropic etching. This processing exposes the top and side surfaces of the oxide 230B and a portion of the surface of the insulator 224. This processing may also etch a portion of the insulator 224, thinning the insulator 224 or exposing a portion of the insulator 222. If a hard mask is used during this processing, it is preferable to also remove the hard mask during this processing. On the other hand, the hard mask may remain on the insulator 280. In this case, it can be removed during a subsequent polishing process of the conductor 260, etc.

[0259] Next, the oxide 230B in the opening 245 is processed to form the oxide 230a (see FIGS. 8A to 8D). This processing can be performed by wet etching or dry etching. However, since this processing requires anisotropic etching of the oxide 230B and control of the thickness of the oxide 230a after processing, dry etching, which has excellent processing controllability, is preferred. As shown in FIG. 8B, this processing results in the formation of an oxide 230a having a recess. The thickness of the oxide 230a in the opening 245 is 5 nm to 100 nm, preferably 10 nm to 50 nm, and more preferably 15 nm to 30 nm. Furthermore, this processing may etch a portion of the insulator 224, thinning the insulator 224 or exposing a portion of the insulator 222.

[0260] The conductor 260 formed in a later step is disposed in a self-aligned manner within the opening 245, that is, within the recess of the oxide 230a.

[0261] Here, it is preferable to perform heat treatment. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere. The heat treatment may also be performed in an atmosphere containing oxygen. For example, the heat treatment may be performed in an atmosphere containing oxygen in addition to nitrogen or an inert gas. The heat treatment may also be performed under reduced pressure. For example, the heat treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour.

[0262] The heat treatment can remove impurities such as hydrogen and water contained in the oxide 230a. It can also repair damage caused to the oxide 230a by dry etching in the above-mentioned process. Furthermore, if the heat treatment is performed in an oxygen-containing atmosphere, oxygen can be added to the oxide 230a. Furthermore, the heat treatment can cause oxygen contained in the insulator 224 to diffuse into the oxide 230a.

[0263] Alternatively, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C.

[0264] Next, in the opening 245, an oxide film 230bA is formed on the insulator 280 so as to have regions in contact with the side surface of the insulator 224, the lower surface and side surface of the oxide 230a, the side surface of the insulator 272, and the side surface of the insulator 280 (see FIGS. 9A to 9D). Note that FIG. 9C shows an example in which the oxide film 230bA is formed so as to be in contact with the insulator 222, but this embodiment is not limited to this. If the insulator 224 is not removed even in regions that do not overlap with the oxide 230a during the formation of the oxide 230a, the oxide film 230bA is formed so as to be in contact with the surface of the insulator 224.

[0265] The oxide film 230bA can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230bA may be formed using a film formation method similar to that of the oxide film 230A, depending on the characteristics desired for the oxide 230b. In this embodiment, the oxide film 230bA can be formed by a sputtering method using a target having an In:Ga:Zn ratio of 4:2:4.1 or 1:3:4 (both atomic ratios).

[0266] The oxide film 230bA may be a laminated film. For example, a sputtering method may be used to deposit an oxide film that will be the lower layer of the oxide 230b using a target with an atomic ratio of In:Ga:Zn=4:2:4.1, and then a sputtering method may be used to deposit an oxide film that will be the upper layer of the oxide 230b using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0267] Subsequently, an insulator 250A is formed on the oxide film 230bA (see FIGS. 9A to 9D).

[0268] The insulator 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable to form a silicon oxynitride film as the insulator 250A by CVD. The film formation temperature for forming the insulator 250A is preferably 350°C or higher and lower than 450°C, particularly around 400°C. By forming the insulator 250A at 400°C, an insulator with fewer impurities can be formed.

[0269] It should be noted that oxygen can be introduced into the insulator 250A by exciting oxygen with microwaves to generate high-density oxygen plasma and exposing the insulator 250A to the oxygen plasma.

[0270] Heat treatment may also be performed under the above-described conditions. The heat treatment can reduce the moisture concentration and hydrogen concentration of the insulator 250A.

[0271] Next, a conductive film 260aA and a conductive film 260bA are sequentially formed (see FIGS. 9A to 9D). The conductive film 260aA and the conductive film 260bA can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Titanium nitride may be formed as the conductive film 260aA, and tungsten may be formed as the conductive film 260bA.

[0272] The conductive film 260aA may be formed of a metal nitride by a CVD method or a sputtering method. By using a metal nitride for the conductive film 260aA, it is possible to prevent the conductive film 260bA from being oxidized by oxygen contained in the insulator 250A and thereby prevent a decrease in conductivity.

[0273] Furthermore, by stacking a low-resistance metal film as the conductive film 260bA, a transistor with a low driving voltage can be provided.

[0274] Subsequently, a heat treatment can be performed. The heat treatment can be performed under the above-mentioned heat treatment conditions. Note that there are cases where the heat treatment is not necessary.

[0275] Next, the conductive film 260bA, the conductive film 260aA, the insulator 250A, and the oxide film 230bA are polished until the insulator 280 is exposed, thereby forming the conductor 260aB, the conductor 260bB, the insulator 250B, and the oxide 230bB (see FIGS. 10A to 10D). The polishing can be performed using a CMP method. This polishing allows the top surfaces of the conductor 260aB, the conductor 260bB, the insulator 250B, and the oxide 230bB to be roughly flush with the top surface of the insulator 280.

[0276] Next, the conductor 260aB, the conductor 260bB, the insulator 250B, and the oxide 230bB are processed so that their upper surfaces are lower than the upper surface of the oxide 230a, thereby forming the conductor 260, the insulator 250, and the oxide 230b having the conductor 260a and the conductor 260b (see FIGS. 11A to 11D). This processing can be performed by wet etching or dry etching. However, this processing requires anisotropic etching of the conductor 260aB, the conductor 260bB, the insulator 250B, and the oxide 230bB, and requires control of the film thickness of the conductor 260, the insulator 250, and the oxide 230b after processing. Therefore, dry etching, which has excellent controllability during processing, is preferable. The thickness of the conductor 260 overlapping the oxide 230a in the opening 245 is 20 nm or more and 200 nm or less, preferably 30 nm or more and 150 nm or less, and more preferably 40 nm or more and 80 nm or less.

[0277] At this time, the conductor 260 is formed so that at least a portion thereof overlaps with the conductor 205 and the oxide 230a. The width of the conductor 260 in the channel length direction (also referred to as the gate length) is determined by the width of the opening 245 provided in the oxide 230a, the thickness of the oxide 230b, and the thickness of the insulator 250. The above width and thickness can be adjusted depending on the performance required for the transistor 200 or the semiconductor device, and the conductor 260 having a desired width can be formed.

[0278] In this way, the conductor 260 is formed so as to be embedded in the opening 245. The formation of the conductor 260 is performed in a self-aligned manner without using lithography, so there is no need to provide a margin for aligning the conductor 260. This reduces the area occupied by the transistor 200, enabling miniaturization and high integration of semiconductor devices. Furthermore, since the lithography process is no longer necessary, improved productivity is expected due to process simplification.

[0279] Furthermore, when miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 260 does not decrease. If the film thickness of the conductor 260 is increased for this purpose, the conductor 260 may have a shape with a high aspect ratio. In this embodiment, the conductor 260 is provided so as to be embedded in the opening 245, and therefore, even if the conductor 260 has a shape with a high aspect ratio, the conductor 260 can be formed without collapsing during the process.

[0280] Next, an insulating film 262A is formed so as to cover the conductor 260, the insulator 250, the oxide 230b, and the insulator 280 (see FIGS. 12A to 12D). In particular, the insulating film 262A is preferably provided so as to contact the upper surfaces of the conductor 260, the insulator 250, and the oxide 230b within the opening 245. The insulating film 262A is preferably an insulating barrier film, and for example, hafnium oxide, silicon nitride, or the like can be used as the insulating film 262A. Alternatively, aluminum oxide may be used as the insulating film 262A. The insulating film 262A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0281] Next, the insulating film 262A is polished until the insulator 272 is exposed, forming the insulator 262 (see FIGS. 13A to 13D). The polishing can be performed by CMP. Preferably, the polishing results in the upper surface of the insulator 262 roughly matching the upper surfaces of the insulators 272 and 280. Furthermore, the polishing results in the opening 245 being filled with the conductor 260, the insulator 250, the oxide 230b, and the insulator 262 formed on the conductor 260, the insulator 250, and the oxide 230b. The thickness of the insulator 262 overlapping the conductor 260 in the opening 245 is 10 nm to 100 nm, preferably 20 nm to 50 nm. However, the thickness of the insulator 262 is not limited to the above, as long as it functions as an etching stopper in a subsequent etching process.

[0282] The polishing does not necessarily have to be performed until the insulator 272 is exposed. It is sufficient to perform the polishing until at least the insulating film 262A on the insulator 280 disappears and the insulator 280 is exposed. Alternatively, the polishing may be performed until the insulator 272 disappears and the oxide 230a is exposed.

[0283] Next, an insulator 281 is formed over the insulators 272 and 280 (see FIGS. 14A to 14D). The insulator 281 can be formed using the same apparatus and material as the insulator 280. For example, the insulator 281 containing silicon oxynitride is formed using a CVD method.

[0284] Next, the insulators 281, 272, and 280 are processed using lithography to form openings 290 that expose the oxide 230a (see FIGS. 15A to 15D).

[0285] Next, an insulating film 241A is formed in the opening 290 and on the insulator 281 (see FIGS. 16A to 16D). The insulating film 241A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 241A, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form a film of aluminum oxide or silicon nitride by the ALD method.

[0286] Next, the insulating film 241A is anisotropically etched to form the insulator 241 (insulators 241a, 241b, and 241c) (see FIGS. 17A to 17D). The anisotropic etching may be performed, for example, by dry etching. At this time, it is preferable to use conditions under which the etching rate of the insulator 262 is slower than that of the insulating film 241A. It is also preferable that the insulator 262 and the insulating film 241A are made of different materials. On the other hand, if the thickness of the insulator 262 is sufficiently large so that the conductor 260 is not exposed by the formation of the insulator 241, this is not limited to the above. In that case, the insulator 262 and the insulating film 241A may be made of the same material. By configuring the sidewall of the opening 290 in this way, it is possible to suppress the penetration of oxygen from the outside and to suppress the diffusion of oxygen into the oxide 243 to be formed next and the conductor 240. On the other hand, if oxygen does not diffuse into the oxide 243 and the conductor 240 within the opening 290, or if the diffusion of oxygen into the oxide 243 and the conductor 240 has little or no effect on the characteristics of the semiconductor device, it is not necessarily necessary to provide the insulator 241.

[0287] Next, an oxide film 243A is formed (see FIGS. 18A to 18D). The oxide film 243A can be formed using a material that can be used for the oxide film 230A. The oxide film 243A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0288] Next, a conductive film 240A is formed (see FIGS. 18A to 18D). The conductive film 240A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A conductive material containing tungsten, copper, or aluminum as a main component can be used for the conductive film 240A. The conductive film 240A may also have a stacked structure. For example, the conductive film 240A may have a structure including a first conductive film containing tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, and a second conductive film on the first conductive film containing a conductive material containing tungsten, copper, or aluminum as a main component.

[0289] The oxide film 243A is preferably made of a low-resistance material or a material whose resistance decreases when it comes into contact with the conductive film 240A. A material whose resistance decreases when it comes into contact with the conductive film 240A refers to one or both of a material whose resistance decreases when it absorbs impurities such as hydrogen contained in the conductive film 240A and a material whose resistance decreases when oxygen is extracted by the conductive film 240A. Examples of such materials include metal oxides formed using a target with an In:Ga:Zn ratio of 4:2:4.1, 5:1:6, 5:1:3, 10:1:3, or 1:1:1 (all atomic ratios), as well as metal oxides such as In-Zn oxide, indium oxide, and indium tin oxide. Furthermore, using the same material for the oxide film 243A as the oxide 230a is preferable because it can suppress an increase in contact resistance.

[0290] Next, a CMP process is performed to remove the layer above the insulator 281, thereby forming the oxide 243 and the conductor 240. Here, it is preferable that the insulator 281 functions as a stopper against the CMP process of the conductive film 240A and the oxide film 243A. Note that the CMP process may remove a portion of the insulator 281.

[0291] Through the above steps, a semiconductor device including the transistor 200 shown in FIGS. 1A to 1D can be manufactured.

[0292] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0293] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0294] <Semiconductor Device Modification 1> Below, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from the above <Structure example of a semiconductor device>, will be described with reference to FIGS. 19A to 19D.

[0295] In the semiconductor device shown in Figures 19A to 19D, structures having the same functions as the structures constituting the semiconductor device shown in <Configuration example of semiconductor device> (see Figures 1A to 1D) are denoted by the same reference numerals.

[0296] 19A to 19D, the structure of the transistor 200 can be the same as that described in detail in <Structural Examples of Semiconductor Device>.

[0297] In the semiconductor device (see FIGS. 1A to 1D) shown above in <Configuration Example of Semiconductor Device>, the transistor 200 has two transistors (transistor 200a and transistor 200b) in one semiconductor layer, but the present invention is not limited to this. As shown in FIGS. 19A to 19D, the transistor 200 may have one transistor (transistor 200a) in one semiconductor layer.

[0298] At this time, one of the source and drain of the transistor 200a is electrically connected to the conductor 240a through an oxide 243a, and the other of the source and drain of the transistor 200a is electrically connected to the conductor 240b through an oxide 243b.

[0299] One of the source and drain of the transistor 200a is electrically connected to the conductor 240a through the oxide 243a provided on the bottom and side surfaces of the conductor 240a, thereby achieving good electrical connection with the conductor 240a. The other of the source and drain of the transistor 200b is electrically connected to the conductor 240b through the oxide 243b provided on the bottom and side surfaces of the conductor 240b, thereby achieving good electrical connection with the conductor 240b.

[0300] For example, by providing a conductor that functions as a bit line electrically connected to the conductor 240a and providing a capacitor electrically connected to the conductor 240b, a semiconductor device including the transistor 200a can function as a memory device.

[0301] <Storage device> A memory device can be configured using a semiconductor device including the transistor 200 and the capacitor 100 electrically connected to the transistor 200 as a memory cell 600. Figures 20A, 20B, and 21A to 21C are top views and cross-sectional views of a memory device and its periphery according to one embodiment of the present invention.

[0302] FIG. 20A is a top view of the memory device. Also, FIGS. 20B and 21A to 21C are cross-sectional views of the memory device. Here, FIG. 20B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 20A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Also, FIG. 21A is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 20A, and is a cross-sectional view of the channel formation region in the direction in which the conductor 260 extends. Note that FIG. 21A represents a cross-section of the transistor 200 in the channel width direction. Also, FIG. 21B is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 20A. Also, FIG. 21C is a cross-sectional view of the portion indicated by the dashed-dotted line A7-A8 in FIG. 20A. Note that in the top view of FIG. 20A, some elements are omitted for clarity.

[0303] As shown in FIG. 20B, an insulator 282 is provided on the conductor 240, the oxide 243, the insulator 241, and the insulator 281, and a conductor 246 is provided so as to be embedded in the insulator 282. The conductor 246 is electrically connected to the conductor 240a and can function as a wiring BL, which will be described later. An insulator 283 is provided on the insulator 282 and the conductor 246, and a conductor 247 is provided so as to be embedded in the insulators 282 and 283. In FIG. 20B, two conductors 247 are provided and are electrically connected to the conductors 240b and 240c, respectively. The capacitors 100a and 100b are provided on the conductor 247 and the insulator 283, and are electrically connected to the conductors 240b and 240c, respectively, via the conductor 247. An insulator 284 is provided over the insulator 283 so as to cover the capacitor 100a and the capacitor 100b.

[0304] The insulators 282, 283, and 284 can be made of the same materials as those used for the insulators 216, 280, and 281. The conductors 246 and 247 can be made of the same materials as those used for the conductors 205, 260, and 240. The conductors 246 and 247 may have a layered structure. For example, the conductors 246 and 247 may have a layered structure of a conductive material containing titanium, titanium nitride, tantalum, or tantalum nitride as a main component and a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 246 and 247 may have a single-layer structure or a layered structure of three or more layers.

[0305] [Capacitor element 100] As shown in FIGS. 20B and 21C, the capacitor 100a is provided to have a region overlapping with the transistor 200a. Similarly, the capacitor 100b is provided to have a region overlapping with the transistor 200b. FIG. 21C is a cross-sectional view of the portion indicated by the dashed dotted line A7-A8 in FIG. 20A, illustrating a connection between the capacitor 100a and the conductor 240a. FIG. 21C illustrates an example in which the capacitor 100a is electrically connected to the conductor 240a through the conductor 247. The capacitor 100b has a structure corresponding to that of the capacitor 100a. Hereinafter, the capacitors 100a and 100b will be referred to as the capacitor 100, and their detailed structures will be described. Unless otherwise specified, the description of the capacitor 100 can be referred to for the capacitors 100a and 100b.

[0306] The capacitor 100 includes a conductor 110, an insulator 130, and a conductor 120 on the insulator 130.

[0307] The capacitance element 100 is configured such that a conductor 110 that functions as a lower electrode (sometimes called a first terminal) and a conductor 120 that functions as an upper electrode (sometimes called a second terminal) face each other across an insulator 130 that functions as a dielectric.

[0308] The capacitor 100 is provided above the transistor 200 so that the conductor 110 is electrically connected to a conductor 240 included in the transistor 200 .

[0309] An insulator 282 is provided on the conductor 240, the oxide 243, the insulator 241, and the insulator 281, an insulator 283 is provided on the insulator 282, and a conductor 247 is provided so as to be embedded in the insulators 282 and 283. The conductor 110 is provided on the conductor 247 and the insulator 283 so as to be electrically connected to the conductor 247.

[0310] The insulator 130 is provided on the insulator 283 so as to cover the conductor 110 .

[0311] The conductor 120 is provided on the insulator 130 and is provided so as to cover at least the top surface and side surfaces of the conductor 110 via the insulator 130. As shown in FIGS. 20B and 21C, the conductor 110 has a bottom surface that is in direct contact with the conductor 247 and side surfaces that are formed into a cylindrical shape. The conductor 120 is provided so as to cover the inside and outside of the cylindrical conductor 110 via the insulator 130, thereby forming the capacitance element 100. By providing the conductor 120 on the inside and outside of the conductor 110 in the capacitance element 100, the inside and outside of the conductor 110 can be used as capacitance.

[0312] The capacitor 100 has a configuration in which an upper electrode and a lower electrode face each other across a dielectric not only on the bottom surface of the conductor 110 but also on the side surface, allowing for a larger capacitance per unit area. Therefore, the higher the height of the conductor 110, the larger the capacitance of the capacitor 100. Furthermore, because the inner and outer side surfaces of the cylindrically formed conductor 110 are used for capacitance, the height of the conductor 110 can be reduced compared to when only the inner or outer side of the conductor 110 is used to form capacitance, and the conductor 110 and the capacitor 100 can be easily formed. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization and high integration of semiconductor devices.

[0313] Conductor 110 and conductor 120 may be any conductor that can be used for conductor 205, conductor 260, or conductor 240. Conductor 110 and conductor 120 are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above metal element or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0314] The conductor 110 or 120 may have a layered structure. For example, the conductor 110 or 120 may have a layered structure of a conductive material mainly composed of titanium, titanium nitride, tantalum, or tantalum nitride, and a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 110 or 120 may have a single-layer structure or a layered structure of three or more layers. The conductor 120 can be used as a common upper electrode for adjacent capacitor elements 100. The conductor 120 can also function as a wiring CAL, which will be described later.

[0315] Furthermore, it is preferable to use an insulator with a large dielectric constant for the insulator 130. For example, an insulator containing oxides of one or both of aluminum and hafnium can be used. As the insulator containing oxides of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), or the like.

[0316] The insulator 130 may also have a stacked structure, for example, a stacked structure of two or more layers selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). For example, it is preferable to form a stacked structure by sequentially depositing hafnium oxide, aluminum oxide, and hafnium oxide by ALD. The thicknesses of the hafnium oxide and aluminum oxide are each 0.5 nm to 5 nm. Such a stacked structure allows the capacitor element 100 to have a large capacitance value and a small leakage current.

[0317] <Configuration example of memory cell 600> 22 to 24 illustrate examples of the configuration of the memory cell 600. FIG.

[0318] 22 and 23 are top views showing layout examples of a memory cell 600, and FIG. 24 shows a circuit configuration example of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell having one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 600 shown in FIGS. 22 to 24 includes two memory cells, one of which includes a transistor 200a and a capacitor 100a, and the other of which includes a transistor 200b and a capacitor 100b. Note that the transistor 200a and the transistor 200b each have a gate (sometimes referred to as a front gate) and a back gate. The memory cells 600 are arranged in a matrix to form a memory cell array.

[0319] 22 and 23 show an example in which the angle between the channel length direction (also referred to as the long axis direction of the oxide 230a, or the direction connecting the conductor 240a and the conductor 240b, or the conductor 240c) of the transistor 200a and the transistor 200b included in the memory cell 600 and the direction in which the wiring BL extends is greater than zero and less than 90°. In this case, the angle between the channel length direction of the transistor 200a and the transistor 200b and the direction in which the wiring WL extends is greater than zero and less than 90°. In other words, the channel length direction of the transistor 200a and the transistor 200b is neither parallel nor perpendicular to the direction in which the wiring BL and the wiring WL extend.

[0320] 22 shows an example in which the channel length directions of the transistors 200a and 200b are parallel to each other in all memory cells 600 in the memory cell array, but this embodiment is not limited to this. As shown in FIG. 23, in the memory cell array, the channel length directions of the transistors 200a and 200b in at least one memory cell 600 may be different from the channel length directions of the transistors 200a and 200b in the other memory cells 600. FIG. 23 shows an example in which the channel length directions of the transistors 200a and 200b in the memory cells 600 differ for each column. In particular, adjacent memory cells 600 in the row direction are arranged so as to be line-symmetrical with respect to the column direction, i.e., the direction in which the wiring WL extends.

[0321] The first terminal of the transistor 200a is connected to the first terminal of the capacitor 100a, the first terminal of the transistor 200b is connected to the first terminal of the capacitor 100b, the second terminal of the transistor 200a and the second terminal of the transistor 200b are connected to the wiring BL, the gate of the transistor 200a and the gate of the transistor 200b are connected to different wirings WL, and the back gate of the transistor 200a and the back gate of the transistor 200b are connected to different wirings BG. The second terminal of the capacitor 100a and the second terminal of the capacitor 100b are each connected to the wiring CAL. The first terminal of the transistor 200 functions as one of the source and drain, and the second terminal functions as the other of the source and drain.

[0322] Here, the second terminal of the capacitor 100a and the second terminal of the capacitor 100b may be electrically connected to a common wiring CAL or may be electrically connected to different wirings CAL. When the second terminal of the capacitor 100a and the second terminal of the capacitor 100b are electrically connected to different wirings CAL, the wirings CAL may be supplied with the same potential or different potentials.

[0323] The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor 100a and the second terminal of the capacitor 100b. When writing and reading data, a low-level potential is preferably applied to the wiring CAL. The wiring BG functions as a wiring for applying a potential to the back gate of the transistor 200a or the transistor 200b. By applying an arbitrary potential to the wiring BG, the threshold voltage of the transistor 200a or the transistor 200b can be increased or decreased.

[0324] The memory cell 600 is not limited to that shown in FIG. 24, and the circuit configuration can be changed. For example, the memory cell 600 may be configured such that the transistors 200a and 200b do not have back gates. In this case, the wiring BG can be omitted. The wiring BG can be appropriately selected according to the characteristics required for the memory cell or the memory cell array.

[0325] By using OS transistors as the transistors 200a and 200b in the memory cell 600, the leakage current of the transistors 200a and 200b can be significantly reduced. That is, written data can be held for a long time by the transistors 200a and 200b, reducing the frequency of refreshing the memory cell. Furthermore, refreshing the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 600.

[0326] <Modification of memory cell 600> Although the above example shows the memory cell 600 having two transistors and two capacitors, this embodiment is not limited to this. The memory cell 600 may have one transistor and one capacitor. Alternatively, the memory cell 600 may have three or more transistors and three or more capacitors.

[0327] 19A to 19D can be used as the memory cell 600. The memory cell can be configured by electrically connecting the conductor 246 functioning as a bit line to the conductor 240a of the transistor 200 shown in FIGS. 19A to 19D and electrically connecting the capacitor 100 to the conductor 240b via the conductor 247.

[0328] 25A and 25B show an example in which a memory cell 600 includes three or more transistors and three or more capacitors. The memory cell 600 shown in FIGS. 25A and 25B includes a plurality of transistors 200a, 200b, and capacitors 100a and 100b. Here, a pair of transistors 200a and 200b sandwiching a wiring BL therebetween, and the capacitors 100a and 100b electrically connected to the transistors 200a and 200b, respectively, are collectively referred to as a memory unit 602. The memory cell 600 shown in FIGS. 25A and 25B includes n memory units (memory units 602_1 to 602_n) (n is an integer greater than or equal to 2). 25A and 25B includes 2n transistors 200 and 2n capacitors 100. The memory units 602_1 to 602_n include a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b (transistors 200a_1 to 200a_n, transistors 200b_1 to 200b_n, capacitors 100a_1 to 100a_n, and capacitors 100b_1 to 100b_n), respectively. That is, the memory cell 600 shown in FIGS. 25A and 25B includes 2n transistors 200 and 2n capacitors 100.

[0329] The transistor 200a and the transistor 200b included in each memory unit 602 are electrically connected to a common wiring BL. Each memory unit 602 may be electrically connected to the common wiring BL or may be electrically connected to an electrically independent wiring BL.

[0330] It is preferable to provide a conductor 207 and a conductor 264 between each memory unit 602. By controlling the voltages applied to the conductor 207 and the conductor 264, it is possible to suppress the flow of current (also called leakage current) between adjacent memory units 602 in the memory cell 600. The conductor 207 and the conductor 264 can be manufactured in the manufacturing process of the conductor 205 and the conductor 260, respectively.

[0331] <Storage device configuration example> 26 shows an example of the configuration of an OS memory device. The memory device 1400 includes a memory cell array 1470 and peripheral circuits. The peripheral circuits include a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. The peripheral circuits may also include a back-gate control circuit 1425 that controls the potential applied to the back-gate of the transistor 200. The back-gate control circuit 1425 can be considered as part of the row circuit 1420.

[0332] The column circuit 1430 includes, for example, a column decoder 1431, a precharge circuit 1432, a sense amplifier 1433, and a write circuit 1434. The precharge circuit 1432 has a function of precharging wiring. The sense amplifier 1433 has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via an output circuit 1440. The row circuit 1420 includes, for example, a row decoder 1421, a word line driver circuit 1422, and the like, and can select a row to access.

[0333] The memory device 1400 is supplied with power supply voltages from the outside, including a low power supply voltage (VSS), a high power supply voltage (VDD) for peripheral circuits, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder 1421 and a column decoder 1431, and WDATA is input to a write circuit 1434.

[0334] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0335] The memory cell array 1470 has a plurality of memory cells 600 arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells 600, the number of memory cells 600 in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells 600, the number of memory cells 600 in one row, etc.

[0336] 26 shows an example in which the memory cell array 1470 and the peripheral circuit are formed on the same plane, but this embodiment is not limited to this. For example, the memory cell array 1470 may be provided so as to overlap the peripheral circuit or at least a part thereof. In this case, the peripheral circuit or at least a part thereof is preferably formed using an OS transistor having an oxide semiconductor or a silicon transistor. That is, a structure in which an OS transistor is stacked on an OS transistor or a structure in which an OS transistor is stacked on a silicon transistor is preferable. For example, a structure in which the memory cell array 1470 formed using OS transistors is stacked on a sense amplifier formed using silicon transistors may be provided so that the sense amplifier and the memory cell array 1470 have overlapping regions.

[0337] 27 shows an example in which a memory cell 600 including a transistor 200 and a capacitor 100 is provided above a transistor 300. The memory cell 600 can be considered to be part of a memory cell array 1470, and the transistor 300 can be considered to be part of a peripheral circuit, for example, a sense amplifier.

[0338] 27 , a wiring 1001 is electrically connected to the source of the transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The other of the source and drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100. Alternatively, the wiring 1003 may be electrically connected to the wiring 1001, the wiring 1002, or the wiring 1007.

[0339] [Transistor 300] The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions.

[0340] Here, an insulator 315 is disposed over the semiconductor region 313, and a conductor 316 is disposed over the insulator 315. The transistors 300 formed in the same layer are electrically isolated by an insulator 312 that functions as an element isolation insulating layer. The insulator 312 can be an insulator similar to the insulator 326 described later. The transistor 300 may be either a p-channel type or an n-channel type.

[0341] The substrate 311 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single-crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b. Alternatively, the substrate 311 may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0342] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0343] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0344] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0345] Here, in the transistor 300 shown in FIG. 27, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Such a transistor 300 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0346] Note that the transistor 300 shown in FIG. 27 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0347] 27, the semiconductor device has a transistor 300 and a transistor 200 stacked one on top of the other. For example, the transistor 300 can be made of a silicon-based semiconductor material, and the transistor 200 can be made of an oxide semiconductor. In this way, the semiconductor device shown in FIG. 27 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers. The semiconductor device shown in FIG. 27 can be fabricated using the same process as a manufacturing device used for silicon-based semiconductor materials, and can also be highly integrated.

[0348] [Wiring layer] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0349] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the wiring 1001, the wiring 1002, the wiring 1007, and the like are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductors 328 and 330 function as plugs or wirings.

[0350] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to enhance flatness.

[0351] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 27, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring. For example, as shown in FIG. 27, the conductor 356 can function as at least one of a wiring connecting the wiring 1001 and the source of the transistor 300, a wiring connecting the wiring 1002 and the drain of the transistor 300, and a wiring connecting the wiring 1007 and the gate of the transistor 300.

[0352] An insulator 360 is disposed on the insulator 354, an insulator 362 is disposed on the insulator 360, an insulator 211 is disposed on the insulator 362, and a memory cell 600 is disposed thereon.

[0353] When the transistor 300 is used as part of a sense amplifier, the wiring 1003 may be connected to at least one of the wiring 1001, the wiring 1002, and the wiring 1007. With this configuration, the distance of the wiring connecting the transistor 200 and the transistor 300 can be made shorter than when the wiring is routed above the transistor 200.

[0354] Moreover, a wiring layer may be provided on the memory cell 600 .

[0355] Insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides. For example, by using a material with a low dielectric constant as the insulator that functions as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0356] For example, the insulators 320, 322, 326, 352, 354, and 362 preferably have a low dielectric constant. For example, the insulators preferably include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulators preferably have a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of suitable resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0357] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0358] For example, the conductors 328, 330, 356, etc. can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. Using a low-resistance conductive material can reduce wiring resistance.

[0359] The above is a description of the configuration example. By using this configuration, a semiconductor device using a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[0360] 27 shows an example in which the transistor 300 in which the channel formation region is formed in the substrate 311 is provided; however, the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 28, a transistor 400 including an oxide semiconductor may be provided under the transistor 200. The semiconductor device shown in FIG. 28 has the same structure as the semiconductor device shown in FIG. 27 except that the transistor 400 is provided instead of the transistor 300.

[0361] 27, the semiconductor device shown in Fig. 28 includes, between the substrate 311 and the insulator 352, an insulator 411, an insulator 412, an insulator 414, an insulator 480, and an insulator 481, a transistor 400 formed in these layers, an oxide 443 electrically connected to the transistor 400 and functioning as a plug, a conductor 440, and an insulator 441 provided on a side surface of the oxide 443. The transistor 400 also includes an insulator 416, an insulator 422, an insulator 424, and an insulator 472 as some of its components. Here, the insulator 411 corresponds to the insulator 211, the insulator 412 corresponds to the insulator 212, the insulator 414 corresponds to the insulator 214, the insulator 416 corresponds to the insulator 216, the insulator 422 corresponds to the insulator 222, the insulator 480 corresponds to the insulator 280, the insulator 481 corresponds to the insulator 281, the transistor 400 corresponds to the transistor 200, the oxide 443 corresponds to the oxide 243, the conductor 440 corresponds to the conductor 240, and the insulator 441 corresponds to the insulator 241. Furthermore, the insulators 416, 422, 424, and 472 correspond to the insulators 216, 222, 224, and 272, respectively.

[0362] That is, the transistor 400 and the layer including the transistor 400 have a structure similar to that of the transistor 200 and the layer including the transistor 200. Therefore, the above description can be referred to for details of the transistor 400 and the layer including the transistor 400.

[0363] Note that the oxide 443, the conductor 440, and the insulator 441 are provided so as to fill openings formed in the insulator 481, the insulator 472, and the insulator 480. The oxide 443 and the conductor 440 function as a plug that connects the wiring 1001 to the source of the transistor 400 or a plug that connects the wiring 1002 to the drain of the transistor 400. The oxide 443 and the conductor 440 may also be provided as a plug that connects the wiring 1007 to the gate of the transistor 400.

[0364] Furthermore, if the memory cell array 1470 is configured to overlap the sense amplifier, the bit lines can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cells.

[0365] Note that the configurations of the peripheral circuits, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0366] 24, the second terminal of the capacitor 100a and the second terminal of the capacitor 100b, which are electrically connected to the wiring CAL, may be connected to different wirings CAL, or the second terminal of the capacitor 100a and the second terminal of the capacitor 100b may be electrically connected to a common wiring CAL. For example, the second terminal of the capacitor 100a and the second terminal of the capacitor 100b may be formed of a single conductor. Furthermore, the second terminals of the capacitors 100 included in adjacent memory cells 600 may be connected to different wirings CAL, or may be electrically connected to a common wiring CAL.

[0367] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0368] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with high design freedom can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

[0369] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0370] (Embodiment 2) 29A and 29B show an example of a chip 1200 on which a semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0371] As shown in FIG. 29A, a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0372] 29B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of the PCB 1201, which is connected to a motherboard 1203.

[0373] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. In this manner, by using a storage device including the memory cell 600 of one embodiment of the present invention as a storage device, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with high design flexibility can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[0374] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and may be used for image processing and multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-accumulate operation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0375] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0376] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0377] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0378] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0379] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0380] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0381] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0382] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0383] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0384] (Embodiment 3) This embodiment mode will describe examples of electronic components and electronic devices in which the memory device or the like described in the above embodiment mode is incorporated.

[0385] <Electronic components> First, an example of an electronic component incorporating memory device 720 will be described with reference to FIGS. 30A and 30B.

[0386] FIG. 30A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 30A has memory device 720 inside mold 711. FIG. 30A omits a portion of the interior of electronic component 700 to show it. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0387] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0388] 30B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.

[0389] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0390] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0391] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0392] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0393] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0394] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0395] A heat sink (heat dissipation plate) may be provided over the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0396] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 30B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0397] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0398] In this manner, by using a memory device including the memory cell 600 of one embodiment of the present invention as the memory device 720, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with high design freedom can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[0399] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0400] (Fourth embodiment) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 31A to 31E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0401] By using a memory device including the memory cell 600 of one embodiment of the present invention as a memory device, a semiconductor device capable of retaining data for a long period of time, a semiconductor device with high data writing speed, a semiconductor device with high design flexibility, or a semiconductor device with low power consumption can be provided.

[0402] 31A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 of the board 1104.

[0403] FIG. 31B is a schematic diagram of the appearance of an SD card, and FIG. 31C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables data to be read from and written to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113, etc.

[0404] FIG. 31D is a schematic diagram of the appearance of an SSD, and FIG. 31E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 of board 1153, etc.

[0405] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0406] (Embodiment 5) A semiconductor device according to one embodiment of the present invention can be used in a memory device, a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a memory device according to one embodiment of the present invention, a processor such as a CPU or a GPU, or a chip are shown in Figures 32A to 32H.

[0407] <Electronic devices and systems> A storage device, a processor, or a chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, and sound players. Furthermore, by providing an electronic device with a storage device, a processor, or a chip according to one embodiment of the present invention, the electronic device can be equipped with artificial intelligence.

[0408] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0409] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0410] By using a memory device including the memory cell 600 of one embodiment of the present invention as a memory device, a semiconductor device capable of retaining data for a long period of time, a semiconductor device with high data writing speed, a semiconductor device with high design flexibility, or a semiconductor device with low power consumption can be provided.

[0411] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 32A to 32H.

[0412] [Information terminal] 32A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0413] The information terminal 5100 can execute applications using artificial intelligence by applying the storage device, the processor, or the chip of one embodiment of the present invention. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, an application that recognizes characters, figures, or the like input by a user to a touch panel provided in the display unit 5102 and displays the characters, figures, or the like on the display unit 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0414] 32B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0415] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a storage device, a processor, or a chip according to one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0416] In the above description, a smartphone and a notebook information terminal are illustrated as examples of electronic devices in Figures 32A and 32B, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0417] [Game consoles] FIG. 32C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The memory device, processor, or chip described in the above embodiment can be incorporated into a memory device, processor, or chip provided on a board of the housing 5301, the housing 5302, or the housing 5303.

[0418] 32D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0419] A game machine with low power consumption can be realized by applying the storage device, processor, or chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0420] Furthermore, by applying a storage device, a processor, or a chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0421] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0422] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0423] 32C and 32D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the storage device, processor, or chip of an embodiment of the present invention is applied are not limited to these. Examples of game machines to which the storage device, processor, or chip of an embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0424] [Mainframe Computer] The storage device, processor, or chip according to one embodiment of the present invention can be applied to a large-scale computer.

[0425] 32E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 32F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0426] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the memory devices, processors, or chips described in the above embodiments can be mounted on the boards.

[0427] The supercomputer 5500 is a large-scale computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a storage device, processor, or chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the impact of heat generation on the circuit itself, peripheral circuits, and modules.

[0428] 32E and 32F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the storage device, processor, or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the storage device, processor, or chip of one embodiment of the present invention is applied include a computer that provides services (a server), a large general-purpose computer (a mainframe), etc.

[0429] [Moving object] The storage device, processor, or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0430] Fig. 32G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0431] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0432] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0433] The memory device, processor, or chip of one embodiment of the present invention can be used as a component of artificial intelligence, and therefore, for example, the chip can be used in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0434] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can also include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A storage device, processor, or chip according to one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0435] [electric appliances] 32H shows an example of the electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0436] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the storage device, processor, or chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0437] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0438] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0439] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Explanation of symbols]

[0440] 100: Capacitor, 110: Conductor, 120: Conductor, 130: Insulator, 200: Transistor, 205: Conductor, 207: Conductor, 211: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 232: Mask, 240: Conductor, 241: Insulator, 243: Oxide, 245: Opening, 246: Conductor, 247: Conductor, 250: Insulator, 260: Conductor, 262: Insulator, 264: Conductor, 272: Insulator, 280: Insulator, 281: Insulator, 282: Insulator, 283: Insulator, 284: Insulator, 290: Opening, 600: Memory cell, 602: Memory unit

Claims

1. A first oxide having a first recess and a second recess; a first insulator on the first recess; a first conductor on the first insulator; a second oxide provided between the first oxide and the first insulator; a second insulator on the first insulator, the first conductor, and the second oxide; a third insulator on the second recess; and a second conductor on the third insulator; and a third oxide provided between the first oxide and the third insulator; a fourth insulator on the third insulator, on the second conductor, and on the third oxide; the first insulator, the first conductor, the second oxide, and the second insulator are provided in the first recess; the third insulator, the second conductor, the third oxide, and the fourth insulator are provided in the second recess; the first conductor has a region facing an inner wall of the first recess with the first insulator and the second oxide interposed therebetween; the second conductor has a region facing an inner wall of the second recess with the third insulator and the third oxide interposed therebetween; the second insulator has a region in contact with an inner wall of the first recess, The fourth insulator has a region in contact with an inner wall of the second recess.

2. A first oxide having a first recess and a second recess; a first insulator on the first recess; a first conductor on the first insulator; a second oxide provided between the first oxide and the first insulator; a second insulator on the first insulator, the first conductor, and the second oxide; a third insulator on the second recess; and a second conductor on the third insulator; and a third oxide provided between the first oxide and the third insulator; a fourth insulator on the third insulator, on the second conductor, and on the third oxide; a fifth insulator having a region in contact with a top surface of the first oxide and a region in contact with a side surface of the first oxide; a sixth insulator having a region corresponding to a side surface of the first oxide, the sixth insulator being disposed through the fifth insulator; the first insulator, the first conductor, the second oxide, and the second insulator are provided in the first recess; the third insulator, the second conductor, the third oxide, and the fourth insulator are provided in the second recess; the first conductor has a region facing an inner wall of the first recess with the first insulator and the second oxide interposed therebetween; the second conductor has a region facing an inner wall of the second recess with the third insulator and the third oxide interposed therebetween; the second insulator has a region in contact with an inner wall of the first recess, The fourth insulator has a region in contact with an inner wall of the second recess.

3. In claim 1 or 2, The first oxide comprises indium, an element M (M is aluminum, gallium, yttrium, or tin), and zinc.

4. In claim 1 or 2, The semiconductor device, wherein the first oxide contains indium.

5. In any one of claims 1 to 4, The second oxide and the third oxide each contain gallium and zinc.

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