Substrate processing method and substrate processing apparatus
The method forms selective deposits on different substrate regions to enable controlled etching, addressing the challenge of protecting one region while etching another, thereby ensuring precise and effective substrate processing.
Patent Information
- Application Number
- JP2022071065
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-11-22
- Filing Date
- 2022-04-22
- Publication Date
- 2025-08-22
- Estimated Expiration
- 2042-04-22
AI Technical Summary
Existing substrate etching processes struggle to selectively etch a second region of a substrate while protecting a first region, particularly when dealing with materials like silicon oxide and silicon nitride, as fluorocarbons deposited on both regions complicate the protection and etching process.
A method involving forming a first deposit on the first region using a specific gas mixture, followed by a second deposit containing fluorine on the second region, and repeatedly removing the second deposit and part of the second region until a stop condition is met, using a substrate processing apparatus with controlled plasma generation and gas supply.
This method achieves selective etching of the second region while effectively protecting the first region, maintaining the integrity of the substrate features and ensuring precise control over the etching process.
Smart Images

Figure 0007728227000001 
Figure 0007728227000002 
Figure 0007728227000003
Abstract
Description
[Technical Field]
[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application is related to U.S. Provisional Patent Application No. 63 / 180,274, filed April 27, 2021, the entire contents of which are incorporated herein by reference.
[0002] The present disclosure relates to a substrate processing method, a substrate processing apparatus, and a substrate processing system that selectively protect a first region of a substrate while etching a second region of the substrate. [Background technology]
[0003] Selective etching of substrates is traditionally performed in the manufacture of electronic devices. Such etching requires the selective etching of a second region of the substrate while protecting a first region. In some processes, the second region formed of silicon oxide is selectively etched relative to the first region formed of silicon nitride. In these processes, fluorocarbons are deposited on the first and second regions of the substrate. The fluorocarbon deposited on the first region is used to protect the first region, and the fluorocarbon deposited on the second region is used to etch the second region. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-173240 Summary of the Invention [Problem to be solved by the invention]
[0005] In one exemplary embodiment of the present disclosure, a substrate processing method is provided for processing a substrate including a first region and a second region having different compositions. [Means for solving the problem]
[0006] The method includes: (a) forming a first deposit preferentially on a first region using a substrate processing apparatus; (b) after step (a), forming a second deposit on a second region, the second deposit containing fluorine and different from the first deposit; and (c) after step (b), removing the second deposit and at least a portion of the second region; and if a stop condition is not satisfied, steps (a) to (c) are repeated in order. [Brief explanation of the drawings]
[0007] [Figure 1A] FIG. 1 shows a substrate comprising a first region and a second region with a deep recess therebetween. [Figure 1B] 1B is a graph comparing deposition rate in a first region of the substrate shown in FIG. 1A with the depth of recesses etched according to comparative processes. [Figure 1C] 1B is a graph comparing deposition rate in a first region of the substrate shown in FIG. 1A with the depth of recesses etched according to a process according to the present disclosure. [Figure 2] FIG. 10 is a diagram showing an example of conditions for direct current superposition (DCS) near the upper electrode. [Figure 3A] 1 is a flowchart of an etching method according to an example embodiment. [Figure 3B] 3B is a flowchart of step STx according to an exemplary embodiment that can be employed in the etching method shown in FIG. 3A. [Figure 3C] 3B is a flowchart of step STc according to an exemplary embodiment that can be employed in the etching method shown in FIG. 3A. [Figure 4] 3D is a timing chart showing the process of forming a deposit on the substrate W in step STc of FIGS. 3A and 3C. [Figure 5A] 3B is a diagram showing an example of a substrate provided in step STa of FIG. 3A. FIG. [Figure 5B] 3B is a diagram showing a first deposit DP formed in a first region of the substrate in step STb of FIG. 3A. FIG. [Figure 5C]FIG. 3B is a diagram showing a silicon-containing deposit DPS formed on the first deposit DP in step STy of FIG. 3A. [Figure 5D] FIG. 3B is a diagram showing a second deposit DPC selectively formed on the silicon-containing deposit DPS in step STz1 of FIG. 3A. [Figure 5E] FIG. 3B shows a substrate obtained as a result of exposure to ions in step STz2 of FIG. 3A. [Figure 5F] FIG. 3D is a diagram showing a first deposit DP selectively formed on a first region in step STcx of FIG. 3C. [Figure 5G] FIG. 10 is a diagram showing a substrate obtained as a result of repeating steps STcx, STc1, and STc2 until a stop condition is satisfied. [Figure 5H] FIG. 10 is a diagram showing the removal of deposits by ashing after etching of the second region R2 is completed. [Figure 6A] 3B is a diagram showing an example of a substrate provided in step STa of FIG. 3A. FIG. [Figure 6B] FIG. 3C is a diagram showing a deposit DPC formed on a substrate in step STx1 of FIG. 3B. [Figure 6C] FIG. 3C is a diagram showing the substrate obtained as a result of exposure to ions in step STx2 of FIG. 3B. [Figure 6D] FIG. 3D is a diagram showing a first deposit DP preferentially formed on the first region in step STcx of FIG. 3C. [Figure 7] 1 is a diagram illustrating an example of a substrate processing apparatus according to the present disclosure. [Figure 8] FIG. 1 illustrates an example of a processing circuit for performing operations according to the present disclosure on a computer. DETAILED DESCRIPTION OF THE INVENTION
[0008] Various exemplary embodiments will now be described in detail with reference to the drawings, in which like reference numerals refer to like or corresponding parts throughout the drawings. The embodiments are illustrated in the accompanying drawings, which are not intended to be limiting. Unless expressly stated otherwise, the drawings are not drawn to scale.
[0009] Throughout the specification, the term "one embodiment" or "embodiment" means that a particular feature, structure, characteristic, operation, or function described in connection with an embodiment is included in at least one embodiment of the presently disclosed subject matter. Thus, appearances of "one embodiment" or "in an embodiment" herein do not necessarily refer to the same embodiment. Furthermore, particular features, structures, characteristics, operations, or functions may be combined in any suitable manner in one or more embodiments. Furthermore, embodiments of the presently disclosed subject matter may include modifications and variations of the described embodiments.
[0010] As used herein and in the appended claims, the singular terms "a," "an," and "the" include the plural unless expressly stated otherwise. That is, as used herein, terms such as "a" mean "one or more" unless expressly indicated otherwise. That is, as used herein, terms such as "a" mean "one or more" unless expressly indicated otherwise. Furthermore, terms such as "left," "right," "top," "bottom," "front," "rear," "side," "height," "length," "width," "upper," "lower," "internal," "external," "inside," "outside," and the like, as used herein, merely indicate points of reference and do not necessarily limit embodiments of the presently disclosed subject matter to a particular orientation or configuration. Furthermore, terms such as "first," "second," "third," and the like, merely identify the number of parts, components, points of reference, actions, and / or functions, etc., described herein and do not necessarily limit embodiments of the presently disclosed subject matter to a particular configuration or orientation.
[0011] Throughout this disclosure, "depression" is used as a type of etched feature, and the two terms ("depression" and "etched feature") are used interchangeably herein. Furthermore, the term "depression" is not limiting and may refer to holes, slits, grooves, recessed cavities, or any other type of pattern where material has been removed in the substrate material being etched.
[0012] 1A shows a substrate SW having a first region R1 and a second region R2 with a deep recess therebetween. Specifically, the substrate SW includes a first region R1 and a second region R2. In one exemplary embodiment, the first region R1 is formed from silicon nitride and the second region R2 is formed from silicon oxide.
[0013] A deposit DP is formed on the first region R1, and a recess RC is provided between the first region R1 and the second region R2. The depth d of the recess RC is indicated. In one exemplary embodiment, the deposit DP is formed on the substrate SW using a mixture of CO gas and Ar gas as a process gas. In another embodiment, the deposit DP may be formed on the substrate SW using a mixture of CHF gas and Ar gas.
[0014] 1B is a graph comparing the deposition amount in the first region R1 of the substrate SW with the depth d (nm) of the recess etched according to the comparative process. As shown in FIG. 1B, the depth d (nm) of the recess when the substrate SW is etched according to the comparative process is compared with the deposition amount in the first region R1.
[0015] In the comparative step, the recess RC is etched to a depth A. In one exemplary embodiment, the recess RC is etched to a depth A of 20 nm to 40 nm. Next, deposits DP are repeatedly formed on the substrate SW while alternately supplying noble gas ions to the substrate SW. In one exemplary embodiment, the deposits DP formed on the substrate SW contain fluorine.
[0016] The recess RC is then etched to a depth B. In one exemplary embodiment, the depth is 50 nm to 80 nm. The procedure for etching the recess RC to a depth B is as follows: (i) forming a first deposit (5 nm or more) on the first region R1; (ii) generating a plasma from a noble gas and forming a second deposit containing fluorine on the substrate SW while alternately supplying the plasma to the substrate SW. Steps (i) and (ii) may be repeated one or more times until the process is complete. The selective processing step and the etching step of the recess RC are performed at a temperature between 120°C and 180°C, although these processes are not limited to this range. In one example, these steps are performed at 150°C.
[0017] 1C shows a graph comparing the deposition rate in the first region R1 of the substrate SW shown in FIG. 1A with the depth d of the recess etched according to the exemplary process according to the present disclosure. In the exemplary process according to the present disclosure, the depth d (nm) of the recess when the substrate SW is etched according to the exemplary process was compared with the deposition rate in the first region R1, as shown in FIG.
[0018] In an exemplary process, first, the recess RC is etched to a depth C. In one exemplary embodiment, the depth C of the recess RC is etched to, but is not limited to, 10 nm to 20 nm. Next, deposits DP are repeatedly formed on the substrate SW while alternately supplying noble gas ions to the substrate SW. In one exemplary embodiment, the deposits DP formed on the substrate SW include fluorine.
[0019] Next, the recess RC is etched to a depth D. In one exemplary embodiment, the etching is performed to a depth of 80 nm to 100 nm. The procedure for etching the recess RC to a depth D is as follows: (a) A first deposit is formed on the first region R1. This first deposit is formed to be thinner than the first deposit formed in step (i) of the comparative process. (b) Next, a second deposit containing fluorine is formed on the substrate SW. (c) Next, a plasma is generated from a noble gas and the plasma is supplied to the substrate SW. Steps (a), (b), and (c) are repeated in this order. The selective processing step and the step of etching the recess RC are performed at a temperature of 150°C to 200°C, but these steps are not limited to this range. In one example, these steps are performed at 170°C.
[0020] FIG. 2 shows an example of conditions for direct current superposition (DCS) near an upper electrode such as the upper electrode 3 illustrated in FIG. 7, which will be described later.
[0021] As shown in Figure 2, voltage V1 and radio frequency (RF) are both supplied to the Si electrode, and voltage V2 is applied only to Si. In one exemplary embodiment, the DC superposition conditions are as follows: Gas: Noble gas (e.g., Ar) + H2 (optional) Power: Inner V1=-800V, Outer V2=-200V (Example: Vl <V2<0(V)) Pressure: 10mTorr to 100mTorr (e.g., 20mTorr)
[0022] FIG. 2 is further described below with reference to FIG. 5C and step STy.
[0023] 3A is a flowchart of an etching method according to one example embodiment. The etching method shown in FIG. 3A (hereinafter referred to as "method MT") starts with step STa. In step STa, a substrate SW is placed on a substrate support of a substrate processing apparatus. The substrate support is provided in a chamber of the substrate processing apparatus. FIG. 7 illustrates an example of a substrate processing apparatus.
[0024] FIG. 7 illustrates an exemplary substrate processing apparatus according to the present disclosure.
[0025] Specifically, FIG. 7 illustrates a substrate processing apparatus 200, such as a capacitively coupled plasma (CCP) system. While a CCP system is shown as an example, any other etching apparatus, such as an inductively coupled plasma (ICP) system, may also be used. The substrate processing apparatus 200 includes a substantially cylindrical reaction chamber 1 made of, for example, aluminum. The reaction chamber 1 is connected to ground potential. A plasma-resistant film is formed on the inner wall surface of the reaction chamber 1. This film may be a film formed by anodizing or a ceramic film such as a film made of yttrium oxide. When high-frequency power is supplied to at least one of the upper electrode 3 and the base 4 (which functions as a lower electrode for generating plasma in the reaction chamber 1), plasma 2 is generated with a substrate W to be processed sandwiched between the upper electrode 3 and the base 4. The plasma 2 is formed near the substrate W, and the substrate W is held on the upper surface of an electrostatic chuck 5, as described in detail below. The base 4 is substantially disc-shaped and conductive.
[0026] The gas source 8 includes multiple gas sources, each controlled through a corresponding series of flow rate controls. The gas source 8 supplies gas to the reaction chamber 1 through one or more gas lines.
[0027] The substrate processing apparatus 200 further includes a first high frequency power supply 6 that generates high frequency energy in the range of 27 MHz to 100 MHz, an exemplary frequency being 60 MHz. The first high frequency power supply 6 is connected to the upper electrode 3 via a matching circuit, and this matching circuit matches the output impedance of the first high frequency power supply 6 with the impedance of the upper electrode 3.
[0028] The substrate processing apparatus 200 further includes a second high frequency power supply 7 that generates bias high frequency energy to attract ions to the substrate W. The operating frequency of the second high frequency power supply 7 is lower than the operating frequency of the first high frequency power supply 6, and is typically in the range of 300 kHz to 13.56 MHz. In an alternative embodiment, multiple high frequency power supplies 6, 7 may be connected to the same electrode (lower electrode 4).
[0029] The upper electrode 3 is equipped with a variable direct current (DC) power supply 10 as a second power supply. The variable DC power supply 10 can also function as a DC bias for the radio frequency energy applied to the upper electrode from the first radio frequency power supply 6. The variability of the DC power supply 10 allows for control of the behavior of the ion energy so that the etching rate can be controlled depending on the process being performed.
[0030] The high-frequency energy generated by the high-frequency power supply 7 may be pulsed. When bias power is supplied to the base / bottom electrode, etching mainly occurs. When bias power is not supplied to the base / bottom electrode, deposition mainly occurs. By pulsing the bias power, the etching and deposition stages can be separated. Etching occurs after the formation of a protective film, so the sidewalls of the recess are protected from side etching. In addition, the balance between etching and deposition can be controlled by changing the pulse duty ratio (bias-on time / (bias-on time + bias-off time)). The longer the bias-off time, the thicker the protective film can be formed, thereby improving protection. Increasing the bias-on time increases the etching rate.
[0031] In one embodiment, the substrate processing apparatus 200 may have a dedicated control circuit such as the processing circuit illustrated in Fig. 8. The control circuit executes a control program stored in a memory and controls each component of the substrate processing apparatus 200 based on recipe data stored in a storage device.
[0032] The substrate processing apparatus 200 includes an exhaust device 9 connected to the internal atmosphere of the reaction chamber 1. The exhaust device 9 includes a pressure control device such as an automatic pressure control valve and a vacuum pump (e.g., a turbomolecular pump), and is configured to control the pressure reduction of the reaction chamber 1 and exhaust gas from the reaction chamber 1.
[0033] In the substrate processing apparatus 200, high frequency power for generating plasma is supplied to the upper electrode 3. Alternatively, the high frequency power may be supplied to the base 4. The method according to the present disclosure is also applicable to substrate processing apparatuses other than CCP plasma processing apparatuses. More specifically, the method may be performed using any plasma processing apparatus, such as an inductively coupled plasma processing apparatus or a plasma processing apparatus that generates plasma using surface waves such as microwaves.
[0034] Returning to FIG. 3A , the substrate W includes a first region R1 and a second region R2. In one exemplary embodiment, the first region R1 is formed of a different material than the second region R2. The material of the first region R1 may be oxygen-free and may include silicon nitride. The material of the second region R2 may include silicon and oxygen and may include silicon oxide. The material of the second region R2 may include a low-k material including silicon, carbon, oxygen, and hydrogen.
[0035] FIG. 5A is a partially enlarged cross-sectional view of an exemplary substrate W processed using the etching method shown in FIG. 3A. The substrate W shown in FIG. 5A includes a first region R1 and a second region R2. The substrate W may further include an underlayer region UR. The first region R1 of the substrate W shown in FIG. 5A includes regions R11 and R12. Region R11 is formed of silicon nitride and defines a recess. Region R11 is provided on the underlayer region UR. Region R12 extends on both sides of region R11. Region R12 is formed of silicon nitride or silicon carbide. The second region R2 of the substrate W shown in FIG. 5A is formed of silicon oxide and is provided within the recess defined by region R11. That is, the second region R2 is surrounded by the first region R1. When the substrate W shown in FIG. 5A is processed using method MT, the second region R2 is etched in a self-aligned manner.
[0036] Next, the steps subsequent to step STa of the method MT will be described with reference to the substrate W.
[0037] In some embodiments, step STx may be performed after step STa. In other embodiments, step STx is not performed and processing proceeds to step STb. In step STx, the first region R1 is etched until it reaches a predetermined aspect ratio or greater. Step STx is further described below with reference to Figures 3B and 6A-6D.
[0038] In step STb, as shown in FIG. 5B, a deposit DP is preferentially formed on the first region R1.
[0039] 5B shows a first deposit DP formed on a first region of a substrate in step STb of FIG. 3A. The first deposit DP includes carbon. In one exemplary embodiment, the first deposit DP is formed using a plasma generated from a process gas that includes carbon and does not include fluorine.
[0040] In step STb, plasma is generated from the processing gas in the chamber of the substrate processing apparatus 200 .
[0041] In one exemplary embodiment, the process gas used in step STb may include a first gas and a second gas, and may further include a noble gas such as argon gas or helium gas.
[0042] The first gas contains carbon but does not contain fluorine. Examples of the first gas include CO gas, COS gas, C2H2 gas, C2H4 gas, CH4 gas, C2H6 gas, and H2 gas.
[0043] The first gas may not contain hydrogen. The first gas may contain a gas that contains carbon but does not contain fluorine, such as carbon monoxide gas (CO gas) or carbonyl sulfide gas (COS gas).
[0044] The second gas may contain carbon and fluorine or hydrogen. Examples of such second gases include hydrofluorocarbon gas, fluorocarbon gas, and hydrocarbon gas. The hydrofluorocarbon gas may be, for example, CHF3 gas, CH3F gas, or CH2F2 gas. The fluorocarbon gas may be, for example, C4F6 gas. The second gas containing carbon and hydrogen may be, for example, CH4 gas.
[0045] The flow rate of the first gas may be higher than the flow rate of the second gas. The ratio of the flow rate of the second gas to the flow rate of the first gas may be 0.2 or less. The flow rate of the carbon-containing, fluorine-free gas in the first gas may be 30 sccm or more and 200 sccm or less. The flow rate of the carbon-containing, fluorine-free gas in the first gas may be 90 sccm or more and 130 sccm or less. The flow rate of the noble gas in the processing gas may be 0 sccm or more and 1000 sccm or less. The flow rate of the noble gas in the processing gas may be 350 sccm or less.
[0046] The flow rate of each gas contained in the process gas can be determined by the volume of the internal space 10s of the chamber 10, etc. In step STb, chemical species (carbon species) from the plasma are supplied to the substrate. The supplied chemical species form a carbon-containing deposit DP preferentially on the first region R1, as shown in FIG. 5B.
[0047] In the process STb using the processing gas, not only is the deposit DP preferentially formed on the first region R1, but also a thin protective film is formed on the sidewalls defining the recess, thereby protecting the sidewalls from the plasma.
[0048] The process gas used in step STb may be a mixed gas containing CO gas and hydrogen gas (H2 gas). This process gas allows the deposit DP to be preferentially formed on the first region R1. The deposit DP functions as a protective film with excellent resistance to etching in step STc. The ratio of the flow rate of H2 gas to the total flow rate of CO gas and H2 gas contained in the process gas may be 1 / 19 or more and 2 / 17 or less. Using a process gas with such a ratio increases the verticality of the side surface of the deposit DP formed on the first region R1.
[0049] In the step STb, the energy of the ions supplied to the substrate W may be equal to or greater than 0 eV and equal to or less than 70 eV. In this case, the reduction in the opening of the recess due to the deposit DP is suppressed.
[0050] In one embodiment, the substrate processing apparatus used in step STb may be a capacitively coupled plasma processing apparatus. When using a capacitively coupled plasma processing apparatus, high-frequency power for generating plasma may be supplied to the upper electrode. In this case, the plasma can be formed in a region away from the substrate W. The frequency of the high-frequency power may be 60 MHz or higher. In another embodiment, the substrate processing apparatus used in step STb may be an inductively coupled plasma processing apparatus.
[0051] In step STb, a deposit DP is preferentially formed on the first region R1. Step STb can be performed at least when the aspect ratio of the recess defined by the first region R1 and the second region R2 of the substrate W is 4 or less.
[0052] In step STb of method MT, carbon species generated from the process gas are selectively deposited on the first region R1. Deposition of carbon species generated from the process gas is suppressed on the second region R2 containing oxygen. In method MT, etching of the second region R2 is performed while deposits DP are selectively present on the first region R1. Therefore, method MT makes it possible to etch the second region R2 while selectively protecting the first region R1 from the second region R2. According to method MT, deposits DP are preferentially formed on the first region R1. This suppresses blocking of the opening of the recess defined by the first region R1 and the second region R2.
[0053] The carbon species generated from CO gas in step STb are ionic. CH4 gas or CH3F gas is likely to generate radicals such as CH2 or CHF. These radicals are highly reactive and tend to deposit isotropically on the surface of the substrate W. In contrast, ionic species deposit anisotropically on the substrate W. That is, ionic species adhere more to the upper surface of the first region R1 than to the wall surfaces defining the recess. Carbon monoxide is likely to desorb from the surface of the substrate W. Therefore, to adsorb carbon monoxide on the surface of the substrate W, it is necessary to remove oxygen from the surface of the substrate W by bombarding the surface with ions. Furthermore, carbon monoxide has a simple structure and is therefore difficult to crosslink. Therefore, to deposit carbon monoxide on the surface of the substrate W, dangling bonds must be formed on the surface of the substrate W. The carbon species generated from CO gas in step STb are ionic. Therefore, the carbon species can remove oxygen from the top surface of the first region R1, form dangling bonds on the top surface, and selectively deposit the carbon species on the first region R1.
[0054] In some embodiments, step STy may be performed after step STb. In other embodiments, step STy is not performed, and processing proceeds to step STz1. In step STy, a silicon-containing deposit DPS is formed on the first deposit DP and the second region R2, as shown in FIG. 5C.
[0055] In one embodiment, the silicon-containing deposit DPS may be formed near the upper electrode using DC superposition in step STy, as shown in Figure 2. When a noble gas (e.g., Ar) is supplied into the chamber and a direct current is applied to the upper electrode, ions in the noble gas are generated, and sputtering of the Si-containing upper electrode generates Si and secondary electrons. When the substrate surface is exposed to the generated Si and secondary electrons, the silicon-containing deposit DPS is formed.
[0056] In another embodiment, the silicon-containing deposit DPS may be formed in step STy using plasma-enhanced chemical vapor deposition (PECVD). While supplying a silicon-containing gas (e.g., SiCl) into a chamber, high-frequency power is supplied to generate plasma, thereby forming the silicon-containing deposit DPS on the first deposit DP.
[0057] In step STz1, as shown in FIG. 5D , a fluorine-containing second deposit DPC is formed on the substrate W. In one exemplary embodiment, when step STy is performed, the second deposit DPC is formed on the silicon-containing deposit DPS in the first region R1 and the second region R2. In another embodiment, when step STy is not performed, the second deposit DPC is formed not only on the deposit DP in region R1 but also on the silicon oxide film in the second region R2. In one exemplary embodiment, the second deposit DPC includes fluorine.
[0058] The second deposit DPC may be formed using plasma generated from a fluorocarbon gas in a chamber of the substrate processing apparatus 200. Examples of fluorocarbon gases include, but are not limited to, CF4 gas, C4F6 gas, and C4F8 gas. The processing gas may further include a noble gas such as argon gas or helium gas.
[0059] In step STz2, as shown in FIG. 5E, plasma is generated from the noble gas in the chamber, and a portion of the second region R2 is removed while supplying noble gas ions to the substrate W. Specifically, ions in the noble gas are supplied to the substrate W and collide with the second deposit DPC on the second region R2 to activate the second deposit DPC. The activated species from the second deposit DPC react with the second region R2 to remove a portion of the second region R2.
[0060] The silicon-containing deposit DPS and the second deposit DPC on the first region R1 are also removed. The first deposit DP on the first region R1 is also partially removed. In one exemplary embodiment, the noble gas is Ar gas, but a gas other than Ar gas may also be used. Step STz2 continues so as not to completely consume the deposit DP on the first region R1.
[0061] After performing step STz2, the process proceeds to step STc. In step STc, the second region R2 is selectively etched relative to the first region R1. Specifically, the second region R2 is selectively etched while supplying noble gas ions to the substrate W. In one embodiment, the second region R2 is etched using chemical species from plasma generated from an etching gas. In this case, plasma is generated from the etching gas in a chamber of a substrate processing apparatus. The etching gas is selected depending on the material of the second region R2. The etching gas includes, for example, a fluorocarbon gas. The etching gas may further include a noble gas such as argon gas and an oxygen-containing gas such as oxygen gas.
[0062] The substrate processing apparatus used in step STb may also be used as an etching apparatus in step STc. In this case, steps STb and STc are performed without removing the substrate W from the chamber of the substrate processing apparatus. Alternatively, the substrate processing apparatus used in step STb may be different from the substrate processing apparatus used in step STc. In this case, between steps STb and STc, the substrate W is transferred from the substrate processing apparatus used in step STb to the etching apparatus used in step STc via only a vacuum environment.
[0063] Step STc will be further described below with reference to FIG. 3C.
[0064] The method MT finally proceeds to step STJ, where it is determined whether a stopping condition has been met. In one exemplary embodiment, this determination is performed by a processing circuit, the details of which are described in more detail below with reference to FIG. 8.
[0065] If it is determined in step STJ that the stopping condition is not satisfied, the process returns to step STc and repeats step STc. If it is determined that the stopping condition is satisfied, the method MT is completed.
[0066] In one exemplary embodiment of step STJ, a stop condition is satisfied when the number of times step STc is processed reaches a threshold value. The threshold value of the number of times processing may be a predetermined value or may be set based on user input, etc. If the stop condition is not satisfied in step STJ, the process returns to step STc and step STc is repeated. Specifically, as shown in FIGS. 5F and 5G and described with reference to FIG. 3C, step STc is performed again to etch the second region R2.
[0067] Returning to step STx, the details of step STx are shown in Fig. 3B. After providing a substrate W in step STa, step STx is performed. Such a substrate W is shown in Fig. 6A. This substrate W corresponds to the substrate W shown in Fig. 5A.
[0068] The process of step STx begins with step STx1, which forms a fluorine-containing deposit DPC on the substrate W as shown in FIG. 6B. This fluorine-containing deposit DPC may be made of the same material as the deposit DPC shown in FIG. 5D used in step STz1. In one exemplary embodiment, the fluorine-containing deposit DPC is formed in the first region R1 and the second region R2. The fluorine-containing deposit DPC may be formed using plasma generated from a fluorocarbon gas in a chamber of the substrate processing apparatus 200. Examples of fluorocarbon gases include, but are not limited to, CF4 gas, C4F6 gas, and C4F8 gas. The process gas may further include a noble gas such as argon gas or helium gas.
[0069] When step STx1 is performed in the substrate processing apparatus 200, a processing gas is supplied from the gas source 8 into the reaction chamber 1. Furthermore, in step STx1, high-frequency power is supplied from the second high-frequency power supply 7 to the base 4. Furthermore, in step STx1, the pressure in the space within the reaction chamber 1 is set to a predetermined pressure. For example, the pressure in the space within the reaction chamber 1 is set to a range of 5 mTorr (0.6667 Pa) to 80 mTorr (10.67 Pa), but other pressures may also be set. Furthermore, in step STx1, the distance between the upper electrode 3 and the top surface of the base 4 is set to a range of 20 mm to 90 mm. Plasma of the processing gas is generated in the reaction chamber 1, and the substrate W placed on the base 4 is exposed to the plasma. Furthermore, in step STx1, a voltage may be applied to the upper electrode 3 from the power supply 10. The voltage applied from the power supply 10 to the upper electrode 3 may be −150 V or less. That is, the voltage applied from the power supply 10 to the upper electrode 3 may be a negative voltage having an absolute value of 150 V or more. During the process STx1, the operation of each component of the substrate processing apparatus 200 can be controlled by a processing circuit which will be described with reference to FIG.
[0070] At the start of step STx1, activated atomic and / or molecular species generated from fluorocarbon, such as activated fluorine species, collide with the first region R1 and the second region R2 of the substrate W. Therefore, a fluorine-containing deposit DPC is formed on the first region R1 and the second region R2. As the processing time of step STx1 increases, the thickness of the deposit DPC increases.
[0071] After step STx1, step STx2 is performed. In step STx2, the second region R2 is removed while supplying noble gas ions to the substrate W. This is shown in FIG. 6C. In one exemplary embodiment, ions of the noble gas collide with the deposit DPC on the second region R2 to activate the deposit DPC in the second region R2. The activated species from the deposit DPC react with the second region R2 to remove the second region R2. In an embodiment, the deposit DPC on the first region R1 may be partially or completely removed. The noble gas is, for example, Ar gas, but may be other gases.
[0072] The processing time of step STx1 and the processing time of step STx2 can be set appropriately. In this embodiment, the processing time of step STx1 may be set to a ratio in the range of 30% to 70% of the total processing time of step STx1 and step STx2. However, other ratios may also be used.
[0073] In process STx2, high-frequency power is supplied from the high-frequency power supply 7 to the base 4, as in process STx1. Furthermore, in process STx2, the pressure in the space within the reaction chamber 1 is set, as in process STx1. Furthermore, in process STx2, the distance between the upper electrode 3 and the top surface of the base 4 is set, as in process STx1. Plasma is generated in the reaction chamber 1, and the substrate W placed on the base 4 is exposed to the plasma. Furthermore, in process STx2, a voltage may be applied to the upper electrode 3 from the power supply 10, as in process STx1.
[0074] In step STx2, activated species, such as ions of noble gas atoms, are bombarded with the deposit DP. As a result, the second region R2 is etched by fluorocarbon radicals in the deposit DP, as shown in FIG. 6C. Furthermore, step STx2 reduces the thickness of the deposit DP. Furthermore, in step STx2, the thickness of the deposit DPC on the first region R1 is also reduced, as shown in FIG. 6C.
[0075] After step STx2, step STx3 is performed. In step STx3, it is determined whether the first region R1 has reached a predetermined aspect ratio relative to the second region R2. In one exemplary embodiment, this determination is performed by a processing circuit as illustrated in FIG. 8.
[0076] If it is determined in step STx3 that the predetermined aspect ratio has not been reached, the process returns to step STx1, and steps STx1 and STx2 are repeated. If it is determined that the predetermined aspect ratio has been reached, step STx is completed, and method MT proceeds to step STb.
[0077] 6D illustrates the state of the substrate W after the completion of step STx and then step STb. As shown in FIG. 6D, the first deposit DP is preferentially formed on the first region R1 that has reached a predetermined aspect ratio or greater relative to the second region R2.
[0078] The selectivity of the first region R1 when step STx is performed is higher than the selectivity of the first region R1 when step STx is not performed. Specifically, as a result of performing step STx, a predetermined aspect ratio is generated between the first region R1 and the second region R2, so the selectivity of the first region R1 is higher. In other words, when step STx is performed, the first deposit DP is less likely to form on the second region R2 than on the first region R1.
[0079] Returning to step STc, the details of step STc are shown in FIG. 3C. Step STc is performed after step STz2. Furthermore, if it is determined that the stop condition is not satisfied in step STJ, step STc may be repeated. Such a substrate W is shown in FIG. 5E.
[0080] The process of step STc begins with step STcx, which preferentially forms a first deposit DP on the first region R1, as shown in FIG. 5F. The first deposit DP in this process may be the same material as the deposit DP described with reference to step STb and FIG. 5B. However, the first deposit DP deposited in step STcx may have a different thickness than the deposit DP deposited in step STb and shown in FIG. 5B. Furthermore, the process of step STcx may be performed using different pressure conditions and / or processing duration than those used in step STb.
[0081] After completion of step STcx, step STcy may be performed. Step STcy is an optional step for preferentially forming a silicon-containing deposit DPS on the first deposit DP formed in step STcx. However, in some embodiments, step STcy is omitted, and the silicon-containing deposit DPS is not formed on the first deposit DP.
[0082] The process then proceeds to step STc1, where a fluorine-containing second deposit DPC is formed on the substrate W, as shown in FIG. 5G. The fluorine-containing deposit DPC is formed in both the first region R1 and the second region R2. In an embodiment in which a silicon-containing deposit DPS is formed on the first deposit DP in step STcy, the fluorine-containing deposit DPC is formed on the silicon-containing deposit DPS. In an embodiment in which step STcy is omitted and a silicon-containing deposit DPS is not formed, the fluorine-containing deposit DPC is formed on the first deposit DP in the first region R1.
[0083] Next, the process proceeds to step STc2, where the second region R2 is etched by noble gas ions supplied to the substrate W. Specifically, the second region R2 is selectively etched while noble gas ions are supplied to the substrate W.
[0084] After step STc2 is completed, step STc is completed, and method MT proceeds to step STJ. As described above, in step STJ, it may be determined that the stop condition is not satisfied. If the stop condition is not satisfied, step STc is repeated to further etch the second region R2.
[0085] FIG. 5H shows the substrate W after the deposits DP have been removed by ashing. In one embodiment, after etching of the second region R2 is completed, the deposits DP may be removed from the first region R1 by ashing. This step may be optionally performed after step STJ. In one embodiment, the deposits DP are removed by etching using chemical species contained in plasma generated from an ashing gas. In this case, the plasma is generated from the ashing gas in the chamber of the ashing apparatus. The ashing gas may include an oxygen-containing gas, such as oxygen gas. The ashing gas may be a mixed gas containing N2 gas and H2 gas.
[0086] 4 shows a timing chart for forming a deposit on the substrate W in step STc in FIGS. 3A and 3C. As shown in FIG. 4, the supply of various gases and the high-frequency bias is turned on and off during steps STcx, STc1, and STc2. Ar gas is continuously supplied throughout step STc.
[0087] In step STcx, CO gas is supplied while the first deposit DP is formed in the first region R1. Thereafter, the supply of CO gas is stopped before and during steps STc1 and STc2. Thereafter, when step STc is repeated, the supply of CO gas is resumed before and during step STcx.
[0088] During the implementation of process STcx, C x F y The supply of gas is stopped. Then, during the execution of step STc1, x F y Gas is supplied, and before and during step STc2, C x F y Stop the gas supply. When repeating step STc, during step STcx, x F y Turn off the gas supply.
[0089] During the duration of each of steps STcx, STc1, and STc2, a 100 MHz radio frequency (HF) is applied at an output of 100 W to 1000 W. The HF power is reduced between each step, and is applied again at the start of each step and during its duration.
[0090] During the duration of each of steps STcx and STc1, a 40 MHz radio frequency bias is applied at an output of 0 W to 300 W. The radio frequency bias is reduced between each step. During the duration of step STc2, a 40 MHz radio frequency bias is applied at an output of 100 W to 600 W, and after step STc2 is completed, the radio frequency bias is reduced until the repetition of step STc begins.
[0091] FIG. 8 is a block diagram of a processing circuit that performs the operations described herein on a computer. FIG. 8 illustrates a processing circuit 300 that can be used to control all of the control processes, statements, or blocks of the flowchart on a computer or cloud. These control processes, statements, or blocks represent modules, segments, or portions of code containing one or more executable instructions for implementing specific logical functions or steps of the processes. Those skilled in the art will appreciate that alternative implementations are within the scope of the exemplary embodiments of the present disclosure, and that functions may be performed in a different order than that shown or described, such as substantially concurrently or in reverse order, depending on the functionality involved. The various elements, features, and processes described herein may be used independently of each other or combined in various ways. All possible combinations and subcombinations are within the scope of the present disclosure.
[0092] In FIG. 8, the processing circuit 300 includes a CPU 301 that performs one or more control processes described above / below. Process data and instructions can be stored in a memory 302. These process data and instructions can be stored on a storage medium disk 304, such as a hard disk drive (HDD), a portable storage medium, or a remote storage device. Furthermore, the claimed disclosure is not limited by the type of computer-readable medium on which instructions for processes according to the present invention are stored. For example, these instructions can be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device, such as a server or computer, with which the processing circuit 300 communicates. Furthermore, each process can be stored on a network storage device, a cloud storage device, or other remotely accessible storage device and executed by the processing circuit 300.
[0093] Furthermore, the claimed disclosure may be provided as a utility application, a background daemon, a component of an operating system, or a combination thereof, and may execute in conjunction with CPU 301 and an operating system known to those skilled in the art, such as Microsoft Windows®, UNIX®, Solaris, LINUX®, Apple MAC-OS, etc.
[0094] The hardware elements making up the processing circuit 300 can be realized by various circuit elements. Furthermore, each function of the above-described embodiments can be implemented by a circuit including one or more processing circuits. As shown in Figure 8, the processing circuit includes a specific programmed processing unit, such as a processing unit (CPU) 301. The processing circuit also includes devices such as application specific integrated circuits (ASICs) or conventional circuit components configured to perform the described functions.
[0095] In FIG. 8 , the processing circuit 300 includes a CPU 301 that performs the above-described processing. The processing circuit 300 may be a general-purpose computer or a specific dedicated machine. In one embodiment, the processing circuit 301 controls the voltage and the robot arm to replace the ESC without exposing the reaction chamber 1 to the external atmosphere. If the processing circuit 301 is programmed to replace the ESC in situ, the processing circuit 300 functions as a specific dedicated machine. The processing circuit 300 may be included within the substrate processing apparatus 200 or may be able to communicate locally with the substrate processing apparatus 200. In one embodiment, the processing circuit 300 may be remote from the substrate processing apparatus 200 and provide processing instructions to the substrate processing apparatus 200 via a network 550.
[0096] Alternatively or additionally, CPU 301 may be implemented on an FPGA, ASIC, PLD, or may use discrete logic circuitry, as will be appreciated by those skilled in the art. Furthermore, CPU 301 may be implemented as multiple processing units that cooperate to perform the instructions of the processes of the present invention described above in parallel.
[0097] The processing circuit 300 of FIG. 8 also includes a network controller 306, such as an Intel Ethernet PRO network interface card from Intel Corporation of America, for interfacing with a network 550. As can be appreciated, the network 550 can be a public network such as the Internet, a private network such as a LAN or WAN, or any combination thereof, and can also include subordinate networks such as PSTN or ISDN. The network 550 can also be wired, such as an Ethernet network, or wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network can also be Wi-Fi, Bluetooth, or any other known form of wireless communication.
[0098] The processing circuit 300 further includes a display device controller 308, such as a graphics card or graphics adapter, for interfacing with a display device 309, such as a monitor. A general-purpose I / O interface 312 interfaces with a keyboard and / or mouse 314 and a touch panel 316, which may be integral with or separate from the display device 309. The general-purpose I / O interface also connects to various peripheral devices 318, such as printers and scanners.
[0099] The general purpose storage controller 324 is connected to the storage media disk 304 via a communications bus 326, such as ISA, EISA, VESA, PCI, etc., and all components of the processing circuit 300 are interconnected. For the sake of brevity, the display device 309, keyboard and / or mouse 314, and the general features and functions of the display device controller 308, storage controller 324, network controller 306, and general purpose I / O interface 312 are not described herein as they are well known.
[0100] The exemplary circuit elements described in this disclosure may be substituted with other elements and may have different structures than the examples described herein. Additionally, circuits configured to implement the features described herein may be implemented in multiple circuit units (e.g., chips) or these features may be combined as circuits in a single chipset.
[0101] The functions and features described herein may also be performed by various distributed components on a system. For example, one or more processing devices may perform these functions, in which case the processing devices are distributed across multiple components communicating over a network. Distributed components may include various human interface and communication devices (e.g., display monitors, smartphones, tablets, personal digital assistants (PDAs)), as well as one or more client and server machines that can share processing. The network may be a private network, such as a LAN or WAN, or a public network, such as the Internet. Input to the system may be received directly by a user or remotely as a real-time or batch process. Furthermore, portions of the embodiments may be implemented on modules or hardware other than those described above. Accordingly, other embodiments are within the scope of the claims.
[0102] The entire disclosures of U.S. Patent Application Publication Nos. 2015 / 0243522 and 2018 / 0151333, and Japanese Patent Application Laid-Open No. 2021-029988 are incorporated herein by reference.
[0103] While embodiments of the presently disclosed subject matter have been described, those skilled in the art will recognize that the foregoing is merely illustrative, not limiting, and has been presented by way of example only. Thus, while particular configurations have been described herein, other configurations may be employed. Numerous modifications and other embodiments (e.g., combinations, rearrangements, etc.) are possible from the present disclosure and are within the skill of those skilled in the art and are intended to be encompassed within the scope of the presently disclosed subject matter and any equivalents thereof. Features of the presently disclosed embodiments may be combined, rearranged, or omitted, etc., within the scope of the present invention to achieve further embodiments. Furthermore, only certain features may be advantageously used, without the corresponding use of other features. Accordingly, the applicant intends to embrace all such alternatives, modifications, equivalents, and variations that fall within the spirit and scope of the presently disclosed subject matter. [Explanation of symbols]
[0104] 1 Reaction chamber 2. Plasma 3 Upper electrode 4 base 5 Electrostatic Chuck 6 1st high frequency power supply 7 Second high frequency power supply 8 Gas Source 9 Exhaust system 10 Variable DC power supply
Claims
1. 1. A substrate processing method for processing a substrate including a first region and a second region having different compositions, comprising: (a) forming a first deposit preferentially on the first region by a substrate processing apparatus having a chamber for accommodating the substrate; (b) after step (a), forming a second deposit on the second region, the second deposit comprising fluorine and different from the first deposit; (c) after step (b), removing the second deposit and at least a portion of the second region; and if the stopping condition is not satisfied, repeating steps (a) to (c) in order; further comprising supplying a carbon-containing gas into the chamber during step (a); The substrate processing method, wherein the carbon-containing gas is CO gas.
2. 1. A substrate processing method for processing a substrate including a first region and a second region having different compositions, comprising: (a) forming a first deposit preferentially on the first region by a substrate processing apparatus including a chamber that accommodates the substrate and an upper electrode provided on an upper portion of the chamber; (b) after step (a), forming a second deposit on the second region, the second deposit comprising fluorine and different from the first deposit; (c) after step (b), removing the second deposit and at least a portion of the second region; and if the stopping condition is not satisfied, repeating steps (a) to (c) in order; The substrate processing method further comprises applying a direct current (DC) voltage to the upper electrode after step (a) and before step (b).
3. 3. The substrate processing method according to claim 2, wherein the DC voltage is applied using a capacitively coupled plasma (CCP) processing apparatus.
4. the first region includes SiN or Si; The second region is SiO 2 The substrate processing method according to claim 1 or 2, comprising:
5. 3. The substrate processing method according to claim 1, wherein step (a) or step (b) is performed by plasma enhanced chemical vapor deposition (PECVD).
6. 3. The substrate processing method according to claim 1, wherein step (c) is carried out using plasma generated from a noble gas.
7. 3. The substrate processing method according to claim 1, wherein a fluorocarbon gas is supplied during the step (b).
8. 3. The substrate processing method according to claim 1, wherein the first deposit formed in step (a) in a first cycle of the substrate processing method is thicker than another first deposit formed in step (a) in another subsequent cycle of the substrate processing method.
9. 3. The substrate processing method according to claim 1, wherein the duration of any one of steps (a), (b), and (c) is adjusted for each cycle of the substrate processing method.
10. 10. The substrate processing method of claim 9, wherein the first deposit formed in step (a) in the (N+1)th cycle is thicker than another first deposit formed in step (a) in the Nth cycle, where N is a natural number.
11. The substrate processing method of claim 9 , wherein the duration of step (a) in the (N+1)th cycle is longer than the duration of step (a) in the Nth cycle.
12. 3. The substrate processing method according to claim 1, wherein step (a) is started when an aspect ratio of a recess defined by the first region and the second region of the substrate reaches 1 or more.
13. 3. The substrate processing method according to claim 1, wherein the bias power in the (N+1)th cycle is greater than another bias power in the Nth cycle.
14. 3. The substrate processing method according to claim 1, wherein steps (a), (b), and (c) are performed in the same chamber.
15. 3. The substrate processing method according to claim 1, wherein steps (b) and (c) are carried out in a chamber different from the chamber used to carry out step (a).
16. 3. The substrate processing method according to claim 1, wherein an inductively coupled plasma (ICP) processing apparatus is used.
17. 1. A substrate processing apparatus for processing a substrate including a first region and a second region having different compositions, the apparatus comprising: a chamber containing the substrate; (a) controlling the formation of a first deposit preferentially on the first region; (b) controlling, after step (a), the step of forming a second deposit on the second region, the second deposit comprising fluorine and different from the first deposit; (c) after step (b), a processing circuit configured to control removing the second deposit and at least a portion of the second region; and Equipped with the processing circuitry is further configured to repeat steps (a) through (c) in sequence if a stopping condition is not satisfied; the processing circuitry is further configured to supply a carbon-containing gas into the chamber during step (a); The substrate processing apparatus, wherein the carbon-containing gas is CO gas.
18. 1. A substrate processing apparatus for processing a substrate including a first region and a second region having different compositions, the apparatus comprising: a chamber containing the substrate; an upper electrode provided at an upper portion of the chamber; (a) controlling the formation of a first deposit preferentially on the first region; (b) controlling, after step (a), the step of forming a second deposit on the second region, the second deposit comprising fluorine and different from the first deposit; (c) after step (b), a processing circuit configured to control removing the second deposit and at least a portion of the second region; and Equipped with the processing circuitry is further configured to repeat steps (a) through (c) in sequence if a stopping condition is not satisfied; The substrate processing apparatus, wherein the processing circuitry is further configured to apply a direct current (DC) voltage to the upper electrode after step (a) and before step (b).
19. A substrate processing apparatus comprising: a chamber for accommodating a substrate, the substrate having a first region and a second region having different compositions; Processing circuit and 1. A substrate processing system comprising: (a) controlling the substrate processing apparatus to preferentially form a first deposit on the first region; (b) after step (a), controlling the substrate processing apparatus to form a second deposit on the second region, the second deposit including fluorine and different from the first deposit; (c) after step (b), controlling the substrate processing apparatus to remove the second deposit and at least a portion of the second region; the processing circuitry is further configured to repeat steps (a) through (c) in sequence if a stopping condition is not satisfied; the processing circuitry is further configured to supply a carbon-containing gas into the chamber during step (a); The substrate processing system, wherein the carbon-containing gas is CO gas.
20. A substrate processing apparatus comprising: a chamber for accommodating a substrate; and an upper electrode provided on an upper portion of the chamber, the substrate including a first region and a second region having mutually different compositions; Processing circuit and 1. A substrate processing system comprising: (a) controlling the substrate processing apparatus to preferentially form a first deposit on the first region; (b) after step (a), controlling the substrate processing apparatus to form a second deposit on the second region, the second deposit including fluorine and different from the first deposit; (c) after step (b), controlling the substrate processing apparatus to remove the second deposit and at least a portion of the second region; the processing circuitry is further configured to repeat steps (a) through (c) in sequence if a stopping condition is not satisfied; The substrate processing system, wherein the processing circuitry is further configured to apply a direct current (DC) voltage to the upper electrode after step (a) and before step (b).
Citation Information
Patent Citations
Plasma etching method using selective polymer deposition md method of forming contact holes using the same
JP2001068462A
Plasma-etching method and computer-readable storage medium
JP2008021791A
Etching method
JP2015173240A
Etching method
JP2019009189A
Film etching method
JP2020119918A