Delta-sigma A / D converter and battery impedance measuring device

Abstract

To add output signals of an integrator at the same timing without using an operational amplifier.SOLUTION: A delta sigma A / D converter 5 includes: a first integrator 1 that samples an input voltage in accordance with a first clock signal φ1; input side and output side chopping switches 12, 14, 15 which preform a chopping operation to replace alternately positive / negative side input terminals and positive / negative side output terminals in accordance with a second clock signal φ2 that is in opposite phase to the first clock signal; a second integrator 2 arranged in a subsequent stage of the first integrator; a capacitive element for sampling and a capacitive element for adding which are arranged on an input side of the second integrator and which sample an output signal of the first integrator in accordance with the second clock signal, on one side of a differential configuration; a capacitive element for odd number subtraction which samples first and second output signals in accordance with an odd numbered clock φ2a of the second clock signal; and a capacitive element for even number subtraction which samples the second output signal in accordance with an even numbered clock φ2b of the second clock signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a delta-sigma A / D converter and a battery impedance measuring device using the A / D converter. [Background technology]

[0002] For example, Patent Document 1 and Figure 7 of Non-Patent Document 1 disclose a CIFF (Cascade of Integrators with Feed-Forward summation) type delta-sigma A / D converter. This A / D converter includes first and second integrators and has a forward path for performing summation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-171484 [Non-patent literature]

[0004] [Non-Patent Document 1] A Single-Bit 2nd-Order CIFF Delta-Sigma Modulator for Precision Measurement of Battery Current,Gi-Gyeong,Bae,Ji-Min Cheon,(jkiiect)'20-6,Vol.13,No.3,http: / / dx.doi.org / 10.17661 / jkiiect.2020.13.3.184 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the configuration of Non-Patent Document 1 has a problem in that the value of the forward summation path is not the same timing value in the first integrator. Also, sampling in the second integrator is performed in phase (1), and sampling in the forward summation path is performed in phase (2). There is no problem because the first integrator has the same value in phases (1) and (2). However, if chopping is performed on the input side of the first integrator to reduce noise, the values ​​cannot be set to the same timing. In addition, generally, an adder using an operational amplifier is sometimes provided, but in that case, increases in circuit area and current consumption become a problem.

[0006] The present invention has been made in view of the above circumstances, and its object is to provide a delta-sigma A / D converter that has a function for adding output signals of a first integrator at the same timing without using an operational amplifier in a configuration in which chopping is performed on the input side of the first integrator, and a battery impedance measuring device that uses this A / D converter. [Means for solving the problem]

[0007] According to the delta-sigma A / D converter of claim 1, a first integrator (1) of a differential configuration samples an input voltage in accordance with a first clock signal (φ1). Input-side and output-side chopping switches (12, 14, 15) perform chopping operations that alternately switch the positive and negative input terminals and the positive and negative output terminals of the first integrator in accordance with a second clock signal (φ2) that is in phase opposite to the first clock signal. A second integrator (2) also of a differential configuration is arranged in a subsequent stage of the first integrator.

[0008] On the input side of the second integrator and on one side of the differential configuration, a sampling capacitive element (Cs2) and an adding capacitive element (Cas) sample the first output signal of the first integrator in accordance with the second clock signal. An odd-numbered subtraction capacitive element (Caa) samples the second output signal of the first integrator in accordance with the odd-numbered clock (φ2a) of the second clock signal, and an even-numbered subtraction capacitive element (Cab) samples the second output signal in accordance with the even-numbered clock (φ2b) of the second clock signal.

[0009] The sampling capacitors, the summing capacitors, and the odd-numbered subtraction capacitors integrate the sampled charges in accordance with odd-numbered clocks (φ1a) of the first clock signal, and the sampling capacitors, the summing capacitors, and the even-numbered subtraction capacitors integrate the sampled charges in accordance with even-numbered clocks (φ1b) of the first clock signal. On the other side of the differential configuration, the first output signal and the second output signal are interchanged, and the same operation as on the one side is performed.

[0010] By configuring it in this way, it is possible to add the charge sampled from the output signal of the first integrator by the above operation at the input side of the second integrator as a value at the same timing as the first integrator, without having to provide an adder circuit equipped with an operational amplifier or the like that generates excess current consumption.

[0011] According to a battery impedance measuring device described in claim 2, the device includes the delta-sigma A / D converter (5) described in claim 1, and measures the terminal voltage of a secondary battery (23) and the current flowing through the secondary battery using the delta-sigma A / D converter. The device measures the impedance of the secondary battery based on the measured terminal voltage and current. Generally, measuring battery impedance requires measurement in a low frequency band of approximately 0.1 Hz to 1 kHz, and the A / D converter is also required to have low noise in the same frequency band. When the A / D converter includes, for example, an operational amplifier configured with a MOSFET, the level of low-frequency noise due to flicker noise is high, and chopping technology is used to reduce this noise. Therefore, it is desirable to use the delta-sigma A / D converter described in claim 1 in a device for measuring battery impedance. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a delta-sigma A / D converter according to a first embodiment. [Figure 2] Functional block diagram showing a second-order delta-sigma A / D converter configured with a general summing circuit [Figure 3] Functional block diagram showing a configuration equivalent to that shown in Figure 2 [Figure 4] A diagram showing the waveforms of the clock signals that control the delta-sigma A / D converter. [Figure 5] Diagram explaining the operation of the first integrator (part 1) [Figure 6] Diagram explaining the operation of the first integrator (part 2) [Figure 7] Diagram explaining the operation of the first integrator (part 3) [Figure 8] Diagram explaining the operation of the second integrator (part 1) [Figure 9] Diagram explaining the operation of the second integrator (part 2) [Figure 10] Diagram explaining the operation of the second integrator (part 3) [Figure 11] Diagram explaining the operation of the second integrator (part 4) [Figure 12]A diagram showing the operation of the pseudo-adder circuit [Figure 13] FIG. 10 is a diagram illustrating a configuration of a delta-sigma A / D converter according to a second embodiment. [Figure 14] Functional block diagram showing a second-order delta-sigma A / D converter configured with a general summing circuit [Figure 15] Functional block diagram showing a configuration equivalent to that shown in FIG. 14 [Figure 16] FIG. 10 is a diagram illustrating the configuration of a battery impedance measuring device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] (First embodiment) The CIFF-type second-order delta-sigma A / D converter of this embodiment shown in Figure 1 is derived based on the block configuration of the A / D converter shown in Figure 2. In Figure 2, a first integrator and a second integrator are connected in series, and the output of the first integrator is doubled and added to the output of the second integrator by an adder. The result of this addition is input to a quantizer. This configuration is equivalent to the configuration shown in Figure 3, in which an adder is placed on the input side of the second integrator and the doubled output of the first integrator is added to the same output multiplied by -2 via a delay.

[0014] The delta-sigma A / D converter of this embodiment is implemented as a differential circuit based on the block configuration shown in Fig. 3, and chopping is performed on the input side of the first integrator 1. The delta-sigma A / D converter operates using eight types of clock signals shown in Fig. 4. φ1: Master clock signal, equivalent to the first clock signal. φ1+: Output if the quantizer output is L φ1-: Output if the quantizer output is H φ1a: Odd-numbered clock of φ1 φ1b: Even-numbered clock of φ1 φ2: A clock signal that is the opposite phase of φ1. It corresponds to the second clock signal. φ2a: Odd-numbered clock of φ2 φ2b: The even-numbered clock of φ2 Moreover, regarding the odd-numbered and even-numbered ones, they are relative when the left end of the clock signal φ1 shown in FIG. 4 is, for example, set to "1". Also, for the switches described below, those turned on and off by the above respective clock signals are shown with the clock types attached.

[0015] A series circuit of a switch φ1, a capacitor Cs1 which is a sampling capacitance element, and a first chopping switch 12 is connected to each input terminal of an operational amplifier 11 constituting the first integrator 1. The first chopping switch 12 is composed of two switches φ2a and two switches φ2b. The two switches φ2a are directly connected to each input terminal, and the two switches φ2b are connected so as to cross the positive input terminal and the negative input terminal.

[0016] One end of a capacitor Cd1 constituting a D / A converter 13 and one end of a switch φ1 are connected to the common connection point of the capacitor Cs1 and the first chopping switch 12. The other end of the capacitor Cd1 is commonly connected to one end of switches φ1-, φ1- and φ2, and the other ends of these and the switch φ1 are connected to a reference voltage Vr-, Vr+ and a reference voltage respectively. The reference voltage is, for example, an analog ground level, and the magnitude relationship of these voltages is set to (Vr- < reference voltage < Vr+). The first and second chopping switches 12 and 14 correspond to input-side chopping switches.

[0017] A series circuit of a second chopping switch 14, a capacitor Cf1, and a third chopping switch 15 is connected between the input and output sides of the operational amplifier 11. Like the chopping switch 12, these chopping switches 14 and 15 are composed of two switches φ2a and two switches φ2b. The switch φ2a is connected straight between the negative input terminal and the positive output terminal, and between the positive input terminal and the negative output terminal, while the switch φ2b is connected crosswise so that the polarity of the input side and the output side is reversed. The third chopping switch 15 corresponds to an output side chopping switch. Either the positive side or the negative side output signal of the first integrator 1 corresponds to the first output signal, and the other corresponds to the second output signal.

[0018] A pseudo-adder circuit 3 is disposed between the first integrator 1 and the second integrator 2. A switch φ2, a parallel circuit of capacitors Cs2 and Cas, and a series circuit of a switch φ1, which constitute one polarity side of the pseudo-adder circuit 3, are connected between the output line 16 of the first integrator 1 and the negative input terminal of the operational amplifier 18 that constitutes the second integrator 2. The configuration between the output line 17 of the first integrator 1 and the positive input terminal of the operational amplifier 18 is similar.

[0019] as A series circuit of switch φ2a and capacitor Caa, and a series circuit of switch φ2b and capacitor Cab are connected between the output line 17 and the common connection point of capacitors Cs2, Cas, and switch φ1. Switches φ1a and φ1b are connected between the common connection point of each series circuit and a reference voltage, respectively. The configuration on the side connected to output line 16 is similar. A switch φ2 is connected between the common connection point of capacitors Cs2, Cas, and switch φ1 and the reference voltage. The capacitances of capacitors Cas, Caa, and Cab are set to be equal. Capacitors Cas, Caa, and Cab correspond to the capacitance elements for addition, odd-number subtraction, and even-number operation, respectively.

[0020] A capacitor Cf2 is connected between the input and output terminals of the operational amplifier 18 that constitutes the second integrator 2, and the output terminal is connected to the input terminal of the quantizer 4. The pseudo-adder circuit 3 performs addition with a gain of "2" while utilizing the configuration of the second integrator 2, as will be explained below. The above components constitute the delta-sigma A / D converter 5.

[0021] Next, the operation of this embodiment will be described. First, the operation of the first integrator 1 will be described. In the following Figures 5 to 11, in order to make the operation easier to understand, the illustration of each switch is omitted as appropriate, and the switch parts that are turned on in accordance with each clock are shown by solid lines.

[0022] <φ1: Sampling phase> In the sampling phase shown in FIG. 5, the capacitor Cs1 is charged by the input voltage and sampling is performed.

[0023] <φ2a: Integration phase a> In the integration phase a shown in FIG. 6, the charges on the capacitors Cs1 and Cd1 are integrated onto the capacitor Cf1.

[0024] <φ2b: Integration phase b> In the integration phase b shown in FIG. 7, while the polarities of the input and output terminals of the operational amplifier 11 are switched by the chopping switches 12, 14, and 15, the charges of the capacitors Cs1 and Cd1 are integrated in the capacitor Cf1.

[0025] Next, we will explain the operation of the pseudo adder circuit 3 and the second integrator 2. In the operation of the second integrator 2 shown in Figures 8 to 11, four phases are repeatedly executed by cyclically generating clocks such as φ1a → φ2a → φ1b → φ2b → φ1a → .... Also, explanations involving positive and negative polarities will be given for the upper side in the figures, which is one side of the differential configuration.

[0026] <φ1a: 1st phase> In the first phase shown in FIG. 8, the charges on the capacitors Caa, Cas and Cs2 are added to the capacitor Cf2.

[0027] <φ2a: Second Phase> In the second phase shown in FIG. 9, the capacitors Cas and Cs2 are charged with the positive output of the first integrator 1 and sampled, and the capacitor Caa is charged with the negative output of the first integrator 1 and sampled.

[0028] <φ1b: Third Phase> In the third phase shown in FIG. 10, the charges on the capacitors Cab, Cas and Cs2 are added to the capacitor Cf2.

[0029] <φ2b: 4th phase> In the fourth phase shown in FIG. 11, the capacitors Cas and Cs2 are charged with the positive output of the first integrator 1 and sampled, and the capacitor Cab is charged with the negative output of the first integrator 1 and sampled.

[0030] As a result of repeating the above operations, the time-series calculations for the first and third phases are as shown in Figure 12. The output of each addition result is added with twice the value of the input at that time, but at the timing of the next addition, the doubled value added previously is subtracted. In this way, the input voltages are cumulatively added in sequence.

[0031] As described above, according to this embodiment, in the delta-sigma A / D converter 5, the first integrator 1 samples the input voltage in accordance with the first clock signal φ1. The first to third chopping switches 12, 14, and 15 perform a chopping operation of alternately switching the positive and negative input terminals and the positive and negative output terminals of the first integrator 1 in accordance with the second clock signal φ2.

[0032] On the input side of the second integrator 2 and one side of the differential configuration, the sampling capacitive element Cs2 and the summing capacitive element Cas sample the first output signal of the first integrator 1 in accordance with the second clock signal φ2. The odd-numbered subtraction capacitive element Caa1 samples the second output signal of the first integrator in accordance with the odd-numbered clock φ2a of the second clock signal, and the even-numbered subtraction capacitive element Cab samples the second output signal in accordance with the even-numbered clock φ2b of the second clock signal.

[0033] The sampling capacitor Cs2, the summing capacitor Cas, and the odd-numbered subtraction capacitor Caa integrate the sampled charges in accordance with the odd-numbered clock φ1a of the first clock signal, and the sampling capacitor Cs2, the summing capacitor Cas, and the even-numbered subtraction capacitor Cab integrate the sampled charges in accordance with the even-numbered clock φ1b of the first clock signal. On the other side of the differential configuration, the first output signal and the second output signal are interchanged, and the same operation as on the one side is performed.

[0034] By configuring it in this manner, it is possible to add the charge sampled from the output signal of the first integrator 1 by the operation of the pseudo-adder circuit 3 arranged on the input side of the second integrator 2 as a value at the same timing as the first integrator 1, without having to provide an adder circuit equipped with an operational amplifier or the like that generates excess current consumption.

[0035] (Second embodiment) Hereinafter, the same parts as in the first embodiment will be assigned the same reference numerals and their explanation will be omitted, and only different parts will be explained. The delta-sigma A / D converter 6 of the second embodiment shown in Fig. 13 has a configuration in which the pseudo adder circuit 3 of the delta-sigma A / D converter 5 of the first embodiment is replaced with a pseudo adder circuit 7. The delta-sigma A / D converter 6 has a forward path in the pseudo adder circuit 7 for adding the voltages input to the first integrator 1.

[0036] 2 and 3 of the first embodiment, if the block configuration shown in Fig. 14 is assumed, it becomes equivalent to the block configuration shown in Fig. 15, and the latter block configuration is implemented as a differential circuit to form the delta-sigma A / D converter 6. The input terminals of the delta-sigma A / D converter 6 are designated as 8M and 8P, respectively, and the configuration of the upper side of the pseudo adder circuit 7 in the figure will be described below.

[0037] Between the input terminal 8M and the common connection point of the capacitors Cs2 to Cab, there is connected a series circuit of a switch φ2 and a capacitor Cbs, which is an adding capacitance element. Between the input terminal 8P and the common connection point, there are connected in parallel a series circuit of a switch φ2a and a capacitor Cba, which is an odd-number subtraction capacitance element, and a series circuit of a switch φ2b and a capacitor Cbb, which is an even-number subtraction capacitance element. Between the common connection point of each series circuit and a reference voltage, there are connected switches φ1a and φ1b, respectively. In the configuration on the lower side of the figure, the input terminals 8M and 8P are swapped with those in the configuration described above. The operation of the parts added to the pseudo adding circuit 7 is the same as that of the corresponding capacitance elements in the first embodiment.

[0038] (Third embodiment) The third embodiment shown in Fig. 16 shows a configuration in which the delta-sigma A / D converter 5 of the first embodiment is applied to a lock-in amplifier type battery impedance measuring device 21. Hereinafter, this will be simply referred to as the measuring device 21. The measuring device 21 is configured as an IC, and measures the impedance of each of 24 unit cells 23(1) to 23(24) that make up an assembled battery 22. A series circuit of a load 24, an N-channel MOSFET 25, and a shunt resistor Rsh is connected in parallel to the assembled battery 22.

[0039] An RC filter 26 is connected to each unit cell 23, which is a secondary battery, and both ends of a capacitor constituting the RC filter 26 are connected to each input terminal of a delta-sigma A / D converter 5, indicated by "ADC" in the figure. That is, the terminal voltage of the unit cell 23 is measured and A / D converted by the delta-sigma A / D converter 5. The data output from the delta-sigma A / D converter 5 is input to a decimation filter 27, which performs a data thinning process. The output of the decimation filter 27 is branched into two and input to an impedance calculation unit 30 via a multiplier 28I and an LPF 29I, and a multiplier 28Q and an LPF 29Q. The SIN signal and the COS signal generated by a SIN / COS generation unit 31 are input to the multipliers 28I and 28Q, and orthogonal transformation is performed.

[0040] A set of A / D converter 5 to LPF 29 is also provided for shunt resistor Rsh, and each input terminal of the corresponding A / D converter 5 is connected to both ends of shunt resistor Rsh via a resistive element Rz. A capacitor Cz is also connected between the above input terminals. A PWM (Pulse Width Modulation) signal or a PDM (Pulse Density Modulation) signal output from a PWM / PDM modulator 33 is applied to the gate of FET 25. When FET 25 is turned on, the A / D converter 5 detects a terminal voltage corresponding to the current flowing from the battery pack 22 through the load 24 to the shunt resistor Rsh.

[0041] The impedance calculation unit 30 receives each input and outputs the calculated impedance of the unit cell 23 to a register 32. An interface 34 for communicating with the outside is connected to the register 32, and the impedance value data stored in the register 32 is transmitted to an external higher-level control device or the like. By writing data to the register 32 from the outside via the interface 34, the frequency setting of the SIN / COS generation unit 31 and the modulation method of the PWM / PDM modulator 33 are set. Furthermore, when the register 32 receives a measurement start command via the interface 34, the SIN / COS generation unit 31 starts operating, and accordingly the PWM / PDM modulator 33 outputs a modulated excitation signal.

[0042] Generally, when measuring the impedance of a battery, measurements must be made in a low frequency band of about 0.1 Hz to 1 kHz, and the A / D converter must also have low noise in the same frequency band. If the A / D converter includes an operational amplifier configured with, for example, a MOSFET, the level of low-frequency noise due to flicker noise is high. This noise can be reduced by chopping, so a delta-sigma A / D converter 5 is suitable for the device 21 that measures the impedance of the unit cell 23.

[0043] (Other embodiments) The present invention may be applied to devices other than battery impedance measuring devices. Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0044] In the drawing, 1 denotes a first integrator, 2 denotes a second integrator, 3 denotes a pseudo-adder circuit, 4 denotes a quantizer, 5 denotes a delta-sigma A / D converter, and Cs2, Cas, Caa, and Cbb denote capacitors.

Claims

1. a first integrator (1) having a differential configuration and sampling an input voltage in accordance with a first clock signal (φ1); input-side and output-side chopping switches (12, 14, 15) that perform a chopping operation of alternately switching the positive and negative input terminals and the positive and negative output terminals of the first integrator in accordance with a second clock signal (φ2) that is in opposite phase to the first clock signal; a second integrator (2) having a differential configuration and arranged in a subsequent stage of the first integrator; is arranged on the input side of the second integrator, On one side of the differential arrangement: a sampling capacitive element (Cs2) and a summing capacitive element (Cas) that sample the first output signal of the first integrator in accordance with the second clock signal; an odd-numbered subtraction capacitance element (Caa) that samples the second output signal of the first integrator in accordance with an odd-numbered clock (φ2a) of the second clock signal; an even-numbered subtraction capacitance element (Cab) that samples the second output signal in accordance with an even-numbered clock (φ2b) of the second clock signal; Integrating the sampled charges in the sampling capacitor, the addition capacitor, and the odd-numbered subtraction capacitor in accordance with the odd-numbered clock (φ1a) of the first clock signal; operates to integrate the charges sampled in the sampling capacitance element, the addition capacitance element, and the even-numbered subtraction capacitance element in accordance with an even-numbered clock (φ1b) of the first clock signal; On the other side of the differential configuration, the delta-sigma A / D converter exchanges the first output signal with the second output signal and performs the same operation as on the one side.

2. A delta-sigma A / D converter (5) according to claim 1 is provided, A battery impedance measuring device that measures the terminal voltage of a secondary battery (23) and the current flowing through the secondary battery using the delta-sigma A / D converter, and measures the impedance of the secondary battery based on the measured terminal voltage and current.

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