VFET contact formation

Abstract

An embodiment of the present invention may include a vertical field effect transistor (VFET) structure having a first VFET and a second VFET, and a method for fabricating the structure. The first VFET may include one liner between the first source / drain epitaxial layer and the contact. The second VFET may include two liners between the second source / drain epitaxial layer and the contact. This may allow for proper contact liner matching for different VFET devices.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor devices, and more particularly to contact formation in vertical field effect transistors (VFETs). [Background technology]

[0002] VFETs have been pursued as a potential device option for scaling complementary metal-oxide semiconductor (CMOS) technology to the 5-nanometer (nm) node and beyond. In contrast to planar CMOS devices, VFETs are arranged vertically, with a vertical fin or nanowire extending upward from a substrate. This fin or nanowire forms the transistor's channel region. Source and drain regions are in electrical contact with the top and bottom of the channel region, and a gate is located on one or more of the sidewalls of the fin or nanowire. Thus, in a VFET, the direction of current flow between the source and drain regions is perpendicular to the major surface of the substrate.

[0003] A key feature of VFETs is their flexibility in vertical device scaling, which allows them to operate without lateral scaling constraints. The ability to select appropriate silicide and contact liner for the source / drain epitaxial regions is a key factor in tailoring the contact resistance of such devices. Conventional techniques allow for such liner selection, but at the cost of additional lithography steps.

[0004] Therefore, there is a need in the art to solve the aforementioned problems. Summary of the Invention

[0005] Viewed from a first aspect, the present invention provides a semiconductor device comprising: a first vertical field effect transistor (VFET), the first VFET having a first source / drain epitaxial layer and at least one liner between the first source / drain epitaxial layer and a first contact; and a second VFET, the second VFET having a second source / drain epitaxial layer and at least two liners between the second source / drain epitaxial layer and a second contact, the number of liners on the second VFET being greater than the number of liners on the first VFET.

[0006] Viewed from a further aspect, the present invention provides a method of forming a semiconductor device, the method including forming a first vertical field effect transistor (VFET) having a first source / drain epi and a second VFET having a second source / drain epi; performing a first ion implant into the second source / drain epi to form implanted source / drain epi; selectively depositing a first liner metal on the implanted source / drain epi; and performing a second ion implant, wherein the second ion implant is a blanket ion implant, and the first liner metal prevents implantation into the second source / drain epi.

[0007] Viewed from a further aspect, the present invention provides a semiconductor device comprising a first vertical field effect transistor (VFET), the first VFET having a first source / drain epi and one liner between the first source / drain epi and a first contact, and a second VFET having a second source / drain epi and two liners between the second source / drain epi and a second contact.

[0008] Viewed from a further aspect, the present invention provides a method of forming a semiconductor device, the method including forming a first vertical field effect transistor (VFET) having a first source / drain epi and a second VFET having a second source / drain epi; performing a first ion implant into the second source / drain epi to form implanted source / drain epi; selectively depositing a first liner metal on the implanted source / drain epi; and performing a second ion implant, wherein the second ion implant is a blanket ion implant, and the first liner metal prevents implantation into the second source / drain epi.

[0009] Viewed from a further aspect, the present invention provides a method of forming a semiconductor device, the method including: forming a first vertical field effect transistor (VFET) having a first source / drain epitaxial layer and a second VFET having a second source / drain epitaxial layer; forming a cap on the first source / drain epitaxial layer; performing a first ion implantation into the second source / drain epitaxial layer to form implanted source / drain epitaxial layers, the first ion implantation being a blanket ion implantation, the cap preventing implantation into the first source / drain epitaxial layer; and selectively depositing a first liner metal on the implanted source / drain epitaxial layers, the second ion implantation being a blanket ion implantation, the first liner metal preventing implantation into the second source / drain epitaxial layer.

[0010] Embodiments of the present invention may include a vertical field effect transistor (VFET) structure having a first VFET and a second VFET. The first VFET may include one liner between the first source / drain epi and the contact. The second VFET may include two liners between the second source / drain epi and the contact. This may allow for proper contact liner matching for different VFET devices.

[0011] Embodiments may further include the first VFET as a pFET and the second VFET as an nFET, which may allow for proper contact liner matching for different pFET and nFET devices.

[0012] Embodiments may further include a pFET liner located over the titanium liner over the second VFET, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0013] Embodiments may further include a top surface of the first source / drain epi below a top surface of the second source / drain epi, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0014] Embodiments may further include a titanium liner containing a pFET dopant, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0015] Embodiments of the present invention may include a vertical field effect transistor (VFET) structure having a first VFET and a second VFET. The first VFET may include at least one liner between the first source / drain epitaxial layer and the contact. The second VFET may include at least two liners between the second source / drain epitaxial layer and the contact. This may allow for proper contact liner matching for different VFET devices. The number of liners on the second VFET may be greater than the number of liners on the first VFET.

[0016] Embodiments may further include the first VFET as a pFET and the second VFET as an nFET, which may allow for proper contact liner matching for different pFET and nFET devices.

[0017] Embodiments may further include a pFET liner located over the titanium liner over the second VFET, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0018] Embodiments may further include a top surface of the first source / drain epi below a top surface of the second source / drain epi, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0019] Embodiments may further include a titanium liner containing a pFET dopant, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0020] Embodiments may include a method of forming a VFET structure. The method may include forming a first VFET having a first source / drain epi and a second VFET having a second source / drain epi. The method may include performing a first ion implant into the second source / drain epi to form an implanted source / drain epi. The method may include selectively depositing a first liner over the implanted source / drain epi. The method may include performing a second blanket implant, which may enable proper contact liner matching for different devices.

[0021] Embodiments may further include the first VFET as a pFET and the second VFET as an nFET, which may allow for proper contact liner matching for different pFET and nFET devices.

[0022] Embodiments may further include a pFET liner located over the titanium liner over the second VFET, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0023] Embodiments may further include a top surface of the first source / drain epi below a top surface of the second source / drain epi, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0024] Embodiments may further include a titanium liner containing a pFET dopant, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0025] Embodiments may include a method of forming a VFET structure. The method may include forming a first VFET having a first source / drain epi and a second VFET having a second source / drain epi. The method may include forming a cap over the first source / drain epi. The method may include performing a first ion implantation into the second source / drain epi to form an implanted source / drain epi, the cap preventing ion implantation into the first source / drain epi. The method may include selectively depositing a first liner over the implanted source / drain epi. The method may include performing a second blanket implant, which may enable proper contact liner matching for different devices.

[0026] Embodiments may further include the first VFET as a pFET and the second VFET as an nFET, which may allow for proper contact liner matching for different pFET and nFET devices.

[0027] Embodiments may further include a pFET liner located over the titanium liner over the second VFET, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0028] Embodiments may further include a top surface of the first source / drain epi below a top surface of the second source / drain epi, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0029] Embodiments may further include a titanium liner containing a pFET dopant, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0030] In embodiments, forming the cap may include depositing a dielectric over the first source / drain epi and planarizing the dielectric so that a top surface of the cap is substantially coplanar with a top surface of the second source / drain epi, which may allow proper contact liner matching for different pFET and nFET devices while minimizing process steps.

[0031] The invention will now be described, by way of example only, with reference to preferred embodiments as illustrated in the following figures. [Brief explanation of the drawings]

[0032] [Figure 1] 1A-1C illustrate two VFET structures in a first region and a second region before forming a top contact according to an example embodiment. [Figure 2] 1A-1C illustrate two VFET structures after deposition of dummy contacts according to an example embodiment. [Figure 3] 10 shows two VFET structures after removing the dummy contacts on top of the pFET structure and growing the top S / D epitaxy of the PFET while the NFET region is covered with a contact mask, according to an example embodiment. [Figure 4] 1A-1C illustrate two VFET structures after deposition of a protective dielectric, according to an example embodiment. [Figure 5] FIG. 1 illustrates two VFET structures after chemical mechanical polishing (CMP) according to an example embodiment. [Figure 6] FIG. 10 illustrates two VFET structures after removing the dummy contacts over the second region and forming a second epilayer, according to an example embodiment. [Figure 7] 1A-1C illustrate two VFET structures after deposition of a top dielectric, according to an example embodiment. [Figure 8] 1A-1C illustrate two VFET structures after forming trenches in the top dielectric according to an example embodiment. [Figure 9] 10A-10C illustrate low energy implantation and selective metal formation at second region contacts according to an example embodiment. [Figure 10] 10A-10C illustrate silicide formation in second area contacts according to example embodiments. [Figure 11] 1A-1C illustrate the removal of protective oxide over contacts in the first region according to an exemplary embodiment. [Figure 12] 1A-1C illustrate low energy implantation and contact liner deposition at contacts in a first region according to an exemplary embodiment. [Figure 13] 10A-10C illustrate the formation of silicide in first region contacts according to an example embodiment. [Figure 14] 1A-1C illustrate deposition of metal contacts according to an exemplary embodiment.

[0033] Elements in the figures are not necessarily to scale and are not intended to depict specific parameters of the invention. Dimensions of elements may be exaggerated for clarity and ease of illustration. For exact dimensions, reference should be made to the detailed description. The drawings are intended to depict only typical embodiments of the invention and therefore should not be considered as limiting the scope of the invention. Like numbering in the drawings represents like elements. DETAILED DESCRIPTION OF THE INVENTION

[0034] Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0035] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods as shown in the drawings. Terms such as "above," "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, although there may be an intervening element, such as an interfacial structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0036] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some instances may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on unique features or elements of various embodiments of the present invention.

[0037] The ability to select appropriate silicide and contact liner for the source / drain epitaxial regions is a key factor for tailoring the contact resistance of such devices. Conventional techniques allow for such liner selection at the expense of additional lithography steps. The proposed method and resulting structure allows for appropriate silicide formation for nFET and pFET devices, ensuring that materials from one type of device do not adversely affect the other, while minimizing additional lithography steps.

[0038] Referring to FIG. 1 , two VFET structures are depicted, a pFET in a first region 10 and an nFET in a second region 20, prior to forming top contacts, according to an exemplary embodiment. The pFET structure in the first region 10 includes a first fin 101 disposed on a substrate 100, and the nFET structure in the second region 20 includes a second fin 102 disposed on the substrate 100. The first region 10 and the second region 20 are separated by a shallow trench isolation (STI) 110. Located on the surface of the substrate 100 and in contact with the first fin 101 in the first region 10 is a pFET source / drain 120. Located on the surface of the substrate 100 and in contact with the second fin 102 in the second region 20 is an nFET source / drain 125. A bottom spacer 130 may be disposed on the pFET source / drain 120 and the nFET source / drain 125. A gate stack 140 may be disposed in contact with the first fin 101 and the second fin 102. A protective cap 150 may be disposed over the gate stack 140, and a first interlayer dielectric (ILD) 170 may fill the remainder of the hierarchy. A trench formed in the ILD 170 may expose the top surfaces of the first fin 101 and the second fin 102. A top spacer 160 may be disposed in the trench while still exposing a portion of the first fin 101 and the second fin 102.

[0039] The first fin 101 and the second fin 102 may be formed from a layer on top of the substrate 100. According to an exemplary embodiment, the substrate 100 is a bulk semiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge), or bulk III-V semiconductor wafer, or a combination thereof. Alternatively, the substrate 100 may be a semiconductor-on-insulator (SOI) wafer. An SOI wafer includes an SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide, it is referred to herein as a buried oxide, or BOX. The SOI layer may include any suitable semiconductor, such as Si, Ge, SiGe, or a III-V semiconductor, or a combination thereof. The substrate 100 may already have pre-built structures (not shown), such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc.

[0040] Shallow trench isolation (STI) regions 110 are frequently used in semiconductor technology to isolate active areas within a substrate 100 and prevent current leakage between adjacent components. Processes for forming STI regions 110 are well known in the art and generally involve etching the substrate 100 to form recesses that can later be filled with an insulating material using any deposition method known in the art. In some embodiments, the STI regions 108 may be composed of any low-k material, including, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, or fluoride-doped silicate glass.

[0041] The pFET source / drains 120 and nFET source / drains 125 may be formed from different epitaxial materials. The epitaxial materials can be grown from gas or liquid precursors. The epitaxial materials can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium, germanium or carbon doped silicon (Si:C), or combinations thereof, can be doped during deposition (in-situ doping) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration of the bottom S / D region 106 is 1×10 19 cm -3 From 2 x 10 21 cm -3 in the range of 2 x 10 20 cm -3 and 1×10 21 cm -3 It can be between.

[0042] The bottom spacer 130 can include a dielectric material such as, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof. The dielectric material can be a low-k material having a dielectric constant of less than about 7, less than about 5, or even less than about 2.5. The bottom spacer 130 can be formed using a combination of known deposition and etching processes, such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, and etching processes including reactive ion etching (RIE), wet etching, or isotropic gas-phase dry etching.

[0043] As shown, the gate stack 140 is formed in direct contact with the channel fin 112. For ease of illustration, the gate stack 140 is depicted as only one layer. However, as known by those skilled in the art, the gate stack 140 may include a gate dielectric and a gate conductor / metal (e.g., a work function metal (WFM)) deposited on the bottom spacer 130 and adjacent to a portion of the channel fin 112. In some embodiments, the gate stack 140 is deposited by ALD.

[0044] The gate dielectric (not shown) can be formed from one or more gate dielectric films. The gate dielectric film can be, for example, a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of materials suitable for the high-k film include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials having a dielectric constant greater than 7.0 include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium tantalum lead oxide, and zinc lead niobate. The gate dielectric film can further include dopants such as lanthanum and aluminum. The gate dielectric film can be formed by any suitable deposition process, such as CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes. The thickness of the gate dielectric film can vary depending on the deposition process as well as the composition and number of high-k materials used.

[0045] The gate conductor (not shown) of the gate stack 140 can comprise doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material may further include dopants incorporated during or after deposition. In some embodiments, the gate conductor can be a WFM deposited on the gate dielectric film by a suitable deposition process, such as, for example, CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering. The type of WFM depends on the type of transistor and can differ between n-FET and p-FET devices. P-type WFMs include compositions such as titanium nitride (TiN), ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. N-type WFMs include compositions such as titanium carbide (TiC), titanium aluminum carbide (TiAlC), hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, or any combinations thereof. The gate conductor can further include tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), or nickel (Ni) material on the WFM layer of the gate conductor. The gate conductor can be deposited by a suitable deposition process, such as, for example, CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering.

[0046] In this embodiment, the gate stack 140 is conformally deposited. After the deposition of the gate stack 140, a patterning process is performed to etch away the unwanted gate stack 140.

[0047] A protective cap 150 may be located above the gate stack 140 and may act as a protective layer over the gate stack 140. In an exemplary embodiment, the protective cap may be SiN.

[0048] The first ILD 170 is formed to fill gaps between gate structures and other existing devices. The first ILD 170 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the first ILD 170 may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics. After deposition of the first ILD 170, trenches may be formed using lithography and etching techniques to expose the top surfaces of the first fin 101 and the second fin 102.

[0049] The top spacer 160 can include a dielectric material such as, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof. The dielectric material can be a low-k material having a dielectric constant of less than about 7, less than about 5, or even less than about 2.5. The top spacer 160 can be formed using a combination of known deposition and etching processes, such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, and etching processes including reactive ion etching (RIE), wet etching, or isotropic vapor-phase dry etching. After deposition, a chemical-mechanical polishing (CMP) process is performed to remove excess dielectric from the top surface of the first ILD 170.

[0050] Referring to FIG. 2 , according to an exemplary embodiment, a dummy contact 180 may be deposited on the VFET structure. In such an embodiment, the dummy contact 180 may be made of any suitable sacrificial material, such as amorphous silicon, polycrystalline silicon, or amorphous carbon. The dummy layer may be deposited by any suitable deposition technique known in the art, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), or liquid mist chemical vapor deposition (LSMCD). Following deposition, a chemical-mechanical polishing (CMP) process is performed to remove excess dielectric from the top surface of the first ILD 170, so that the only remaining portion of the dummy layer is the dummy contact 180.

[0051] Referring to FIG. 3 , an exemplary embodiment may involve forming a contact mask 190, removing the dummy contact 180 over the pFET structure, and forming a first epi-contact 200. The contact mask 190 is formed to cover the dummy contact 180 in the second region 20. Suitable materials for the contact mask 190 include, but are not limited to, nitride materials such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), or a combination thereof, or oxide materials such as silicon oxide (SiOx), or both. The contact mask 190 may be deposited using any typical technique and patterned using a lithography process, after which the unpatterned material may be etched away.

[0052] The dummy contacts 180 may be removed by any suitable etching process known in the art that can selectively remove the dummy contacts 180 without substantially removing material from the surrounding structure. In an exemplary embodiment, the dummy contacts 180 may be removed by, for example, a reactive ion etching (RIE) process that can selectively remove silicon. Wet chemistry can be used to selectively remove a-Si (e.g., (NH4)OH).

[0053] The first epi contact 200 can be grown in the void created by the removal of the dummy contact 180 in the first region 10. The first epi contact 200 can be made of any suitable source / drain material and can be grown to a height just below the top of the first ILD 170, which can allow for the formation of a protective cap 215 deep enough to protect the first epi contact 200 from ion implantation. For example, the first epi contact 200 can be about 10 to about 20 nm below the top surface of the ILD 170, although other distances are contemplated based on the ion implantation process used. The epitaxial material can be grown from gas or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium, germanium or carbon doped silicon (Si:C), or a combination thereof, can be doped during deposition (in situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic), or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration in the bottom S / D region 106 is between 1×10 19 cm -3 From 2 x 10 21 cm -3 in the range of 2 x 10 20 cm -3 and 1×10 21 cm -3It can be between.

[0054] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or epitaxially grown" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the grown semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In an epitaxial deposition process, chemical reactants supplied from gas sources are controlled and system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move across the surface in the direction of the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which it was formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystal plane will have a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to formation on semiconductor surfaces and generally does not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0055] In some embodiments, the gas source for deposition of epitaxial semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon (Si) layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. An epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. A carrier gas such as hydrogen, nitrogen, helium, or argon can be used.

[0056] Referring to FIG. 4 , according to an exemplary embodiment, deposition of a protective dielectric 210 may occur. The protective dielectric 210 may be selected to be selectively removed relative to each of the first ILD 170 and the top spacer 160. The protective dielectric 210 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the protective dielectric 210 may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k materials, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics. In an exemplary embodiment, the protective dielectric may be Si:C or SiBCN.

[0057] Referring to FIG. 5, according to an exemplary embodiment, chemical mechanical polishing (CMP) can create a protective cap 215 from the protective dielectric 210 over the first epi contact 200.

[0058] 6, according to an exemplary embodiment, removal of dummy contact 180 in second region 20 may be performed, followed by formation of second epi-contact 220. Dummy contact 180 may be removed by any suitable etching process known in the art that can selectively remove dummy contact 180 without substantially removing material from the surrounding structure. In an exemplary embodiment, dummy contact 180 may be removed by, for example, a reactive ion etching (RIE) process that can selectively remove silicon.

[0059] The second epi-contact 220 can be grown from a gas or liquid precursor in the void created by the removal of the dummy contact 180 in the second region 20. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. The epitaxial silicon, silicon germanium, germanium- or carbon-doped silicon (Si:C), or combinations thereof, can be doped during deposition (in situ doping) by adding dopants, either n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration in the bottom S / D region 106 is 1×10 19 cm -3 From 4×10 21 cm -3 in the range of 2 x 10 20 cm -3 and 4×10 21 cm -3 It can be between.

[0060] 7, according to an exemplary embodiment, deposition of the upper dielectric layer 230 may occur. The upper dielectric layer 230 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials forming the upper dielectric layer 230 may include silicon oxide, silicon nitride, hydrogenated silicon oxide, silicon-based low-k materials, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics. After deposition of the upper dielectric layer 230, trenches may be formed using lithography and etching techniques to expose the top surfaces of the first fin 101 and the second fin 102.

[0061] 8 , according to an exemplary embodiment, forming a trench in an upper dielectric layer 230 over the first epi contact 200 and the second epi contact 220 may be performed, resulting in a second ILD 235. After depositing the upper dielectric layer 230, forming a trench using lithography and etching techniques may be performed, resulting in the second ILD 235 and exposing the top surfaces of the first fin 101 and the second fin 102.

[0062] Referring to FIG. 9, according to an exemplary embodiment, a low-energy implant may be performed prior to the formation of the second metal contact 240. The ion implantation process may be selected so that the implant depth is no deeper than the protective cap 215. The ion implantation process may be a blanket ion implantation. Alternatively, a selective implantation process may be employed using a patterned mask (not shown) to implant ions only into the second epi contact 220. Alternatively, a mask may be used that allows implantation of different ions and / or ion concentrations. The ions are implanted using a conventional ion beam implanter operating at standard conditions.

[0063] Ions are typically about 5E13 to about 5E15 atoms / cm 2More typically, the ions are implanted at an energy of about 0.5 to about 5 keV using an ion dose of about 3E14 to about 3E15 atoms / cm. 2 The ions are implanted at an energy of about 1 to about 2 keV using an ion dose of 0.01 keV. The implantation is typically performed at a substrate temperature of about room temperature to about 200°C, with a substrate temperature of about room temperature being more typical. Note that the ion dose may vary depending on the particular ions being implanted. The energy selected for the ion implantation is such that the majority of the ion implant remains in the portion of the second epi contact 220 that is consumed during the silicidation process. Illustrative examples of ions that may be employed for nFET materials include, but are not limited to, phosphorus and arsenic. Illustrative examples of ions that may be employed for pFET materials include, but are not limited to, boron, gallium, and aluminum.

[0064] The second metal contact 240 may be made of, for example, tantalum or tantalum nitride, or titanium and titanium nitride, and may include one or more layers of liner material as an adhesion layer for subsequent tungsten deposition. The second metal contact 240 may be formed using a deposition technique, such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, or a combination of methods, and may occur selectively on the exposed portion of the second epi contact 220. In an exemplary embodiment in which the second region 20 includes an nFET device, the use of a titanium liner may allow the selective deposition of titanium to occur primarily on the surface of the second epi contact 220.

[0065] Referring to FIG. 10, according to an exemplary embodiment, the formation of second silicide 250 can occur from second epi contact 220 and second metal contact 240, resulting in second epi contact 225 and second metal contact 245. The annealing step used at this point of the present invention to induce the formation of second silicide 250 is performed at a temperature of about 600°C or higher. Typically, the anneal is performed at a temperature of about 750°C to about 1100°C. The anneal can be performed in an inert atmosphere such as He, Ar, Ne, Kr, Xe, N2, or mixtures thereof, such as He-Ar, or in a reducing environment such as H2 or forming gas. The anneal can be performed for sub-millisecond or longer periods, with anneal times of about 10 seconds to about 30 minutes being more typical. Very short anneals can be achieved using laser annealing. The anneal can be performed using a single annealing temperature or multiple annealing temperatures. The anneal may also include various ramp-up, soak, and cool-down cycles as needed.

[0066] 11, according to an exemplary embodiment, removal of the protective cap 215 over the first epi-contact 200 may occur. Removal of the protective cap 215 may be performed using any selective etching technique, such as RIE, that can remove the dielectric material used to form the protective cap 215 while retaining the second ILD 235.

[0067] Referring to FIG. 12, according to an exemplary embodiment, a low-energy implant in the first epi contact 200 and deposition of the second contact liner 260 can occur. The ion implantation process can be a blanket ion implantation. Alternatively, a selective implantation process can be employed using a patterned mask (not shown) to implant ions only into the second epi contact 220. Alternatively, a mask can be used that can implant different ions and / or ion concentrations. The ions are implanted using conventional ion beam implantation equipment operating at standard conditions.

[0068] Ions are typically about 5E13 to about 5E15 atoms / cm 2 More typically, the ions are implanted at an energy of about 0.5 to about 5 keV using an ion dose of about 3E14 to about 3E15 atoms / cm. 2 The ions are implanted at an energy of about 1 to about 2 keV using an ion dose of 0.01 keV. The implantation is typically performed at a substrate temperature of about room temperature to about 200°C, with a substrate temperature of about room temperature being more typical. Note that the ion dose may vary depending on the particular ions being implanted. The energy selected for the ion implantation is such that the majority of the ion implant remains in the portion of the second epi contact 220 that is consumed during the silicidation process. Illustrative examples of ions that may be employed for nFET materials include, but are not limited to, phosphorus and arsenic. Illustrative examples of ions that may be employed for pFET materials include, but are not limited to, boron, gallium, and aluminum.

[0069] The second contact liner 260 may be made of, for example, tantalum or tantalum nitride, or titanium and titanium nitride, or may include one or more layers of liner material as an adhesion layer for subsequent tungsten deposition. The second contact liner 260 may be formed using a deposition technique, such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, or a combination of methods, and may occur selectively on the exposed portions of the second epi-contact 220. In an exemplary embodiment in which the first region 10 includes a pFET device, the second contact liner 260 may be a high work function metal, such as Pt, Ni, or Pt / Ni. Additionally, additional TiN or TaN may be deposited to promote adhesion between the contact 280 and the resulting first metal contact 265.

[0070] Referring to FIG. 13, according to an exemplary embodiment, formation of a first silicide 270 from the first epi contact 200 and the second contact liner 260 occurs, resulting in the first epi contact 205 and the first metal contact 265. The annealing step used at this point of the present invention to induce the formation of the first silicide 270 is performed at a temperature of about 600°C or higher. Typically, the anneal is performed at a temperature between about 750°C and about 1100°C. The anneal may be performed in an inert atmosphere such as He, Ar, Ne, Kr, Xe, N2, or mixtures thereof, such as He-Ar, or in a reducing environment such as H2 or forming gas. The anneal is performed for sub-millisecond or longer periods, with annealing times of about 10 seconds to about 30 minutes being more typical. Very short anneals are achieved using laser annealing. The anneal may be performed using a single annealing temperature, or multiple annealing temperatures may be used. The anneal may also include various ramp-up, soak, and cool-down cycles as needed.

[0071] 14, according to an exemplary embodiment, deposition of metal contacts 280 may occur. Metal contacts 280 may include, for example, copper, cobalt, aluminum, or tungsten. Metal contacts 280 may be formed using a filing technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, or a combination of methods, may occur selectively on exposed portions, or may be performed with CMP after blanket deposition.

[0072] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to commercially available technology, or to enable others skilled in the art to understand the embodiments disclosed herein. Therefore, it is intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. A semiconductor device, a first vertical field effect transistor (VFET), the first VFET having a first source / drain epi, and at least one liner between the first source / drain epi and a first contact; a second VFET, the second VFET having a second source / drain epi, at least two liners between the second source / drain epi and a second contact, the number of liners on the second VFET being greater than the number of liners on the first VFET; A semiconductor device comprising:

2. the at least one liner between the first source / drain epi and the first contact comprises a single liner between the first source / drain epi and the first contact; the at least two liners between the second source / drain epi and the second contact comprise two liners between the second source / drain epi and the second contact; The semiconductor device according to claim 1 .

3. The semiconductor device of claim 1 , wherein the first VFET comprises a pFET and the second VFET comprises an nFET.

4. 4. The semiconductor device of claim 1, wherein the at least two liners comprise a liner for a pFET overlying a titanium liner.

5. The semiconductor device of claim 1 , wherein the at least one liner comprises a liner for a pFET.

6. 6. The semiconductor device of claim 1, wherein a top surface of the first source / drain epitaxial layer is below a top surface of the second source / drain epitaxial layer.

7. The semiconductor device of claim 4 , wherein the titanium liner comprises a p-type dopant.

8. 1. A method of forming a semiconductor device, comprising: forming a first vertical field effect transistor (VFET) having a first source / drain epi and a second VFET having a second source / drain epi; performing a first ion implant into the second source / drain epi to form an implanted source / drain epi; selectively depositing a first liner metal on the implanted source / drain epi; performing a second ion implantation, the second ion implantation being a blanket ion implantation, the first liner metal preventing implantation into the second source / drain epi; A method comprising:

9. 9. The method of claim 8, wherein the first VFET comprises a pFET and the second VFET comprises an nFET.

10. 10. The method of claim 8 or 9, wherein the first liner metal comprises titanium.

11. 11. The method of any one of claims 8 to 10, wherein a top surface of the first source / drain epi is below a top surface of the second source / drain epi.

12. 12. The method of claim 8, wherein the first liner metal further comprises a p-type dopant.

13. forming a cap on the first source / drain epi; 13. The method of any one of claims 8 to 12, wherein the first ion implant is a blanket ion implant and the cap prevents implantation into the first source / drain epi.

14. forming the cap depositing a dielectric layer over the first source / drain epi; planarizing the dielectric for the cap, wherein a top surface of the cap is substantially coplanar with a top surface of an ILD surrounding the first VFET and the second VFET; 14. The method of claim 13, comprising:

15. 15. The method of claim 13 or 14, wherein forming the cap occurs before forming the second source / drain epi.

16. 16. The method of any one of claims 13 to 15, wherein a top surface of the cap is substantially coplanar with a top surface of the second source / drain epi.

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