Level Shift Circuit

Abstract

To provide a level shift circuit that can transmit a signal even when a power supply potential of a secondary side circuit is less than or equal to GND.SOLUTION: A level shift circuit comprises: a first conductivity type level shift transistor that performs level-shifting of a signal from a primary side circuit to a secondary side circuit between the primary side circuit which has a primary side reference potential as a reference and the secondary side circuit which has a secondary side reference potential being independent of the primary side reference potential as a reference; a diode that is connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit; a capacitor that is connected to the diode in parallel; and an inverter that inverts a signal. A control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit, a second main electrode is connected to an output of the inverter, the inverter operates between the primary side reference potential and the primary side power supply, and the diode is connected to a secondary side power supply of the secondary side circuit through a resistance element.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a level shift circuit that transmits a signal on a low voltage side to a high voltage side having a different reference potential. [Background technology]

[0002] Power device control ICs such as HVICs (High Voltage MOS Gate Driver ICs) are high-voltage ICs that drive the gates of switching devices using input signals from a microcomputer, etc. As shown in Fig. 1 of Patent Document 1, for example, an HVIC includes a high-side gate driver circuit that drives the high-voltage side (high side) switching device and a low-side gate driver circuit that drives the low-voltage side (low side) switching device.

[0003] The high-side gate drive circuit has a high-voltage level shift circuit that transmits the low-voltage signal to the high-voltage side, which has a different reference potential. The high-voltage level shift circuit converts the voltage signal of the primary circuit, which is referenced to ground potential (GND), into a current signal using a high-voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and transmits the current signal to the secondary circuit, which is referenced to floating potential. The transmitted current signal is restored to a voltage signal in the secondary circuit.

[0004] More specifically, when an on-pulse synchronized with the rising edge of the high-side input signal is input to the high-side gate drive circuit, the gate potential of the high-voltage MOSFET in the high-voltage level shift circuit fluctuates from GND to the power supply potential of the primary circuit, opening the gate-source and turning it on. While on, current flows from the power supply of the secondary circuit to GND in the primary circuit via the high-voltage MOSFET. This current signal is converted into a voltage signal by a resistive element in the secondary circuit, transmitting the current signal to the secondary circuit. When an off-pulse synchronized with the falling edge of the high-side input signal is input, the gate potential of the high-voltage MOSFET in the high-voltage level shift circuit fluctuates from the power supply potential of the primary circuit to GND, closing the gate-source and turning it off. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-196276 Summary of the Invention [Problem to be solved by the invention]

[0006] In the case of the conventional high-voltage level shift circuit described above, when the power supply of the secondary circuit falls below GND, the current flowing from the transmission signal source, i.e., the secondary circuit to the primary circuit, is attenuated, which can result in a phenomenon in which signal transmission becomes impossible.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a level shift circuit that can transmit signals even when the power supply of the secondary side circuit falls below GND. [Means for solving the problem]

[0008] A level shift circuit according to the present disclosure is provided between a primary side circuit based on a primary side reference potential and a secondary side circuit based on a secondary side reference potential independent of the primary side reference potential, and includes: a level shift transistor of a first conductivity type that level-shifts a signal from the primary side circuit to the secondary side circuit; a diode connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit; a capacitor connected in parallel with the diode; and an inverter that inverts the signal, wherein a control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit and a second main electrode is connected to an output of the inverter, the inverter operates between the primary side reference potential and the primary side power supply, and the diode is connected to the secondary side power supply of the secondary side circuit via a resistive element. [Effects of the Invention]

[0009] In the level shift circuit according to the present disclosure, when the secondary power supply is equal to or lower than the primary reference potential and the level shift transistor is turned on, the potential of the electrode on the primary circuit side of the capacitor drops to the primary reference potential. At the moment of the drop, the potential of the electrode on the secondary circuit side of the capacitor also drops accordingly, as the potentials of the two electrodes of the capacitor attempt to maintain their held state. The voltage drop is applied to the resistor element, allowing a signal to be transmitted to the secondary circuit. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing the configuration of an HVIC incorporating a high-voltage level shift circuit according to the present disclosure. [Figure 2] 1 is a circuit diagram illustrating a configuration of a high-voltage level shift circuit according to a first embodiment of the present disclosure. [Figure 3] 1 is a circuit diagram illustrating a configuration of a high-voltage level shift circuit according to a first embodiment of the present disclosure. [Figure 4] FIG. 10 is a circuit diagram illustrating a configuration of a high-voltage level shift circuit according to a second embodiment of the present disclosure. [Figure 5] FIG. 10 is a circuit diagram illustrating a configuration of a high-voltage level shift circuit according to a second embodiment of the present disclosure. [Figure 6] This is a circuit diagram showing the configuration of the high-voltage level shift circuit according to Embodiment 3 of the present disclosure. [Figure 7] This is a circuit diagram showing the configuration of the high-voltage level shift circuit according to Embodiment 3 of the present disclosure. Embodiments for Carrying Out the Invention

[0011] <Configuration of HVIC> FIG. 1 is a diagram showing the configuration of an HVIC 100 incorporating the high-voltage level shift circuit according to the present disclosure. The HVIC 100 includes a high-side gate drive circuit 101 that drives a high-side switching device Q1 and a low-side gate drive circuit 102 that drives a low-side switching device Q2. The high-side switching device Q1 and the low-side switching device Q2 are both N-channel MOSFETs, and freewheeling diodes P1 and P2 are connected in anti-parallel, respectively. In FIG. 1, the high-side switching device Q1 and the low-side switching device Q2 are MOSFETs, but an IGBT (Insulated Gate Bipolar Transistor) can also be used.

[0012] Hereinafter, the configuration of the high-side gate drive circuit 101 will be described. The high-side gate drive circuit 101 includes an on-pulse generation circuit 11, an off-pulse generation circuit 12, a high-voltage level shift circuit 13, a high-voltage level shift circuit 14, a resistance element 19, a resistance element 20, a NOT gate 21, a NOT gate 22, a latch circuit 24, and an output circuit 25.

[0013] The high-side input signal HIN input to the high-side gate drive circuit 101 is input to the on-pulse generation circuit 11 and the off-pulse generation circuit 12. The on-pulse generation circuit 11 generates an on-pulse synchronized with the rising timing of the high-side input signal HIN. The off-pulse generation circuit 12 generates an off-pulse synchronized with the falling timing of the high-side input signal HIN.

[0014] The output of the on-pulse generation circuit 11 is connected to the gate of a high-voltage MOSFET for level shifting in the high-voltage level shift circuit 13. The drain of the high-voltage MOSFET is fixed to a high-side power supply voltage VB, which is the power supply for the secondary circuit (referred to as the "secondary-side power supply"), via a resistor element 19, and is connected to the input terminal of a latch circuit 24 via a NOT gate 21. The source of the high-voltage MOSFET is connected to a ground potential GND, which is the reference potential for the primary circuit (referred to as the "primary-side reference potential"). Note that the high-side power supply voltage VB may be referred to as the high-side power supply VB, and the ground potential GND may be simply referred to as GND.

[0015] The output of the off-pulse generating circuit 12 is connected to the gate of a high-voltage MOSFET for level shifting in the high-voltage level shift circuit 14. The drain of the high-voltage MOSFET is fixed to the high-side power supply voltage VB via a resistive element 20, and is connected to the input terminal of a latch circuit 24 via a NOT gate 22. The source of the high-voltage MOSFET is connected to the ground potential GND. The specific configurations of the high-voltage level shift circuits 13 and 14 will be described later.

[0016] The latch circuit 24 is configured by an RS flip-flop circuit or the like, and latches the outputs from the NOT gates 21 and 22 and outputs them to the output circuit 25 .

[0017] The output circuit 25 outputs a signal to the output terminal U OUT The output voltage to the secondary side is switched between the high-side power supply voltage VB, which serves as the reference potential for the secondary side circuit (called the "secondary side reference potential"), and the high-side floating potential VS.

[0018] <First Embodiment> <Device configuration> 2 is a circuit diagram showing a configuration of a high-voltage level shift circuit 131 according to the first embodiment of the present disclosure. Note that, hereinafter, with a high-voltage MOSFET Q10, which is a level shift transistor, as a boundary, the on-pulse generation circuit 11 side will be referred to as a primary-side circuit, and the NOT gate 21 side will be referred to as a secondary-side circuit. Note that the high-voltage level shift circuit 131 is a circuit corresponding to the high-voltage level shift circuit 13 shown in FIG. 1.

[0019] 2, the gate of the high-voltage MOSFET Q10 of the high-voltage level shift circuit 131 is connected to a low-side power supply VCC, which is the power supply for the primary circuit (referred to as the "primary-side power supply"), and the source is supplied with an on-pulse output from an on-pulse generating circuit 11 via an inverter INV1. The voltage supplied from the low-side power supply VCC may also be referred to as a low-side power supply voltage VCC.

[0020] The inverter INV1 operates between the low-side power supply voltage VCC supplied from the low-side power supply VCC and GND.

[0021] The drain of the high-voltage MOSFET Q10 is connected to the cathode of a forward diode D1, which is connected in parallel with a capacitor C1.

[0022] The anode of the forward diode D1 is connected to the high-side power supply VB via a resistor 19. The anode of the forward diode D1 is also connected to the input of a NOT gate 21. The NOT gate 21 operates between the high-side power supply voltage VB and the high-side floating potential VS.

[0023] 3 is a circuit diagram showing the configuration of the high-voltage level shift circuit 141 according to the embodiment 1. The high-voltage level shift circuit 141 is a circuit corresponding to the high-voltage level shift circuit 14 shown in FIG.

[0024] The configuration of high-voltage level shift circuit 141 is the same as that of high-voltage level shift circuit 131 shown in Fig. 2, with only the connection relationship between the primary side circuit and the secondary side circuit being different. That is, the source of high-voltage MOSFET Q10 of high-voltage level shift circuit 141 is supplied with an off-pulse output from off-pulse generation circuit 12 via inverter INV1, and the anode of forward diode D1 is supplied with high-side power supply voltage VB via resistor element 20. The anode of forward diode D1 is also connected to the input of NOT gate 22. NOT gate 22 operates between high-side power supply voltage VB and high-side floating potential VS.

[0025] <Operation> The operation of the high-voltage level shift circuit 131 will be described below, but the operation of the high-voltage level shift circuit 141 is the same, so the description of the operation will be omitted.

[0026] Assume that the initial state is a state in which a low-level signal, i.e., a voltage equal to or lower than the threshold voltage of inverter INV1, is applied to the input of inverter INV1. Here, a voltage equal to or lower than the threshold voltage of inverter INV1 refers to a voltage equal to or lower than the threshold voltage of the N-channel MOSFET but higher than the threshold voltage of the P-channel MOSFET in the series connection of P-channel MOSFET and N-channel MOSFET that make up inverter INV1. In this state, the P-channel MOSFET is on, connecting the low-side power supply voltage VCC to the source of high-voltage MOSFET Q10, and the gate and source potentials of high-voltage MOSFET Q10 are equal to the low-side power supply voltage VCC, so that high-voltage MOSFET Q10 is off.

[0027] Next, when a high-level signal is input to the input of inverter INV1, the P-channel MOSFET that constitutes inverter INV1 turns off and the N-channel MOSFET turns on, the source potential of high-voltage MOSFET Q10 falls to GND, and high-voltage MOSFET Q10 turns on. At this time, if the high-side power supply voltage VB is higher than GND, current flows from high-side power supply VB to high-voltage MOSFET Q10, generating a voltage signal ΔV in resistor 19 and transmitting the signal to the secondary-side circuit.

[0028] Meanwhile, when the high-side power supply voltage VB is below GND and the high-voltage MOSFET Q10 is turned on, the potential of the electrode on the primary circuit side of capacitor C1 drops to GND. The moment this happens, the potentials of the two electrodes of capacitor C1 attempt to maintain their held state, causing the potential of the electrode on the secondary circuit side of capacitor C1 to drop accordingly. If the voltage drop is ΔV, then a voltage ΔV is applied to resistor 19, transmitting a signal to the secondary circuit. After that, the voltage ΔV gradually drops according to the time constant of the RC circuit formed by capacitor C1 and resistor 19, and the electrode on the secondary circuit side of capacitor C1 rises to the high-side power supply voltage VB. At this time, a transient drain current flows.

[0029] Furthermore, when the high-side power supply voltage VB is equal to or lower than GND, there is a possibility that a current will flow from the drain side of the high-voltage MOSFET Q10 to the back gate (GND), but this current is blocked by the diode D1.

[0030] In this way, the high-voltage level shift circuit 131 of the first embodiment can transmit a signal to the secondary-side circuit even when the high-side power supply voltage VB of the secondary-side circuit drops to GND or lower.

[0031] <Embodiment 2> <Device configuration> Fig. 4 is a circuit diagram showing a configuration of a high-voltage level shift circuit 132 according to a second embodiment of the present disclosure. In Fig. 4, the same components as those in the high-voltage level shift circuit 131 described using Fig. 2 are denoted by the same reference numerals, and duplicated explanations will be omitted. The high-voltage level shift circuit 132 is a circuit corresponding to the high-voltage level shift circuit 13 shown in Fig. 1.

[0032] As shown in FIG. 4, in the high-voltage level shift circuit 132, a P-channel MOSFET Q11 is provided which is connected between the source of a high-voltage MOSFET Q10 and GND, and the low-side power supply voltage VCC is applied to the gate of the MOSFET Q11.

[0033] Fig. 5 is a circuit diagram showing the configuration of high-voltage level shift circuit 142 according to embodiment 2. The configuration of high-voltage level shift circuit 142 is the same as that of high-voltage level shift circuit 132 shown in Fig. 4, and the connection relationship between the primary side circuit and the secondary side circuit is the same as that of high-voltage level shift circuit 131 shown in Fig. 3.

[0034] <Operation> The operation of the high-voltage level shift circuit 132 will be described below, but since the operation of the high-voltage level shift circuit 142 is the same, a description of the operation of the high-voltage level shift circuit 142 will be omitted.

[0035] First, consider the case where the high-side floating potential VS increases sharply using the high-voltage level shift circuit 131, that is, the potential between the high-side floating potential VS and GND increases sharply, causing a positive voltage change (+dv / dt).

[0036] At this time, a displacement current flows from the secondary side circuit to the primary side circuit. The displacement current behaves as follows depending on the state of the input to the high-voltage level shift circuit 131.

[0037] First, when a high-level signal is input to the inverter INV1, the N-channel MOSFET that constitutes the inverter INV1 turns on, and the displacement current flows to GND via the N-channel MOSFET.

[0038] Next, when a low-level signal is input to the inverter INV1, the N-channel MOSFET that constitutes the inverter INV1 turns off, causing high impedance between the inverter INV and GND, making it difficult for current to flow toward GND.As a result, there is a possibility that displacement current will flow from the drain side of the P-channel MOSFET that constitutes the inverter INV1 toward the back gate (GND) via a parasitic diode in the body of the P-channel MOSFET.

[0039] On the other hand, as shown in FIG. 4, in the high-voltage level shift circuit 132, a P-channel MOSFET Q11 is provided between the source of the high-voltage MOSFET Q10 and GND, and when a low-level signal is input to the inverter INV1, the MOSFET Q11 is in the off state.

[0040] Meanwhile, there is high impedance between inverter INV1 and GND, making it difficult for current to flow toward GND. However, if +dv / dt occurs at this time, a displacement current flows from the secondary circuit to the primary circuit, causing the potential on the source side of MOSFET Q11 to rise, turning on the normally-off MOSFET Q11 and allowing the displacement current to flow to GND via MOSFET Q11.

[0041] In this way, the high-voltage level shift circuit 132 of the second embodiment can release the displacement current that occurs when the high-side floating potential VS increases sharply to the primary-side reference potential GND regardless of the input state, thereby suppressing the occurrence of problems caused by the displacement current.

[0042] In addition, even in the high-voltage level shift circuit 132, even if the high-side power supply voltage VB of the secondary-side circuit drops to GND or lower, it is possible to transmit a signal to the secondary-side circuit.

[0043] <Third Embodiment> <Device configuration> 6 is a circuit diagram showing a configuration of a high-voltage level shift circuit 133 according to the third embodiment of the present disclosure. The high-voltage level shift circuit 133 is a circuit corresponding to the high-voltage level shift circuit 13 shown in FIG.

[0044] 6, the gate of high-voltage MOSFET Q10 in high-voltage level shift circuit 133 is connected to the low-side power supply VCC of the primary circuit, and a P-channel MOSFET Q16 is connected between the gate and source of high-voltage MOSFET Q10. Furthermore, an N-channel MOSFET Q15 is connected between the source of high-voltage MOSFET Q10 and GND, and when P-channel MOSFET Q16 is turned off and MOSFET Q15 is turned on, the high-voltage MOSFET Q10 is turned on.

[0045] The gate of MOSFET Q16 is configured to receive an on-pulse output from on-pulse generating circuit 11 via serially connected inverters INV2 and INV3. Although not shown, inverters INV2 and INV3 operate between low-side power supply voltage VCC and GND.

[0046] The drain of the high-voltage MOSFET Q10 is connected to the cathode of a forward diode D1, which is connected in parallel with a capacitor C1.

[0047] The anode of the forward diode D1 is connected to the high-side power supply VB via a resistor 19. The anode of the forward diode D1 is also connected to the input of a NOT gate 21.

[0048] A P-channel MOSFET Q12, a resistor R1, and an N-channel MOSFET Q13 are connected in series between the low-side power supply VCC and GND, and an inverter INV 2 The output of is connected.

[0049] An N-channel MOSFET Q14 is connected between the connection node between resistor R1 and MOSFET Q13 and GND. The gate of MOSFET Q14 is connected in common with the gate of MOSFET Q15 to the connection node between resistor R1 and MOSFET Q13. MOSFET Q15 forms the primary side of a current mirror circuit, and resistor R1 and MOSFET Q14 form the secondary side of the current mirror circuit.

[0050] 7 is a circuit diagram showing the configuration of a high-voltage level shift circuit 143 according to embodiment 3. The high-voltage level shift circuit 143 is a circuit corresponding to the high-voltage level shift circuit 14 shown in FIG.

[0051] 2, the only difference is the connection between the primary and secondary circuits. That is, an off-pulse output from off-pulse generating circuit 12 is applied to the gate of MOSFET Q16 of high-voltage level shift circuit 143 via serially connected inverters INV2 and INV3, and the anode of forward diode D1 is connected to high-side power supply VB via resistor 20. The anode of forward diode D1 is also connected to the input of NOT gate 22.

[0052] <Operation> The operation of the high-voltage level shift circuit 133 will be described below, but since the operation of the high-voltage level shift circuit 143 is the same, a description of the operation of the high-voltage level shift circuit 143 will be omitted.

[0053] In the initial state, a low-level signal, i.e., a voltage equal to or lower than the threshold voltage of the inverter INV2, is applied to the input of the inverter INV2. Here, the definition of the voltage equal to or lower than the threshold voltage of the inverter INV2 is the same as the definition of the voltage equal to or lower than the threshold voltage of the inverter INV1 described in the first embodiment.

[0054] When a low-level signal is input to the input of inverter INV2, inverter INV2 outputs a high-level signal. The high-level signal output by inverter INV2 turns on MOSFET Q13, but MOSFET Q12 turns off, so the current mirror circuit does not operate. The high-level signal output by inverter INV2 is input to inverter IV3, which outputs a low-level signal and turns on MOSFET Q16. However, MOSFET Q15 does not turn on, so high-voltage MOSFET Q10 remains off.

[0055] Next, when a high-level signal is input to the input of inverter INV2, inverter INV2 outputs a low-level signal. The low-level signal output by inverter INV2 turns on MOSFET Q12 but turns off MOSFET Q13. The low-level signal output by inverter INV2 is input to inverter IV3, which outputs a high-level signal, turns off MOSFET Q16, and disconnects the connection between the low-side power supply VCC and the source of high-voltage MOSFET Q10.

[0056] If MOSFET Q14 and MOSFET Q15 have equivalent capabilities, the drain current of MOSFET Q14 will be the same as the drain current of MOSFET Q15. The drain current of MOSFET Q15 is the drain current of high-voltage MOSFET Q10, and is therefore equivalent to the drain current of MOSFET Q14, i.e., the current flowing through resistor R1. In other words, the drain current of high-voltage MOSFET Q10 can be limited when a high-level signal is input to the input of inverter INV2.

[0057] In this way, the high-voltage level shift circuit 133 of the third embodiment is provided with a current mirror circuit, thereby being able to limit the drain current of the high-voltage MOSFET Q10 and preventing an overcurrent from flowing through the high-voltage MOSFET Q10.

[0058] In addition, even in the high-voltage level shift circuit 133, it is possible to transmit a signal to the secondary-side circuit even if the high-side power supply voltage VB of the secondary-side circuit drops to GND or lower.

[0059] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate. [Explanation of symbols]

[0060] C1 capacitor, D1 diode, GND ground potential, IV1, IV2, IV3 inverters, Q10 high-voltage MOSFET, Q11, Q12, Q13, Q14, Q15, Q16 MOSFETs, VB high-side power supply, VCC low-side power supply, VS high-side floating potential.

Claims

1. a first conductivity type level shift transistor that level-shifts a signal from a primary side circuit referenced to a primary side reference potential and a secondary side circuit referenced to a secondary side reference potential independent of the primary side reference potential, between the primary side circuit and the secondary side circuit; a diode connected in a forward direction between the first main electrode of the level shift transistor and the secondary side circuit; a capacitor connected in parallel with the diode; an inverter that inverts the signal; a control electrode of the level shift transistor is connected to a primary power supply of the primary circuit, and a second main electrode is connected to an output of the inverter; The inverter is operates between the primary-side reference potential and the primary-side power supply; The diode is a level shift circuit connected to the secondary power supply of the secondary circuit via a resistive element;

2. 2. The level shift circuit according to claim 1, further comprising a transistor of a second conductivity type connected between the second main electrode of the level shift transistor and the primary-side reference potential, the control electrode of the transistor being connected to the primary-side power supply.

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