Semiconductor Devices

Abstract

To provide an LDMOS transistor which can achieve both of high breakdown voltage and low on-resistance.SOLUTION: A semiconductor device comprises: a P-type body region 6 which is formed on a main surface of a semiconductor substrate 1; an N-type source region 9; an N-type drift region 7; an N-type drain region 10; a gate electrode 13 which is formed via a gate insulation film 12; a first field plate 13 which is formed via a first insulation film 8 on the drift region; a plurality of second field plates 16a, 19a which are in contact with the source region or gate electrode and formed via a second insulation film 14 on the first field plate; a P-type first buried region 4; and a P-type second buried region 5 which has the smaller impurity density than the impurity density of the first buried region. The first and second field plates, as going toward the upper layer, have a smaller distance in the semiconductor substrate plane direction from the drain region, and are in a prescribed relation with the distances LB1, LB2 between the first and second buried regions and the drain region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the structure of a semiconductor device, and in particular to a technique that is effective when applied to a high-voltage LDMOS transistor that requires a high breakdown voltage of 100 V or more. [Background technology]

[0002] LDMOS (Lateral Double-Diffused MOS) transistors, which have a breakdown voltage of approximately 30V or more, are formed on semiconductor substrates and are used in drive circuits that use inductors such as automotive solenoids and fan motors, and capacitive elements such as piezoelectric elements as loads.

[0003] In order to achieve low on-resistance while ensuring a high breakdown voltage in this LDMOS transistor, a known transistor structure is one in which the impurity concentration in the drift region through which current flows is increased, and an impurity layer (buried layer) with an opposite conductivity type to that of the drift region is provided below the drift region (Patent Document 1).

[0004] 8, a conventional N-type LDMOS transistor 400 has a P-type buried layer 4 extending from the P-type body region below the N-type drift region 7, and a first field plate of a gate electrode 13 is provided on an insulating layer 8 above the drift region 7, and second field plates 16a, 19a made up of multiple wiring layers formed on interlayer insulating films 14, 17 above the first field plate. The distance LB from the drain 10 of the P-type buried layer 4 is designed to be smaller than the distance LF1 from the drain of the first field plate and larger than the distance LF3 from the drain of an upper wiring layer 19a constituting the second field plate.

[0005] With this configuration, the impurity concentration of the drift region 7 can be reduced to 1 ×10 16 / cm 3Even with the above relatively high concentration, the electric potential can be made uniform without causing electric field concentration in the drift region 7 when the transistor is in the off state. As a result, transistor characteristics that combine high breakdown voltage and low on-resistance are obtained. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-98883 Summary of the Invention [Problem to be solved by the invention]

[0007] However, although the N-type LDMOS transistor described in Patent Document 1 can obtain a relatively high breakdown voltage in the off state, it exhibits a characteristic that the current does not saturate in the drain current saturation region when the transistor is in the on state, but increases with an increase in the source-drain voltage (Vds).

[0008] Figure 9 shows the Vds dependence of the drain current (Ids) in the on / off states of the N-type LDMOS transistor shown in Figure 8. In the on state with a voltage applied to the gate, the drain current is divided into a linear region (Region 1) where Ids changes linearly with Vds, a saturation region (Region 2) where Ids changes little with Vds, and an avalanche region (Region 3) where Ids changes greatly with Vds. Within the saturation region (Region 2), there is a region (Region 2b) where Vds increases gradually with increasing Vds. This region arises from a Vds that is relatively low compared to the off-state breakdown voltage (BVoff). If a transistor with such characteristics is used in a current mirror circuit, the mirror ratio will change depending on the amount of current.

[0009] Furthermore, as shown in FIG. 9, in this transistor, Vds, which is the avalanche region (Region 3) where Ids changes significantly with respect to Vds, is also relatively small with respect to BVoff.

[0010] Therefore, for example, in a drive circuit in which an inductor serves as a load, if a high Vds is applied during the transition period from the off state to the on state and the transistor enters the avalanche region (Region 3), a large drain current will flow, causing the element to be destroyed.

[0011] Furthermore, in a drive circuit using this transistor, if the operating conditions are such that the transistor transiently passes through the saturation region of Region 2b during switching operation, the transistor characteristics change over time, which poses a reliability problem.

[0012] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a high-voltage LDMOS field effect transistor that has high performance and is capable of achieving both a high voltage and a low on-resistance.

[0013] Specifically, the objective is to provide a high-voltage LDMOS transistor with off-state breakdown voltage and low on-state resistance, which has current characteristics in which the drain current has little dependency on the source-drain voltage in the saturation region of the drain current.

[0014] Another object of the present invention is to provide a high-voltage LDMOS transistor having off-state breakdown voltage and low on-resistance characteristics, which has a large source-drain voltage at which the drain current begins to increase rapidly in the avalanche region of the drain current.

[0015] Another object of the present invention is to provide a transistor having high reliability characteristics in which the change over time of characteristics such as on-resistance is small. [Means for solving the problem]

[0016] In order to solve the above problems, the present invention provides a semiconductor device comprising: a body region of a first conductivity type formed on a main surface of a semiconductor substrate; a source region of a second conductivity type formed on a surface of the body region; a drift region of the second conductivity type formed so as to be in contact with the body region; a drain region of the second conductivity type formed on the drift region; a gate electrode formed on the body region between the source region and the drift region and on the drift region on the source region side via a gate insulating film; a first field plate extending from the gate electrode towards the drain region and formed on the drift region via a first insulating film; a second field plate made of a plurality of wiring layers in contact with the source region or the gate electrode and formed on the first field plate via a second insulating film; and a second buried region of the first conductivity type adjacent to the first buried region and formed below the drift region in the direction of the drain region, the second buried region having an impurity concentration lower than that of the first buried region, wherein the plurality of wiring layers constituting the second field plate are such that the distance to the drain region of an upper wiring layer is shorter than the distance to the drain region of a lower wiring layer, the distance to the drain region of a lower wiring layer is shorter than the distance to the drain region of the first field plate, the distance to the drain region of the uppermost wiring layer is shorter than the distance to the drain region of the second buried region, and the distance to the drain region of the first field plate is longer than the distance to the drain region of the first buried region. [Effects of the Invention]

[0017] According to the present invention, a high-voltage LDMOS field effect transistor with high performance that can achieve both a high breakdown voltage and a low on-resistance can be realized.

[0018] According to the present invention, it is possible to realize an LDMOS transistor having a high off-state breakdown voltage and low on-state resistance, and having current characteristics in which the drain current has little dependency on the source-drain voltage in the saturation region of the drain current.

[0019] Furthermore, according to the present invention, it is possible to realize an LDMOS transistor having a high off-state breakdown voltage and low on-state resistance, and having a large source-drain voltage in the avalanche region (Region 3) where the drain current begins to increase rapidly.

[0020] Furthermore, according to the present invention, a highly reliable transistor can be realized in which the time-dependent change in transistor characteristics such as on-resistance is small.

[0021] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a diagram showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. [Figure 2] 2 is a diagram showing the impurity concentration distribution in the direction parallel to the main surface of the substrate along the dashed line AA' of the semiconductor device of FIG. 1. FIG. [Figure 3] FIG. 10 is a diagram showing drain current characteristics of a conventional semiconductor device. [Figure 4] FIG. 3 is a diagram showing equipotential potential distribution in the on-state of the semiconductor device according to the first embodiment of the present invention. [Figure 5] FIG. 4 is a diagram showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention. [Figure 7] 7 is a diagram showing the impurity concentration distribution in the direction parallel to the main surface of the substrate along the dashed line BB' of the semiconductor device of FIG. 6. FIG. [Figure 8] FIG. 1 is a diagram showing a cross-sectional structure of a conventional semiconductor device. [Figure 9] FIG. 10 is a diagram showing drain current characteristics of a conventional semiconductor device. [Figure 10] FIG. 10 is a diagram showing equipotential potential distribution in a conventional semiconductor device in an on-state. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. [Example]

[0024] A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

[0025] As shown in FIG. 1, the semiconductor device of this embodiment is an N-type LDMOS transistor 100, which is formed on an SOI semiconductor substrate in which an insulating layer 2 is formed on a P-type semiconductor substrate 1, and a P-type semiconductor layer 3 is formed on the insulating layer 2.

[0026] The SOI semiconductor substrate has a first buried region 4, for example, with an impurity concentration of 4 ×10 16 / cm 3 The P-type semiconductor layer is formed in such a manner that it is connected to a P body region 6 of a P-type semiconductor layer formed on an SOI semiconductor substrate, and the P-type semiconductor layer that becomes the second buried region 5 is adjacent to the first buried region 4 in a direction parallel to the main surface of the substrate. FIG. 2 shows the impurity concentration distribution in the direction parallel to the main surface of the substrate along the dashed line A-A' in FIG. 1. The impurity concentration of the second buried region 5 is, for example, 2 ×10 16 / cm 3 and is set to be in the range of 1 / 3 to 2 / 3 of the impurity concentration of the first buried region 4.

[0027] Also, adjacent to the P body region 6 and above the first buried region 4 and the second buried region 5, a region having an impurity concentration of, for example, 5 ×10 16 / cm 3 A drift region 7 made of an N-type semiconductor layer is formed, and a source region 9 of the N-type semiconductor layer and a P body connection region 11 are formed on the surface of the P body region 6. An N-type drain region 10 is formed on the N-type drift region 7. Adjacent to the source region 9, a gate oxide film 12 made of an insulating layer is formed on the SOI semiconductor substrate, and a gate electrode 13 made of N-type polysilicon is formed on part of the P body region 6 and part of the drift region 7 on the source region 9 side, with the gate oxide film 12 interposed therebetween.

[0028] Furthermore, an STI (Shallow Trench Isolation) made up of an insulating layer 8 is formed on the drift region 7, and a gate electrode 13 extends onto a part of the STI to form a first field plate 13.

[0029] Next, an interlayer insulating film 14 is deposited on the SOI semiconductor substrate, and a portion of the interlayer insulating film 14 is opened to form contacts 15a made of a metal layer such as aluminum (Al) on the source region 9 and the P body connection region 11, and contact 15b on the drain region 10.

[0030] First wiring layers 16a and 16b made of a metal layer such as aluminum (Al) are formed on interlayer insulating film 14 and connected to contacts 15a and 15b, respectively. First wiring layer 16a connected to contact 15a forms a source electrode, and extends toward the drain region to form a second field plate.

[0031] Furthermore, an interlayer insulating film 17 is deposited on the first wiring layers 16a and 16b, and a portion of the interlayer insulating film 17 is opened to form wiring connection holes 18a and 18b made of a metal layer such as aluminum (Al) on the first wiring layers 16a and 16b, respectively. Second wiring layers 19a and 19b made of a metal layer such as aluminum (Al) are formed on the interlayer insulating film 17 and connected to the wiring connection holes 18a and 18b, respectively. The second wiring layer 19a connected to the wiring connection hole 18a forms a source electrode and extends toward the drain region to form a second field plate.

[0032] Here, as shown in FIG. 1, when the distance in the plane direction of the semiconductor substrate between first field plate 13 and drain region 10 is defined as LF1, the distance in the plane direction of the semiconductor substrate between second field plate 16a made of the first wiring layer and drain region 10 is defined as LF2, and the distance in the plane direction of the semiconductor substrate between second field plate 19a made of the second wiring layer and drain region 10 is defined as LF3, LF1, LF2, and LF3 satisfy the relationship shown in equation (1).

[0033]

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[0034] That is, the distance of the first and second field plates (13, 16a, 19a) from the drain region 10 in the plane direction of the semiconductor substrate becomes smaller as the first and second field plates (13, 16a, 19a) are placed in the upper layers.

[0035] Furthermore, when the distance between the first buried region 4 and the drain region 10 in the plane direction of the semiconductor substrate is LB1, and the distance between the second buried region 5 and the drain region 10 in the plane direction of the semiconductor substrate is LB2, LB1, LB2, LF1, and LF3 are related by equations (2) and (3).

[0036]

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[0037]

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[0038] That is, the distances LB1 and LB2 between the first and second buried regions (4, 5) and the drain region 10 are smaller than the distance LF1 between the first field plate 13 and the drain region 10, and are larger than the distance LF3 between the second field plate 19a of the wiring in the uppermost layer and the drain region 10.

[0039] 3, the saturation current characteristics of the transistor 100 when it is on can be reduced, and the Vds dependency of the drain current (Ids) in the saturation region (Region 2) can be reduced. Also, the Vds voltage at which the avalanche region (Region 3) is reached, where Ids increases significantly with Vds, can be set close to the off-state breakdown voltage (BVoff).

[0040] Next, we will explain why such characteristics are obtained. Figure 4 shows the potential distribution when a relatively high voltage of 5 V is applied between the gate and source of transistor 100, and the source-drain voltage (Vds) is 300 V, and the drain current is in the saturation region (Region 2). ×10 16 / cm 3 Despite the relatively high potential of the drift region 7, the electric field is distributed without local concentration due to the resurf effect of the first field plate 13, the second field plate (16a, 19a), and the first and second buried layers (4, 5). Furthermore, in the transistor 400 with the conventional structure shown in FIG. 8, the electric field is not uniform in the buried layer 4, and the electric field concentrates in a direction closer to the drain region 10, as shown in FIG. 10. In contrast, the electric potential is uniformly distributed within the first buried layer 4 and the second buried layer 5, suppressing electric field concentration. As a result, the avalanche current due to impact ionization is suppressed, and as a result, the drain current (Ids) in the saturation region (Region 2) has a small Vds dependency, and the Vds at which the avalanche region (Region 3) begins can be increased.

[0041] In order to make the electric potential in the drift region 7 more uniform and obtain a higher breakdown voltage, it is more desirable to configure the drift region 7 so as to satisfy the relationship given by equation (4), but this is not a limitation.

[0042]

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[0043] In this embodiment, the second field plate 16a is electrically connected to the N-type source region 9 (body region 6), but the same effect can be obtained when it is electrically connected to the gate electrode and the first field plate 13.

[0044] Furthermore, although an example using an N-type MOS transistor has been described in this embodiment, the same effect can be obtained with a P-type MOS transistor.

[0045] Furthermore, even when an IGBT structure is formed by providing a PN junction structure in the N-type drain region 10 of an N-type MOS transistor, suppressing electric field concentration in the drift region makes it possible to reduce the device size while achieving a high breakdown voltage. In this case, in the structure shown in Figure 1, the N-type source region 9 becomes the "emitter region" and the N-type drain region 10 becomes the "collector region." [Example]

[0046] Referring to FIG. 5, a semiconductor device according to a second embodiment of the present invention will be described, focusing mainly on the differences from the first embodiment.

[0047] The difference from the first embodiment is that an N-type LDMOS transistor 200 has an interlayer insulating film 20 deposited on a second wiring layer (19a, 19b), wiring connection holes (21a, 21b) opened in the interlayer insulating film 20 are connected to the second wiring layer (19a, 19b), and a third wiring layer (22a, 22b) is formed on the interlayer insulating film 20. The third wiring layer 22a, which serves as a source electrode, extends toward the drain region 10 and constitutes a second field plate.

[0048] Here, when the distance in the plane direction of the semiconductor substrate between the second field plate 22a made of the third wiring and the drain region 10 is LF4 as shown in FIG. 5, LF1, LF2, LF3, and LF4 are related by equation (5).

[0049]

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[0050] That is, the distance of the first field plate 13 and the second field plate (16a, 19a, 22a) from the drain region 10 in the plane direction of the semiconductor substrate becomes smaller as the first field plate 13 and the second field plate (16a, 19a, 22a) are placed in the upper layers.

[0051] Furthermore, LF1, LB1, LB2, and LF4 are related by equations (2) and (6).

[0052]

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[0053]

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[0054] That is, the distances LB1 and LB2 between the first and second buried regions (4, 5) and the drain region 10 are smaller than the distance LF1 between the first field plate 13 and the drain 10, and are larger than the distance LF4 between the second field plate 22a of the wiring in the uppermost layer and the drain region 10.

[0055] This configuration makes it possible to make the potential distribution in the drift region 7 more uniform than in the transistor 100 of the first embodiment, and in a transistor with a higher breakdown voltage, it is possible to obtain saturation current characteristics in which the drain current (Ids) has a small Vds dependency, as shown in FIG. 3. [Example]

[0056] Referring to FIG. 6, a semiconductor device according to a third embodiment of the present invention will be described, focusing mainly on the differences from the second embodiment.

[0057] The difference from the second embodiment is that in the N-type LDMOS transistor 300, a third buried region 23 made of a P-type semiconductor layer is provided in the semiconductor substrate adjacent to the second buried region 5 and below the drift region 7. FIG. 7 shows the impurity concentration distribution in the direction parallel to the main surface of the substrate along the dashed line B-B' in FIG. 6, and the impurity concentration of the third buried region 23 is, for example, 1 ×10 16 / cm 3 The impurity concentration of the second buried region 5 is about 1 / 3 to 2 / 3.

[0058] As shown in FIG. 6, when the distance between the third buried region 23 and the drain region 10 in the plane direction of the semiconductor substrate is LB3, LB1, LB3, LF1, and LF4 satisfy the relationships of formulas (2) and (7).

[0059]

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[0060]

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[0061] With this configuration, the potential distribution in the buried regions (4, 5, 23) can be made more uniform than in the transistor 200 of the second embodiment, and a saturation current characteristic in which the drain current (Ids) has less Vds dependency can be obtained in a transistor with high breakdown voltage.

[0062] In order to make the electric potential in the drift region 7 more uniform and obtain a higher breakdown voltage, it is desirable to configure the drift region 7 so as to satisfy the relationship given by equation (8), but this is not limitative.

[0063]

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[0064] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0065] 1...P-type (semiconductor) substrate 2...Insulating layer 3...P-type semiconductor layer 4...First embedded region 5...Second embedded region 6...P body region 7...Drift region 8...STI 9...Source region 10...Drain region 11...P body connection area 12...Gate oxide film 13...gate electrode (first field plate) 14...Interlayer insulating film 15a, b...Contact 16a...first wiring layer (source electrode, second field plate) 16b...first wiring layer (drain electrode) 17...Interlayer insulating film 18a, b...Wiring connection holes 19a...Second wiring layer (source electrode, second field plate) 19b...Second wiring layer (drain electrode) 20...Interlayer insulating film 21a, b... Wiring connection holes 22a...Top wiring layer (source electrode, second field plate) 22b...Top wiring layer (drain electrode) 23...Third buried region 100...N-type LDMOS transistor of the first embodiment 200...N-type LDMOS transistor of the second embodiment 300...N-type LDMOS transistor of the third embodiment 400...N-type LDMOS transistor with conventional structure

Claims

1. a body region of a first conductivity type formed on a main surface of a semiconductor substrate; a source region of a second conductivity type formed on a surface of the body region; a drift region of a second conductivity type formed in contact with the body region; a drain region of a second conductivity type formed on the drift region; a gate electrode formed on the body region between the source region and the drift region and on the drift region on the source region side via a gate insulating film; a first field plate extending from the gate electrode toward the drain region and formed on the drift region via a first insulating film; a second field plate made of a plurality of wiring layers, the second field plate being in contact with the source region or the gate electrode and formed on the first field plate with a second insulating film interposed therebetween; a first buried region of a first conductivity type in contact with the body region and formed below the drift region; a second buried region of a first conductivity type adjacent to the first buried region, formed below the drift region and extending toward the drain region, the second buried region having an impurity concentration lower than that of the first buried region; in a plurality of wiring layers constituting the second field plate, a distance to the drain region of an upper wiring layer is shorter than a distance to the drain region of a lower wiring layer, and a distance to the drain region of a lowermost wiring layer is shorter than a distance to the drain region of the first field plate; a distance between the uppermost wiring layer and the drain region is shorter than a distance between the second buried region and the drain region; a first buried region formed in the first field plate and a second buried region formed in the second field plate and a second buried region formed in the first ...

2. 2. The semiconductor device according to claim 1, The impurity concentration of the drift region is 1×10 １６ / cm ３ The impurity concentration of the first buried region is 1×10 １６ / cm ３ Bigger, The semiconductor device is characterized in that the impurity concentration of the second buried region is set to a value between 1 / 3 and 2 / 3 of the impurity concentration of the first buried region.

3. 3. The semiconductor device according to claim 1, wherein In the plurality of wiring layers that form the second field plate, a distance between the wiring layer at the bottom layer and the drain region is smaller than a distance between the first buried region and the drain region; a second buried region formed on the first buried region and a second buried region formed on the second buried region;

4. 4. The semiconductor device according to claim 3, a third buried region of the first conductivity type adjacent to the second buried region, below the drift region, and extending toward the drain region, the third buried region having an impurity concentration lower than that of the second buried region; a second field plate formed on the second buried region and a second field plate formed on the second buried region; a second buried region formed on the second buried region and a second field plate formed on the second buried region;

5. 5. The semiconductor device according to claim 4, 2. A semiconductor device comprising: a semiconductor device having an impurity concentration of the third buried region set to a value that is one-third to two-thirds of the impurity concentration of the second buried region;

6. 6. The semiconductor device according to claim 1, The semiconductor device is characterized in that the semiconductor substrate is an SOI substrate having a buried insulating layer in a semiconductor layer.

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