Semiconductor devices, electronic devices

Abstract

This semiconductor device comprises, for instance, one or a plurality of first subcontacts that are electrically conductive with a substrate. At least one of the first subcontacts is formed in an element placement region on the substrate and has lower impedance than the substrate. At least one of the first subcontacts can be adjacent to a circuit element formed on the element placement region. An epitaxial layer of a second conductivity type is formed on the substrate, which is of a first conductivity type, and the first subcontact can include first wiring with lower impedance than the substrate and a semiconductor region of the first conductivity type that passes through the epitaxial layer and is conductive with the first wiring and the substrate.

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a semiconductor device and an electronic device using the same. [Background technology]

[0002] In recent years, there has been an increasing demand for improved noise characteristics for semiconductor devices incorporated into various applications (including not only consumer devices but also industrial devices and in-vehicle devices).

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-33917 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional semiconductor devices have room for further improvement in terms of their noise characteristics (particularly electromagnetic susceptibility).

[0006] In view of the above-mentioned problems that the inventors of the present application have found, the invention disclosed in this specification has an object to provide a semiconductor device with excellent noise characteristics and an electronic device using the same. [Means for solving the problem]

[0007] For example, the semiconductor device disclosed in this specification has one or more first sub-contacts electrically connected to a substrate, at least one of which is formed in an element placement region on the substrate and is configured to have a lower impedance than the substrate.

[0008] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0009] According to the invention disclosed in this specification, it is possible to provide a semiconductor device with excellent noise characteristics and an electronic device using the same. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a comparative example of a semiconductor device. [Figure 2] FIG. 2 is a diagram showing a first embodiment of a semiconductor device. [Figure 3] FIG. 3 is a diagram for explaining the basic concept of improving noise characteristics by adjusting impedance. [Figure 4] FIG. 4 is a diagram showing how a low-pass filter is formed inside an operational amplifier using resistors. [Figure 5] FIG. 5 is a diagram showing a second embodiment of the semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of an operational amplifier. [Figure 7] FIG. 7 is a diagram showing a third embodiment of the semiconductor device. [Figure 8] FIG. 8 is a diagram showing an example of packaging. [Figure 9] FIG. 9 is a diagram showing an example of a wiring layout. [Figure 10] FIG. 10 is a diagram showing a schematic α-β longitudinal section. [Figure 11] FIG. 11 is a diagram showing a fourth embodiment of the semiconductor device. [Figure 12] FIG. 12 is a diagram showing a measurement circuit for a radio wave emission test. [Figure 13] FIG. 13 is a diagram showing an example of the results of the radio wave emission test. [Figure 14]FIG. 14 is a diagram showing the appearance of the vehicle. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Semiconductor device (comparison example)> First, before describing the novel embodiment of the semiconductor device, a comparative example for comparison will be briefly described.

[0012] FIG. 1 is a diagram (top: plan view, bottom: longitudinal cross-sectional view) showing a semiconductor device according to a comparative example. In a semiconductor device 100 according to this comparative example, an n-type epitaxial layer 102 having the same crystal plane as a p-type substrate 101 is formed on the surface of the p-type substrate 101. A plurality of circuit elements (only an npn bipolar transistor 110 and a pnp bipolar transistor 120 are illustrated in this figure) are formed in an element placement region A on the p-type substrate 101, and the respective circuit elements are electrically isolated by a p-type element isolation region 103. Insulating layers 104 and 104x are formed on the surface of the n-type epitaxial layer 102. In particular, the insulating layer 104x, which covers the openings of the circuit elements (i.e., regions where conductive members for electrically connecting the circuit elements and the wiring layer can be formed), is thinner than the insulating layer 104, which covers the other portions.

[0013] The transistor 110 is formed by an n-type semiconductor region 111, an n-type semiconductor region 112, a p-type semiconductor region 113, an n-type semiconductor region 114, a p-type semiconductor region 115, and a conductive member .

[0014] The n-type semiconductor region 111 is buried in the boundary surface between the p-type substrate 101 and the n-type epitaxial layer 102. A parasitic capacitor Cp exists between the p-type substrate 101 and the n-type semiconductor region 111.

[0015] The n-type semiconductor region 112 is formed so as to surround a part of the n-type epitaxial layer 102 along the outer periphery of the n-type semiconductor region 111. The n-type semiconductor regions 111 and 112 (and the n-type epitaxial layer 102 that is electrically connected to them) correspond to the collector (C) of the transistor 110. At least a part of the surface of the n-type semiconductor region 112 is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0016] The p-type semiconductor region 113 is formed on the surface of the n-type epitaxial layer 102 surrounded by the n-type semiconductor regions 111 and 112 .

[0017] The n-type semiconductor region 114 is formed on the surface of the p-type semiconductor region 113. The n-type semiconductor region 114 corresponds to the emitter (E) of the transistor 110, and at least a part of its surface is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0018] The p-type semiconductor region 115 is formed on the surface of the p-type semiconductor region 113. The p-type semiconductor regions 113 and 115 correspond to the base (B) of the transistor 110, and at least a part of the surface of the p-type semiconductor region 115 is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0019] The conductive member 116 electrically connects the wiring L11 and the n-type semiconductor region 112 (collector (C)). For ease of illustration, the conductive members and wiring connected to the n-type semiconductor region 114 (emitter (E)) and the p-type semiconductor region 115 (base (B)) are omitted from the drawing.

[0020] On the other hand, the transistor 120 is formed by an n-type semiconductor region 121 , an n-type semiconductor region 122 , a p-type semiconductor region 123 , a p-type semiconductor region 124 , a p-type semiconductor region 125 , and a conductive member 126 .

[0021] N-type semiconductor region 121 is buried in the boundary surface between p-type substrate 101 and n-type epitaxial layer 102. A parasitic capacitor Cp exists between p-type substrate 101 and n-type semiconductor region 121.

[0022] The n-type semiconductor region 122 is formed so as to surround a part of the n-type epitaxial layer 102 along the outer periphery of the n-type semiconductor region 121. The n-type semiconductor regions 121 and 122 (and the n-type epitaxial layer 102 that is electrically connected to them) correspond to the base (B) of the transistor 120, and at least a part of the surface of the n-type semiconductor region 122 is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0023] The p-type semiconductor region 123 is formed on the surface of the n-type epitaxial layer 102 surrounded by the n-type semiconductor regions 121 and 122 so as to have a ring shape in a plan view.

[0024] The p-type semiconductor region 124 is formed on the surface of the p-type semiconductor region 123. The p-type semiconductor regions 123 and 124 correspond to the collector (C) of the transistor 120, and at least a part of the surface of the p-type semiconductor region 124 is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0025] The p-type semiconductor region 125 is formed at a position surrounded by the p-type semiconductor region 124 on the surface of the n-type epitaxial layer 102, which is surrounded by the n-type semiconductor regions 121 and 122. The p-type semiconductor region 125 corresponds to the emitter (E) of the transistor 120, and at least a part of its surface is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0026] The conductive member 126 electrically connects the wiring L12 and the n-type semiconductor region 122 (base (B)). For ease of illustration, the conductive members and wiring connected to the p-type semiconductor region 124 (collector (C)) and the p-type semiconductor region 125 (emitter (E)) are omitted from the drawing.

[0027] In the semiconductor device 100 of this comparative example, the distance between circuit elements (in this figure, the distance between transistors 110 and 120) is kept as large as possible, and shielding wiring L13 is laid between the two elements, thereby preventing noise propagation on the surface (upper layer) of the semiconductor device 100.

[0028] However, even if the above-mentioned noise countermeasures were taken, it was difficult to suppress the propagation of noise that travels inside (lower layer) the semiconductor device 100 via the p-type substrate 101 due to the influence of the parasitic capacitor Cp associated with the transistors 110 and 120.

[0029] A new embodiment that can solve these problems will be proposed below.

[0030] <Semiconductor Device (First Embodiment)> 2 is a diagram showing a first embodiment of a semiconductor device (upper: plan view, lower: longitudinal cross-sectional view). The semiconductor device 100 of this embodiment is based on the comparative example (FIG. 1) described above, but is newly provided with a first sub-contact 130 and a second sub-contact 140.

[0031] The first sub-contact 130 is disposed adjacent to each of the transistors 110 and 120 (in this drawing, it is interposed between the transistors 110 and 120) formed in the element placement area A. The first sub-contact 130, together with the previously described shielding wiring L13, is formed of a p-type semiconductor region 131, a p-type semiconductor region 132, and a conductive member 133.

[0032] The p-type semiconductor region 131 penetrates the n-type epitaxial layer 102 in the vertical direction from the surface to the bottom, and provides electrical conduction between the wiring L13 and the p-type substrate 101. Note that the p-type semiconductor region 131 does not form circuit elements such as transistors (excluding parasitic elements). The wiring L13 may be electrically connected to a ground pad, for example. The p-type semiconductor region 131 may be formed in the same process as the p-type element isolation portion 103.

[0033] The p-type semiconductor region 132 is formed on the surface of the p-type semiconductor region 131. At least a part of the surface of the p-type semiconductor region 132 is exposed without being covered by the insulating layers 104 and 104x for electrical conduction with the wiring layers.

[0034] The aforementioned p-type semiconductor region 131 has a relatively low concentration of p-type impurities and therefore a high impedance. Therefore, the impedance is reduced by adding a p-type semiconductor region 132, which has a higher concentration of p-type impurities than the p-type semiconductor region 131. Furthermore, the p-type semiconductor region 132 is electrically connected to the wiring L13 via the conductive member 133, and therefore a low impedance is achieved for the first sub-contact 130 as a whole.

[0035] The conductive member 133 electrically connects the wiring L13 and the p-type semiconductor region 132.

[0036] Incidentally, the wiring L13 has a lower impedance than the p-type substrate 101. Specifically, the surface resistivity of the wiring L13 (for example, an Al wiring) is several tens of mΩ / sq, whereas the surface resistivity of the p-type substrate 101 is several hundreds of Ω.

[0037] Therefore, for example, noise traveling inside (lower layer) of semiconductor device 100 from transistor 110 via p-type substrate 101 propagates to first sub-contact 130 without reaching transistor 120, and is finally released from wiring L13 to the ground pad. Furthermore, noise traveling on the surface (upper layer) of semiconductor device 100 is absorbed by wiring L13, as in the comparative example described above (FIG. 1).

[0038] In this way, by introducing the first sub-contact 130 (=adjusting the impedance of the p-type substrate 101), it is possible to improve the noise characteristics (particularly the electromagnetic susceptibility) of the semiconductor device 100.

[0039] In addition, in order to enhance the effect of improving noise characteristics, it is desirable to design the width W3 of the first sub-contact 130 to be greater than the minimum process width of the circuit elements formed in the element placement area A (in this figure, the minimum process widths W1 and W2 of transistors 110 and 120, respectively).

[0040] Generally, the minimum process widths W1 and W2 of the transistors 110 and 120, respectively, are often several tens of μm (approximately 50 μm). In view of this, it is desirable that the width W3 of the first sub-contact 130 be 50 μm or more (preferably 60 μm or more).

[0041] In this figure, the width W3 of the first sub-contact 130 is defined as the width of the region sandwiched between the p-type element isolation regions 103, but for example, the width W3 of the first sub-contact 130 may also be defined as the width of the p-type semiconductor region 131 or the width of the wiring L13.

[0042] On the other hand, the second sub-contact 140 is arranged, for example, along the outer periphery of the p-type substrate 101 as a GND guard ring that surrounds the periphery of the element placement area A. The second sub-contact 140 is formed of a p-type semiconductor region 141, a p-type semiconductor region 142, and a conductive member 143 together with the wiring L14.

[0043] The p-type semiconductor region 141 penetrates the n-type epitaxial layer 102 in the vertical direction from the surface to the bottom, and provides electrical conduction between the wiring L14 and the p-type substrate 101. Note that the p-type semiconductor region 141 does not form circuit elements (excluding parasitic elements) such as transistors. Furthermore, it is sufficient that the wiring L14 is electrically connected to a ground pad, for example. The p-type semiconductor region 141 may be formed in a common process together with the p-type element isolation portion 103 and the p-type semiconductor region 131.

[0044] The p-type semiconductor region 142 is formed on the surface of the p-type semiconductor region 141. At least a part of the surface of the p-type semiconductor region 142 is exposed without being covered by the insulating layers 104 and 104x.

[0045] The aforementioned p-type semiconductor region 141 has a relatively low concentration of p-type impurities and therefore a high impedance. Therefore, the impedance is reduced by adding a p-type semiconductor region 142, which has a higher concentration of p-type impurities than the p-type semiconductor region 141. Furthermore, the p-type semiconductor region 142 is electrically connected to the wiring L14 via the conductive member 143, and therefore the second sub-contact 140 as a whole achieves a low impedance.

[0046] The conductive member 143 electrically connects the wiring L14 and the p-type semiconductor region 142.

[0047] Incidentally, like the previously mentioned wiring L13, the wiring L14 has a lower impedance than the p-type substrate 101. Therefore, for example, it becomes possible for the second sub-contact 140 to absorb noise that attempts to enter the inside of the chip of the semiconductor device 100.

[0048] Among the various circuit blocks that can be integrated into the semiconductor device 100, an operational amplifier (particularly a differential input stage) is one that should be particularly protected from noise interference. Therefore, the following will discuss improving the noise characteristics of an operational amplifier by adjusting its impedance.

[0049] <Op-amp> FIG. 3 is a diagram for explaining the basic concept of improving the noise characteristics of an operational amplifier by adjusting impedance.

[0050] As shown in this figure, the noise signals input from outside to the operational amplifier 1 of this configuration example mainly include a noise signal N0 input to the power supply terminal VCC, a noise signal N1 input to the non-inverting input terminal IN+, and a noise signal N2 input to the inverting input terminal IN- due to fluctuations in the output terminal OUT and interference from the noise input line.

[0051] Therefore, the operational amplifier 1 of this configuration example has a resistor R0 (corresponding to a power supply resistor) connected to the power supply terminal VCC, and resistors R1 and R2 (corresponding to input resistors) connected to the non-inverting input terminal IN+ and the inverting input terminal IN-, respectively. With this configuration, it is possible to increase the terminal impedance of each of the power supply terminal VCC, the non-inverting input terminal IN+, and the inverting input terminal IN-, thereby making it possible to suppress the input of noise signals N0 to N2.

[0052] FIG. 4 is a diagram showing how a low-pass filter (a so-called EMI (electro-magnetic interference) filter) is formed inside the operational amplifier 1 using resistors R0 to R2.

[0053] As shown in this diagram, resistor R0 forms a low-pass filter together with parasitic capacitor C0 associated with the power supply line of operational amplifier 1. Resistors R1 and R2 also form low-pass filters together with parasitic capacitors C1 and C2 associated with pnp bipolar transistors Q1 and Q2, respectively, which form the input stage of operational amplifier 1.

[0054] In this way, in the operational amplifier 1 of this configuration example, the parasitic capacitors C0 to C2 associated with each part are used as components of the low-pass filter. With this configuration, there is no need to add a separate capacitor to form a low-pass filter, so there is no deterioration in the phase margin of the operational amplifier 1 and no increase in the circuit area.

[0055] The resistance value R of each of the resistors R1 and R2 may be set based on the capacitance value C of each of the parasitic capacitors C1 and C2 and the target cutoff frequency fc of the low-pass filter, according to the following equation (1).

[0056] R=1 / (2π·fc·C) … (1)

[0057] For example, when C=8.5 pF and fc=20 MHz, R should be set to approximately 900 Ω.

[0058] The resistance value of resistor R0 can also basically be set based on equation (1) above. However, since resistor R0 is inserted in the power supply line of operational amplifier 1, careful attention should be paid to setting the resistance value so that the power supply voltage of operational amplifier 1 does not fall below its minimum driving voltage. If only an extremely small resistor can be used for resistor R0, a minimum necessary capacitor may be added separately along with parasitic capacitor C0.

[0059] <Semiconductor Device (Second Embodiment)> 5 is a diagram showing a second embodiment of a semiconductor device. The semiconductor device 100 of this embodiment is a monolithic semiconductor integrated circuit device known as an operational amplifier IC, and is configured by integrating an operational amplifier 1, a reference current setting unit 2, an electrostatic protection element 3 (electrostatic protection diodes D1 and D2), a power supply line L1, a ground line L2, a reference current setting line L3, and an output line L4.

[0060] In addition, the semiconductor device 100 has a plurality of external terminals (a power supply terminal VCC, a non-inverting input terminal IN+, an inverting input terminal IN-, a ground terminal VEE, and an output terminal OUT) as means for establishing electrical connection with the outside of the device.

[0061] As explained above, the operational amplifier 1 has resistors R1 and R2 that form a low-pass filter together with parasitic capacitors C1 and C2 (not shown in FIG. 4). Specifically, the non-inverting input node (+) of the operational amplifier 1 is connected to the non-inverting input terminal IN+ of the semiconductor device 100 via resistor R1. The inverting input node (-) of the operational amplifier 1 is connected to the inverting input terminal IN- of the semiconductor device 100 via resistor R2. Note that while this figure shows an example in which a single-channel operational amplifier 1 is integrated into the semiconductor device 100, multiple-channel operational amplifiers 1 may also be integrated.

[0062] The reference current setting unit 2 sets the reference current Iref that flows inside the operational amplifier 1 .

[0063] The power supply line L1 is laid between the power supply terminal VCC of the semiconductor device 100 and the power supply nodes of the operational amplifier 1 and the reference current setting unit 2. The ground line L2 is laid between the ground terminal VEE of the semiconductor device 100 and the ground nodes of the operational amplifier 1 and the reference current setting unit 2. The reference current setting line L3 is laid between the reference current setting node of the operational amplifier 1 and the output node of the reference current setting unit 2. The output line L4 is laid between the output node of the operational amplifier 1 and the output terminal OUT of the semiconductor device 100.

[0064] The cathode of the electrostatic protection diode D1 is connected to the non-inverting input terminal IN+ of the semiconductor device 100. The cathode of the electrostatic protection diode D2 is connected to the inverting input terminal IN- of the semiconductor device 100. The anodes of the electrostatic protection diodes D1 and D2 are both connected to the ground terminal VEE of the semiconductor device 100. In this way, a configuration including the electrostatic protection diodes D1 and D2 can improve surge resistance.

[0065] In general semiconductor devices, a bypass capacitor (e.g., 100 pF) is often inserted between the power supply terminal and the ground terminal to stabilize the power supply voltage. However, inserting a bypass capacitor between the power supply terminal VCC and the ground terminal VEE of the semiconductor device 100 reduces the input impedance of the power supply terminal VCC for high-frequency signals, making it easier for noise signals (= high-frequency signals) to reach the power supply node of the operational amplifier 1, thereby deteriorating the noise characteristics of the operational amplifier 1.

[0066] Therefore, in the semiconductor device 100 of this embodiment, as shown by the dashed line in the figure, no bypass capacitor is connected between the power supply terminal VCC and the ground terminal VEE, and further, the parasitic capacitance associated with the power supply line L1 and the ground line L2 is reduced as much as possible (for example, to 20 pF or less). With this configuration, the input impedance of the power supply terminal VCC for high-frequency signals increases, making it more difficult for noise signals to reach the power supply node of the operational amplifier 1, thereby improving the noise characteristics of the operational amplifier 1.

[0067] 6 is a diagram showing an example configuration of operational amplifier 1. In addition to the aforementioned pnp bipolar transistors Q1 and Q2, operational amplifier 1 of this example configuration includes pnp bipolar transistors Q3 to Q6, npn bipolar transistors Q7 to Q13, resistor R3, capacitor C3, and current sources I1 to I7. Each of current sources I1 to I7 supplies reference current Iref (or a constant current corresponding to the reference current Iref) set by reference current setting unit 2.

[0068] The first terminals of the current sources I1 to I3 are all connected to the power supply terminal VCC. The second terminal of the current source I1 is connected to the emitter of the transistor Q2 and the base of the transistor Q3. The second terminal of the current source I2 is connected to the emitters of the transistors Q3 and Q4. The second terminal of the current source I3 is connected to the emitter of the transistor Q1 and the base of the transistor Q4.

[0069] The base of transistor Q1 is connected to the non-inverting input terminal IN+ via a resistor R1 (not shown) (see FIGS. 3 to 5). The base of transistor Q2 is connected to the inverting input terminal IN- via a resistor R2 (not shown) (see FIGS. 3 to 5). The collectors of transistors Q1 and Q2 are both connected to the ground terminal VEE.

[0070] The collector of transistor Q3 is connected to the collector of transistor Q7. The collector of transistor Q4 is connected to the collector of transistor Q8. The bases of transistors Q7 and Q8 are both connected to the collector of transistor Q7. The emitters of transistors Q7 and Q8 are both connected to ground terminal VEE.

[0071] The current sources I1 to I3, the transistors Q1 to Q4, and the transistors Q7 and Q8 connected in this manner form a differential input stage 1X of the operational amplifier 1.

[0072] The first terminals of current sources I4 and I5 are both connected to power supply terminal VCC. The second terminal of current source I4 is connected to the emitter of transistor Q5 and the base of transistor Q9. The second terminal of current source I5 is connected to the collector of transistor Q9.

[0073] The base of transistor Q5 is connected to the collector of transistor Q8 and the first terminal of capacitor C3. The second terminal of capacitor C3 is connected to the collector of transistor Q10. The emitter of transistor Q9 is connected to the base of transistor Q10. The collector of transistor Q5 and the emitter of transistor Q10 are both connected to ground terminal VEE.

[0074] A first terminal of current source I6 and the collectors of transistors Q12 and Q13 are all connected to power supply terminal VCC. A second terminal of current source I6 is connected to the collectors of transistors Q10 and Q11 and the base of transistor Q12. The emitter of transistor Q12 is connected to the base of transistor Q13. The emitter of transistor Q13 is connected to the base of transistor Q11 and the first terminal of resistor R3.

[0075] The emitters of transistors Q6 and Q11, the second terminal of resistor R3, and the first terminal of current source I7 are all connected to output terminal OUT. The base of transistor Q6 is connected to the collector of transistor Q10. The second terminal of current source I7 and the collector of transistor Q6 are all connected to ground terminal VEE.

[0076] The current sources I4 to I7, transistors Q5 and Q6, transistors Q9 to Q13, capacitor C3, and resistor R3 connected in this manner form an amplification output stage 1Y of the operational amplifier 1.

[0077] However, the circuit configuration shown in this figure is merely an example, and any circuit configuration may be adopted as long as the operational amplifier 1 can achieve the desired operation.

[0078] When the device structure of the first embodiment (FIG. 2) is applied to the semiconductor device 100 of the second embodiment (FIG. 5), for example, the first sub-contact 130 may be provided adjacent to the transistors Q1 and Q2 that form the differential input stage 1X of the operational amplifier 1. From the opposite perspective, the transistor 110 in FIG. 2 can be understood as the transistors Q1 and Q2. With such a device structure, it is possible to effectively suppress noise interference in the operational amplifier 1.

[0079] <Semiconductor Device (Third Embodiment)> 7 is a diagram showing a third embodiment of a semiconductor device. The semiconductor device 100 of this embodiment is configured by integrating two-channel operational amplifiers 1a and 1b (corresponding to the aforementioned operational amplifier 1). For convenience of illustration, components other than the operational amplifiers 1a and 1b are omitted.

[0080] Furthermore, it is preferable to adopt an SOP (Small Outline Package), SSOP (Shrink SOP), or MSOP (Micro SOP) in which a total of eight external terminals (1st to 8th pins), four pins being led out from each of two opposing sides, as the package of the semiconductor device 100. In this figure, pins 1 to 4 are provided on the first side of the package, and pins 5 to 8 are provided on the second side of the package.

[0081] Pin 1 is the output terminal OUT1 of the first channel, and is connected to the output terminal of the operational amplifier 1a. Pin 2 is the inverting input terminal IN1- of the first channel, and is connected to the inverting input terminal (-) of the operational amplifier 1a. Pin 3 is the non-inverting input terminal IN1+ of the first channel, and is connected to the non-inverting input terminal (+) of the operational amplifier 1a. Pin 4 is the ground terminal VEE.

[0082] Pin 5 is the non-inverting input terminal IN2+ of the second channel, which is connected to the non-inverting input terminal (+) of operational amplifier 1b. Pin 6 is the inverting input terminal IN2- of the second channel, which is connected to the inverting input terminal (-) of operational amplifier 1b. Pin 7 is the output terminal OUT2 of the second channel, which is connected to the output terminal of operational amplifier 1b. Pin 8 is the power supply terminal VCC.

[0083] In this way, the external terminals for the first channel (pins 1 to 3) are all provided on the first side of the package, and the external terminals for the second channel (pins 5 to 7) are all provided on the second side of the package.

[0084] Although the figure shows an example in which two-channel operational amplifiers 1a and 1b are integrated, it is also possible to integrate, for example, a four-channel operational amplifier. In that case, for example, a 14-pin SOP, SSOP, or MSOP can be suitably used.

[0085] 8 is a diagram showing an example of packaging in the third embodiment. In the semiconductor device 100, a semiconductor chip 300 integrating operational amplifiers 1a and 1b and the like is mounted on an island 310 and sealed with a mold resin 320. Hereinafter, the up, down, left, and right directions on the paper are defined as the up, down, left, and right directions in a plan view of the semiconductor device 100 (or the semiconductor chip 300).

[0086] The semiconductor chip 300 has eight pads P1 to P8. Pad P1 is a pad corresponding to the output terminal of the operational amplifier 1a and is connected to the tip side of pin 1 (OUT1) via a wire W1. Pad P2 is a pad corresponding to the inverting input terminal (-) of the operational amplifier 1a and is connected to pin 2 (IN1-) via a wire W2. Pad P3 is a pad corresponding to the non-inverting input terminal (+) of the operational amplifier 1a and is connected to pin 3 (IN1+) via a wire W3. Pad P4 is a ground pad and is connected to the tip side of pin 4 (VEE) via a wire W4.

[0087] Pad P5 corresponds to the non-inverting input terminal (+) of operational amplifier 1b and is connected to pin 5 (IN2+) via wire W5. Pad P6 corresponds to the inverting input terminal (-) of operational amplifier 1b and is connected to pin 6 (IN2-) via wire W6. Pad P7 corresponds to the output terminal of operational amplifier 1b and is connected to pin 7 (OUT 2 Pad P8 is a power supply pad and is connected to the tip of pin 8 (VCC) via wire W8.

[0088] The pads P1 to P8 are arranged along the outer periphery of the semiconductor chip 300 in an order corresponding to pins 1 to 8. This makes it possible to shorten the lengths of the wires W1 to W8 connecting the pads and pins.

[0089] Also, when looking at the frame area inside the package, pin 1 (OUT1), pin 4 (VEE), pin 5 (IN2+), and pin 8 (VCC) are all larger than pin 2 (IN-), pin 3 (IN1+), pin 6 (IN2-), and pin 7 (OUT2).

[0090] That is, looking at the top and bottom of the paper, pin 1 (OUT1) and pin 4 (VEE) have parts that protrude more than pin 2 (IN1-) and pin 3 (IN1+). Similarly, pin 5 (IN2+) and pin 8 (VCC) have parts that protrude more than pin 6 (IN2-) and pin 7 (OUT2).

[0091] Furthermore, looking left and right on the paper, pin 1 (OUT1) and pin 4 (VEE) partially overlap with island 310. Similarly, pin 5 (IN2+) and pin 8 (VCC) partially overlap with island 310.

[0092] Furthermore, support frames 330 and 340 for supporting the island 310 are formed between pin 1 (OUT) and pin 8 (VCC), and between pin 4 (VEE) and pin 5 (IN2+), respectively.

[0093] 9 is a diagram showing an example of a wiring layout in the third embodiment. In the following, the up, down, left, and right directions on the paper are defined as the up, down, left, and right directions in a plan view of the semiconductor chip 300, and the wiring layout (and pad arrangement) will be described with appropriate reference to the above-mentioned FIGS. 7 and 8.

[0094] The left side of the semiconductor chip 300 in this figure corresponds to the top side of the semiconductor chip 300 in Fig. 8. Similarly, the right side, top side, and bottom side of the semiconductor chip 300 in this figure correspond to the bottom side, right side, and left side of the semiconductor chip 300 in Fig. 8, respectively. In other words, the semiconductor chip 300 in this figure corresponds to the semiconductor chip 300 in Fig. 8 rotated 90 degrees counterclockwise.

[0095] In addition, in a plan view of the semiconductor chip 300, the positions at which the pads P1 to P8 are provided correspond to the positions shown in FIG.

[0096] Specifically, the pad P1 (OUT1) and the pad P2 (IN1-) are arranged in the vicinity of the upper left corner 300a of the semiconductor chip 300, from the top to the bottom of the paper, in the order of pads P1 and P2.

[0097] The pads P3 (IN1+), P4 (VEE), and P5 (IN2+) are arranged in this order from left to right on the paper near the bottom edge of the semiconductor chip 300. The pad P4 is provided at approximately the center of the bottom edge of the semiconductor chip 300 in the left-right direction.

[0098] The pad P6 (IN2-) and the pad P7 (OUT2) are arranged in the vicinity of the upper right corner 300d of the semiconductor chip 300, from the bottom to the top of the page, in the order of pads P6 and P7.

[0099] The pad P8 (VCC) is provided in the vicinity of the upper side of the semiconductor chip 300, at approximately the center of the upper side in the left-right direction.

[0100] The power supply line L1 is laid out while bending or branching from the pad P8 (VCC) toward various circuit elements (for example, operational amplifiers 1a and 1b and reference current setting unit 2) formed in the element placement area A. In this figure, a wiring layout in which two power supply lines L1 extend in the vertical direction of the paper is illustrated, but another power supply line L1 may be laid out extending in the other direction.

[0101] Element placement area A occupies the center of the semiconductor chip 300 and is surrounded by pads P1 to P8. Inside element placement area A, circuit blocks are formed in the following order from left to right on the page: operational amplifier 1a (including a differential input stage 1Xa and an amplifier output stage 1Ya), reference current setting section 2 and electrostatic protection element 3, and operational amplifier 1b (including a differential input stage 1Xb and an amplifier output stage 1Yb). Of course, other circuit blocks may also be formed in element placement area A.

[0102] In this figure, corresponding to FIG. 10 described later, the wirings L11 and L12 connected to the operational amplifier 1a and the reference current setting section 2, respectively, are depicted by thick dashed lines.

[0103] Furthermore, wiring lines L13a and L13b are respectively laid between the differential input stage 1Xa of the operational amplifier 1a and the reference current setting unit 2, and between the differential input stage 1Xb of the operational amplifier 1b and the reference current setting unit 2. These wiring lines L13a and L13b form first sub-contacts 130a and 130b, respectively, which have lower impedance than the p-type substrate 101 (see also FIG. 10 described later).

[0104] The wiring L13 forming the first sub-contact 130 is divided into a plurality of wirings L13a and L13b laid inside the element placement area A. That is, the semiconductor chip 300 has a plurality of first sub-contacts 130 formed therein that are electrically connected to the p-type substrate 101, and some of these are arranged inside the element placement area A.

[0105] The plurality of wirings L13 are arranged in a stepping-stone pattern from the element placement area A to the pad P4 (VEE), and at least one of them is electrically connected to the pad P4 (VEE). That is, some of the plurality of wirings L13 are directly connected to the pad P4 (VEE), while others are electrically floating. The reason for dividing the wiring L13 into a plurality of wirings is to lay another wiring (for example, a power supply line L1) formed in the same wiring layer in the gap area between the plurality of wirings L13.

[0106] By adopting such a wiring layout, a low-impedance noise propagation path can be formed via a series of adjacent wirings L13 arranged like stepping stones, without interfering with the installation of the power supply line L1, etc. As a result, noise propagating inside the element placement area A can be absorbed by the wiring L13 and ultimately released to the pad P4 (VEE), thereby improving the noise characteristics of each of the operational amplifiers 1a and 1b.

[0107] Furthermore, among the multiple circuit elements formed within the element placement area A, it is desirable to design the width of the wiring L13a and L13b adjacent to specific circuit elements (for example, transistors forming the differential input stages 1Xa and 1Xb of the operational amplifiers 1a and 1b, respectively) that should avoid noise interference, to be wider than the width of the wiring L13 that is not adjacent to the specific circuit elements.

[0108] Furthermore, as shown in this figure, it is desirable that the wiring L13 (and therefore the first sub-contact 130) be formed between the differential input stages 1Xa and 1Xb and the power supply line L1, between the amplifier output stages 1Ya and 1Yb and the power supply line L1 or the reference current setting section 2, and between the electrostatic protection element 3 and the power supply line L1.

[0109] The power supply line L1 and the wirings L11 and L12 are several μm wide (for example, 2 to 9 μm). On the other hand, the wiring L13 is several tens of μm wide (for example, 50 μm or more). Thus, the wiring L13 (and therefore the width of the first sub-contact 130) is at least five times, and more preferably at least ten times, the width of the power supply line L1 and the wirings L11 and L12.

[0110] Furthermore, the reference current setting section 2 and the power supply line L1, and the power supply line L1 and the wiring L13 (and therefore the first sub-contact 130) are adjacent to each other.

[0111] Furthermore, wiring L13 (and thus first sub-contact 130) has a first portion (for example, a portion adjacent to differential input stage 1Xa or 1Xb) whose distance to differential input stage 1Xa or 1Xb is shorter than the distance to amplifier output stage 1Ya or 1Yb, and a second portion (for example, a portion adjacent to amplifier output stage 1Ya or 1Yb) whose distance to differential input stage 1Xa or 1Xb is longer than the distance to amplifier output stage 1Ya or 1Yb, and in a planar view of semiconductor chip 300, the width of the first portion is greater than the width of the second portion.

[0112] The power supply line L1 passes through a plurality of wires L13 (and therefore the first sub-contacts 130) and is connected to the differential input stages 1Xa and 1Xb.

[0113] Furthermore, the wiring L13 (and therefore the first sub-contact 130) is arranged so as to run vertically or transversely through an approximately central region of the element placement area A in a plan view of the semiconductor chip 300. The above-mentioned approximately central region refers to an area that is at least a predetermined length (for example, 1 / 5 or more of the total length of the upper and lower sides of the element placement area A) away from two sides (the left and right sides in this drawing) of the element placement area A that are approximately parallel to the laying direction of the wiring L13 (the vertical direction on the paper) in a plan view of the semiconductor chip 300.

[0114] In addition, wiring L14 that forms the second sub-contact 140 is laid on the outer periphery of the semiconductor chip 300. Therefore, for example, it becomes possible for the second sub-contact 140 to absorb noise that attempts to enter the inside of the chip of the semiconductor device 100.

[0115] The wiring L14 does not necessarily have to be formed in a continuous loop, and for example, four wirings L14 formed in straight lines along each side may be laid out. In this case, the wirings L14 on each side may be laid out so as to interlock with each other in a plan view at the four corners of the semiconductor chip 300 (see, for example, the upper left corner 300a, the lower left corner 300b, and the lower right corner 300c of the semiconductor chip 300).

[0116] FIG. 10 is a diagram schematically showing the α-β longitudinal cross section of FIG. 9. The device structure in this diagram is basically the same as that of the first embodiment (FIG. 2) described above, and transistors 110a and 110b are illustrated as exemplary circuit elements forming operational amplifiers 1a and 1b (particularly differential input stages 1Xa and 1Xb), respectively. Furthermore, a transistor 120 is illustrated as an exemplary circuit element forming the reference current setting unit 2. Note that, corresponding to FIG. 9, wirings L11 and L12 are connected to the transistors 110a and 120, respectively.

[0117] Furthermore, first sub-contacts 130a and 130b are provided between the transistor 110a and the transistor 120 (and the power supply line L1) and between the transistor 110b and the transistor 120 (and the power supply line L1), respectively.

[0118] Therefore, for example, noise traveling inside (lower layer) of semiconductor device 100 from transistor 110a via p-type substrate 101 propagates to first sub-contact 130a without reaching transistor 120, and is finally released from wiring L13a to pad P4 (ground pad). Furthermore, noise traveling on the surface (upper layer) of semiconductor device 100 is absorbed by wiring L13a, as in the comparative example described above (FIG. 1).

[0119] Furthermore, the semiconductor device 100 is provided with a second sub-contact 140 as a GND guard ring that surrounds the periphery of the element placement area A. Therefore, the second sub-contact 140 can absorb noise that attempts to enter the interior of the semiconductor chip 300. These effects are basically the same as those of the first embodiment (FIG. 2) described above.

[0120] In this figure, following the example of FIG. 2, only npn bipolar transistors 110a and 110b and a pnp bipolar transistor 120 are shown as circuit elements formed in element placement area A, but it goes without saying that other circuit elements such as NMOSFETs or PMOSFETs may also be formed.

[0121] Furthermore, the circuit blocks for which noise interference needs to be prevented differ depending on the application and field of the semiconductor device 100. Therefore, it is important to provide the first sub-contact 130 in an appropriate position.

[0122] <Semiconductor Device (Fourth Embodiment)> FIG. 11 is a diagram illustrating a fourth embodiment of a semiconductor device. Similar to the second embodiment (FIG. 4), the semiconductor device 100 of this embodiment integrates a one-channel operational amplifier 1 (including a differential input stage 1X and an amplifier output stage 1Y (the amplifier stage 1Y1 and the output stage 1Y2 are depicted separately in this figure)) and a reference current setting unit 2. In this case, for example, first sub-contacts 130 (only the wiring L13 is depicted in this figure) may be arranged so as to sandwich both sides (top and bottom in this figure) of the differential input stage 1X of the operational amplifier 1. That is, the wiring L13 (and therefore the first sub-contact 130) may be arranged between the differential input stage 1X and the reference current setting unit 2, and between the differential input stage 1X and the amplifier output stage 1Y (the amplifier stage 1Y1 and the output stage 1Y2).

[0123] At least a part of the power supply line L1 is preferably placed between the differential input stage 1X and the amplifier output stage 1Y.

[0124] Furthermore, as shown in this figure, it is preferable to arrange the wiring L13 between the differential input stage 1X and the power supply line L1, between the amplifier output stage 1Y (amplifier stage 1Y1 and output stage 1Y2) and the power supply line L1, and between the amplifier output stage 1Y (particularly output stage 1Y2) and the reference current setting unit 2 or the input pad (IN+, IN-).

[0125] Additionally, it is preferable to arrange second sub-contacts 140 along the outer periphery of the semiconductor device 100.

[0126] As explained above, such a device structure can block the propagation of not only noise that propagates on the surface (upper layer) of the semiconductor device 100, but also noise that propagates inside (lower layer) the semiconductor device 100, thereby making it possible to effectively suppress noise interference in the operational amplifier 1.

[0127] <Noise characteristics evaluation> 12 is a diagram showing a measurement circuit for a radio wave emission test in which the semiconductor device 100 is a DUT (device under test). In addition to the semiconductor device 100 serving as the DUT, the measurement circuit 200 for the radio wave emission test includes a signal generator 201, an amplifier 202, an antenna 203, a pseudo power supply 204 (e.g., VCC=12V), a wire harness 205, and an oscilloscope 206. Of these, the antenna 203, the pseudo power supply 204, the wire harness 250, and the semiconductor device 100 serving as the DUT are all placed in an anechoic chamber 207.

[0128] In a radio wave emission test using measurement circuit 200, a noise signal having a predetermined field strength (e.g., 200 Vrms) is radiated from antenna 203 toward a noise injection point on wire harness 205. The total length of wire harness 205 is 150 cm, and the distance from the noise injection point to semiconductor device 100 is 75 cm. The distance from antenna 203 to the noise injection point is 100 cm. These dimensions comply with ISO11452-2.

[0129] In the above-described measuring circuit 200, if the wire harness 205 is connected to the power supply terminal VCC of the semiconductor device 100, a noise signal is indirectly injected into the power supply terminal VCC of the semiconductor device 100. At this time, the frequency of the noise signal is swept within a predetermined range (for example, 200 MHz to 1 GHz) while the output voltage appearing at the output terminal OUT (or output terminal OUT1 or OUT2) of the semiconductor device 100 is successively read, thereby making it possible to obtain a plot of frequency vs. output voltage.

[0130] 13 is a diagram showing an example of the results of a radio wave emission test, in which the horizontal axis represents the frequency of the noise signal, and the vertical axis represents the output voltage of the semiconductor device 100.

[0131] Moreover, the solid lines show the test results when the semiconductor device 100 of the first to fourth embodiments (see Figures 2 to 11) was used as the DUT, and the dashed lines show the test results when the semiconductor device 100 of the comparative example (Figure 1) was used as the DUT.

[0132] As can be seen from this figure, the semiconductor device 100 of the first to fourth embodiments can significantly suppress noise peaks over the entire frequency sweep range. As such, the semiconductor device 100 of the first to fourth embodiments has excellent noise characteristics (particularly electromagnetic susceptibility), and output fluctuations are extremely small even when noise is input. Therefore, noise countermeasures for sets incorporating the semiconductor device 100 are simplified, making them extremely easy to use.

[0133] <Application to vehicles> 14 is a diagram showing the exterior of a vehicle X. The vehicle X in this figure is equipped with various electronic devices X11 to X18 that operate on power supplied from a battery.

[0134] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0135] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0136] The electronic device X11 is an electronic control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related controls (such as torque control and power regeneration control).

[0137] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0138] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0139] The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0140] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0141] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0142] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0143] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0144] The semiconductor device 100 described above can be incorporated into any of the electronic devices X11 to X18.

[0145] <Summary> The following provides a general description of the various embodiments disclosed herein.

[0146] For example, the semiconductor device disclosed in this specification has one or more first sub-contacts electrically connected to a substrate, at least one of which is formed in an element placement region on the substrate and has a configuration (first configuration) that has a lower impedance than the substrate.

[0147] In the semiconductor device having the first configuration, at least one of the first sub-contacts may be adjacent to a circuit element formed in the element placement region (second configuration).

[0148] Furthermore, a semiconductor device having the above first or second configuration may have a configuration (third configuration) in which an epitaxial layer of a second conductivity type is formed on the substrate of a first conductivity type, and the first sub-contact includes a first wiring having a lower impedance than the substrate, and a semiconductor region of the first conductivity type that penetrates the epitaxial layer and provides electrical conductivity between the first wiring and the substrate.

[0149] Furthermore, the semiconductor device having the third configuration may have a configuration (fourth configuration) in which second wirings are laid between a plurality of the first wirings.

[0150] Furthermore, in a semiconductor device having the third or fourth configuration, the width of the first wiring adjacent to a specific circuit element may be wider than the width of the first wiring not adjacent to the specific circuit element (fifth configuration).

[0151] In the semiconductor device having the fifth configuration, the specific circuit element may be a transistor forming a differential input stage (sixth configuration).

[0152] In addition, in the semiconductor device having any one of the first to sixth configurations, at least one of the first sub-contacts may be configured to be electrically connected to a ground pad (seventh configuration).

[0153] Furthermore, in the semiconductor device having any of the first to seventh configurations, the width of the first sub-contact may be configured to be equal to or greater than the minimum width of a circuit element formed in the element placement region (eighth configuration).

[0154] Furthermore, the semiconductor device having any one of the first to eighth configurations may be configured (ninth configuration) to further include a second sub-contact formed so as to surround the periphery of the element placement region.

[0155] Furthermore, in a semiconductor device having any of the first to ninth configurations above, the insulating layer covering the opening of the circuit element formed in the element placement region may be configured to be thinner than the insulating layer covering other portions (tenth configuration).

[0156] In the semiconductor device having any one of the first to tenth configurations, the first sub-contact is provided between a differential input stage of an operational amplifier and a power supply line, The aforementioned The amplifier output stage of the operational amplifier The aforementioned Between the power supply line and the electrostatic protection element The aforementioned It may be configured (eleventh configuration) that the power supply line is provided between the power supply line and at least one of the power supply lines.

[0157] In addition, in the semiconductor device having the eleventh configuration, at least a part of the power supply line may be arranged between the differential input stage and the amplifier output stage (twelfth configuration).

[0158] In addition, in a plan view of the semiconductor device having the eleventh or twelfth configuration, the width of the first sub-contact may be five times or more the width of the power supply line (thirteenth configuration).

[0159] In addition, in a semiconductor device having any of the above configurations 11 to 13, the reference current setting section that sets the reference current of the operational amplifier and the power supply line, and the power supply line and the first sub-contact may be configured adjacent to each other (configuration 14).

[0160] In addition, in the semiconductor device having any one of the eleventh to fourteenth configurations, the first sub-contact may be arranged between the differential input stage and the amplification output stage (fifteenth configuration).

[0161] Furthermore, in a semiconductor device having any of the above-mentioned configurations 11 to 15, the first sub-contact may have a first portion whose distance to the differential input stage is shorter than the distance to the amplifier output stage, and a second portion whose distance to the differential input stage is longer than the distance to the amplifier output stage, and the width of the first portion may be larger than the width of the second portion in a planar view (configuration 16).

[0162] In addition, in a semiconductor device having any of the above-mentioned configurations 11 to 16, the power supply line may be configured (configuration 17) to pass between a plurality of the first sub-contacts and be connected to the differential input stage.

[0163] Furthermore, in the semiconductor device having any one of the first to seventeenth configurations, the first sub-contact may be configured (eighteenth configuration) to be arranged in a substantially central region of the element arrangement region in a plan view.

[0164] In the semiconductor device having the eighteenth configuration, the first sub-contact may be configured to extend vertically or transversely across the approximately central region (nineteenth configuration).

[0165] Furthermore, the electronic device disclosed in this specification has a configuration (20th configuration) that includes a semiconductor device having any one of the first to nineteenth configurations.

[0166] <Other variations> In the above embodiment, an operational amplifier used in an in-vehicle device is given as an example, but the application is not limited to this in any way, and the operational amplifier can be widely and generally applied to a wide range of applications, including consumer devices and industrial devices.

[0167] Furthermore, in addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. For example, bipolar transistors can be substituted for MOS field-effect transistors, or the logic levels of various signals can be inverted. In other words, the above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is not limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Industrial Applicability]

[0168] The semiconductor device (or operational amplifier) ​​disclosed in this specification can be used in, for example, in-vehicle equipment, consumer equipment, or industrial equipment. [Explanation of symbols]

[0169] 1, 1a, 1b operational amplifiers 1X, 1Xa, 1Xb differential input stage 1Y, 1Ya, 1Yb, 1Y1, 1Y2 amplifier output stage 2 Reference current setting section 3. Electrostatic protection element 100 Semiconductor device 101 p-type substrate 102 n-type epitaxial layer 103 p-type element isolation section 104, 104x insulating layer 110, 110a, 110b npn bipolar transistor 111 n-type semiconductor region 112 n-type semiconductor region 113 p-type semiconductor region 114 n-type semiconductor region 115 p-type semiconductor region 116 Conductive materials 120 PNP bipolar transistor 121 n-type semiconductor region 122 n-type semiconductor region 123 p-type semiconductor region 124 p-type semiconductor region 125 p-type semiconductor region 126 Conductive materials 130, 130a, 130b First sub-contact 131 p-type semiconductor region 132 p-type semiconductor region 133 Conductive materials 140 Second Sub-Contact 141 p-type semiconductor region 142 p-type semiconductor region 143 Conductive materials 200 Measuring circuit (radio emission test) 201 Signal Generator 202 Amplifier 203 Antenna 204 Pseudo power supply 205 Wire harness 206 Oscilloscope 207 Radio Wave Anechoic Chamber 300 semiconductor chips 300a~300d Upper left corner, lower left corner, lower right corner, upper right corner 310 Island 320 Molding resin 330, 340 support frame A. Element placement area C0, C1, C2 parasitic capacitors C3 capacitor Cp Parasitic capacitor D1, D2 electrostatic protection diodes I1~I7 Current source L1 Power line L2 ground line L3 Reference current setting line L4 output line L11, L12, L13, L13a, L13b, L14 wiring P1~P8 pads Q1~Q6 pnp bipolar transistors Q7~Q13 npn bipolar transistors R0 resistance (power supply resistance) R1, R2 Resistors (input resistors) R3 resistance W1~W8 wires X vehicle X11~X18 Electronic equipment

Claims

1. the first sub-contact has one or more first sub-contacts electrically connected to a substrate, at least one of the first sub-contacts being formed in an element placement region on the substrate and having a lower impedance than the substrate; an epitaxial layer of a second conductivity type is formed on the substrate of a first conductivity type; The first sub-contact is a first wiring having a lower impedance than the substrate; the first conductivity type semiconductor region penetrating the epitaxial layer and electrically connecting the first wiring to the substrate; 10. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein at least one of said first sub-contacts is adjacent to a circuit element formed in said element placement region.

3. 3. The semiconductor device according to claim 1, wherein a second wiring is laid between a plurality of the first wirings.

4. 4. The semiconductor device according to claim 1, wherein a width of the first wiring adjacent to a specific circuit element is wider than a width of the first wiring not adjacent to the specific circuit element.

5. 5. The semiconductor device according to claim 4, wherein the specific circuit element is a transistor forming a differential input stage.

6. 6. The semiconductor device according to claim 1, wherein at least one of the first sub-contacts is electrically connected to a ground pad.

7. 7. The semiconductor device according to claim 1, wherein the width of said first sub-contact is equal to or greater than the minimum width of a circuit element formed in said element placement region.

8. 8. The semiconductor device according to claim 1, further comprising a second sub-contact formed so as to surround the periphery of said element placement region.

9. 9. The semiconductor device according to claim 1, wherein the insulating layer covering the openings of the circuit elements formed in the element placement region is thinner than the insulating layer covering the other portions.

10. The semiconductor device according to any one of claims 1 to 9, wherein the first sub-contact is provided at least one of between a differential input stage of an operational amplifier and a power supply line, between an amplification output stage of the operational amplifier and the power supply line, and between an electrostatic protection element and the power supply line.

11. A semiconductor device having one or more first sub-contacts electrically connected to a substrate, at least one of which is formed in an element placement area on the substrate and has a lower impedance than the substrate; The semiconductor device, wherein the first sub-contact is provided at least one of between a differential input stage of an operational amplifier and a power supply line, between an amplification output stage of the operational amplifier and the power supply line, and between an electrostatic protection element and the power supply line.

12. 12. The semiconductor device according to claim 10, wherein at least a portion of the power supply line is provided between the differential input stage and the amplifier output stage.

13. 13. The semiconductor device according to claim 10, wherein the width of said first sub-contact is five times or more the width of said power supply line in a plan view.

14. 14. The semiconductor device according to claim 10, wherein a reference current setting section that sets a reference current of the operational amplifier and the power supply line, and the power supply line and the first sub-contact are adjacent to each other.

15. 15. The semiconductor device according to claim 10, wherein the first sub-contact is disposed between the differential input stage and the amplifier output stage.

16. the first sub-contact has a first portion whose distance to the differential input stage is shorter than its distance to the amplifier output stage, and a second portion whose distance to the differential input stage is longer than its distance to the amplifier output stage; 16. The semiconductor device according to claim 10, wherein the width of said first portion is larger than the width of said second portion in a plan view.

17. 17. The semiconductor device according to claim 10, wherein the power supply line passes through a plurality of the first sub-contacts and is connected to the differential input stage.

18. 18. The semiconductor device according to claim 1, wherein the first sub-contact is arranged in a substantially central region of the element arrangement region in a plan view.

19. The semiconductor device according to claim 18 , wherein the first sub-contact extends longitudinally or transversely across the substantially central region.

20. An electronic device comprising the semiconductor device according to any one of claims 1 to 19.

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