Image sensor and electronic device

Abstract

To provide an imaging element and an electronic apparatus with which it is possible to reduce the area of substrates.SOLUTION: The present invention comprises: a first substrate on which a plurality of photoelectric conversion elements and a transfer transistor that is formed for each photoelectric conversion element and used to transfer the electric signal outputted from the photoelectric conversion element; and a second substrate on which, for each set in units of two or more photoelectric conversion elements, one or more pixel transistors are formed that are shared by the set. On the first substrate is formed, as the output terminal side of each transfer transistor, a floating diffusion that temporarily holds the electric signal outputted from each photoelectric conversion element, and a second wiring linked to each of the floating diffusions is connected to one contact that a plurality of second wirings share and connected via the contact to a first wiring formed on the second substrate.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to an imaging element and an electronic device such as a camera equipped with the imaging element. [Background technology]

[0002] For example, in an imaging device such as a CMOS (Complementary Metal Oxide Semiconductor), a configuration is known in which a first semiconductor substrate on which a pixel region is formed and a second semiconductor substrate on which a logic circuit is formed are stacked (see, for example, Patent Document 1, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-245506 Summary of the Invention [Problem to be solved by the invention]

[0004] In the imaging device disclosed in Patent Document 1, a photoelectric conversion element and a pixel transistor for reading out an electrical signal corresponding to the amount of light received by the photoelectric conversion element are formed on the same semiconductor substrate. However, with this configuration, it is not possible to sufficiently reduce the area of ​​the substrate (the space on the surface of the substrate where circuit components such as transistors are formed).

[0005] Therefore, it is conceivable to stack a substrate (first substrate) on which photoelectric conversion elements are formed and a substrate (second substrate) on which pixel transistors are formed separately. In such a configuration, for example, it is assumed that a plurality of photoelectric conversion elements that correspond one-to-one to a plurality of pixels share one pixel transistor. In this case, among elements (for example, circuit components such as transistors) formed on the first substrate, a plurality of first elements each formed for each photoelectric conversion element are commonly connected to a second element that is a shared element.

[0006] In the above configuration, it is necessary to connect each of the first elements on the first substrate with a contact to the wiring formed on the second substrate that connects to the second element they share, which increases the number of wiring contacts and increases the area.

[0007] The present disclosure aims to provide an imaging element and an electronic device that can reduce the area of ​​a substrate. [Means for solving the problem]

[0008] In order to achieve the above object, the imaging element of the present disclosure is an imaging element comprising: a first substrate on which a plurality of photoelectric conversion elements are formed; a second substrate on which pixel transistors shared by groups of two or more photoelectric conversion elements are formed; and wiring that connects to second elements shared by a plurality of first elements formed for each photoelectric conversion element among a plurality of elements formed on the first substrate, the second wiring being connected to the first wiring formed on the second substrate by one contact and to which the plurality of first elements are connected.

[0009] Here, the term "element" refers to a concept that includes some or all of the circuit components, such as photoelectric conversion elements, transistors, and wiring (including electrodes), formed on a substrate (semiconductor substrate). Furthermore, a "pixel transistor" is a transistor that reads out an electrical signal corresponding to the amount of light received by a photoelectric conversion element and that can be shared by multiple photoelectric conversion elements (pixels). For example, a pixel transistor includes at least an amplifier transistor that amplifies and outputs the electrical signal supplied from the photoelectric conversion element.

[0010] (Operation) In the imaging element of the present disclosure, a wiring is provided that is connected to a second element shared by multiple first elements on a first substrate, and is connected to the first wiring formed on the second substrate by a single contact, and to which the multiple first elements are connected. In other words, this second wiring aggregates the multiple first elements and is connected by a single contact to the wiring that is connected to the second element shared (commonly connected) by the multiple first elements. This allows only one contact to be formed on the first wiring to connect the multiple first elements in an aggregated unit to the first wiring, thereby reducing the number of contacts and the area of ​​the first wiring.

[0011] Furthermore, in the imaging element of the present disclosure, the first substrate on which the photoelectric conversion elements are formed and the second substrate on which the pixel transistors are formed are stacked separately, which makes it possible to reduce the area on the substrate. [Effects of the Invention]

[0012] According to the present disclosure, the area of ​​the substrate can be reduced. Note that the effects described herein are not necessarily limited to those described herein, and may be any of the effects described in the present disclosure. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging element applied to each embodiment of the present disclosure. [Figure 2] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 3] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 4] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 5] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 6] FIG. 10 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 7]2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the vertical direction. [Figure 8] FIG. 10 is a diagram showing a modified example of an N-type semiconductor region that configures the photodiode of the first embodiment. [Figure 9] 4A and 4B are diagrams illustrating a modified example of the structure of the image sensor according to the first embodiment. [Figure 10] FIG. 10 is a diagram showing the arrangement of bonding points between a second substrate and a third substrate. [Figure 11] 10A and 10B are diagrams showing modified examples of the arrangement of the bonding points between the second substrate and the third substrate. [Figure 12] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 13] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 14] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 1. FIG. [Figure 15] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 1. FIG. [Figure 16] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 1. FIG. [Figure 17] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 1. FIG. [Figure 18] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 19] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 20] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 21] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 22] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 23] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 24]5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 25] 5A to 5C are diagrams for explaining an example of a method for manufacturing the image sensor according to the first embodiment. [Figure 26] FIG. 10 is a diagram showing a part of a cross section of an imaging element in the case where a configuration in which no wiring is provided is adopted. [Figure 27] FIG. 2 is a diagram illustrating a part of a cross section of the imaging element according to the first embodiment. [Figure 28] FIG. 2 is a schematic plan view of a first substrate of the first embodiment. [Figure 29] FIG. 3 is a schematic plan view of a second substrate of the first embodiment. [Figure 30] FIG. 2 is a schematic plan view showing a state in which the second substrate and the first substrate of the first embodiment are superimposed on each other. [Figure 31] FIG. 10 is a diagram showing a modified example of the wiring layout. [Figure 32] FIG. 4 is a schematic plan view of a first substrate according to a modified example of the first embodiment. [Figure 33] FIG. 10 is a schematic plan view of a second substrate according to a modified example of the first embodiment. [Figure 34] FIG. 10 is a diagram showing a part of a cross section of an imaging element according to a fourth embodiment. [Figure 35] FIG. 10 is a diagram showing a part of a cross section of an imaging element according to a fifth embodiment. [Figure 36] FIG. 13 is a diagram showing a part of a cross section of an imaging element according to a sixth embodiment. [Figure 37] FIG. 13 is a diagram showing a part of a cross section of an image sensor according to a modified example of the sixth embodiment. [Figure 38] 1 is a diagram illustrating an example of the configuration of a camera, which is an example of an electronic device to which an imaging element according to the present disclosure is applied. [Figure 39] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 40] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 41] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 42]2 is a diagram illustrating an example of a sensor pixel and a readout circuit in FIG. 1. [Figure 43] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the vertical direction. [Figure 44] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 45] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 46] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 47] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 48] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 49] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 50] 2 is a diagram illustrating an example of a cross-sectional configuration of the imaging element in FIG. 1 in the horizontal direction. [Figure 51] FIG. 10 is a diagram illustrating an example of a circuit configuration of an imaging device including the imaging device according to the above embodiment and its modified example. [Figure 52] FIG. 52 is a diagram showing an example in which the imaging element of FIG. 51 is configured by stacking three substrates. [Figure 53] 10 is a diagram illustrating an example in which a logic circuit is formed separately on a substrate on which sensor pixels are provided and a substrate on which a readout circuit is provided. FIG. [Figure 54] FIG. 10 is a diagram showing an example in which a logic circuit is formed on a third substrate. [Figure 55] FIG. 2 is a diagram illustrating an example of a schematic configuration of an imaging system including the imaging element. [Figure 56] FIG. 56 is a diagram showing an example of an imaging procedure in the imaging system of FIG. 55. [Figure 57] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 58] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 59] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 60] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, examples of an imaging device and an electronic device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The description will be given in the following order. 1. Example of the schematic configuration of an image sensor 2. First embodiment (example of configuration of image sensor) 3. Second embodiment (example of configuration of image sensor) 4. Third embodiment (example of configuration of image sensor) 5. Fourth embodiment (example of configuration of image sensor) 6. Fifth embodiment (example of configuration of image sensor) 7. Sixth embodiment (example of configuration of image sensor) 8. Seventh embodiment (example of configuration of electronic device) 9. Variations 10. Application Examples 11.Application Examples

[0015] <1. Example of the schematic configuration of an image sensor> 1 is a diagram showing an example of a schematic configuration of an image sensor 1 applied to each embodiment of the present disclosure. The image sensor 1 converts received light into an electrical signal and outputs it as a pixel signal. In this example, the image sensor 1 is configured as a CMOS image sensor.

[0016] 1 illustrates an example of a schematic configuration of an imaging element 1 according to an embodiment of the present disclosure. The imaging element 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging element 1 is an imaging device with a three-dimensional structure formed by bonding together the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0017] The first substrate 10 has, on a semiconductor substrate 11, a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within a pixel region 13 of the first substrate 10. The second substrate 20 has, on a semiconductor substrate 303, a readout circuit 22 for every four sensor pixels 12. The readout circuit 22 outputs pixel signals based on electric charges output from the sensor pixels 12. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has, on a semiconductor substrate 31, a logic circuit 32 that processes pixel signals. The logic circuit 32 has, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout for each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low-resistance region made of silicide such as CoSi2 or NiSi formed using a salicide (self-aligned silicide) process may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0018] The vertical drive circuit 33, for example, sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts signal levels of the pixel signals by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0019] Fig. 2 shows an example of a sensor pixel 12 and a readout circuit 22. Below, a case will be described in which four sensor pixels 12 share one readout circuit 22, as shown in Fig. 2. Here, "shared" means that the outputs of the four sensor pixels 12 are input to a common readout circuit 22.

[0020] The sensor pixels 12 have common components. In Fig. 2, in order to distinguish the components of the sensor pixels 12 from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of the sensor pixels 12. Hereinafter, when it is necessary to distinguish the components of the sensor pixels 12 from one another, identification numbers are added to the end of the reference numerals of the components of the sensor pixels 12. However, when it is not necessary to distinguish the components of the sensor pixels 12 from one another, the identification numbers at the end of the reference numerals of the components of the sensor pixels 12 are omitted.

[0021] Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of a "photoelectric conversion element" in the present disclosure. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 23. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0022] The floating diffusions FD of the sensor pixels 12 that share one readout circuit 22 are electrically connected to each other and to the input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel drive line 23 (see FIG. 1). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to a vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see FIG. 1).

[0023] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP forms a source follower amplifier and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0024] As described above, each unit (hereinafter sometimes referred to as a "shared unit" or "shared unit circuit") in which four sensor pixels 12 share one readout circuit 22 includes four photoelectric conversion elements PD, four transfer transistors TR corresponding one-to-one to the four photoelectric conversion elements PD, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL. In this example, the four pixels (sensor pixels 12 including at least a photoelectric conversion element PD) share a combination of one amplification transistor AMP, one reset transistor RST, and one selection transistor SEL. In this example, the combination of one amplification transistor AMP, one reset transistor RST, and one selection transistor SEL corresponds to a "pixel transistor."

[0025] As described above, the first substrate 10, which corresponds to the "first substrate" of the present disclosure, has a plurality of photodiodes PD formed thereon, each of which corresponds one-to-one with a plurality of pixels. More specifically, the first substrate 10 also has a transfer transistor TR formed thereon for each of the plurality of photodiodes PD, for transferring an electrical signal output from the photodiode PD to a pixel transistor. Here, two photodiodes PD included in the plurality of photodiodes PD formed on the first substrate 10 correspond to a "first photoelectric conversion element" and a "second photoelectric conversion element." The transfer transistor TR connected to the photodiode PD corresponding to the first photoelectric conversion element corresponds to a "first transfer transistor," and the transfer transistor TR connected to the photodiode PD corresponding to the second photoelectric conversion element corresponds to a "second transfer transistor." In other words, the first substrate 10 can be considered to have a first photoelectric conversion element and a second photoelectric conversion element formed thereon, a first transfer transistor connected to the first photoelectric conversion element, and a second transfer transistor connected to the second photoelectric conversion element.

[0026] Furthermore, on the second substrate 20, which corresponds to the "second substrate" of the present disclosure, a pixel transistor shared by each group of two or more (four in this example) photodiodes PD is formed. More specifically, on the second substrate 20, for each group or groups, a pixel transistor including at least one amplifier transistor AMP that amplifies and outputs an electrical signal transferred from each of two or more transfer transistors TR included in the group is formed. Here, it can be considered that the second substrate has pixel transistors connected to the first photoelectric conversion element and the second photoelectric conversion element formed thereon.

[0027] As shown in FIG. 3, the select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to the pixel drive line 23 (see FIG. 1). The source of the amplifier transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Furthermore, as shown in FIGS. 4 and 5, an FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplifier transistor AMP.

[0028] The FD transfer transistor FDG is used to change the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is large, the V when converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, the FD capacitance C must be large so that the V when converted to voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Considering these factors, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be varied, thereby changing the conversion efficiency.

[0029] 6 shows an example of a connection between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (e.g., the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. For example, as shown in FIG. 6, when four readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (e.g., the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. Note that in FIG. 6, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the vertical signal lines 24 to distinguish them from one another.

[0030] 2. First Embodiment (Example of imaging element configuration) Next, the configuration of the imaging device 1 according to the first embodiment will be described together with a manufacturing method thereof.

[0031] FIG. 7 is a diagram illustrating a portion of a cross section corresponding to one shared unit circuit in the image sensor 1 of this embodiment. As shown in FIG. 7, the image sensor 1 includes a first substrate 10, a second substrate 20, and a third substrate 30 on which peripheral circuits are formed, stacked and electrically connected. In this example, the peripheral circuits include a logic circuit 32 including a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36, and are formed on the third substrate 30. Alternatively, some or all of the elements included in the peripheral circuits (such as the vertical drive circuit 33, the column signal processing circuit 34, the horizontal drive circuit 35, and the system control circuit 36) may be formed on the first substrate 10 or the second substrate 20. In this example, the third substrate 30 includes at least the logic circuit 32. The logic circuit 32 corresponds to "a logic circuit formed on the second substrate and processing signals generated by the first photoelectric conversion element or the second photoelectric conversion element." The third substrate 30 corresponds to "the third substrate" in this disclosure. 7 indicates the surface where the first substrate 10 and the second substrate 20 are bonded together. Also, the surface 502 shown in Fig. 7 indicates the surface where the second substrate 20 and the third substrate 30 are bonded together.

[0032] The image sensor 1 of this embodiment includes wiring that connects to a second element shared by a plurality of first elements formed for each photodiode PD among the plurality of elements formed on the first substrate 10, the second wiring being connected to the first wiring formed on the second substrate 20 by a single contact, and to which the plurality of first elements are connected. In the example of FIG. 7 , the image sensor 1 includes wiring 301 ("second wiring") that connects the output terminal sides ("first elements") of the plurality of transfer transistors TR to wiring D1 ("first wiring") formed on the second substrate 20 by a single contact. Wiring D1 is also wiring that connects to the gate ("second element") of the amplification transistor AMP shared (connected in common) by the output terminal sides of the plurality of transfer transistors TR. This will be described in more detail below.

[0033] The configuration of the image sensor 1 shown in FIG. 7 will be described below. As shown in FIG. 7, the first substrate 10 is configured by laminating an insulating layer 240 on a semiconductor substrate 11. The first substrate 10 has the insulating layer 240 as part of an interlayer insulating film 51. The insulating layer 240 is provided in the gap between the semiconductor substrate 11 and a semiconductor substrate 303, which will be described later. The semiconductor substrate 11 is configured of a silicon substrate. The semiconductor substrate 11 has, for example, a P-type semiconductor region 204 (P well) in and near a part of its surface, and has a photodiode PD of a conductivity type (N-type) different from that of the P-type semiconductor region 204 in the other region (a region deeper than the P-type semiconductor region 204).

[0034] A plurality of photodiodes PD are formed on the first substrate 10. A plurality of transfer transistors TR are also formed on the first substrate 10 in one-to-one correspondence with the plurality of photodiodes PD. In the example of FIG. 7, the photodiodes PD are formed in an N-type semiconductor region, and a P-type semiconductor region 202 different from the photodiodes PD is formed so as to cover the side surfaces of the photodiodes PD. Each photodiode PD is electrically isolated by a pixel isolation section 203 for isolating (compartmentalizing) the pixels. For example, the pixel isolation section 203 is made of a metal, an insulating film (e.g., SiO2), a combination thereof, or the like.

[0035] An insulating film 211 is formed on the lower surface of the photodiode PD so as to cover the first substrate 10. The insulating film 211 is formed of, for example, a film having a fixed charge. An additional insulating film may be formed between the insulating film 211 and the color filter 212 as a planarization film 213. The insulating film 211 is formed of, for example, a metal oxide film such as hafnium oxide, tantalum oxide, or aluminum oxide, and the planarization film 213 is formed of, for example, an insulating film such as silicon oxide or silicon nitride. Note that the insulating film 211 and the planarization film 213 may each be provided in multiple layers. An on-chip lens 214 is formed below the color filter 212. The on-chip lens 214 collects irradiated light, and the collected light is guided to the photodiode PD via the color filter 212.

[0036] An N-type transfer transistor TR is formed on the photodiode PD. More specifically, a P-type semiconductor region 204 (P-well) is formed on the photodiode PD on the first substrate 10, and an N-type drain region 221 and an N-type source region 222 are formed near the surface of this semiconductor region 204. A gate electrode 223 is formed between the N-type drain region 221 and the N-type source region 222 on the semiconductor region 204. In this example, the gate electrode 223 is connected to the photodiode PD. In this example, the P-type semiconductor region 202 covering the side surface of the photodiode PD protrudes so as to cover part of the side surface of the semiconductor region 204, but this is not limiting and the depth of the P-type semiconductor region 202 is arbitrary. For example, the upper surface of the semiconductor region 202 and the lower surface of the semiconductor region 204 may be at the same height.

[0037] The depth of the photodiode PD may also be arbitrary, and for example, as shown in FIG. 8, a part of the photodiode PD may reach the same height as the surface of the P-type semiconductor region 204 in which the transfer transistor TR is formed. In such a case, it is preferable that a P-type semiconductor region is formed on the N-type photodiode PD, but it may not be formed as shown in FIG. 8. Furthermore, for example, as shown in FIG. 9, the gate electrode 223 of the transfer transistor TR may be formed on the semiconductor region 204 without being connected to the photodiode PD. In other words, the transfer transistor TR may have a planar transfer gate (gate electrode 223).

[0038] 7, the explanation will continue. As shown in Fig. 7, the source region 222 of each transfer transistor TR is connected to a wiring 301. In this example, the source region 222 is an N-type semiconductor region, so the wiring 301 is formed of P-type polysilicon. Each transfer transistor TR and the wiring 301 are covered with an insulating layer 240, and a semiconductor substrate 303 is formed on the insulating layer 240.

[0039] Here, the combination of semiconductor substrate 303 and each element formed on this semiconductor substrate 303 can be considered to correspond to the "second substrate" of the present disclosure, or semiconductor substrate 303 alone can be considered to correspond to the "second substrate" of the present disclosure. Similarly, with respect to first substrate 10, the combination of the base silicon substrate and each element formed on this silicon substrate can be considered to correspond to the "first substrate" of the present disclosure, or the silicon substrate alone can be considered to correspond to the "first substrate" of the present disclosure.

[0040] As described above, pixel transistors including at least the amplification transistor AMP are formed on the second substrate 20. In this example, each transistor included in the pixel transistor is an N-channel type MOS transistor, and therefore the semiconductor substrate 303 is a P-type silicon substrate.

[0041] The wiring 301 is connected to wiring D1 formed on the second substrate 20 via a contact Ct that penetrates the semiconductor substrate 303. In this example, the second substrate 20 is configured by laminating an insulating layer 245 on the semiconductor substrate 303. The second substrate 20 has the insulating layer 245 as part of an interlayer insulating film 51. The insulating layer 245 is provided in the gap between the semiconductor substrate 303 and a semiconductor substrate 31 (described later). The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided on the front surface side (the third substrate 30 side) of the semiconductor substrate 303. The second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 303 facing the front surface side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face-to-back. The second substrate 20 further includes an insulating layer 53 that penetrates the semiconductor substrate 303 and is located in the same layer as the semiconductor substrate 303. The second substrate 20 includes the insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided so as to cover the side surfaces of the contacts Ct that penetrate the semiconductor substrate 303.

[0042] The stacked body made up of the first substrate 10 and the second substrate 20 has one contact Ct for each sensor pixel 12. The first substrate 10 and the second substrate 20 are electrically connected to each other by the contact Ct. Specifically, the contact Ct is electrically connected to the floating diffusion FD and a wiring D1, which will be described later.

[0043] The stacked body made up of the first substrate 10 and the second substrate 20 further has through-hole wires 47, 48 (see FIG. 12 , etc., described later) provided in the interlayer insulating film 51. The stacked body has one through-hole wire 47 and one through-hole wire 48 for each sensor pixel 12. The through-hole wires 47, 48 each extend in a normal direction to the semiconductor substrate 303 and penetrate the semiconductor substrate 303. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-hole wires 47, 48. Specifically, the through-hole wire 47 is electrically connected to the P-type semiconductor region 204 of the semiconductor substrate 11 and to wiring in the second substrate 20. The through-hole wire 48 is electrically connected to the gate electrode 223 of the transfer transistor TR and the pixel drive line 23.

[0044] The contact Ct penetrates the insulating layer 245 and is connected to the wiring D1 included in the wiring layer 246 formed on the insulating layer 245. The wiring layer 246 includes, for example, an insulating layer 247, a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided in the insulating layer 247, etc. The wiring layer 246 further includes, for example, a plurality of pad electrodes 58 provided in the insulating layer 247. Each pad electrode 58 is formed of a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 246. Each pad electrode 58 is used for electrically connecting the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30 together. For example, one pad electrode 58 is provided for each pixel driving line 23 and vertical signal line 24. Here, the total number of pad electrodes 58 (or the total number of junctions between pad electrodes 58 and pad electrodes 64 (described later)) is smaller than the total number of sensor pixels 12 included in the first substrate 10.

[0045] The above-mentioned wiring D1 is connected to the gate electrode 311 of the amplification transistor AMP via the contact Ct2. The region from the source region 222 to the gate electrode 311 via the wiring 301 and wiring D1 is a region that functions as the above-mentioned FD.

[0046] That is, the wiring 301 aggregates the source regions 222 (output terminal side) of each transfer transistor TR on the first substrate 10. The wiring 301 connects the aggregated source regions 222 to a wiring D1 on the second substrate 20, which is connected to the gate electrode 311 of the amplifier transistor AMP shared by the source regions 222 of each transfer transistor TR, via a single contact Ct. Note that in this example, the wiring 301 is formed integrally, but is not limited to this. For example, the wiring 301 may be formed by connecting wirings formed from different materials. For example, the wiring 301 may be formed by connecting a wiring extending vertically from the source region 222 (output terminal side, FD) of each transfer transistor TR and a common wiring extending horizontally, which are formed from different materials.

[0047] Here, the source region 222 (output terminal side) of the transfer transistor TR corresponds to a "first element" formed for each photodiode PD among the multiple elements formed on the first substrate 10. The gate electrode 311 (gate) of the amplification transistor AMP corresponds to a "second element" to which the multiple first elements are commonly connected. The wiring D1 is a wiring connected to a second element shared by the multiple first elements, and corresponds to the "first wiring" formed on the second substrate 20. The wiring D1 also corresponds to the "second wiring formed on the second substrate 20." The wiring 301 is connected to the first wiring via one contact Ct and corresponds to the "second wiring" to which the multiple first elements are connected. As described above, the wiring 301 is connected (indirectly connected) to the corresponding photodiode PD via the source region 222 of each transfer transistor TR. In other words, the wiring 301 can also be considered to be "a first wiring formed on the first substrate 10 and connected to the first photoelectric conversion element and the second photoelectric conversion element." Note that "connection" in this disclosure includes not only a direct connection but also an indirect connection as described above. The wiring 301 is connected to the source region 222 of each transfer transistor TR. In other words, the wiring 301 can be considered to be connected to a first floating diffusion region connected to the first transfer transistor and a second floating diffusion region connected to the second transfer transistor. The contact Ct corresponds to "a third wiring formed to penetrate the first substrate 10 and the second substrate 20 and connected to the first wiring and the second wiring."

[0048] The third substrate 30 is formed, for example, by laminating an interlayer insulating film 61 on a semiconductor substrate 31. The semiconductor substrate 31 is formed of a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided on the front surface side of the semiconductor substrate 31. The third substrate 30 further includes, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed, for example, of Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used to electrically connect the second substrate 20 and the third substrate 30 and to bond the second substrate 20 and the third substrate 30 together. The number of pad electrodes 64 does not necessarily have to be multiple; even one pad electrode 64 can be electrically connected to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64. That is, the gate electrode 223 of the transfer transistor TR is electrically connected to the logic circuit 32 via the above-mentioned contact Ct and the pad electrodes 58, 64. The third substrate 30 is bonded to the second substrate 20 with the surface of the semiconductor substrate 31 facing the surface of the semiconductor substrate 303. That is, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0049] 10, a junction 503 between the pad electrode 58 of the second substrate 20 and the pad electrode 64 of the third substrate 30 overlaps the pixel region 13. However, this is not limiting, and a configuration as shown in FIG. 11, for example, may be used. In the configuration of FIG. 11, the junction 503 between the pad electrode 58 of the second substrate 20 and the pad electrode 64 of the third substrate 30 overlaps an area outside the pixel region 13. In other words, the pad electrode 58 of the second substrate 20 may be disposed outside the pixel region 13 and connected to the pad electrode 64 of the third substrate 30.

[0050] 12 and 13 illustrate an example of a horizontal cross-sectional configuration of the image sensor 1. The upper diagrams in FIGS. 12 and 13 illustrate an example of a cross-sectional configuration at cross section Sec1 in FIG. 7, and the lower diagrams in FIGS. 12 and 13 illustrate an example of a cross-sectional configuration at cross section Sec2 in FIG. 7. FIG. 12 illustrates an example of a configuration in which two sets of four 2×2 sensor pixels 12 are arranged in the second direction V2, and FIG. 13 illustrates an example of a configuration in which four 2×2 sensor pixels 12 are arranged in the first direction V1 and the second direction V2. Note that in the upper cross-sectional views in FIGS. 12 and 13, an example of a surface configuration of the semiconductor substrate 11 is superimposed on the diagram illustrating the example of the cross-sectional configuration at cross section Sec1 in FIG. 7, and the insulating layer 240 is omitted. In the lower cross-sectional views in FIGS. 12 and 13, an example of a surface configuration of the semiconductor substrate 303 is superimposed on the diagram illustrating the example of the cross-sectional configuration at cross section Sec2 in FIG. 7.

[0051] As shown in FIGS. 12 and 13, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a strip shape in a first direction V1 (the vertical direction in FIG. 12, the horizontal direction in FIG. 13) within the plane of the first substrate 10. Note that FIGS. 12 and 13 illustrate an example in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two columns in the first direction V1. The first direction V1 is parallel to one of two arrangement directions (e.g., the row direction and the column direction) of the plurality of sensor pixels 12 arranged in a matrix (e.g., the column direction). In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the pixel separator 203. In the four sensor pixels 12 that share the readout circuit 22, the gate electrodes 223 of the four transfer transistors TR are arranged to surround the four floating diffusions FD, and for example, the four gate electrodes 223 form a circular ring shape.

[0052] The insulating layer 53 present in the portion of the semiconductor substrate 303 through which the contact Ct penetrates is composed of multiple blocks extending in a first direction V1. The semiconductor substrate 303 extends in the first direction V1 and is composed of multiple island-shaped blocks 303A arranged side by side in a second direction V2 perpendicular to the first direction V1, with the insulating layer 53 interposed therebetween. Each block 303A is provided with, for example, multiple sets of reset transistors RST, amplification transistors AMP, and selection transistors SEL. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, an amplification transistor AMP in the block 303A adjacent to the left of the insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 303A adjacent to the right of the insulating layer 53.

[0053] 14, 15, 16, and 17 show examples of wiring layouts in the horizontal plane of the image sensor 1. Figures 14 to 17 illustrate a case in which one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12. The wirings shown in Figures 14 to 17 are provided in different layers of the wiring layer 246, for example.

[0054] Four adjacent contacts Ct are electrically connected to a wiring D1, for example, as shown in Fig. 14. Four adjacent contacts Ct are further electrically connected to the gate of the amplification transistor AMP included in the block 303A on the left of the insulating layer 53 and the gate of the reset transistor RST included in the block 303A on the right of the insulating layer 53, via the wiring D1 and the contacts Ct2, for example, as shown in Fig. 14.

[0055] For example, as shown in FIG. 15, the power supply line VDD is disposed at a position facing the readout circuits 22 arranged side by side in the second direction V2. For example, as shown in FIG. 15, the power supply line VDD is electrically connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction V2 via a contact Ct2. For example, as shown in FIG. 15, two pixel drive lines 23 are disposed at a position facing the readout circuits 22 arranged side by side in the second direction V2. For example, as shown in FIG. 15, one pixel drive line 23 is a wiring RSTG electrically connected to the gate of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction V2. For example, as shown in FIG. 15, the other pixel drive line 23 is a wiring SELG electrically connected to the gate of the selection transistor SEL of each readout circuit 22 arranged side by side in the second direction V2. In each read circuit 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25, for example, as shown in FIG.

[0056] Two power supply lines VSS are arranged at positions facing the readout circuits 22 arranged side by side in the second direction V2, as shown in FIG. 16, for example. Each power supply line VSS is electrically connected to a plurality of through-wires 47 at a position facing the sensor pixels 12 arranged side by side in the second direction V2, as shown in FIG. 16, for example. Four pixel drive lines 23 are arranged at positions facing the readout circuits 22 arranged side by side in the second direction V2, as shown in FIG. 16, for example. Each of the four pixel drive lines 23 is a line TRG electrically connected to the through-wire 48 of one of the four sensor pixels 12 corresponding to each readout circuit 22 arranged side by side in the second direction V2, as shown in FIG. 16, for example. In other words, the four pixel drive lines 23 (first control lines) are electrically connected to the gate electrodes 223 of the transfer transistors TR of the sensor pixels 12 arranged side by side in the second direction V2. In FIG. 16, in order to distinguish each wiring TRG, an identifier (1, 2, 3, 4) is added to the end of each wiring TRG.

[0057] The vertical signal line 24 is disposed at a position facing each readout circuit 22 arranged side by side in the first direction V1, as shown in Fig. 17. The vertical signal line 24 (output line) is electrically connected to the output terminal (the source of the amplification transistor AMP) of each readout circuit 22 arranged side by side in the first direction V1, as shown in Fig. 17.

[0058] Next, a method for manufacturing the image sensor 1 of this embodiment will be described. First, a semiconductor region and a pixel separator 203 are formed in the first substrate 10, which is a silicon substrate, and a photodiode PD and a transfer transistor TR are formed for each pixel. As shown in FIG. 18, an N-type drain region 221 and an N-type source region 222 are formed near the surface of a P-type semiconductor region (P well) 204 partitioned by the pixel separator 203. A gate electrode 223 is then formed between them. More specifically, an opening connecting to the underlying photodiode PD (not shown in FIG. 18) is provided between the N-type drain region 221 and the N-type source region 222 in the P-type semiconductor region 204. The gate electrode 223 is then formed to fill the opening. In this example, the gate electrode 223 is connected to the photodiode PD formed below the semiconductor region 204 (see FIG. 7). Note that the region 205 shown in FIG. 7 represents the region for one pixel partitioned by the pixel separator 203.

[0059] Furthermore, an electrode 230 for connecting the photodiode PD to a reference potential line that supplies a reference potential (for example, ground) is formed on the P-type semiconductor region 204. This electrode 230 is formed for each pixel and connected to the photodiode PD (not shown).

[0060] In this example, the transfer transistor TR is an N-channel MOS transistor, and its drain region 221 is an N-type semiconductor region. Therefore, the drain region 221 of the transfer transistor TR is connected to a P-type semiconductor region 202 covering the side surface of the photodiode PD. As can be seen from the circuit diagram of FIG. 2, of the two terminals of the photodiode PD, the terminal not connected to the transfer transistor TR (the input side terminal) is connected to the reference potential line. Therefore, in this example, the photodiode PD is connected to the reference potential line via the electrode 230. Therefore, the electrode 230 connected to the photodiode PD formed in the N-type semiconductor region is formed of P-type polysilicon.

[0061] In this manner, after the N-type drain region 221, the N-type source region 222, the gate electrode 223, and the electrode 230 are formed for each pixel in the P-type semiconductor region 204, they are covered with an insulating layer 240. The insulating layer 240 is made of an oxide film such as SiO2.

[0062] 19, the insulating layer 240 is etched to form a wiring groove 241 for forming a wiring 301a that aggregates the source regions 222 of the multiple transfer transistors TR, and a wiring groove 242 for forming a wiring 301b that aggregates the multiple electrodes 230. Hereinafter, when there is no need to distinguish between the wiring 301a and the wiring 301b, they may be simply referred to as "wiring 301."

[0063] As described above, in this example, the source region 222 of the transfer transistor TR is an N-type semiconductor region, and therefore the wiring 301a connected thereto is formed of P-type polysilicon. On the other hand, the electrode 230 is P-type polysilicon, and therefore the wiring 301b connected thereto is formed of N-type polysilicon.

[0064] That is, when the transfer transistor TR is an N-type transistor, the wiring 301a that aggregates the output terminal sides of the multiple transfer transistors TR is made of P-type polysilicon. Also, as described above, in this case, the electrode 230 connected to the photodiode PD formed in an N-type semiconductor region is made of P-type polysilicon. Therefore, the wiring 301b that aggregates the multiple electrodes 230 is made of N-type polysilicon.

[0065] Next, a film of P-type polysilicon, which will be the material for the wiring 301a, is formed so as to fill the wiring trench 241 formed in Fig. 19, and a film of N-type polysilicon, which will be the material for the wiring 301b, is formed so as to fill the wiring trench 242. Then, the resulting structure is polished by, for example, CMP (Chemical Mechanical Polishing), to form the wiring 301a and the wiring 301b (see Fig. 20).

[0066] In this example, the wiring 301a is connected to the source regions 222 of the four transfer transistors TR that correspond one-to-one to the four photodiodes PD for every four photodiodes PD (for every set of four photodiodes PD). In other words, the wiring 301a aggregates the source regions 222 of the four transfer transistors TR that correspond one-to-one to the four photodiodes PD for every four photodiodes PD. The wiring 301a is then connected to the wiring D1 by one contact Ct in order to connect the aggregated source regions 222 to the wiring D1 on the second substrate 20 that is connected to the gate electrode 311 of the amplifier transistor AMP that is shared by the aggregated source regions 222. In this example, one contact Ct is formed for every four source regions 222. In this example, the source region 222 of the transfer transistor TR corresponds to the "first element," the gate electrode 311 of the amplification transistor AMP corresponds to the "second element," the wiring D1 corresponds to the "first wiring" or the "second wiring formed on the second substrate," and the wiring 301a corresponds to the "second wiring" or the "first wiring formed on the first substrate and connected to the first photoelectric conversion element and the second photoelectric conversion element." Note that the number of pixels in the aggregation unit by the wiring 301a is not limited to four and can be changed arbitrarily.

[0067] In this example, the wiring 301b is connected to four electrodes 230, one for each of the four photodiodes PD, in a one-to-one correspondence with the four photodiodes PD. In other words, the wiring 301b aggregates the four electrodes 230, one for each of the four photodiodes PD. The wiring 301b is then connected to the wiring D1 via one contact Ct in order to connect the aggregated electrodes 230 to the wiring D1 on the second substrate 20, which is connected to the reference potential line shared by the electrodes 230. In this example, one contact Ct is formed for each of the four electrodes 230. The wiring D1 connected to the reference potential line is a different wiring from the wiring D1 connected to the gate electrode 311 of the amplification transistor AMP described above (however, both are wirings formed on the insulating layer 245 of the second substrate 20). In this example, the electrode 230 corresponds to the "first element," the reference potential line corresponds to the "second element," the wiring D1 corresponds to the "first wiring," and the wiring 301b corresponds to the "second wiring." The number of pixels in the aggregation unit formed by the wiring 301b is not limited to four and can be changed arbitrarily. As described above, the wiring 301b is connected (indirectly connected) to the corresponding photodiode PD via each electrode 230. In other words, the wiring 301b can also be considered to correspond to the "first wiring formed on the first substrate and connected to the first photoelectric conversion element and the second photoelectric conversion element." The wiring D1 can also be considered to correspond to the "second wiring formed on the second substrate."

[0068] In this example, it is assumed that the reference potential line is formed on the second substrate 20, but this is not limitative and the reference potential line may be formed on another substrate (such as the third substrate 30). In other words, the "second element" is not limited to an element formed on the second substrate 20.

[0069] Next, as shown in FIG. 21, an insulating layer 240 is formed on the wiring 301a and the wiring 301b, and then a P-type semiconductor substrate 303 is attached thereon and thinned.

[0070] Next, as shown in Fig. 22, a portion of the semiconductor substrate 303 facing the wiring 301 is opened, and a pixel transistor is formed on the semiconductor substrate 303. Note that, although the example in Fig. 12 illustrates the amplifier transistor AMP and the select transistor SEL, a reset transistor RST (not shown) is also formed on the semiconductor substrate 303. As shown in Fig. 12, an N-type drain region 312 and an N-type source region 313 are formed near the surface of the semiconductor substrate 303. Then, a gate electrode 311 is formed between them to form the amplifier transistor AMP.

[0071] As described above, an N-type drain region 321 and an N-type source region 322 are formed near the surface of the semiconductor substrate 303, and a gate electrode 323 is formed between them to form a select transistor SEL. A reset transistor RST (not shown) is also formed in the same manner. Then, an insulating layer 245 is formed (deposited) so as to cover the openings and pixel transistors (amplification transistor AMP, select transistor SEL, etc.) formed as described above.

[0072] 23, contacts Ct and Ct2 are formed to connect the wiring 301 and each element of the second substrate 20 to the wiring D1. In this example, contacts Ct are formed for each of the drain region 312 of the amplifier transistor AMP, the wiring 301, and the source region 322 of the select transistor SEL, and a contact Ct2 is formed for the gate electrode 311 of the amplifier transistor AMP.

[0073] One possible method for forming the contacts Ct and Ct2 is to etch an insulating layer to form openings for forming the contacts Ct and Ct2, form a barrier layer on the inner surface of the opening to provide electrical insulation, and then fill the opening with the material for the contacts Ct and Ct2. In this example, the insulating layer provided in the opening of the semiconductor substrate 303 (the insulating layer covering the side surface of the contact Ct) becomes the insulating layer 53 described above. An example of a material for the contacts Ct and Ct2 is tungsten. The barrier layer is made of, for example, Ti, TiN, Ta, or TaN. However, the method and material for forming the contacts Ct and Ct2 are not limited to these and are arbitrary, and various known techniques can be used.

[0074] 24, the wiring D1 to which the contacts Ct and Ct2 are connected is formed on the insulating layer 245. In this example, the wiring D1 is made of copper (Cu). Note that the method and material for forming the wiring D1 are arbitrary, and various known techniques can be used.

[0075] 25, the above-mentioned wiring layer 246 is formed on the insulating layer 245. Thereafter, the third substrate 30 on which the peripheral circuit is formed is bonded, and a color filter and an on-chip lens are formed for each pixel, thereby obtaining the configuration shown in FIG.

[0076] Next, the operation and effect of the image sensor 1 of this embodiment will be described. Here, for example, assume a configuration in which the above-described wiring 301 (wiring 301a or wiring 301b) is not formed. In this configuration, as shown in FIG. 26 , the source region 222 (output terminal side) of each transfer transistor TR is individually connected to wiring D1 connected to the gate electrode 311 of the amplifier transistor AMP via contacts Ct. Focusing on one shared unit, it is necessary to connect four contacts Ct corresponding one-to-one to the source regions 222 of the four transfer transistors TR to the wiring D1 of the second substrate 20 connected to the gate electrode 311 of the amplifier transistor AMP. This increases the number of contacts of the wiring D1, resulting in a larger area. Furthermore, the opening area of ​​the semiconductor substrate 303 through which the contacts Ct pass also becomes larger.

[0077] Furthermore, in the above configuration (the configuration shown in FIG. 26), each electrode 230 is also individually connected to the wiring D1 connected to the reference potential line via a contact Ct. Focusing on one shared unit, it is necessary to connect four contacts Ct in one-to-one correspondence with the four electrodes 230 to the wiring D1 of the second substrate 20 connected to the reference potential line. This increases the number of contacts on the wiring D1, resulting in a larger area. Furthermore, the opening area of ​​the semiconductor substrate 303 through which the contacts Ct pass also becomes larger.

[0078] Therefore, in the above configuration, the capacitance (parasitic capacitance) associated with the wiring D1 formed on the second substrate 20 increases, which may affect the photoelectric conversion efficiency. For example, the photoelectric conversion efficiency may decrease.

[0079] Therefore, in this embodiment, a wiring 301 is provided which is connected to a second element (the gate electrode 311 of the amplification transistor AMP or the reference potential line) shared by a plurality of first elements such as the output terminal side of the transfer transistor TR and the electrode 230, and which is connected to the wiring D1 formed on the second substrate 20 by one contact Ct and to which the plurality of first elements are connected.

[0080] In other words, this wiring 301 aggregates multiple first elements and connects them via a single contact Ct to wiring D1, which is connected to a second element shared by the multiple first elements. This allows only one contact Ct to be formed on wiring D1 to connect the multiple first elements of an aggregate unit to wiring D1, thereby reducing the number of contacts and the area of ​​wiring D1. This therefore reduces the capacitance associated with wiring D1, thereby improving the photoelectric conversion efficiency.

[0081] 27, in the image sensor 1 of this embodiment, a wiring 301a is provided for connecting the source region 222 (output terminal side) of each transfer transistor TR to a wiring D1 formed on the second substrate 20 via one contact Ct. The wiring D1 is a wiring connected to the gate electrode 311 of the amplification transistor AMP shared by the source regions 222 of each transfer transistor TR. In addition, in the image sensor 1 of this embodiment, a wiring 301b is also provided for connecting each electrode 230 to the wiring D1 formed on the second substrate 20 via one contact Ct. The wiring D1 is a wiring connected to a reference potential line to which each electrode 230 is commonly connected.

[0082] FIG. 28 is a schematic plan view of the first substrate 10 of this embodiment. Each of the multiple regions 250 partitioned by the pixel separators 203 corresponds to one pixel. A region 260 shown in FIG. 28 indicates a set of connection points 261 between the source region 222 and the wiring 301a for each of four transfer transistors TR that correspond one-to-one to four photodiodes PD, which form a unit that shares a pixel transistor. A region 270 shown in FIG. 28 indicates a set of connection points 271 between the electrodes 230 and the wiring 301b for each of four electrodes 230 that correspond one-to-one to four photodiodes PD, which form a unit that shares a reference potential line.

[0083] 29 is a schematic plan view of the second substrate 20 of this embodiment. As described above, on the second substrate 20, a pixel transistor shared by the four photodiodes PD is formed for each of four photodiodes PD. An area 280 shown in FIG. 29 indicates an area where the gate electrodes of the pixel transistors of one shared unit circuit are formed. More specifically, the area shown indicates an area where the gate electrode 311 of the amplification transistor AMP, the gate electrode 323 of the selection transistor SEL, and the gate electrode 333 of the reset transistor RST are formed.

[0084] 30 is a schematic plan view of the second substrate 20 and the first substrate 10 superimposed on each other in this embodiment. In the example of FIG. 30, for each group of four photodiodes PD (the number of groups is arbitrary), the wiring 301a is connected to the source regions 222 of four transfer transistors TR that correspond one-to-one to the four photodiodes PD included in the group. The wiring 301a is connected, via one contact Ct, to a wiring D1 (not shown) that is connected to a gate electrode 311 of an amplifier transistor AMP shared by the four source regions 222. In other words, the wiring 301a collects, for each group of four photodiodes PD, the source regions 222 of four transfer transistors TR that correspond one-to-one to the four photodiodes PD. The wiring 301a is connected, via one contact Ct, to a wiring D1 that is connected to a gate electrode of an amplifier transistor AMP shared by the four source regions 222.

[0085] As a result, only one contact needs to be formed on the wiring D1 to connect the source regions 222 of the four transfer transistors TR, which correspond one-to-one to the four photodiodes PD of the aggregation unit, to the wiring D1. This reduces the number of contacts and the area of ​​the wiring D1. Therefore, the capacitance associated with the wiring D1 can be reduced, thereby improving the photoelectric conversion efficiency.

[0086] 30, the wiring 301b is connected to four electrodes 230 that correspond one-to-one to the four photodiodes PD included in each set of four photodiodes PD. The wiring 301b is connected, via one contact Ct, to wiring D1 (not shown) that is connected to a reference potential line shared by the four electrodes 230. In other words, the wiring 301b collects, for each set of four photodiodes PD, the four electrodes 230 that correspond one-to-one to the four photodiodes PD, and is connected, via one contact Ct, to wiring D1 that is connected to a reference potential line shared by these electrodes.

[0087] As a result, only one contact is required to be formed on the wiring D1 to connect the four electrodes 230, which correspond one-to-one to the four photodiodes PD of each aggregation unit, to the wiring D1, thereby reducing the number of contacts and the area of ​​the wiring D1. Therefore, the capacitance associated with the wiring D1 can be reduced, thereby improving the photoelectric conversion efficiency. In the above description, the wiring 301 (wiring 301a or wiring 301b) aggregates multiple first elements and is connected to the wiring D1 connected to the second element shared by the multiple first elements via one contact Ct. However, this is not a limitation, and the number of contacts Ct may be two or more. In short, the wiring 301 may be connected to the wiring D1 via fewer contacts Ct than the number of aggregation units. This configuration allows the number of contacts and the area of ​​the wiring D1 to be reduced.

[0088] In this example, the four pixels that form the unit aggregated by wiring 301a and the four pixels that form the unit aggregated by wiring 301b do not completely coincide with each other, and some of them (two pixels in this example) overlap, but this is not limited to this.

[0089] Furthermore, in this embodiment, the first substrate 10 on which the photodiodes PD are formed and the second substrate 20 on which the pixel transistors are formed are stacked separately, which makes it possible to reduce the area (planar space) of the substrates. More specifically, by separating the first substrate 10 and the second substrate 20, the areas of the photodiodes PD and the pixel transistors can be increased compared to a configuration in which the photodiodes PD and the pixel transistors are provided on the same substrate. This improves photoelectric conversion efficiency and reduces transistor noise.

[0090] Furthermore, by separating the first substrate 10 and the second substrate 20, the number of pixels per unit area can be increased compared to a configuration in which the photodiode PD and the pixel transistor are provided on the same substrate, thereby improving the resolution.

[0091] Furthermore, as described above, in this embodiment, the first substrate 10 and the second substrate 20 are connected within the pixel region 13 using through electrodes (contacts Ct and through wirings 47 and 48), and the second substrate 20 and the third substrate 30 are joined using pad electrodes 58 and 64. This reduces the area required for inter-substrate connection compared to a configuration in which through-connection vias (TSVs (Thorough Si Vias)) are provided in the peripheral region around the pixel region 13 to connect the substrates, thereby reducing the chip size. Alternatively, the pixel region 13 can be expanded even with the same chip area. It would be even more effective if all inter-substrate connections could be completed within the pixel region.

[0092] Furthermore, in this embodiment, the wiring 301 (wiring 301a or wiring 301b) is provided closer to the light incident surface than the second substrate 20 (in this example, in the lower layer of the second substrate 20) (see, for example, FIG. 17). As a result, the opening formed in the region of the semiconductor substrate 303 of the second substrate 20 facing the wiring 301 only needs to be large enough to pass one contact Ct through. Therefore, according to this embodiment, the opening formed in the semiconductor substrate 303 can be made small.

[0093] In the embodiment described above, the output terminal side of the transfer transistor TR and the electrode 230 are given as examples of the "first element," and the gate electrode 311 of the amplification transistor AMP and the reference potential line are given as examples of the "second element," but the present invention is not limited to these. In short, the first element is an element formed for each photodiode PD among the multiple elements formed on the first substrate 10, and the second element is an element formed on the second substrate 20 that is shared by the multiple first elements.

[0094] Furthermore, in this embodiment, the wiring 301a and the wiring 301b are alternately arranged in the vertical direction (see FIG. 30), but the layout of the wiring 301 is not limited to this and can be changed as desired depending on design conditions, etc. For example, as shown in FIG. 31, the wiring 301a and the wiring 301b may be alternately arranged in the horizontal direction. FIG. 32 is a schematic plan view of the first substrate 10 in this case, and FIG. 33 is a schematic plan view of the second substrate 20 in this case. In FIGS. 32 and 33, elements common to the above-described embodiment are denoted by the same reference numerals.

[0095] 3. Second embodiment (Example of imaging element configuration) Next, an example of the configuration of an image sensor according to the second embodiment will be described. Note that the basic configuration of the image sensor according to this embodiment is the same as the image sensor 1 according to the first embodiment described above, so only the differences from the first embodiment will be described. The configuration other than the differences is the same as that of the first embodiment described above.

[0096] In the first embodiment described above, the transfer transistor TR is configured as an N-channel MOS transistor, but in this embodiment, the transfer transistor TR is configured as a P-channel MOS transistor (an example of a P-type transistor). Therefore, the semiconductor region 204 formed on the photodiode PD is an N-type semiconductor region, and the drain region 221 and source region 222 of the transfer transistor TR formed near the surface of the semiconductor region 204 are P-type semiconductor regions. Therefore, the wiring 301a that aggregates the source regions 222 of each transfer transistor TR is formed of N-type polysilicon.

[0097] That is, when the transfer transistors TR are P-type transistors, the wiring 301a for connecting the output terminal sides of the multiple transfer transistors TR to the wiring D1 with one contact is made of N-type polysilicon.

[0098] Furthermore, the N-type drain region 221 of the transfer transistor TR is connected to the P-type semiconductor region covering the side surface of the photodiode PD, and therefore the photodiode PD is connected to the electrode 230. Therefore, in this example, the electrode 230 is formed of N-type polysilicon, and therefore the wiring 301b that aggregates the electrodes 230 is formed of P-type polysilicon.

[0099] That is, in this embodiment, the electrode 230 connected to the photodiode PD is formed of N-type polysilicon, and the wiring 301b for connecting the multiple electrodes 230 to the wiring D1 with one contact is formed of P-type polysilicon.

[0100] The configuration of this embodiment as described above also provides the same effects as those of the first embodiment. That is, only one contact Ct is required to be formed on the wiring D1 in order to connect multiple first elements (multiple first elements in an aggregate unit), such as the output terminal side of the transfer transistor TR and the electrode 230 formed on the first substrate 10, to the wiring D1. Therefore, the number and area of ​​the contacts on the wiring D1 can be reduced, and the capacitance associated with the wiring D1 can be reduced. This allows for improved photoelectric conversion efficiency.

[0101] 4. Third Embodiment (Example of imaging element configuration) Next, an example of the configuration of an image sensor according to the third embodiment will be described. Note that the basic configuration of the image sensor according to this embodiment is the same as the image sensor 1 according to the first embodiment described above, so only the differences from the first embodiment will be described. The configuration other than the differences is the same as that of the first embodiment described above.

[0102] In the first embodiment described above, the wiring (wiring 301a or wiring 301b) is made of polysilicon, but this is not limiting, and for example, the wiring 301 may be formed to contain tungsten (W). This makes it possible to reduce the resistance of the wiring 301 compared to when the wiring 301 is made of polysilicon.

[0103] Furthermore, even with this configuration, the same effects as those of the first embodiment described above can be obtained. That is, only one contact Ct is required to be formed on the wiring D1 in order to connect multiple first elements (multiple first elements in an aggregate unit), such as the output terminal side of the transfer transistor TR and the electrode 230 formed on the first substrate 10, to the wiring D1. Therefore, the number and area of ​​the contacts on the wiring D1 can be reduced, and the capacitance associated with the wiring D1 can be reduced. This allows the photoelectric conversion efficiency to be improved.

[0104] 5. Fourth Embodiment (Example of imaging element configuration) Next, an example of the configuration of an image sensor according to the fourth embodiment will be described. Note that the basic configuration of the image sensor according to this embodiment is the same as the image sensor 1 according to the first embodiment described above, so only the differences from the first embodiment will be described. The configuration other than the differences is the same as that of the first embodiment described above.

[0105] 34, in this embodiment, the wiring 301a and the wiring 301b are arranged in openings formed in the second substrate 20 (semiconductor substrate 303). Here, the "openings formed in the second substrate 20" corresponds to the inside of a region (insulating region) of the insulating film 230 formed between a first semiconductor region of the second substrate 20 (for example, a region where the amplification transistor AMP is formed) and a second semiconductor region of the second substrate 20 (for example, a region where the select transistor SEL is formed). This has the advantageous effect of reducing the height in the stacking direction.

[0106] Furthermore, even with this configuration, the same effects as those of the first embodiment described above can be obtained. That is, only one contact Ct is required to be formed on the wiring D1 in order to connect multiple first elements (multiple first elements in an aggregate unit), such as the output terminal side of the transfer transistor TR and the electrode 230 formed on the first substrate 10, to the wiring D1. Therefore, the number and area of ​​the contacts on the wiring D1 can be reduced, and the capacitance associated with the wiring D1 can be reduced. This allows the photoelectric conversion efficiency to be improved.

[0107] This embodiment can also be applied to the second embodiment described above. For example, the wiring 301a may be arranged in an opening formed in the second substrate 20, the transfer transistor TR may be a P-type transistor, and the wiring 301a may be made of N-type polysilicon. Also, for example, the wiring 301b may be arranged in an opening formed in the second substrate 20, the electrode 230 connected to the photodiode PD may be made of N-type polysilicon, and the wiring 301b may be made of P-type polysilicon.

[0108] This embodiment can also be applied to the above-described third embodiment. For example, the wiring 301 (the wiring 301a or the wiring 301b) may be disposed in an opening formed in the second substrate 20, and the wiring 301 may be formed to contain tungsten (W).

[0109] 6. Fifth Embodiment (Example of imaging element configuration) Next, an example of the configuration of an image sensor according to the fifth embodiment will be described. Note that the basic configuration of the image sensor according to this embodiment is the same as the image sensor 1 according to the first embodiment described above, so only the differences from the first embodiment will be described. The configuration other than the differences is the same as that of the first embodiment described above.

[0110] In this embodiment, the wiring 301 (the wiring 301a or the wiring 301b) is arranged between the second element (the gate electrode 311 of the amplifier transistor AMP or the reference potential line) and the wiring D1. For example, as shown in FIG. 35, the wiring 301a is arranged between the gate electrode 311 of the amplifier transistor AMP formed on the second substrate 20 and the wiring D1.

[0111] Even with this configuration, the same effects as those of the first embodiment described above can be obtained. That is, only one contact Ct is required to be formed on the wiring D1 in order to connect multiple first elements (multiple first elements in an aggregate unit), such as the output terminal side of the transfer transistor TR and the electrode 230 formed on the first substrate 10, to the wiring D1. Therefore, the number and area of ​​the contacts on the wiring D1 can be reduced, and the capacitance associated with the wiring D1 can be reduced. This can improve the photoelectric conversion efficiency.

[0112] This embodiment can also be applied to the second embodiment. For example, the wiring 301a may be arranged in an opening formed in the second substrate 20, and may be arranged between the gate electrode 311 of the amplifier transistor AMP and the wiring D1, the transfer transistor TR may be a P-type transistor, and the wiring 301a may be made of N-type polysilicon. Also, for example, the wiring 301b may be arranged between the reference potential line and the wiring D1, the electrode 230 connected to the photodiode PD may be made of N-type polysilicon, and the wiring 301b may be made of P-type polysilicon.

[0113] This embodiment can also be applied to the third embodiment. For example, the wiring 301a may be disposed between the gate electrode 311 of the amplifier transistor AMP and the wiring D1, and the wiring 301a may be formed to contain tungsten (W). Also, for example, the wiring 301b may be disposed between the reference potential line and the wiring D1, and the wiring 301b may be formed to contain tungsten (W).

[0114] 7. Sixth Embodiment (Example of imaging element configuration) Next, an example of the configuration of an image sensor according to the sixth embodiment will be described. Note that the basic configuration of the image sensor according to this embodiment is the same as the image sensor 1 according to the first embodiment described above, so only the differences from the first embodiment will be described. The configuration other than the differences is the same as that of the first embodiment described above.

[0115] In this embodiment, only the wiring 301a is provided as shown in Fig. 36. Here, the above-mentioned wiring 301b is not provided, and each electrode 230 is connected to the wiring D1 via an individual contact.

[0116] Even with this configuration, only one contact Ct is required to be formed on the wiring D1 (the wiring D1 connected to the gate electrode 311 of the amplifier transistor AMP) in order to commonly connect the output terminal sides of the multiple transfer transistors TR formed on the first substrate 10 to the wiring D1. Therefore, the number and area of ​​the contacts on the wiring D1 connected to the gate electrode 311 of the amplifier transistor AMP can be reduced.

[0117] 37, for example, a configuration in which only the wiring 301b is provided is also possible. In this case, the above-mentioned wiring 301a is not provided, and the output terminal side (the source region 222 in this example) of each transfer transistor TR is connected to the wiring D1 via an individual contact.

[0118] Even with this configuration, only one contact Ct is required to be formed on the wiring D1 (the wiring D1 connected to the reference potential line) to commonly connect the multiple electrodes 230 formed on the first substrate 10 to the wiring D1. Therefore, the number and area of ​​the contacts on the wiring D1 connected to the reference potential line can be reduced.

[0119] In short, it is possible to have a configuration in which the above-mentioned wiring 301a is provided but the above-mentioned wiring 301b is not provided, or conversely, it is possible to have a configuration in which the above-mentioned wiring 301b is provided but the above-mentioned wiring 301a is not provided.

[0120] This embodiment can also be applied to the second embodiment, in which the transfer transistor TR is a P-type transistor and the wiring 301a is made of N-type polysilicon. Also, the electrode 230 connected to the photodiode PD may be made of N-type polysilicon and the wiring 301b may be made of P-type polysilicon.

[0121] This embodiment can also be applied to the third embodiment described above, and the wiring 301 (the wiring 301a or the wiring 301b) may be formed to contain tungsten (W).

[0122] This embodiment can also be applied to the fourth embodiment. For example, in a configuration in which the above-described wiring 301a is provided but the above-described wiring 301b is not provided, the wiring 301a may be disposed in an opening formed in the second substrate 20. In addition, in a configuration in which the above-described wiring 301b is provided but the above-described wiring 301a is not provided, the wiring 301b may be disposed in an opening formed in the second substrate 20.

[0123] Furthermore, this embodiment can also be applied to the fifth embodiment. For example, a configuration may be adopted in which the above-described wiring 301a is provided but the above-described wiring 301b is not provided, and the wiring 301a is disposed between the gate electrode 311 of the amplification transistor AMP and the wiring D1. Also, for example, a configuration may be adopted in which the above-described wiring 301b is provided but the above-described wiring 301a is not provided, and the wiring 301b is disposed between the reference potential line and the wiring D1.

[0124] In short, this embodiment can be applied to each of the second to fifth embodiments described above.

[0125] 8. Seventh Embodiment (Example of electronic device configuration) The imaging elements described in the above embodiments can be applied to various portable terminal devices such as digital still cameras, digital video cameras, and camera-equipped mobile phones, as well as electronic devices such as printers. Fig. 38 is a diagram showing an example of the configuration of a camera 1000, which is an example of an electronic device to which the imaging element of the present disclosure is applied. This camera 1000 is exemplified as a video camera capable of capturing still images or videos.

[0126] As shown in FIG. 38, the camera 1000 includes at least a lens group 1011, an image sensor 1012, and a DSP circuit 1013.

[0127] The lens group 1011 takes in incident light (image light) from a subject and guides it to the image sensor 1012. In this example, the lens group 1011 corresponds to an example of an "optical system" for guiding incident light to the image sensor.

[0128] The image sensor 1012 converts incident light into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1013. The image sensor 1012 may be any of the image sensors according to the above-described embodiments.

[0129] The DSP circuit 1013 performs predetermined image processing on the pixel signals supplied from the image sensor 1012, and outputs a set of pixel signals per pixel after the processing (a set of pixel signals for one frame) as a video signal. In this example, the DSP circuit 1013 corresponds to an example of a "processing unit" that processes the signals output from the image sensor.

[0130] The video signal output from the DSP circuit 1013 is temporarily stored in a frame memory or the like, and then recorded on a recording medium such as a DVD (Digital Versatile Disk) or flash memory, or displayed on a display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel.

[0131] <9. Variations> Modifications of the imaging device 1 will be described below.

[0132] [Variation A] In each of the above embodiments, the number of pixels in the sharing unit is four, but this is not limited thereto and the number of pixels in the sharing unit can be changed arbitrarily. For example, as shown in FIGS. 39 and 40 , the number of pixels in the sharing unit may be two. That is, the second substrate 20 may have a readout circuit 22 for every two sensor pixels 12. FIG. 39 shows a modified example of the sensor pixels 12 and readout circuits 22 shown in FIG. 2. FIG. 40 shows a modified example of the sensor pixels 12 and readout circuits 22 shown in FIG. 3.

[0133] 41 and 42, the number of pixels in a sharing unit may be one. That is, the second substrate 20 may have a readout circuit 22 for every two sensor pixels 12. FIG. 41 shows a modified example of the sensor pixels 12 and readout circuits 22 shown in FIG. 2. FIG. 42 shows a modified example of the sensor pixels 12 and readout circuits 22 shown in FIG. 3.

[0134] [Variation B] FIG. 43 shows a modified example of the vertical cross-sectional configuration of the image sensor 1. In this modified example, the second substrate 20 and the third substrate 30 are electrically connected in a region of the first substrate 10 facing the peripheral region 14. The peripheral region 14 corresponds to the frame region of the first substrate 10 and is provided on the periphery of the pixel region 13. In this modified example, the second substrate 20 has a plurality of pad electrodes 58 in a region facing the peripheral region 14, and the third substrate 30 has a plurality of pad electrodes 64 in a region facing the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14.

[0135] As described above, in this modification, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14. This reduces the risk of hindering miniaturization of the area per pixel compared to when the pad electrodes 58, 64 are bonded to each other in the region facing the pixel region 13. Therefore, it is possible to provide an image sensor 1 with a three-layer structure that does not hinder miniaturization of the area per pixel, while maintaining the same chip size as before.

[0136] [Variation C] 44 and 45 show a modified horizontal cross-sectional configuration of the image sensor 1. The upper views of FIGS. 44 and 45 show a modified cross-sectional configuration at cross-section Sec1 of FIG. 7, and the lower views of FIG. 23 show a modified cross-sectional configuration at cross-section Sec2 of FIG. 7. In the upper cross-sectional views of FIGS. 44 and 45, a modified surface configuration of semiconductor substrate 11 of FIG. 7 is superimposed on a view showing a modified cross-sectional configuration at cross-section Sec1 of FIG. 7, and insulating layer 240 is omitted. In the lower cross-sectional views of FIGS. 44 and 45, a modified surface configuration of semiconductor substrate 303 is superimposed on a view showing a modified cross-sectional configuration at cross-section Sec2 of FIG. 7.

[0137] As shown in FIGS. 44 and 45, the contacts Ct, the through wires 47, and the through wires 48 (the dots arranged in a matrix in the figures) are arranged in a strip shape in the first direction V1 (the left-right direction in FIGS. 44 and 45) within the plane of the first substrate 10. Note that FIGS. 44 and 45 illustrate an example in which the contacts Ct, the through wires 47, and the through wires 48 are arranged in two rows in the first direction V1. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusions FD, and for example, the four transfer gates TG form a ring shape.

[0138] The insulating layer 53 is composed of a plurality of blocks extending in a first direction V1. The semiconductor substrate 303 is composed of a plurality of island-shaped blocks 303A extending in the first direction V1 and arranged side by side in a second direction V2 perpendicular to the first direction V1, with the insulating layer 53 interposed therebetween. Each block 303A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is, for example, not arranged directly opposite the four sensor pixels 12 but arranged offset in the second direction V2.

[0139] 44, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area on the second substrate 20 that is shifted in the second direction V2 from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL in one block 303A.

[0140] 45, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG located in an area on the second substrate 20 that is shifted in the second direction V2 from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD transfer transistor FDG in one block 303A.

[0141] In this modification, the single readout circuit 22 shared by the four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed offset in the second direction V2 from a position directly opposite the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured using a common impurity region. As a result, the size of the readout circuit 22 can be reduced or other portions within the readout circuit 22 can be increased in size.

[0142] [Variation D] 46 shows a modified example of the horizontal cross-sectional configuration of the imaging device 1. In FIG. 46, a modified example of the cross-sectional configuration of FIG.

[0143] In this modification, the semiconductor substrate 303 is composed of a plurality of island-shaped blocks 303A arranged side by side in the first direction V1 and the second direction V2 with an insulating layer 53 interposed therebetween. Each block 303A is provided with, for example, a set of reset transistor RST, amplifying transistor AMP, and selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and degradation of image quality due to reduced resolution and color mixing on a reproduced image can be suppressed.

[0144] [Variation E] 47 shows a modified example of the horizontal cross-sectional configuration of the imaging device 1. In FIG. 47, a modified example of the cross-sectional configuration of FIG.

[0145] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12 but is disposed offset in the first direction V1. In this modification, similar to modification D, the semiconductor substrate 303 is further configured with a plurality of island-shaped blocks 303A arranged side by side in the first direction V1 and the second direction V2 with an insulating layer 53 interposed therebetween. Each block 303A includes, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this modification, a plurality of through wires 47 and a plurality of contacts Ct are also arranged in the second direction V2. Specifically, the plurality of through wires 47 are disposed between four contacts Ct sharing a certain readout circuit 22 and four through wire contacts Ct sharing another readout circuit 22 adjacent to the readout circuit 22 in the second direction V2. In this configuration, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through wires 47, thereby suppressing image quality degradation due to reduced resolution and color mixing in a reproduced image.

[0146] [Variation F] 48 shows an example of a horizontal cross-sectional configuration of the imaging device 1. In FIG. 48, a modification of the cross-sectional configuration in FIG.

[0147] In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Therefore, in this modification, one contact Ct is provided for every four sensor pixels 12.

[0148] Among the plurality of sensor pixels 12 arranged in a matrix, four sensor pixels 12 that share one floating diffusion FD are shifted in the first direction V1 by the amount of one sensor pixel 12, and the four sensor pixels 12 that correspond to the area are referred to as four sensor pixels 12A for convenience. In this modification, the first substrate 10 shares a through wiring 47 with each of the four sensor pixels 12A. Therefore, in this modification, one through wiring 47 is provided for each of the four sensor pixels 12A.

[0149] In this modification, the first substrate 10 has a pixel isolation portion 203 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation portion 43 does not completely surround the sensor pixel 12, and has gaps (unformed regions) near the floating diffusion FD (through wiring 54) and near the through wiring 47. These gaps enable four sensor pixels 12 to share one through wiring 54, or four sensor pixels 12A to share one through wiring 47. In this modification, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0150] Fig. 49 shows an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Fig. 49 shows a modification of the cross-sectional configuration of Fig. 46. In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has a pixel separating portion 203 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0151] Fig. 50 shows an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Fig. 50 shows a modification of the cross-sectional configuration of Fig. 47. In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has a pixel separating portion 203 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0152] [Variation G] 51 shows an example of a circuit configuration of the image sensor 1 according to a modified example. The image sensor 1 according to this modified example is a CMOS image sensor equipped with a column-parallel ADC.

[0153] As shown in Figure 51, the imaging element 1 of this modified example is configured to have a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion element, are arranged two-dimensionally in a matrix, as well as a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36.

[0154] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0155] The vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0156] Although not shown here, the sensor pixel 12 may have, for example, a configuration including a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Also, although not shown here, the readout circuit 22 may have, for example, a three-transistor configuration including a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0157] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and pixel drive lines 23 are wired for each row of this m-row by n-column pixel arrangement, and vertical signal lines 24 are wired for each column. One end of each of the pixel drive lines 23 is connected to an output terminal of a vertical drive circuit 33 corresponding to each row. The vertical drive circuit 33 is configured with a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the pixel drive lines 23.

[0158] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24, and converts the analog signals output from each sensor pixel 12 in the pixel region 13 for each column into digital signals and outputs them.

[0159] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as means for generating a reference voltage Vref having a so-called ramp waveform, the level of which changes in a sloping manner as time passes. However, the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0160] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK given from the system control circuit 36 ​​under the control of a control signal CS1 given from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column processing unit 15.

[0161] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to an operation mode between a normal frame rate mode using a progressive scan method in which information from all of the sensor pixels 12 is read out, and a high-speed frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased by N times, for example, twice, compared to the normal frame rate mode. This operation mode switching is performed under control of control signals CS2 and CS3 provided by the system control circuit 36. An external system controller (not shown) also provides the system control circuit 36 ​​with instruction information for switching between the normal frame rate mode and the high-speed frame rate mode.

[0162] The ADCs 34-1 to 34-m all have the same configuration, and the following description will be given taking the ADC 34-m as an example. The ADC 34-m includes a comparator 34A, a counting means such as an up / down counter (denoted as U / DCNT in the drawing) 34B, a transfer switch 34C, and a memory device 34D.

[0163] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with the reference voltage Vref of a ramp waveform supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes "H" level, and when the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco becomes "L" level.

[0164] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 given from the system control circuit 36, a clock CK is given from the system control circuit 36 ​​simultaneously with the DAC 18A, and by counting down (DOWN) or up (UP) in synchronization with the clock CK, the up / down counter 34B measures the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation.

[0165] Specifically, in the normal frame rate mode, when reading out a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0166] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, the comparison time for the first readout is measured by counting down from the previous count result during the first readout operation, and the comparison time for the second readout is measured by counting up during the second readout operation.

[0167] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 36, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0168] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the count results of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0169] In this way, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line 24 are converted into N-bit digital signals by the operations of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m and stored in the memory device 34D.

[0170] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of this horizontal drive circuit 35, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are read out in order to a horizontal output line 37 and output via the horizontal output line 37 as imaging data.

[0171] Although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits other than the above components that perform various signal processing on the imaging data output via the horizontal output line 37.

[0172] In the image sensor 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37 can be controlled independently.

[0173] [Variation H] FIG. 52 shows an example of the image sensor 1 of FIG. 51 configured by stacking three substrates (first substrate 10, second substrate 20, and third substrate 30). In this modification, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. A readout circuit region 15 including a plurality of readout circuits 22 is formed in the center of the second substrate 20, and the vertical drive circuit 33 is formed around the readout circuit region 15. A column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed on the third substrate 30. As a result, as with the above embodiment and its modifications, the structure electrically connecting the substrates does not increase the chip size or hinder miniaturization of the area per pixel. As a result, it is possible to provide an image sensor 1 with a three-layer structure that does not hinder miniaturization of the area per pixel while maintaining the same chip size as before. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0174] [Variation I] FIG. 53 shows a modified cross-sectional configuration of the image sensor 1 according to this modification. In the first embodiment and its modifications, the image sensor 1 is configured by stacking three substrates (first substrate 10, second substrate 20, and third substrate 30). However, in the first embodiment and its modifications, the image sensor 1 may be configured by stacking two substrates (first substrate 10 and second substrate 20). In this case, the logic circuit 32 is formed separately on the first substrate 10 and the second substrate 20, as shown in FIG. 53, for example. Here, the circuit 32A of the logic circuit 32 provided on the first substrate 10 side includes a transistor having a gate structure in which a high-dielectric-constant film made of a material (e.g., high-k) that can withstand high-temperature processes and a metal gate electrode are stacked. On the other hand, in the circuit 32B provided on the second substrate 20 side, a low-resistance region 26 made of silicide, such as CoSi2 or NiSi, is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode using a salicide (self-aligned silicide) process. The low-resistance region made of silicide is formed from a compound of the semiconductor substrate material and a metal. This allows a high-temperature process, such as thermal oxidation, to be used when forming the sensor pixel 12. Furthermore, in the circuit 32B provided on the second substrate 20 side of the logic circuit 32, if the low-resistance region 26 made of silicide is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be increased.

[0175] FIG. 54 shows a modified cross-sectional configuration of the image sensor 1 according to the first embodiment and its modifications. In the logic circuit 32 of the third substrate 30 according to the first embodiment and its modifications, low-resistance regions 37 made of silicide, such as CoSi2 or NiSi, may be formed on the surface of the impurity diffusion region in contact with the source and drain electrodes using a salicide (self-aligned silicide) process. This allows a high-temperature process, such as thermal oxidation, to be used when forming the sensor pixels 12. Furthermore, if the low-resistance regions 37 made of silicide are formed on the surface of the impurity diffusion region in contact with the source and drain electrodes in the logic circuit 32, contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be increased.

[0176] <10. Application Examples> FIG. 55 shows an example of a schematic configuration of an imaging system 2 including the imaging element 1 described above.

[0177] The imaging system 2 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 2 includes, for example, the imaging element 1, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the imaging element 1, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus line 147.

[0178] The imaging element 1 outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes the signal (image data) output from the imaging element 1. The frame memory 142 temporarily stores the image data processed by the DSP circuit 141 on a frame-by-frame basis. The display unit 143 is a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the imaging element 1. The storage unit 144 records image data of moving or still images captured by the imaging element 1 in a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation commands for various functions of the imaging system 2 in accordance with user operations. The power supply unit 146 appropriately supplies various power sources to the imaging element 1, DSP circuit 141, frame memory 142, display unit 143, storage unit 144, and operation unit 145 as operating power sources.

[0179] Next, the imaging procedure in the imaging system 2 will be described.

[0180] 56 shows an example of a flowchart of the imaging operation in the imaging system 2. The user operates the operation unit 145 to instruct the start of imaging (step S101). Then, the operation unit 145 transmits an imaging command to the imaging element 1 (step S102). Upon receiving the imaging command, the imaging element 1 (specifically, the system control circuit 36) executes imaging in a predetermined imaging method (step S103).

[0181] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 141. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 141 stores the image data that has undergone the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage unit 144 (step S105). In this manner, imaging is performed in the imaging system 2.

[0182] In this application example, the imaging element 1 is applied to an imaging system 2. This allows the imaging element 1 to be made smaller or have higher definition, and therefore a small or high-definition imaging system 2 can be provided.

[0183] <11. Application Examples> [Application example 1] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0184] FIG. 57 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0185] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 57, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0186] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0187] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0188] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0189] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0190] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0191] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0192] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0193] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0194] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 57, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0195] FIG. 58 is a diagram showing an example of the installation position of the imaging unit 12031.

[0196] In FIG. 58, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0197] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0198] 58 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0199] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0200] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0201] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0202] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0203] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging element 1 according to the above-described embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a high-resolution captured image with little noise, thereby enabling high-precision control using the captured image in the mobile object control system.

[0204] [Application example 2] FIG. 59 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0205] Figure 59 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0206] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0207] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0208] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0209] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0210] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0211] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0212] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0213] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0214] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0215] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0216] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0217] FIG. 60 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0218] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0219] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0220] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0221] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0222] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0223] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0224] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0225] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0226] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0227] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0228] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0229] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0230] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0231] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0232] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0233] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0234] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0235] Although the present disclosure has been described above by way of embodiments, modifications thereof, application examples, and applied examples, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0236] Furthermore, the effects of each embodiment described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0237] The present disclosure can also be configured as follows. (1) a first substrate on which a plurality of photoelectric conversion elements are formed; a second substrate on which pixel transistors shared by each group of two or more photoelectric conversion elements are formed; and a second wiring for connecting a plurality of first elements, each formed for each of the photoelectric conversion elements, among the plurality of elements formed on the first substrate, to a second element shared by the plurality of first elements, the second wiring being for connecting the plurality of first elements to the first wiring formed on the second substrate with one contact. Image sensor. (2) The second wiring is For each set of two or more photoelectric conversion elements, a plurality of the first elements are connected in one-to-one correspondence with two or more of the photoelectric conversion elements included in the set, and are connected by one contact to the first wiring connected to the second element shared by the plurality of the first elements; The imaging element according to (1). (3) the second wiring is disposed closer to the light incident surface than the second substrate; An imaging element according to (1) or (2). (4) a transfer transistor is formed on the first substrate for each of the photoelectric conversion elements to transfer an electrical signal output from the photoelectric conversion element to the pixel transistor; the pixel transistors are formed on the second substrate, each of which includes, for one or more groups, at least one amplification transistor that amplifies and outputs an electrical signal transferred from each of the two or more transfer transistors included in the group; the first element includes an output terminal side of the transfer transistor; the second element includes a gate of the amplifying transistor; The imaging device according to any one of (1) to (3). (5) an output terminal side of the transfer transistor is a floating diffusion that temporarily holds an electrical signal output from the photoelectric conversion element; The imaging element according to (4). (6) the transfer transistor is an N-type transistor, the second wiring is formed of P-type polysilicon; The imaging element according to (4) or (5). (7) the first element includes an electrode connected to the photoelectric conversion element; the second element includes a reference potential line to which a reference potential is supplied; the electrode is formed of P-type polysilicon, the second wiring for connecting the plurality of electrodes to the first wiring connected to the reference potential line with one contact is formed of N-type polysilicon; The imaging element according to (6). (8) the transfer transistor is a P-type transistor, the second wiring is formed of N-type polysilicon; The imaging element according to (4). (9) the first element includes an electrode connected to the photoelectric conversion element; the second element includes a reference potential line to which a reference potential is supplied; the electrode is formed of N-type polysilicon, the second wiring for connecting the plurality of electrodes to the first wiring connected to the reference potential line through one contact is formed of P-type polysilicon; The imaging element according to (8). (10) the first element includes an electrode connected to the photoelectric conversion element; the second element includes a reference potential line to which a reference potential is supplied; The imaging device according to any one of (1) to (4). (11) The second wiring is formed containing tungsten. The imaging device according to any one of (1) to (4) and (10). (12) the second wiring is disposed in an insulating region formed between a first semiconductor region of the second substrate and a second semiconductor region of the second substrate; The imaging device according to any one of (1), (2), and (4) to (11). (13) the second wiring is disposed between the second element and the first wiring; The imaging device according to any one of (1), (2), and (4) to (11). (14) An imaging element; an optical system for guiding incident light to the imaging element; a processing unit that processes a signal output from the imaging element, The imaging element is a first substrate on which a plurality of photoelectric conversion elements are formed; a second substrate on which pixel transistors shared by each group of two or more photoelectric conversion elements are formed; and a second wiring for connecting a plurality of first elements, each formed for each of the photoelectric conversion elements, among the plurality of elements formed on the first substrate, to a second element shared by the plurality of first elements, the second wiring being for connecting the plurality of first elements to the first wiring formed on the second substrate with one contact. electronic equipment. (15) a first substrate on which a first photoelectric conversion element and a second photoelectric conversion element are formed; a first wiring formed on the first substrate and connected to the first photoelectric conversion element and the second photoelectric conversion element; a second substrate on which pixel transistors connected to the first photoelectric conversion elements and the second photoelectric conversion elements are formed; a second wiring formed on the second substrate; a third wiring formed to penetrate the first substrate and the second substrate and connected to the first wiring and the second wiring; Image sensor. (16) The pixel transistor includes at least one of an amplification transistor, a reset transistor, and a selection transistor. The imaging element according to (15). (17) the first substrate has a first transfer transistor connected to the first photoelectric conversion element and a second transfer transistor connected to the second photoelectric conversion element; The imaging element according to (15) or (16). (18) the first wiring is connected to a first floating diffusion region connected to the first transfer transistor and a second floating diffusion region connected to the second transfer transistor; The imaging element according to (17). (19) a third substrate laminated on the second substrate and having a logic circuit that processes a signal generated by the first photoelectric conversion element or the second photoelectric conversion element; The imaging element according to (18). (20) An imaging element; an optical system for guiding incident light to the imaging element; a processing unit that processes a signal output from the imaging element, The imaging element is a first substrate on which a first photoelectric conversion element and a second photoelectric conversion element are formed; a first wiring formed on the first substrate and connected to the first photoelectric conversion element and the second photoelectric conversion element; a second substrate on which pixel transistors connected to the first photoelectric conversion elements and the second photoelectric conversion elements are formed; a second wiring formed on the second substrate; a third wiring formed to penetrate the first substrate and the second substrate and connected to the first wiring and the second wiring; electronic equipment. [Explanation of symbols]

[0238] 1··imaging element, 10··first substrate, 20··second substrate, 30··third substrate, 202··semiconductor region, 203··pixel separation section, 204··semiconductor region, 221··drain region, 222··source region, 223··gate electrode, 301a, 301b··wiring, 311··gate electrode, 312··drain region, 313··source region, 321··drain region, 322··source region, 323··gate electrode, AMP··amplifying transistor, Ct, Ct2··contact, D1··wiring, PD··photodiode, RST··reset transistor, SEL··selection transistor, TR··transfer transistor

Claims

1. a first substrate on which a plurality of photoelectric conversion elements and transfer transistors formed for each of the photoelectric conversion elements for transferring electrical signals output from the photoelectric conversion elements are formed; a second substrate on which one or more pixel transistors shared by each group of two or more photoelectric conversion elements are formed; Equipped with a floating diffusion that temporarily holds an electrical signal output from each of the photoelectric conversion elements is formed on the first substrate as an output terminal side of each of the transfer transistors; a second wiring connected to each of the floating diffusions is connected to one contact shared by a plurality of the second wirings, and is connected to a first wiring formed on the second substrate via the contact; the transfer transistor is an N-type transistor, the second wiring is formed of P-type polysilicon; Image sensor.

2. A first substrate on which a plurality of photoelectric conversion elements and transfer transistors formed for each of the photoelectric conversion elements for transferring electrical signals output from the photoelectric conversion elements are formed; a second substrate on which one or more pixel transistors shared by each group of two or more photoelectric conversion elements are formed; Equipped with a floating diffusion that temporarily holds an electrical signal output from each of the photoelectric conversion elements is formed on the first substrate as an output terminal side of each of the transfer transistors; a second wiring connected to each of the floating diffusions is connected to one contact shared by a plurality of the second wirings, and is connected to a first wiring formed on the second substrate via the contact; the transfer transistor is a P-type transistor, the second wiring is formed of N-type polysilicon; Image sensor.

3. The image sensor according to claim 1 , wherein the contact is formed on the first substrate and the second substrate, and electrically connects the first substrate and the second substrate.

4. the contact is formed to penetrate an insulating region located between a first semiconductor region of the second substrate and a second semiconductor region of the second substrate; The imaging device according to claim 3 .

5. the pixel transistors including at least an amplifier transistor that amplifies and outputs an electrical signal transferred from each of the transfer transistors are formed in the first semiconductor region or the second semiconductor region of the second substrate; the first wiring is connected to the amplification transistor; The imaging device according to claim 4 .

6. the pixel transistor includes a selection transistor; The imaging device according to claim 5 .

7. the first wiring is formed containing copper; The imaging device according to any one of claims 1 to 6.

8. a third substrate laminated on the second substrate and having a logic circuit for processing signals generated by the photoelectric conversion elements; The imaging device according to any one of claims 1 to 7.

9. 9. The imaging element according to claim 8, wherein a plurality of pad electrodes are formed on each of the surfaces of the second substrate and the third substrate facing each other, for electrically connecting and bonding the second substrate and the third substrate together.

10. The pad electrode is formed containing copper. The imaging device according to claim 9 .

11. The imaging element according to any one of claims 1 to 10, wherein in a cross section of the imaging element cut along a first direction perpendicular to the surface of the first substrate, each of the second wirings extends in the first direction.

12. The imaging device according to claim 11 , wherein each of the second wirings is connected to a third wiring formed on the first substrate, and the third wirings are connected to the contacts.

13. The image sensor according to claim 12 , wherein in the cross section, the third wiring extends in a second direction that intersects with and is parallel to a surface of the first substrate.

14. The image sensor according to claim 13 , wherein in the cross section, the length of each of the second wirings in the second direction is shorter than the length of each of the third wirings in the second direction.

15. The imaging element according to any one of claims 1 to 14, wherein the gate electrodes of the transfer transistors are arranged adjacent to the floating diffusion and are connected to a fifth wiring formed on the second substrate via a through electrode.

16. An imaging element; an optical system for guiding incident light to the imaging element; a processing unit that processes a signal output from the imaging element, The imaging element is a first substrate on which a plurality of photoelectric conversion elements and transfer transistors formed for each of the photoelectric conversion elements for transferring electrical signals output from the photoelectric conversion elements are formed; a second substrate on which one or more pixel transistors shared by each group of two or more photoelectric conversion elements are formed; and a floating diffusion that temporarily holds an electrical signal output from each of the photoelectric conversion elements is formed on the first substrate as an output terminal side of each of the transfer transistors; a second wiring connected to each of the floating diffusions is connected to one contact shared by a plurality of the second wirings, and is connected to a first wiring formed on the second substrate via the contact; the transfer transistor is an N-type transistor, the second wiring is formed of P-type polysilicon; electronic equipment.

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