Semiconductor Devices

Abstract

To provide a high-quality semiconductor device.SOLUTION: A semiconductor device of an embodiment includes a plurality of transistors connected in series between an input end and an output end. The plurality of transistors include a first transistor having a first and a second end used for serial connection, and a second transistor having a third and a fourth end used for serial connection, a first gate, and a first body. The third end is connected to the second end. The semiconductor device further includes a third transistor and a first diode connected in series between the first body and the first end. The third transistor includes a second gate connected to the first gate. An anode of the first diode is provided on the first body side between the first body and the first end, and a cathode of the first diode is provided on the first end side between the first body and the first end.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Switch circuits used in mobile terminals and the like are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,715,133 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a high-quality semiconductor device. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes an input terminal and an output terminal, and a plurality of transistors connected in series between the input terminal and the output terminal, wherein the plurality of transistors include a first transistor having a first terminal and a second terminal used for the series connection, and a second transistor having a third terminal and a fourth terminal used for the series connection, a first gate, and a first body, the third terminal of the second transistor being connected to the second terminal; the semiconductor device further includes a third transistor and a first diode connected in series between the first body and the first terminal, the third transistor having a second gate connected to the first gate, an anode of the first diode being located on the first body side of the first body and the first terminal, and a cathode of the first diode being located on the first terminal side of the first body and the first terminal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a wireless device including a switch circuit according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a circuit configuration of a switch circuit according to the first embodiment. [Figure 3] FIG. 2 is a diagram for explaining the structure of a transistor in the switch circuit according to the first embodiment. [Figure 4] 3A and 3B are diagrams for explaining various currents that flow through the switch circuit according to the first embodiment while the switch circuit is in an off state. [Figure 5] 3 is a diagram for explaining the operation of the switch circuit according to the first embodiment when a first high-frequency signal is input to the switch circuit. FIG. [Figure 6] 4A and 4B are diagrams for explaining the operation of the switch circuit according to the first embodiment when a second high-frequency signal is input to the switch circuit. [Figure 7] 5A and 5B are diagrams for explaining the operation of the switch circuit according to the first embodiment when a third high-frequency signal is input to the switch circuit. [Figure 8] FIG. 10 is a diagram showing an example of a graph illustrating the relationship between the high-frequency power of a high-frequency signal and the bias voltages of a first terminal and a body of a transistor when the high-frequency signal is input to the switch circuit according to the first embodiment. [Figure 9] FIG. 4 is a diagram showing an example of a graph illustrating the relationship between the high-frequency power of a high-frequency signal and the power of third-order distortion caused by the influence of a feedback circuit when the high-frequency signal is input to the switch circuit according to the first embodiment. [Figure 10] FIG. 4 is a diagram for explaining another example of the circuit configuration of the switch circuit according to the first embodiment. [Figure 11] FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a second embodiment. [Figure 12] FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a third embodiment. [Figure 13] FIG. 10 is a diagram for explaining the operation of the switch circuit according to the third embodiment when a third high-frequency signal is input to the switch circuit. [Figure 14]FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a fourth embodiment. [Figure 15] FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a fifth embodiment. [Figure 16] FIG. 13 is a diagram showing an example of a circuit configuration of a switch circuit according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned common reference symbols. When multiple components having the same reference symbol are to be distinguished from one another, a subscript will be added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol will be assigned to the multiple components, without a subscript.

[0008] Each functional block can be realized by either hardware or software, or a combination of both. Furthermore, it is not essential that each functional block be distinguished as described below. For example, some functions may be performed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional block may be further divided into smaller functional sub-blocks. Furthermore, the names of each functional block and each component in the following description are for convenience and do not limit the configuration and operation of each functional block and each component.

[0009] First Embodiment The semiconductor device according to the first embodiment will be described below. Hereinafter, this semiconductor device will also be referred to as a switch circuit 1.

[0010] [Configuration example] (1) Wireless equipment FIG. 1 is a block diagram showing an example of the configuration of a wireless device WD including a switch circuit 1 according to the first embodiment. The wireless device WD is, for example, a smartphone, a feature phone, a mobile terminal (e.g., a tablet terminal), a personal computer, a game console, a router, or a base station. The wireless device WD transmits and receives signals using communication standards such as LTE (registered trademark) (Long Term Evolution) and / or Wi-Fi. Reference numerals 1a, 1b, 1c, 1d, and 1e shown in FIG. 1 will be referred to in the description of the following embodiments.

[0011] In addition to the switch circuit 1, the wireless device WD includes, for example, an antenna ANT, switch circuits 2, 3, and 4, signal processing circuits 5 and 6, and a control circuit .

[0012] The antenna ANT receives high frequency signals from other devices (for example, a base station or other wireless devices) and is also capable of transmitting high frequency signals from the wireless device WD to other devices.

[0013] The control circuit 7 transmits control signals CNT to, for example, the switch circuits 1, 2, 3, and 4 and to the signal processing circuits 5 and 6. Whether each of the switch circuits 1, 2, 3, and 4 is in an on state or an off state is controlled by the control signal CNT that the switch circuit receives from the control circuit 7. While a switch circuit is in an on state, the switch circuit is capable of transmitting a signal between its first terminal and its second terminal. On the other hand, while a switch circuit is in an off state, the switch circuit does not transmit a signal between its first terminal and its second terminal. The signal processing circuits 5 and 6 each process a signal based on the control signal CNT that they receive from the control circuit 7.

[0014] A first terminal of the switch circuit 1 is connected to the antenna ANT, and a second terminal of the switch circuit 1 is connected to the signal processing circuit 5. The switch circuit 1 receives a control signal CNT1 from the control circuit 7. While the switch circuit 1 is in an on state based on the control signal CNT1, the switch circuit 1 transmits, for example, a high-frequency signal received by the wireless device WD via the antenna ANT to the signal processing circuit 5.

[0015] A first terminal of the switch circuit 2 is connected to a signal path between the switch circuit 1 and the signal processing circuit 5. A second terminal of the switch circuit 2 is, for example, grounded.

[0016] The switch circuit 2 receives a control signal CNT2 from the control circuit 7. For example, the switch circuit 2 is in an ON state based on the control signal CNT2 while the switch circuit 1 is in an OFF state. While in the ON state, the switch circuit 2 fixes the potential of the signal path between the switch circuit 1 and the signal processing circuit 5 to the ground potential.

[0017] The signal processing circuit 5 receives the high-frequency signal transmitted via the switch circuit 1, and executes various processes on the high-frequency signal based on a control signal CNT3 received from the control circuit .

[0018] A first terminal of the switch circuit 3 is connected to the antenna ANT, and a second terminal of the switch circuit 3 is connected to the signal processing circuit 6. The switch circuit 3 receives, for example, a control signal CNT2 from the control circuit 7. While the switch circuit 3 is in an on state based on the control signal CNT2, it transmits, for example, a high-frequency signal received by the wireless device WD via the antenna ANT to the signal processing circuit 6. The frequency band of the high-frequency signal transmitted by the switch circuit 3 is different, for example, from the frequency band of the high-frequency signal transmitted by the switch circuit 1. The switch circuits 1 and 3 are selectively turned on under the control of, for example, the control circuit 7.

[0019] A first terminal of the switch circuit 4 is connected to a signal path between the switch circuit 3 and the signal processing circuit 6. A second terminal of the switch circuit 4 is, for example, grounded. The switch circuit 4 receives, for example, a control signal CNT1 from the control circuit 7. For example, the switch circuit 4 is in an ON state based on the control signal CNT1 while the switch circuit 3 is in an OFF state. While in the ON state, the switch circuit 4 fixes the potential of the signal path between the switch circuit 3 and the signal processing circuit 6 to the ground potential.

[0020] The signal processing circuit 6 receives the high frequency signal transmitted via the switch circuit 3, and executes various processes on the high frequency signal based on a control signal CNT4 received from the control circuit .

[0021] In the above description, the switch circuits 1 and 3 each transmit a high-frequency signal that the wireless device WD receives from another device. However, the switch circuits 1 and 3 are not limited to this. Either of the switch circuits 1 and 3 may transmit a high-frequency signal that the wireless device WD transmits to another device.

[0022] The following description focuses on the switch circuit 1.

[0023] (2) Switch circuit 2 shows an example of the circuit configuration of the switch circuit 1 according to the first embodiment. In FIG. 2, the circuit symbol for each transistor indicates that one end of the transistor is the drain and the other end is the source, but the drain and source may be interchanged depending on the relationship between the potentials of the two ends. In FIG. 2, various voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12, and VR23 are shown, but these voltages will be referred to in the description of an operation example described later.

[0024] The switch circuit 1 includes n transistors (n is a natural number): M1, M2, M3, M4, M5, . . . , M(n-2), M(n-1), and Mn. Each of these transistors is a field effect transistor (FET), such as an n-channel metal oxide semiconductor (MOS) transistor. Unless otherwise specified, the same applies to other components referred to as transistors in this specification. In FIG. 2, a first end and a second end of the switch circuit 1 are indicated as a terminal IN and a terminal OUT, respectively.

[0025] The switch circuit 1 further includes resistors Rg1, Rg2, Rg3, Rg4, Rg5, ..., Rg(n-2), Rg(n-1), and Rgn, and resistors Rb1, Rb2, Rb3, Rb4, ..., Rb(n-2), Rb(n-1), and Rbn. The switch circuit 1 further includes resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), Rds(3,1), Rds(3,2), Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), ···, Rds(n-2,1), Rds(n-2,2), Rds(n-1,1), Rds(n-1,2), Rds(n,1), and Rds(n,2).

[0026] The resistance values ​​of resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), Rds(3,1), Rds(3,2), Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), . . ., Rds(n-2,1), Rds(n-2,2), Rds(n-1,1), Rds(n-1,2), Rds(n,1), and Rds(n,2) are, for example, substantially the same R1. Below, we will explain the case where the resistance values ​​of these resistors Rds are substantially the same.

[0027] Transistors M1, M2, M3, M4, M5, . . . , M(n-2), M(n-1), and Mn are connected in series between terminal IN and terminal OUT. More specifically, the first terminal of transistor M1 is connected to terminal IN, and the first terminal of transistor M2 is connected to the second terminal of transistor M1. The first terminal of transistor M3 is connected to the second terminal of transistor M2, and the first terminal of transistor M4 is connected to the second terminal of transistor M3. The same applies to the connection relationship between transistors M4, M5, . . . , M(n-2), M(n-1), and Mn, and terminal OUT is connected to the second terminal of transistor Mn.

[0028] A resistor Rg1 is connected between the gate of transistor M1 (hereinafter also referred to as the control terminal) and the gate of transistor M2. A resistor Rg2 is connected between the gate of transistor M2 and the gate of transistor M3. A resistor Rg3 is connected between the gate of transistor M3 and the gate of transistor M4. The same applies to resistors Rg4, Rg5, . . . , Rg(n-2), and Rg(n-1). One end of a resistor Rgn is further connected to the gate of transistor Mn. The other end of the resistor Rgn is connected to a node to which a signal GB is input. FIG. 2 shows the control terminal to which the signal GB is input to the switch circuit 1. The signal GB is, for example, the control signal CNT1 described with reference to FIG. 1. The signal GB can be changed between a high (H) level and a low (L) level, for example, by the control circuit 7. In this specification, when the term "level" is used, it refers to a voltage level unless otherwise specified.

[0029] A resistor Rb1 is connected between the body of transistor M1 (hereinafter also referred to as the back gate) and the body of transistor M2. A resistor Rb2 is connected between the body of transistor M2 and the body of transistor M3. A resistor Rb3 is connected between the body of transistor M3 and the body of transistor M4. The same applies to the resistors Rb4, ..., Rb(n-2), and Rb(n-1). One end of resistor Rbn is further connected to the body of transistor Mn. The other end of resistor Rbn is connected to a node to which signal BB is input. Figure 2 also shows a control terminal to which signal BB is input to switch circuit 1. Signal BB is supplied by, for example, a control circuit 7. The voltage of signal BB is set, for example, according to the voltage of signal GB.

[0030] One end of resistor Rds(1,1) is connected to a first end of transistor M1, one end of resistor Rds(1,2) is connected to the other end of resistor Rds(1,2), and a second end of transistor M1 is connected to the other end of resistor Rds(1,2). One end of resistor Rds(2,1) is connected to a first end of transistor M2, one end of resistor Rds(2,2) is connected to the other end of resistor Rds(2,1), and a second end of transistor M2 is connected to the other end of resistor Rds(2,2). One end of resistor Rds(3,1) is connected to a first end of transistor M3, one end of resistor Rds(3,2) is connected to the other end of resistor Rds(3,1), and a second end of transistor M3 is connected to the other end of resistor Rds(3,2). The same is true for resistors Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), ···, Rds(n-2,1), Rds(n-2,2), Rds(n-1,1), Rds(n-1,2), Rds(n,1), and Rds(n,2).

[0031] Each of the resistors Rg, Rb, and Rds is formed using, for example, polysilicon.

[0032] The switch circuit 1 further includes, as components of the feedback circuit, for example, transistors Tr(1,3), Tr(1,4), Tr(2,1), Tr(2,2), Tr(2,3), Tr(2,4), Tr(3,1), Tr(3,2), Tr(3,3), Tr(3,4), Tr(4,1), Tr(4,2), Tr(4,3), Tr(4,4), Tr(5,1), Tr(5,2), Tr(5,3), Tr(5,4), Tr(n-2,1), Tr(n-2,2), Tr(n-2,3), Tr(n-2,4), Tr(n-1,1), Tr(n-1,2), Tr(n-1,3), Tr(n-1,4), Tr(n,1), and Tr(n,2).

[0033] The transistors Tr(1,3) and Tr(1,4) correspond to the transistor M1.

[0034] A first terminal of transistor Tr(1,3) is connected to the body of transistor M1, and a gate of transistor Tr(1,3) is connected to the gate of transistor M1. A second terminal of transistor Tr(1,3) is connected to a first terminal of transistor Tr(1,4) and the gate of transistor Tr(1,4). Thus, a diode-connected transistor Tr(1,4) is connected to a second terminal of transistor Tr(1,3). A second terminal of transistor Tr(1,4) is connected to a node connecting resistors Rds(2,1) and Rds(2,2).

[0035] The following explanation holds for each case where the integer k is from 2 to n-1. Transistors Tr(k,1), Tr(k,2), Tr(k,3), and Tr(k,4) are associated with transistor Mk.

[0036] A first terminal of transistor Tr(k,1) is connected to the body of transistor Mk, and a gate of transistor Tr(k,1) is connected to the gate of transistor Mk. A second terminal of transistor Tr(k,1) is connected to a first terminal of transistor Tr(k,2) and the gate of transistor Tr(k,2). Thus, a diode-connected transistor Tr(k,2) is connected to a second terminal of transistor Tr(k,1). A second terminal of transistor Tr(k,2) is connected to a node connecting resistors Rds(k-1,1) and Rds(k-1,2).

[0037] A first terminal of transistor Tr(k,3) is connected to the body of transistor Mk, and a gate of transistor Tr(k,3) is connected to the gate of transistor Mk. A second terminal of transistor Tr(k,3) is connected to a first terminal of transistor Tr(k,4) and the gate of transistor Tr(k,4). Thus, a diode-connected transistor Tr(k,4) is connected to a second terminal of transistor Tr(k,3). A second terminal of transistor Tr(k,4) is connected to a node connecting resistors Rds(k+1,1) and Rds(k+1,2).

[0038] The transistors Tr(n,1) and Tr(n,2) correspond to the transistor Mn.

[0039] The first terminal of transistor Tr(n,1) is connected to the body of transistor Mn, and the gate of transistor Tr(n,1) is connected to the gate of transistor Mn. The second terminal of transistor Tr(n,1) is connected to the first terminal of transistor Tr(n,2) and the gate of transistor Tr(n,2). Thus, the diode-connected transistor Tr(n,2) is connected to the second terminal of transistor Tr(n,1). The second terminal of transistor Tr(n,2) is connected to the node connecting resistors Rds(n-1,1) and Rds(n-1,2).

[0040] While the signal GB is at H level, the transistors M1, M2, M3, M4, M5, . . . , M(n-2), M(n-1), and Mn are each in an ON state, that is, the switch circuit 1 is in an ON state.

[0041] While signal GB is at an L level, transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn are each in an OFF state, i.e., switch circuit 1 is in an OFF state. While switch circuit 1 is in an OFF state, due to the connection relationship of resistor Rds described above, a voltage obtained by dividing the voltage applied between terminal IN and terminal OUT is applied to transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn, respectively. The voltages applied to transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn, respectively, are substantially the same.

[0042] If the potential (hereinafter also referred to as voltage) of the body of transistor M2 is higher than the voltage at the second end of transistor Tr(2,2), current flows from the body through transistors Tr(2,1) and Tr(2,2) while transistors Tr(2,1) and Tr(2,2) are in the on state. When current flows in this manner, the voltage of the body drops. Whether transistor Tr(2,1) is in the on state or off state depends on the voltage at the gate of transistor M2. This is because the gate of transistor Tr(2,1) is connected to the gate of transistor M2.

[0043] If the voltage of the body of transistor M2 is higher than the voltage at the second end of transistor Tr(2,4), current flows from the body through transistors Tr(2,3) and Tr(2,4) while transistors Tr(2,3) and Tr(2,4) are on. This current flow also causes the body voltage to drop. Whether transistor Tr(2,3) is on or off depends on the voltage at the gate of transistor M2. This is because the gate of transistor Tr(2,3) is connected to the gate of transistor M2.

[0044] The above description is related to the transistors Tr(2,1), Tr(2,2), Tr(2,3), and Tr(2,4) associated with the transistor M2. The same description applies to each of the other transistors M associated with the transistor M.

[0045] In the above description, for example, the second terminal of transistor Tr(2,2) is connected to the node connecting resistors Rds(1,1) and Rds(1,2). In this connection relationship, if the resistance value of resistor Rds(1,1) is extremely small, for example, it can be interpreted that the second terminal of transistor Tr(2,2) is connected to the first terminal of transistor M1 without an intervening resistor element. If the resistance value of resistor Rds(1,1) is extremely small, for example, the resistance value of resistor Rds(1,2) differs from the resistance value of resistor Rds(1,1). The same applies to the other transistors Tr described as being connected in a similar manner.

[0046] In the above description, for example, a transistor Tr(2,1) having a gate connected to the gate of transistor M2 and a diode-connected transistor Tr(2,2) are provided in the path from the body of transistor M2 to the first end of transistor M1 in the order of transistor Tr(2,1) and transistor Tr(2,2). However, this embodiment is not limited to this. The transistors Tr(2,1) and Tr(2,2) may be provided in the reverse order in the path from the body of transistor M2 to the first end of transistor M1. The same applies to the other transistors Tr described as being connected in a similar manner.

[0047] In the above, diode-connected transistors such as transistors Tr(1,4), Tr(2,2), Tr(2,4), Tr(3,2), Tr(3,4), . . . , Tr(n-1,2), Tr(n-1,4), and Tr(n,2) have been described as components of the switch circuit 1. In the switch circuit 1, diodes formed by PN junctions may be used instead of the transistors Tr. The same applies to the other diode-connected transistors described in this specification. When simply referring to a "diode" in this specification, it is intended that either a diode-connected transistor or a diode formed by a PN junction may be used as the diode. In either case, the electrodes of the diode are referred to as the anode and cathode in this specification.

[0048] 3 is a diagram illustrating the structure of the transistor M2 of the switch circuit 1 according to the first embodiment. FIG. 3 illustrates a portion of the cross-sectional structure of the switch circuit 1. The structure of the transistor M2 will be described below as an example, but the other transistors M may also have a similar structure to that described below. As an example, a case will be described in which the switch circuit 1 is provided on an SOI (Silicon On Insulator) substrate.

[0049] An oxide film BOX is provided on the upper surface of the semiconductor substrate SB. A semiconductor layer is provided on the upper surface of the oxide film BOX as a body layer BD. The body layer BD is doped with, for example, boron (B) to form a p + The body layer BD is used as an impurity diffusion layer. A source region SR and a drain region DR are provided on the surface of the body layer BD with a gap therebetween. The source region SR and the drain region DR are each doped with, for example, phosphorus (P) to form an n-type impurity diffusion layer. + The gate electrode G is provided on the upper surface of the body layer BD between the source region SR and the drain region DR via a gate insulator GI. The transistor M2 includes the source region SR, the drain region DR, and the gate electrode G.

[0050] The gate of the transistor M2 is connected to other components via a contact plug (not shown) or the like provided on the upper surface of the gate electrode G. Similarly, a first end of the transistor M2 is connected to other components via a contact plug (not shown) or the like provided on the upper surfaces of the drain region DR and the source region SR, and a second end of the transistor M2 is connected to other components via a contact plug (not shown) or the like provided on the upper surfaces of the drain region DR and the source region SR, respectively.

[0051] For example, if the voltage of the drain region DR is higher than the voltage of the body layer BD, a leakage current Ib may flow from the drain region DR to the body layer BD. Similarly, if the voltage of the source region SR is higher than the voltage of the body layer BD, a leakage current Ib may flow from the source region SR to the body layer BD.

[0052] When such a leakage current Ib occurs, the voltage of the body of the transistor M2 may rise. The current flows as described above through the various transistors Tr associated with the transistor M2, thereby suppressing the rise in the voltage.

[0053] [Example of operation] An example of the operation of the switch circuit 1 according to the first embodiment while the switch circuit 1 is in the OFF state will be described below.

[0054] (1) Overview of switch circuit 1 operation 4 is a diagram illustrating various currents that flow through the switch circuit 1 according to the first embodiment while the switch circuit 1 is in an off state. For simplicity of explanation, FIG. 4 illustrates the circuit configuration of the switch circuit 1 when n is 3. The following description will be given for the case where n is 3.

[0055] When a certain high frequency signal is input to the terminal IN, the leakage current Ib described with reference to FIG. 3 may occur in each of the transistors M1, M2, and M3.

[0056] Such a leakage current Ib can increase the bias potential (hereinafter also referred to as the bias voltage) of the body of each of the transistors M1, M2, and M3. More specifically, this is as follows.

[0057] This leakage current Ib can affect the currents flowing through resistors Rb1, Rb2, and Rb3. Figure 4 shows, as an example, how this leakage current Ib contributes to current flow from the body of transistor M1 through resistor Rb1, current flow from the body of transistor M2 through resistor Rb2, and current flow from the body of transistor M3 through resistor Rb3. This changes the amount of voltage drop across the various resistors Rb. The amount of increase in the body bias voltage of each of transistors M1, M2, and M3 described above corresponds to the amount of this change.

[0058] Furthermore, such leakage current Ib may cause the bias voltages at the second terminal of the transistor M1, the first and second terminals of the transistor M2, and the first terminal of the transistor M3 to drop.

[0059] This leakage current Ib may contribute to current flowing from the terminal IN through resistors Rds(1,1) and Rds(1,2) to the node connecting the second terminal of transistor M1 and the first terminal of transistor M2. This leakage current Ib may contribute to current flowing from the terminal OUT through resistors Rds(3,2) and Rds(3,1) to the node connecting the second terminal of transistor M2 and the first terminal of transistor M3. This changes the amount of voltage drop across the various resistors Rds. The amount of drop in the bias voltage at the second terminal of transistor M1, the first and second terminals of transistor M2, and the first terminal of transistor M3 corresponds to the amount of this change.

[0060] Although the above description has been given for the case where n is 3, a similar description also applies when n is an integer other than 3. That is, the leakage current Ib generated in each transistor M may increase the bias voltage of the body of each transistor M, and may decrease the bias voltage of the first terminal and / or the second terminal of each transistor M.

[0061] In the switch circuit 1, the following current may also flow through the feedback circuit. The following description will be given using the currents flowing through the transistors Tr(2,1), Tr(2,2), Tr(2,3), and Tr(2,4) associated with the transistor M2 as an example. Similar descriptions apply to the other transistors M associated with the respective transistors Tr.

[0062] When the voltage of the body of transistor M2 is higher than the voltage of the second terminal of transistor Tr(2,2), the following occurs: While transistors Tr(2,1) and Tr(2,2) are in the on state, current flows from the body to the second terminal. This current contributes to current flow from the second terminal through resistor Rds(1,1) to the node connecting resistor Rds(1,1) and the first terminal of transistor M1.

[0063] When the voltage of the body of transistor M2 is higher than the voltage of the second terminal of transistor Tr(2,4), the following occurs: While transistors Tr(2,3) and Tr(2,4) are in the on state, current flows from the body to the second terminal. This current contributes to current flow from the second terminal through resistor Rds(3,2) to the node connecting resistor Rds(3,2) and the second terminal of transistor M3.

[0064] Although the above description has been given for the case where n is 3, a similar description also applies when n is an integer other than 3. As a result of current flowing from the body of each transistor M via the feedback circuit as described above, the bias voltage of the body of each transistor M is lowered so as to suppress the above-mentioned increase, and the bias voltage of each of the first terminal and / or second terminal of each transistor M is raised so as to suppress the above-mentioned decrease.

[0065] In relation to such an operation, the following will provide a more detailed explanation of an example of the operation of the switch circuit 1 when various high-frequency signals are input to the terminal IN. As with the explanation of Figure 4, the following explanation will focus on the transistor M2 among the series-connected transistors M1, M2, M3, ..., and Mn.

[0066] The following explanation will refer to the various voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12, and VR23 shown in Figure 2. The explanation will also be given assuming that a voltage of 0 volts (V) is applied as a bias voltage to the terminals IN and OUT.

[0067] Voltage VM01 is the voltage at the first end of transistor M1. Voltage VM12 is the voltage at the second end of transistor M1 and the voltage at the first end of transistor M2. Voltage VM23 is the voltage at the second end of transistor M2 and the voltage at the first end of transistor M3. Voltage VM34 is the voltage at the second end of transistor M3 and the voltage at the first end of transistor M4. Voltage VG2 is the voltage at the gate of transistor M2. Voltage VB2 is the voltage at the body of transistor M2. Voltage VR12 is the voltage at the node connecting the second end of transistor Tr(2,2) and resistors Rds(1,1) and Rds(1,2). Voltage VR23 is the voltage at the node connecting the second end of transistor Tr(2,4) and resistors Rds(3,1) and Rds(3,2).

[0068] (2) First Operation Example of Switch Circuit 1 FIG. 5 is a diagram for explaining the operation of the switch circuit 1 when a first high-frequency signal is input to the switch circuit 1 according to the first embodiment.

[0069] FIG. 5 shows an example of the waveforms of voltages VM12, VM23, VG2, VB2, VR12, and VR23 when a first high-frequency signal is input to terminal IN. The horizontal axis represents time. The vertical axis represents voltage values. For ease of reference, the voltage values ​​shown are the potential differences from voltage VM23 at the second end of transistor M2. The various voltage values ​​and signal waveforms mentioned in the following description are thus based on voltage VM23. Furthermore, the voltage values ​​mentioned in the following description are merely examples for the sake of simplicity. The same applies to similar drawings mentioned in the following description.

[0070] When a first high-frequency signal is input to terminal IN, as a result of the voltage division due to the connection relationship of resistor Rds described above, in the example of FIG. 5, the voltage signal applied between the first terminal and the second terminal of each transistor M becomes a high-frequency signal with an amplitude of 2 V. At this time, the signal of voltage VM12 is a high-frequency signal with an amplitude of 2 V. The signal of voltage VR12 is a high-frequency signal with an amplitude of 3 V, and the signal of voltage VR23 is a high-frequency signal with an amplitude of 1 V. These are based on the voltage division by resistors Rds(1,1) and Rds(1,2) and the voltage division by resistors Rds(3,1) and Rds(3,2), respectively. The signal of voltage VR12 is substantially in phase with the signal of voltage VM12, and the signal of voltage VR23 is substantially out of phase with the signal of voltage VM12.

[0071] 5, the L-level voltage of signal GB is −3 V. Therefore, the voltage VG2 signal is a bias voltage signal of −3 V superimposed with a high-frequency signal having an amplitude of 1 V. The voltage VG2 signal is substantially in phase with the voltage VM12 signal. These are due to, for example, the parasitic capacitances occurring between the gate and the first terminal of transistor M2 and between the gate and the second terminal of transistor M2, respectively.

[0072] 5, the voltage of signal BB is also −3 V. Therefore, the voltage VB2 signal is a bias voltage of −3 V superimposed with a high-frequency signal having an amplitude of 1 V. The voltage VB2 signal is substantially in phase with the voltage VM12 signal. These are due to, for example, the parasitic capacitances occurring between the body and the first terminal of transistor M2 and between the body and the second terminal of transistor M2, respectively.

[0073] Whether or not a current flows out of the body of transistor M2 through transistors Tr(2,1) and Tr(2,2) associated with transistor M2 is based on, for example, voltages VB2, VR12, and VG2. Whether or not a current flows out of the body of transistor M2 through transistors Tr(2,3) and Tr(2,4) associated with transistor M2 is based on, for example, voltages VB2, VR23, and VG2.

[0074] Whether or not such a current flows out of the body will be described for each of times T00 and T01. Time T00 is the time when the value of voltage VM12 is maximum, and time T01 is the time when the value of voltage VM12 is minimum.

[0075] At time T00, voltages VB2 and VG2 are −2 V, voltage VR12 is 3 V, and voltage VR23 is −1 V. At this time, because voltage VB2 is lower than voltage VR23, no current flows out of the body through transistors Tr(2,3) and Tr(2,4). Similarly, no current flows out of the body through transistors Tr(2,1) and Tr(2,2).

[0076] At time T01, voltages VB2 and VG2 are −4 V, voltage VR12 is −3 V, and voltage VR23 is 1 V. At this time, because voltage VB2 is lower than voltage VR12, no current flows out of the body through transistors Tr(2,1) and Tr(2,2). Similarly, no current flows out of the body through transistors Tr(2,3) and Tr(2,4).

[0077] Thus, in the example of FIG. 5, voltage VB2 is lower than voltages VR23 and VR12, and therefore no current flows out of the body.

[0078] (3) Second Operation Example of Switch Circuit 1 6 is a diagram illustrating the operation of the switch circuit 1 according to the first embodiment when a second high-frequency signal is input to the switch circuit 1. Fig. 6 shows an example of the waveforms of the voltages VM12, VM23, VG2, VB2, VR12, and VR23 when a second high-frequency signal is input to the terminal IN. The horizontal axis represents time, and the vertical axis represents the voltage value.

[0079] When a second high-frequency signal is input to terminal IN, as a result of voltage division due to the connection relationship of resistor Rds described above, in the example of Fig. 6, the voltage signal applied between the first terminal and the second terminal of each transistor M becomes a high-frequency signal with an amplitude of 3 V. At this time, the signal of voltage VM12 is a high-frequency signal with an amplitude of 3 V, the signal of voltage VR12 is a high-frequency signal with an amplitude of 4.5 V, and the signal of voltage VR23 is a high-frequency signal with an amplitude of 1.5 V. The signal of voltage VR12 is substantially in phase with the signal of voltage VM12, and the signal of voltage VR23 is substantially in opposite phase to the signal of voltage VM12.

[0080] 6, the L level voltage of signal GB is −3 V. Therefore, the signal of voltage VG2 is a signal of −3 V as a bias voltage superimposed with a high frequency signal of 1.5 V amplitude. The signal of voltage VG2 is substantially in phase with the signal of voltage VM12.

[0081] The amplitude of the second high-frequency signal is larger than the amplitude of the first high-frequency signal, and in the example of FIG. 6, a leakage current Ib is generated in transistor M2. This leakage current Ib increases the body bias voltage of transistor M2, as described with reference to FIG. 4. Therefore, while the voltage of signal BB is also −3V, the signal voltage VB2 is a bias voltage signal of −2V increased from −3V, with a high-frequency signal of 1.5V amplitude superimposed on it. The signal voltage VB2 is substantially in phase with the signal voltage VM12. Note that, for simplicity's sake, the example of FIG. 6 assumes no voltage drops at the second terminal of transistor M1, the first and second terminals of transistor M2, and the first terminal of transistor M3, as described with reference to FIG. 4.

[0082] At times T10 and T11, it is determined whether current flows out of the body of transistor M2 through transistors Tr(2,1) and Tr(2,2) or through transistors Tr(2,3) and Tr(2,4). Time T10 is the time when the value of voltage VM12 reaches a maximum, and time T11 is the time when the value of voltage VM12 reaches a minimum.

[0083] At time T10, voltage VB2 is −0.5V, voltage VG2 is −1.5V, voltage VR12 is 4.5V, and voltage VR23 is −1.5V. At this time, voltage VB2 is higher than voltage VR23, but no current flows out of the body through transistors Tr(2,3) and Tr(2,4). This is because voltage VG2 is not high enough to turn on transistor Tr(2,3), so transistor Tr(2,3) is in the off state. Also, as in the example of FIG. 5, voltage VB2 is lower than voltage VR12, so no current flows out of the body through transistors Tr(2,1) and Tr(2,2).

[0084] At time T11, voltage VB2 is −3.5V, voltage VG2 is −4.5V, voltage VR12 is −4.5V, and voltage VR23 is 1.5V. At this time, voltage VB2 is higher than voltage VR12, but no current flows out of the body through transistors Tr(2,1) and Tr(2,2). This is because voltage VG2 is not high enough to turn on transistor Tr(2,1), so transistor Tr(2,1) is in the off state. Also, as in the example of FIG. 5, voltage VB2 is lower than voltage VR23, so no current flows out of the body through transistors Tr(2,3) and Tr(2,4).

[0085] 6, even if the voltage VB2 is higher than the voltage VR23, the transistor Tr(2,3) is in the off state, and even if the voltage VB2 is higher than the voltage VR12, the transistor Tr(2,1) is in the off state. Therefore, no current flows out of the body.

[0086] (4) Third Operation Example of Switch Circuit 1 7 is a diagram illustrating the operation of the switch circuit 1 according to the first embodiment when a third high-frequency signal is input to the switch circuit 1. Fig. 7 shows an example of the waveforms of the voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12, and VR23 when a third high-frequency signal is input to the terminal IN. The horizontal axis represents time. The vertical axis represents the voltage value.

[0087] When a third high-frequency signal is input to terminal IN, as a result of voltage division due to the connection relationship of resistor Rds described above, in the example of FIG. 7, the voltage signal applied between the first terminal and the second terminal of each transistor M becomes a high-frequency signal with an amplitude of 4V. At this time, the signal of voltage VM01 is a high-frequency signal with an amplitude of 8V, the signal of voltage VM12 is a high-frequency signal with an amplitude of 4V, the signal of voltage VM34 is a high-frequency signal with an amplitude of 4V, the signal of voltage VR12 is a high-frequency signal with an amplitude of 6V, and the signal of voltage VR23 is a high-frequency signal with an amplitude of 2V. The signals of voltage VM01, voltage VM12, and voltage VR12 are substantially in phase. The signals of voltage VM34 and voltage VR23 are substantially out of phase with the signal of voltage VM12.

[0088] 7, the L level voltage of signal GB is −3 V. Therefore, the signal of voltage VG2 is a signal of −3 V as a bias voltage superimposed with a high frequency signal of 2 V amplitude. The signal of voltage VG2 is substantially in phase with the signal of voltage VM12.

[0089] 7, the voltage of signal BB is also −3 V. Therefore, the signal of voltage VB2 is a bias voltage of −3 V superimposed with a high-frequency signal having an amplitude of 2 V. The signal of voltage VB2 is substantially in phase with the signal of voltage VM12.

[0090] At times T20 and T21, it is determined whether current flows out of the body of transistor M2 through transistors Tr(2,1) and Tr(2,2) or through transistors Tr(2,3) and Tr(2,4). Time T20 is the time when the value of voltage VM12 reaches a maximum, and time T21 is the time when the value of voltage VM12 reaches a minimum.

[0091] At time T20, voltages VB2 and VG2 are −1 V, voltage VR12 is 6 V, and voltage VR23 is −2 V. At this time, voltage VB2 is higher than voltage VR23, and voltage VG2 is high enough to turn on transistor Tr(2,3). Therefore, transistors Tr(2,3) and Tr(2,4) are on, and current flows out of the body through transistors Tr(2,3) and Tr(2,4). This current flows from the second terminal of transistor Tr(2,4) to the node connecting the second terminal of transistor M3 and the first terminal of transistor M4. This is because voltage VR23 is higher than voltage VM34. This current flow leads to a decrease in the bias voltage of the body. However, as in the example of FIG. 5, voltage VB2 is lower than voltage VR12, so no current flows out of the body through transistors Tr(2,1) and Tr(2,2).

[0092] At time T21, voltages VB2 and VG2 are −5V, voltage VR12 is −6V, and voltage VR23 is 2V. At this time, voltage VB2 is higher than voltage VR12, and voltage VG2 is high enough to turn on transistor Tr(2,1). Therefore, transistors Tr(2,1) and Tr(2,2) are on, and current flows out of the body through transistors Tr(2,1) and Tr(2,2). This current flows from the second terminal of transistor Tr(2,2) to the node connecting the second terminal and the first terminal of transistor M1 because voltage VR12 is higher than voltage VM01. This current flow leads to a decrease in the bias voltage of the body. However, as in the example of FIG. 5, voltage VB2 is lower than voltage VR23, so no current flows out of the body through transistors Tr(2,3) and Tr(2,4).

[0093] The amplitude of the third high-frequency signal is larger than the amplitude of the second high-frequency signal. Therefore, in the example of FIG. 7, a leakage current Ib occurs in transistor M2. This leakage current Ib can increase the bias voltage of the body of transistor M2. However, as described above, current flows from the body through transistors Tr(2,1) and Tr(2,2), and also flows from the body through transistors Tr(2,3) and Tr(2,4). This current flow suppresses the increase in the bias voltage of the body of transistor M2. Therefore, in the example of FIG. 7, unlike the example of FIG. 6, no increase in the bias voltage is observed in the signal of voltage VB2.

[0094] (5) Relationship between the high-frequency power of the input high-frequency signal and various bias voltages FIG. 8 shows an example of a graph illustrating the relationship between the high-frequency power Pin associated with a high-frequency signal and the bias voltages of the first terminal and the body of the transistor M2 when the high-frequency signal is input to the switch circuit 1 according to the first embodiment.

[0095] 8(a) shows the relationship between the high frequency power Pin and the bias voltage VM12bias at the first terminal of the transistor M2. The horizontal axis represents the value of the high frequency power Pin. The vertical axis represents the value of the bias voltage VM12bias.

[0096] As explained with reference to Figures 4, 5, and 6, as the radio frequency power Pin increases, a leakage current Ib is generated in transistor M2, causing the bias voltage VM12bias to decrease. As explained with reference to Figure 7, when the radio frequency power Pin increases further, a current flows from the body of transistor M2 to the node connecting the first terminal of transistor M1 and terminal IN, and a current flows from the body to the node connecting the second terminal of transistor M3 and the first terminal of transistor M4. Similarly, a current also flows to the first terminal and second terminal of transistor M2. This current flow from the body of each transistor M causes the bias voltage VM12bias to increase so as to suppress the decrease.

[0097] 8(b) shows the relationship between the high-frequency power Pin and the bias voltage VB2bias of the body of the transistor M2. The horizontal axis represents the value of the high-frequency power Pin, and the vertical axis represents the value of the bias voltage VB2bias.

[0098] As explained with reference to Figures 4, 5, and 6, as the radio frequency power Pin increases, a leakage current Ib occurs in the transistor M2, causing the bias voltage VB2bias to increase. As explained with reference to Figure 7, when the radio frequency power Pin increases further, a current flows out of the body of the transistor M2. This causes the bias voltage VB2bias to decrease so as to suppress the increase.

[0099] [effect] The operation of the switch circuit 1 according to the first embodiment will be described while it is in the off state. As the high-frequency power associated with the high-frequency signal input to the terminal IN increases, a leakage current Ib may flow from the drain or source of each transistor M to the body.

[0100] For example, when a leakage current Ib occurs in the transistor M2, as described with reference to FIG. 4, the bias voltage of the body of the transistor M2 may increase, and the bias voltages of the first and second terminals of the transistor M2 may decrease. This reduces the potential difference between the body and drain of the transistor M2, making it easier for the parasitic bipolar transistor between the drain and source of the transistor M2 to turn on. When the parasitic bipolar transistor of a certain transistor M turns on, the voltage applied to each of the other transistors M increases, i.e., the breakdown voltage of the switch circuit 1 decreases.

[0101] As described with reference to FIG. 2, the switch circuit 1 includes, as components of the feedback circuit, various transistors Tr associated with each transistor M. The various transistors Tr associated with transistor M2 will now be described. Transistors Tr(2,1) and Tr(2,2) are connected in series between the body of transistor M2 and a first terminal of transistor M1. Transistors Tr(2,3) and Tr(2,4) are connected in series between the body of transistor M2 and a second terminal of transistor M3. As described with reference to FIGS. 4 and 7, current can flow from the bodies of transistors Tr(2,1) and Tr(2,2) to a node connecting the first terminal of transistor M1 and terminal IN, and current can flow from the bodies of transistors Tr(2,3) and Tr(2,4) to a node connecting the second terminal of transistor M3 and a first terminal of transistor M4. The same applies to the other transistors M.

[0102] By allowing current to flow in this manner (hereinafter, this may also be referred to as the operation of a feedback circuit), even if a leakage current Ib occurs in a certain transistor M, an increase in the bias voltage of the body of the transistor M is suppressed, and a decrease in the bias voltage of each of the first terminal and / or second terminal of the transistor M is suppressed. Therefore, the switch circuit 1 according to the first embodiment prevents a decrease in the withstand voltage of the switch circuit 1 due to the leakage current Ib occurring in the transistor M.

[0103] In the example of Figure 6, at time T10, the voltage VB2 of the body of transistor M2 is higher than voltage VR23, but transistor Tr(2,3) is in the off state. This is because the voltage VG2 of the gate of transistor M2, which is connected to the gate of transistor Tr(2,3), is not high enough to turn on transistor Tr(2,3). Similarly, in the example of Figure 6, at time T11, the voltage VB2 of the body of transistor M2 is higher than voltage VR12, but transistor Tr(2,1) is in the off state.

[0104] 6, even if a second high-frequency signal is input to the terminal IN and a leakage current Ib occurs, the bias voltage of the body of each transistor M does not increase enough to turn on the parasitic bipolar transistor of that transistor M, and the bias voltages of the first and second terminals of that transistor M do not decrease enough. In the switch circuit 1 according to the first embodiment, the feedback circuit does not operate even if such a high-frequency signal is input to the terminal IN.

[0105] Consider a case in which the gates of transistors Tr(2,1) and Tr(2,3) in the switch circuit 1 according to the first embodiment are connected to the body of transistor M2 rather than to the gate of transistor M2. That is, consider a case in which diode-connected transistors Tr(2,1) and Tr(2,3) are connected to the body of transistor M2. When various voltages are the same as those at time T10, voltage VB2 is sufficiently higher than voltage VR23, so current flows from the body via transistors Tr(2,3) and Tr(2,4) to a node connecting the second terminal of transistor M3 and the first terminal of transistor M4. When various voltages are the same as those at time T11, voltage VB2 is sufficiently higher than voltage VR12, so current flows from the body via transistors Tr(2,1) and Tr(2,2) to a node connecting the first terminal of transistor M1 and terminal IN. In this way, in a switch circuit in which only a diode is used as a component of the feedback circuit (hereinafter referred to as a switch circuit according to a comparative example), the feedback circuit may operate even when a high-frequency signal of a level that would not cause the feedback circuit to operate is input to terminal IN in switch circuit 1.

[0106] 9 shows an example of a graph illustrating the relationship between the high-frequency power Pin associated with a high-frequency signal and the power Phd3 of third-order distortion generated by the influence of a feedback circuit when the high-frequency signal is input to the switch circuit 1 according to the first embodiment. The horizontal axis represents the value of the high-frequency power Pin. The vertical axis represents the value of the power Phd3. In this graph, values ​​expressed in units of decibel milliwatts (dBmW) (hereinafter referred to as dBm) are plotted for both the high-frequency power Pin and the power Phd3. FIG. 9 also shows a similar graph for a switch circuit according to a comparative example.

[0107] When the feedback circuit operates, current flows out of the body of each transistor M, degrading the linearity of the switch circuit 1. This can increase the power Phd3 of third-order distortion generated in the switch circuit 1. As described above, in the switch circuit according to the comparative example, the feedback circuit operates while the amplitude of the high-frequency signal input to the terminal IN is small, compared to the switch circuit 1 according to the first embodiment. Therefore, in the switch circuit according to the comparative example, the power Phd3 of third-order distortion begins to increase while the high-frequency power Pin is smaller, and the power Phd3 becomes larger, compared to the switch circuit 1 according to the first embodiment. In the switch circuit 1 according to the first embodiment, the power Phd3 begins to increase only after the high-frequency power Pin becomes large enough to activate the feedback circuit, as in the example of FIG. 7. In FIG. 9, as the power Pin further increases, the power Phd in the first embodiment is shown to be larger than that in the comparative example. However, such a power Pin is not actually used because it is large enough to destroy the switch circuit 1, for example.

[0108] As described above, in the switch circuit 1 according to the first embodiment, the feedback circuit does not operate if the parasitic bipolar transistor of each transistor M does not turn on even if a leakage current occurs in each transistor M. As a result, the switch circuit 1 according to the first embodiment can prevent a decrease in the withstand voltage of the switch circuit 1 and suppress degradation of linearity due to the influence of the feedback circuit.

[0109] [Variations] The configuration of the feedback circuit of the switch circuit 1 according to the first embodiment is not limited to that shown in FIG.

[0110] FIG. 10 is a diagram illustrating another example of the circuit configuration of the switch circuit 1 according to the first embodiment. The following description will be given in relation to transistors Tr(3,3) and Tr(3,4) associated with transistor M3, among the various transistors Tr constituting the feedback circuit described with reference to FIG. 2. FIG. 10 illustrates three examples in which the switch circuit 1 includes other transistors Tr associated with transistor M3 as components of the feedback circuit. The same description applies to the other various transistors Tr described with reference to FIG. 2.

[0111] As shown in FIG. 10(a), the switch circuit 1 may further include a transistor Tr(3,5) associated with the transistor M3 as a component of the feedback circuit.

[0112] Transistor Tr(3,5) is connected between transistor Tr(3,4) and a node connecting resistors Rds(4,1) and Rds(4,2). More specifically, the second terminal of transistor Tr(3,4) is connected to the first terminal of transistor Tr(3,5) and the gate of transistor Tr(3,5). Thus, diode-connected transistor Tr(3,5) is connected to the second terminal of transistor Tr(3,4). The second terminal of transistor Tr(3,5) is connected to the node connecting resistors Rds(4,1) and Rds(4,2).

[0113] As shown in FIG. 10(b), the switch circuit 1 may further include a transistor Tr(3,6) associated with the transistor M3 as a component of the feedback circuit.

[0114] Transistor Tr(3,6) is connected between transistor Tr(3,4) and a node connecting resistors Rds(4,1) and Rds(4,2). More specifically, the first terminal of transistor Tr(3,6) is connected to the second terminal of transistor Tr(3,4), and the gate of transistor Tr(3,6) is connected to the gate of transistor Tr(3,4). The second terminal of transistor Tr(3,6) is connected to the node connecting resistors Rds(4,1) and Rds(4,2).

[0115] As shown in FIG. 10(c), the switch circuit 1 may further include a transistor Tr(3,7) associated with the transistor M3 as a component of the feedback circuit.

[0116] Transistor Tr(3,7) is connected between transistor Tr(3,3) and transistor Tr(3,4). More specifically, the first terminal of transistor Tr(3,7) is connected to the second terminal of transistor Tr(3,3), and the gate of transistor Tr(3,7) is connected to the gate of transistor M3. The second terminal of transistor Tr(3,7) is connected to the first terminal of transistor Tr(3,4) and the gate of transistor Tr(3,4).

[0117] The above describes three examples in which three transistors Tr are connected between the body of transistor M3 and the node connecting resistors Rds(4,1) and Rds(4,2). The number of transistors Tr connected between the body and the node is not limited to three and may be, for example, four or more. In this case, the examples shown in (a), (b), and (c) of FIG. 10 may be combined as appropriate.

[0118] In this way, the number and connection relationship of the various transistors Tr connected between the body of transistor M3 and the node connecting resistors Rds(4,1) and Rds(4,2) can be changed as appropriate, taking into consideration the desired voltage difference between the body and the node when current flows from the body to the node, and / or the withstand voltage of the various transistors Tr.

[0119] Second Embodiment The switch circuit 1a according to the second embodiment will be described below. The configuration, operation, and effects of the switch circuit 1a according to the second embodiment will be described, focusing on the differences from those described for the switch circuit 1 according to the first embodiment.

[0120] The explanation given in relation to the switch circuit 1 with reference to Fig. 1 also applies to the switch circuit 1a. More specifically, the explanation given in relation to Fig. 1 applies with the switch circuit 1 replaced with the switch circuit 1a. The following explanation focuses on the switch circuit 1a.

[0121] FIG. 11 shows an example of the circuit configuration of a switch circuit 1a according to the second embodiment. The switch circuit 1a includes, for example, diodes D1, D2, D3, D4, D5, ..., D(n-2), D(n-1), and Dn, each formed of a PN junction, in addition to the components included in the switch circuit 1. The switch circuit 1a has a circuit configuration in which, in the circuit configuration of the switch circuit 1 described with reference to Fig. 2, a diode D is connected between the body and gate of each of the transistors M1, M2, M3, ..., and Mn. More specifically, this is as follows.

[0122] The anode of diode D1 is connected to the body of transistor M1, and the cathode of diode D1 is connected to the gate of transistor M1. The anode of diode D2 is connected to the body of transistor M2, and the cathode of diode D2 is connected to the gate of transistor M2. The anode of diode D3 is connected to the body of transistor M3, and the cathode of diode D3 is connected to the gate of transistor M3. The same applies to diodes D4, D5, ..., D(n-2), D(n-1), and Dn.

[0123] For example, if the voltage of the body of transistor M2 is higher than the voltage of the gate of transistor M2, current can flow from the body to the gate via diode D2. When current flows in this way, the voltage of the body drops. A similar explanation applies to the other diodes D. This current flowing through diodes D can also contribute to suppressing the rise in the bias voltage of the body of transistor M. In particular, these diodes D can operate effectively when the voltage of signal BB is equal to or higher than the voltage of signal GB.

[0124] In the above, diodes D1, D2, D3, D4, D5, . . . , D(n-2), D(n-1), and Dn, each formed of a PN junction, have been described as components of the switch circuit 1a. In the switch circuit 1a, diode-connected transistors may be used instead of the diodes D.

[0125] <Third embodiment> The switch circuit 1b according to the third embodiment will be described below. The configuration, operation, and effects of the switch circuit 1b according to the third embodiment will be described, focusing on the differences from those explained for the switch circuit 1 according to the first embodiment.

[0126] The explanation given in relation to switch circuit 1 with reference to Fig. 1 also applies to switch circuit 1b. More specifically, the explanation given in relation to Fig. 1 applies with switch circuit 1 replaced with switch circuit 1b. The following explanation focuses on switch circuit 1b.

[0127] FIG. 12 shows an example of the circuit configuration of a switch circuit 1b according to the third embodiment. The circuit configuration of the switch circuit 1b is obtained by replacing the resistor connected between the first terminal and the second terminal of each of the transistors M1, M2, M3, ..., and Mn in the circuit configuration of the switch circuit 1 described with reference to Fig. 2 with that of the transistor M as follows: The following explanation applies to each case where the integer i is 1 to n.

[0128] The resistors connected between the first and second terminals of the transistor Mi are replaced from the resistors Rds(i,1) and Rds(i,2) to resistors Rds(i,1)b, Rds(i,2)b, and Rds(i,3)b. More specifically, one terminal of the resistor Rds(i,1)b is connected to the first terminal of the transistor Mi, one terminal of the resistor Rds(i,1)b is connected to the other terminal of the resistor Rds(i,2)b, one terminal of the resistor Rds(i,3)b is connected to the other terminal of the resistor Rds(i,2)b, and the second terminal of the transistor Mi is connected to the other terminal of the resistor Rds(i,3)b.

[0129] When the integer i is any value from 1 to n, the resistance values ​​of the resistors Rds(i,1)b and Rds(i,3)b are, for example, substantially the same R2, and the resistance value of the resistor Rds(i,2)b is, for example, twice R2. Below, we will explain the case where the resistance values ​​of the resistors Rds(i,1)b and Rds(i,3)b are, for example, substantially the same R2, and the resistance value of the resistor Rds(i,2)b is twice R2, when the integer i is any value from 1 to n.

[0130] Next, differences between the connection relationships of the various transistors Tr associated with each transistor M as components of the feedback circuit and those described for the switch circuit 1 according to the first embodiment will be described.

[0131] A second terminal of the transistor Tr(1,4) associated with the transistor M1 is connected to the node connecting the resistors Rds(2,2)b and Rds(2,3)b.

[0132] With respect to the various transistors Tr associated with transistors M2, M3, . . . and M(n-1), the following statements hold for each case where the integer j is from 2 to n-1. A second terminal of the transistor Tr(j,2) is connected to the node connecting the resistors Rds(j-1,1)b and Rds(j-1,2)b. A second terminal of the transistor Tr(j,4) is connected to the node connecting the resistors Rds(j+1,2)b and Rds(j+1,3)b.

[0133] A second terminal of the transistor Tr(n,2) associated with the transistor Mn is connected to the node connecting the resistors Rds(n-1,1)b and Rds(n-1,2)b.

[0134] In the following description, reference will be made to the various voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12b, and VR23b shown in FIG.

[0135] Voltage VR12b is the voltage of the node connecting the second end of transistor Tr(2,2) with resistors Rds(1,1)b and Rds(1,2)b. Voltage VR23b is the voltage of the node connecting the second end of transistor Tr(2,4) with resistors Rds(3,2)b and Rds(3,3)b.

[0136] Fig. 13 is a diagram illustrating the operation of the switch circuit 1b according to the third embodiment when a third high-frequency signal is input to the switch circuit 1b. Fig. 13 shows exemplary waveforms of the voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12b, and VR23b when a third high-frequency signal is input to the terminal IN. The horizontal axis represents time. The vertical axis represents voltage values.

[0137] When a third high-frequency signal is input to terminal IN, the voltage signal applied between the first and second terminals of each transistor M becomes a high-frequency signal with an amplitude of 4 V, as in the example of FIG. 7. As in the example of FIG. 7, the L-level voltage of signal GB is −3 V, and the voltage of signal BB is also −3 V. In this case, the waveforms of voltages VM01, VM12, VM23, VM34, VG2, and VB2 are the same as in the example of FIG. 7.

[0138] The signal of voltage VR12b is a high-frequency signal with an amplitude of 7 V. This is based on voltage division by resistors Rds(1,1)b and Rds(1,2)b and Rds(1,3)b. Similarly, the signal of voltage VR23b is a high-frequency signal with an amplitude of 3 V. The signal of voltage VR12b is substantially in phase with the signal of voltage VM12, and the signal of voltage VR23b is substantially in antiphase with the signal of voltage VM12.

[0139] The following describes times T30 and T31. Time T30 is the time when the value of voltage VM12 reaches a maximum. Time T31 is the time when the value of voltage VM12 reaches a minimum.

[0140] At time T30, similar to time T20 in the example of Figure 7, voltages VB2 and VG2 are -1 V, but voltage VR23b is -3 V, which is lower than the -2 V of voltage VR23 at time T20 in the example of Figure 7. At this time, similar to time T20 in the example of Figure 7, current flows out of the body of transistor M2 via transistors Tr(2,3) and Tr(2,4), but the voltage at the source of transistor Tr(2,4) is lower than at time T20 in the example of Figure 7.

[0141] At time T31, similar to time T21 in the example of Figure 7, voltages VB2 and VG2 are -5 V, but voltage VR12b is -7 V, which is lower than the -6 V of voltage VR12 at time T21 in the example of Figure 7. At this time, similar to time T21 in the example of Figure 7, current flows out of the body of transistor M2 via transistors Tr(2,1) and Tr(2,2), but the voltage at the source of transistor Tr(2,2) is lower than at time T21 in the example of Figure 7.

[0142] The fact that the voltages at the sources of transistors Tr(2,2) and Tr(2,4) are lower in this manner means that, in the switch circuit 1c of the example of FIG. 12, the feedback circuit can operate even if the amplitude of the high-frequency signal input to terminal IN is smaller than in the switch circuit 1 of the example of FIG. 2.

[0143] In the above example, the resistance between the first terminal of transistor M1 and the second terminal of transistor Tr(2,2) is R2, and the resistance between the second terminal of transistor Tr(2,2) and the second terminal of transistor M1 is three times R2. However, this embodiment is not limited to this example. The ratio of the resistance between the first terminal of transistor M1 and the second terminal of transistor Tr(2,2) to the resistance between the second terminal of transistor Tr(2,2) and the second terminal of transistor M1 may be different. For example, the resistance between the first terminal of transistor M1 and the second terminal of transistor Tr(2,2) is between 1 / 3 and 3 times the resistance between the second terminal of transistor Tr(2,2) and the second terminal of transistor M1. The same applies to the other transistors Tr(1,4), Tr(2,4), Tr(3,2), Tr(3,4), Tr(n-1,2), Tr(n-1,4), and Tr(n,2).

[0144] In this way, the switch circuit 1c according to the third embodiment makes it possible to adjust the magnitude of the high frequency power associated with the high frequency signal input to the terminal IN at which the feedback circuit starts to operate.

[0145] <Fourth embodiment> The switch circuit 1c according to the fourth embodiment will be described below. The configuration, operation, and effects of the switch circuit 1c according to the fourth embodiment will be described, focusing on the differences from those explained for the switch circuit 1 according to the first embodiment.

[0146] The explanation given in relation to switch circuit 1 with reference to Fig. 1 also applies to switch circuit 1c. More specifically, the explanation given in relation to Fig. 1 applies with switch circuit 1 replaced with switch circuit 1c. The following explanation focuses on switch circuit 1c.

[0147] FIG. 14 shows an example of the circuit configuration of a switch circuit 1c according to the fourth embodiment. The switch circuit 1c further includes transistors Tr(1,1), Tr(1,2), Tr(n,3), and Tr(n,4) as components of the feedback circuit in addition to the configuration included in the switch circuit 1. The switch circuit 1c has a circuit configuration in which the transistors Tr(1,1), Tr(1,2), Tr(n,3), and Tr(n,4) in the circuit configuration of the switch circuit 1 described with reference to FIG. 2 are connected as follows:

[0148] The transistors Tr(1,1) and Tr(1,2) correspond to the transistor M1.

[0149] A first terminal of transistor Tr(1,1) is connected to the body of transistor M1, and a gate of transistor Tr(1,1) is connected to the gate of transistor M1. A second terminal of transistor Tr(1,1) is connected to a first terminal of transistor Tr(1,2) and the gate of transistor Tr(1,2). Thus, a diode-connected transistor Tr(1,2) is connected to a second terminal of transistor Tr(1,1). A second terminal of transistor Tr(1,2) is connected to a node connecting resistors Rds(2,1) and Rds(2,2).

[0150] The transistors Tr(n,3) and Tr(n,4) are associated with the transistor Mn.

[0151] The first terminal of transistor Tr(n,3) is connected to the body of transistor Mn, and the gate of transistor Tr(n,3) is connected to the gate of transistor Mn. The second terminal of transistor Tr(n,3) is connected to the first terminal of transistor Tr(n,4) and the gate of transistor Tr(n,4). Thus, the diode-connected transistor Tr(n,4) is connected to the second terminal of transistor Tr(n,3). The second terminal of transistor Tr(n,4) is connected to the node connecting resistors Rds(n-1,1) and Rds(n-1,2).

[0152] As described with reference to FIG. 2, current can flow from the body of transistor M1 via transistors Tr(1,1) and Tr(1,2). This current can also contribute to suppressing an increase in the bias voltage of the body of transistor M1 due to leakage current Ib generated in transistor M1. Similarly, current can flow from the body of transistor Mn via transistors Tr(n,3) and Tr(n,4). This current can also contribute to suppressing an increase in the bias voltage of the body of transistor Mn due to leakage current Ib generated in transistor Mn.

[0153] Fifth Embodiment A switch circuit 1d according to the fifth embodiment will be described below. The configuration, operation, and effects of the switch circuit 1d according to the fifth embodiment will be described, focusing on the differences from those described for the switch circuit 1a according to the second embodiment.

[0154] The explanation given in relation to switch circuit 1 with reference to Fig. 1 also applies to switch circuit 1d. More specifically, the explanation given in relation to Fig. 1 applies with switch circuit 1 replaced with switch circuit 1d. The following explanation focuses on switch circuit 1d.

[0155] FIG. 15 shows an example of the circuit configuration of a switch circuit 1d according to the fifth embodiment. The switch circuit 1d has a circuit configuration in which the resistors Rb1, Rb2, Rb3, Rb4, . . . , Rb(n-2), Rb(n-1), and Rbn are omitted from the configuration of the switch circuit 1a. More specifically, this is as follows.

[0156] No polysilicon resistor is provided between the body of transistor M1 and the body of transistor M2. No polysilicon resistor is provided between the body of transistor M2 and the body of transistor M3. No polysilicon resistor is provided between the body of transistor M3 and the body of transistor M4. The same applies to the body of transistor M4 and the body of transistor M5, ..., between the body of transistor M(n-2) and the body of transistor M(n-1), and between the body of transistor M(n-1) and the body of transistor Mn. Furthermore, signal BB is not input to switch circuit 1d.

[0157] As such, the switch circuit 1d does not include any resistors or terminals for applying voltage to the body of the transistor from the outside, which reduces parasitic capacitance and insertion loss that occurs when a signal passes through the switch circuit 1d in the on state.

[0158] Sixth Embodiment The switch circuit 1e according to the sixth embodiment will be described below. The configuration, operation, and effects of the switch circuit 1e according to the sixth embodiment will be described, focusing on the differences from those of the switch circuit 1d according to the fifth embodiment.

[0159] The explanation given in relation to the switch circuit 1 with reference to Fig. 1 also applies to the switch circuit 1e. More specifically, the explanation given in relation to Fig. 1 applies with the switch circuit 1 replaced with the switch circuit 1e. The following explanation focuses on the switch circuit 1e.

[0160] FIG. 16 shows an example of the circuit configuration of a switch circuit 1e according to the sixth embodiment. The switch circuit 1e has a configuration in which a resistor Rcont is further included in the configuration included in the switch circuit 1d, and the connections of the resistors Rg1, Rg2, Rg3, Rg4, Rg5, . . . , Rg(n-2), Rg(n-1), and Rgn are changed. More specifically, the configuration is as follows.

[0161] One end of resistor Rg1 is connected to the gate of transistor M1. The other end of resistor Rg1 is connected to one end of resistor Rcont. One end of resistor Rg2 is connected to the gate of transistor M2. The other end of resistor Rg2 is connected to one end of resistor Rcont. One end of resistor Rg3 is connected to the gate of transistor M3. The other end of resistor Rg3 is connected to one end of resistor Rcont. The same applies to the connection relationships of resistors Rg4, Rg5, ..., Rg(n-1), and Rgn. The other end of resistor Rcont is connected to a node to which signal GB is input. Figure 16 shows the control terminal to which signal GB is input to switch circuit 1e.

[0162] Even if the connections of the resistors Rg1, Rg2, Rg3, ..., Rg(n-1), and Rgn are changed in this way, the switch circuit 1e according to the sixth embodiment can suppress insertion loss, similar to the switch circuit 1d according to the fifth embodiment.

[0163] <Other embodiments> In this specification, the term "connection" refers to an electrical connection, and does not exclude the use of another element therebetween. Furthermore, in this specification, the term "resistance" may refer to a resistive element or a parasitic resistance.

[0164] In this specification, expressions such as "identical," "matched," "constant," and "maintained" are intended to include cases where there is a design error when implementing the technology described in the embodiments. The same applies when the term "substantially" is used in combination with these expressions, such as "substantially identical." Furthermore, expressions such as "applying or supplying a certain voltage" are intended to include both controlling the application or supply of the voltage and actually applying or supplying the voltage. Furthermore, applying or supplying a certain voltage may include, for example, applying or supplying a voltage of 0 V.

[0165] Although several embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0166] 1, 1a, 1b, 1c, 1d, 1e, 2, 3, 4...switch circuit, 5, 6...signal processing circuit, 7...control circuit, WD...radio device, ANT...antenna, M, Tr...transistor, Rg, Rb, Rds...resistor, D...diode, SB...semiconductor substrate, BOX...oxide film, BD...body layer, DR...drain region, SR...source region, G...gate electrode, GI...gate insulator.

Claims

1. A semiconductor device comprising an input terminal, an output terminal, and a plurality of transistors connected in series between the input terminal and the output terminal, The plurality of transistors include: a first transistor having a first end and a second end used in the series connection; a second transistor having a third end and a fourth end, a first gate, and a first body used in the series connection, the third end being connected to the second end; Equipped with The semiconductor device further comprises: a third transistor and a first diode connected in series between the first body and the first end; the third transistor has a second gate connected to the first gate; an anode of the first diode is provided on the first body side of the first body and the first end, and a cathode of the first diode is provided on the first end side of the first body and the first end; Semiconductor device.

2. further comprising a first resistor and a second resistor connected in series between the first end and the second end; the third transistor and the first diode are connected in series between the first body and a node connecting the first resistor and the second resistor; The semiconductor device according to claim 1 .

3. a fourth transistor is used as the first diode; the third transistor has a fifth terminal connected to the first body and a sixth terminal; the fourth transistor has a seventh terminal connected to the sixth terminal, an eighth terminal connected to a node connecting the first resistor and the second resistor, and a third gate connected to the seventh terminal. The semiconductor device according to claim 2 .

4. The plurality of transistors further comprises: a fifth transistor having a ninth terminal and a tenth terminal used in the series connection, the ninth terminal being connected to the fourth terminal; The semiconductor device further comprises: a sixth transistor and a second diode connected in series between the first body and the tenth terminal; the sixth transistor has a fourth gate connected to the first gate; an anode of the second diode is provided on the first body side of the first body and the tenth end, and a cathode of the second diode is provided on the tenth end side of the first body and the tenth end; The semiconductor device according to claim 1 .

5. The plurality of transistors further comprises: a fourth transistor having a fifth terminal and a sixth terminal used in the series connection, the fifth terminal being connected to the fourth terminal; The semiconductor device further comprises: a fifth transistor and a second diode connected in series between the first body and the sixth end; the fifth transistor has a third gate connected to the first gate; an anode of the second diode is provided on the first body side of the first body and the sixth end, and a cathode of the second diode is provided on the sixth end side of the first body and the sixth end, The semiconductor device further comprises: a third resistor and a fourth resistor connected in series between the fifth terminal and the sixth terminal; the fifth transistor and the second diode are connected in series between the first body and a node connecting the third resistor and the fourth resistor; one end of the first resistor is connected to the first end, one end of the second resistor is connected to the other end of the first resistor, and the second end is connected to the other end of the second resistor; one end of the third resistor is connected to the fifth end, one end of the fourth resistor is connected to the other end of the third resistor, and the sixth end is connected to the other end of the fourth resistor; the first resistor and the fourth resistor have the same resistance value, and the second resistor and the third resistor have the same resistance value; The semiconductor device according to claim 2 .

6. further comprising a fifth transistor and a second diode connected in series between the first body and the first end; the fifth transistor and the second diode are connected between the first body and the first end in parallel with the third transistor and the first diode; the fifth transistor has a fourth gate connected to the first gate; an anode of the second diode is provided on the first body side of the first body and the first end, and a cathode of the second diode is provided on the first end side of the first body and the first end; The semiconductor device according to claim 1 .

7. The semiconductor device according to claim 1 , further comprising one or more diodes connected in series with the third transistor and the first diode between the first body and the first end.

8. The semiconductor device according to claim 1 , further comprising a third diode having an anode connected to said first body and a cathode connected to said first gate.

9. further comprising a first resistor and a second resistor connected in series between the first end and the second end, a third resistor and a fourth resistor connected in series between the third end and the fourth end, and a fifth resistor and a sixth resistor connected in series between the ninth end and the tenth end; the third transistor and the first diode are connected in series between the first body and a node connecting the first resistor and the second resistor; the sixth transistor and the second diode are connected in series between the first body and a node connecting the fifth resistor and the sixth resistor; The semiconductor device according to claim 4 .

10. the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor have the same resistance value; The semiconductor device according to claim 9 .

11. the first transistor further has a fifth gate and a second body; the semiconductor device further includes a seventh transistor and a third diode connected in series between the second body and a node connecting the third resistor and the fourth resistor; the seventh transistor has a sixth gate connected to the fifth gate; an anode of the third diode is provided on the second body side of a node connecting the second body to the third resistor and the fourth resistor, and a cathode of the third diode is provided on the node connecting the third resistor and the fourth resistor of a node connecting the second body to the third resistor and the fourth resistor. The semiconductor device according to claim 9 .

12. the fifth transistor further has a seventh gate and a third body; the semiconductor device further includes an eighth transistor and a fourth diode connected in series between the third body and a node connecting the third resistor and the fourth resistor; the eighth transistor has an eighth gate connected to the seventh gate; an anode of the fourth diode is provided on the third body side of a node connecting the third body to the third resistor and the fourth resistor, and a cathode of the fourth diode is provided on the node connecting the third body to the third resistor and the fourth resistor, The semiconductor device according to claim 9 .

13. the first transistor has a second body; 11. The semiconductor device according to claim 1, further comprising a seventh resistor made of polysilicon and connecting said first body and said second body.

14. the first transistor has a second body; 11. The semiconductor device according to claim 1, wherein a resistor using polysilicon connecting said first body and said second body is not provided.

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