Semiconductor Devices

Abstract

To provide a semiconductor device which can suppress an erroneous operation of a level shift element due to surge voltage in an HVIC.SOLUTION: A semiconductor device comprises: a first conductive type substrate 1; a second conductive type well region 12 which is provided on the substrate 1 and is formed with a high potential side circuit; a second conductive type breakdown voltage region 2 which is provided so as to surround the well region 12; a level shift element 10a which has a second conductive type drift region 6a provided on the substrate 1, a second conductive type carrier reception region 7a provided on the upper part of the drift region 6a, a first conductive type base region 3 provided so as to be in contact with the drift region 6a, a first gate electrode 9a provided on the base region 3 and a second conductive type carrier supply region 8a provided on the upper part of the base region 3; a first conductive type isolation region 5a which is provided between the breakdown voltage region 2 and the drift region 6a on the substrate 1; and a second gate electrode 16a which is provided on the isolation region 5a.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A typical high-voltage integrated circuit (HVIC) has an n-type well region on a p-type semiconductor substrate. The n-type well region contains a high-side circuit region (high-side circuit region) where the high-side circuit is formed, and the p-type region surrounding the n-type well region contains a low-side circuit region (low-side circuit region) where the low-side circuit is formed. A high-voltage diode called a high-voltage junction termination (HVJT) is formed between the n-type well region and the p-type region, allowing normal operation even if the voltage in the high-side circuit region is several hundred volts higher than the voltage in the low-side circuit region.

[0003] Typically, a p-type well region is formed above the n-type well region in the high-side circuit area. The VS potential, which is the reference potential of the high-side circuit, is applied to the p-type well region, and the VB potential, which is the power supply potential of the high-side circuit, is applied to the n-type well region.

[0004] Furthermore, a level shift element is required to transmit signals from the low-side circuit to the high-side circuit. The level shift element is generally composed of a high-voltage n-channel MOSFET with a drain region provided in the high-side circuit region and a gate electrode and source region provided in the low-side circuit region. The drain potential (Dr potential) of the level shift element is connected to the VB potential via a level shift resistor. When the gate of the level shift element is off, the Dr potential of the level shift element is higher than the VS potential and approximately equal to the VB potential (VB potential ≒ Dr potential > VS potential). On the other hand, when the gate of the level shift element is on, the Dr potential of the level shift element is lower than the VB potential and approximately equal to the VS potential (VB potential > Dr potential ≒ VS potential).

[0005] In a configuration known as the self-shielding (SS) method, the level shift element is formed using part of the HVJT. The high-side circuit area contains an n-type well region fixed at the VB potential, a p-type well region fixed at the VS potential, and an n-type drift region fixed at the Dr potential of the level shift element. Therefore, it is necessary to separate the n-type well region and the n-type drift region, and a slit-shaped p-type isolation region is used for this separation. If an inversion layer is formed in this p-type isolation region due to surface charges, etc., the VB potential and the Dr potential will be shorted, preventing correct signal transmission when the gate of the level shift element is turned on.

[0006] Therefore, it is known to provide a shield layer above the p-type isolation region to prevent the formation of an inversion layer in the p-type isolation region (see Patent Documents 1 and 2). Patent Document 1 discloses a configuration in which the shield layer is fixed to the Dr potential of the level shift element. Patent Document 2 discloses a configuration in which the shield layer is fixed to the VS potential. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 3917211 specification [Patent Document 2] Patent No. 5733416 specification Summary of the Invention [Problem to be solved by the invention]

[0008] In a conventional HVIC, for example, when a negative voltage surge is applied to the n-type well region of the high-side circuit area, the Dr potential of the level shift element temporarily increases, exceeds the VB potential, and then decreases toward the VS potential. If the Dr potential decreases significantly, the Dr potential may become approximately equal to the VS potential (Dr potential ≒ VS potential) even though the gate of the level shift element is not turned on, which may result in erroneous inversion of the output of the level shift element.

[0009] In view of the above problems, an object of the present invention is to provide a semiconductor device in an HVIC that can suppress malfunction of a level shift element due to a surge voltage. [Means for solving the problem]

[0010] One aspect of the present invention is summarized as a semiconductor device including: (a) a substrate of a first conductivity type; (b) a well region of a second conductivity type provided on the substrate and in which a high-potential side circuit is formed; (c) a breakdown voltage region of the second conductivity type provided so as to surround the periphery of the well region and having a lower impurity concentration than the well region; (d) a drift region of the second conductivity type provided on the substrate; a carrier receiving region of the second conductivity type provided above the drift region and having a higher impurity concentration than the drift region; a base region of the first conductivity type provided in contact with the drift region; a first gate electrode provided on and insulated from the base region; and a carrier supply region of the second conductivity type provided on and insulated from the base region; (e) a separation region of the first conductivity type provided between the breakdown voltage region and the drift region on the substrate; and (f) a second gate electrode provided on and insulated from the separation region and to which a first potential or a second potential higher than the first potential is alternatively applied. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a semiconductor device that can suppress malfunction of a level shift element due to a surge voltage in an HVIC. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA′ in FIG. 2. [Figure 4] 3 is another cross-sectional view taken along the line AA′ in FIG. 2. FIG. [Figure 5]10 is a graph showing a simulation result of the Dr-VS voltage when the VB-GND voltage is applied. [Figure 6] 2 is a circuit diagram of a switching circuit of the semiconductor device according to the first embodiment. FIG. [Figure 7] 4 is a timing chart of the operation of the switching circuit of the semiconductor device according to the first embodiment. [Figure 8] 10 is a graph showing a change in Dr-VS voltage in the semiconductor device according to the first embodiment. [Figure 9] FIG. 2 is a cross-sectional view of a semiconductor device according to a first comparative example. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to a second comparative example. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, first to third embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to third embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0014] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In static induction (SI) thyristors and gate turn-off (GTO) thyristors, the anode region serves as the carrier supply region. The term "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT. In SI thyristors and GTO thyristors, the cathode region functions as the carrier receiving region.

[0015] Furthermore, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are inverted and read as such.

[0016] In this specification, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be reversed, with the first conductivity type being n-type and the second conductivity type being p-type. The "+" and "-" affixed to "n" and "p" indicate a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the "+" and "-" affixed. However, semiconductor regions with the same "n" and "n" affixed do not necessarily have the same impurity concentration. Furthermore, in the following description, components and regions with the "first conductivity type" and "second conductivity type" affixed refer to components and regions made of semiconductor materials, even if not otherwise explicitly stated.

[0017] (First embodiment) 1, the semiconductor device according to the first embodiment is an HVIC 100 that drives a power conversion unit 200, which is one phase of a bridge circuit for power conversion, for example. The power conversion unit 200 includes a high-side switching element T21 and a low-side switching element T22. potentialThe high-potential side switching element T21 and the low-potential side switching element T22 are connected in series to form a half-bridge circuit. potential The high-side switching element T21 and the low-side switching element T22 are exemplified by a metal oxide semiconductor field effect transistor (MOSFET). potential The switching element T22 may be another power switching element such as an IGBT.

[0018] The drain of the high-potential side switching element T21 is connected to the high-potential side HV potential, and potential The source of the high-side switching element T21 is connected to the ground potential (GND potential) on the low-side. potential The connection point 106 of the drain of the side switching element T22 is connected to the VS potential on the negative side of the high potential side power supply (high potential side power supply) 105 and a load (not shown) such as a motor, and the VS potential is supplied to the load via the connection point 106.

[0019] The HVIC 100 applies a drive signal to the gate of the high potential side switching element T21 to turn the gate of the high potential side switching element T21 on and off in response to an input signal IN from an external microcomputer, etc. The HVIC 100 includes a low potential side circuit (low side circuit) 101, a level shift circuit 103, and a high potential side circuit (high side circuit) 102.

[0020] The low-side circuit 101 is connected to a VCC potential, which is the positive side of a low-potential power supply (low-potential power supply) 104, and a GND potential, which is the negative side. The low-side circuit 101 operates with the GND potential as its reference potential and the VCC potential, which is higher than the GND potential, as its power supply potential. The low-side circuit 101 generates an on / off signal with the GND potential as its reference in response to an input signal IN from an external microcomputer or the like, and outputs the signal to the level shift circuit 103.

[0021] The level shift circuit 103 converts the on / off signal based on the GND potential from the low-side circuit 101 into an on / off signal based on the VS potential. The level shift circuit 103 includes level shift elements T11 and T12 and level shift resistors R1 and R2. The level shift elements T11 and T12 are configured, for example, with n-channel MOSFETs. The gates of the level shift elements T11 and T12 are connected to the low-side circuit 101, and the sources of the level shift elements T11 and T12 are connected to the GND potential. The drain of the level shift element T11 is connected to the high-side circuit 102 and one end of the level shift resistor R1. The other end of the level shift resistor R1 is connected to the VB potential. The drain of the level shift element T12 is connected to the high-side circuit 102 and one end of the level shift resistor R2. The other end of the level shift resistor R2 is connected to the VB potential. 。 Cathode of protection diode D1 is at VB potential The anode of the protection diode D1 is connected to the GND potential.

[0022] High-side circuit 102 operates using the VS potential as a reference potential and a VB potential higher than VS as a power supply potential. High-side circuit 102 outputs a drive signal to the gate of high-side switching element T21 in response to an on / off signal from level shift circuit 103, thereby driving the gate of high-side switching element T21. High-side circuit 102 includes, for example, a CMOS circuit of n-channel MOSFET and p-channel MOSFET in its output stage.

[0023] The VB potential is the highest potential applied to the HVIC100, and in a normal state where there is no noise, it is maintained about 15 V higher than the VS potential. potential The VS potential repeatedly rises and falls between the HV potential on the high potential side (for example, about 400 V to 600 V) and the GND potential on the low potential side, fluctuating between 0 V and several hundred V. Note that the VS potential may also become negative.

[0024] FIG. 2 shows the planar layout of the HVIC 100. The HVIC 100 is a first conductivity type (p - The high-side circuit area 12 is provided on a substrate (semiconductor chip) 1 of the semiconductor device type. - The mold substrate 1 is made of, for example, a silicon (Si) substrate. The substrate 1 may be made of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or diamond. The substrate 1 may also be made of a p - The semiconductor layer may be made of an epitaxial layer of the same material.

[0025] The high-side circuit region 12 corresponds to the high-side circuit 102 shown in FIG. 1. As shown in FIG. 2, the high-side circuit region 12 has a substantially rectangular planar pattern. The high-side circuit region 12 is composed of a well region of a second conductivity type (n-type). A VB potential is applied to the high-side circuit region 12. A p-type well region 13 is provided above the high-side circuit region 12. A VS potential is applied to the well region 13. In FIG. 2, various elements included in the high-side circuit region 12 and the well region 13 are not shown.

[0026] A voltage-resistant region 2 configured with a high voltage junction termination (HVJT) is provided in a ring shape so as to surround the periphery of the high side circuit region 12. Inner circumference The high-side circuit region 12 on the side of the withstand voltage region 2 is electrically separated from the low-potential side circuit region (low-side circuit region) formed on the substrate 1 on the outer periphery of the withstand voltage region 2. The low-side circuit region formed on the substrate 1 corresponds to the low-side circuit 101 in FIG. 1. In FIG. 2, various elements included in the low-side circuit region are not shown. + The contact regions 11a and 11b are provided in a C-shape or a U-shape. A VB potential is applied to the contact regions 11a and 11b.

[0027] A p-type base region 3 is provided in an annular shape so as to surround the periphery of the voltage-resistant region 2. The voltage-resistant region 2 forms a high-voltage diode through a pn junction with the base region 3. The high-voltage diode corresponds to the protection diode D1 shown in FIG. 1. The p-type base region 3 is provided in an annular shape so as to surround the periphery of the base region 3 and is in contact with the base region 3. + A base contact region 4 is provided in a ring shape. A GND potential is applied to the base contact region 4. The outer periphery of the base contact region 4 is surrounded by the base body 1.

[0028] Level shift elements 10a and 10b are each provided in a part of the withstand voltage region 2. The locations of the level shift elements 10a and 10b are not particularly limited as long as they are provided in a part of the withstand voltage region 2. The level shift elements 10a and 10b correspond to the level shift elements T11 and T12 shown in FIG. 1. The level shift elements 10a and 10b are configured by high-voltage n-channel MOSFETs.

[0029] The level shift elements 10a and 10b are slit-shaped p - The level shift element 10a is formed in the SS type surrounded by isolation regions (slit regions) 5a and 5b. - The isolation region 5a is formed in a C-shape or U-shape around the level shift element 10a. character The edge of the isolation region 5a is in contact with the base region 3. The level shift element 10a is - Drift region 6a,n of type + Mold carrier receiving regions (drain regions) 7a, n +The high-side transistor 12 includes a carrier supply region (source region) 8a and a control electrode (gate electrode) 9a. The drift region 6a is formed from a part of the voltage-withstanding region 2 and is electrically isolated from the voltage-withstanding region 2 by the isolation region 5a. The drain region 7a, the source region 8a, and the gate electrode 9a have, for example, linear planar shapes extending parallel to each other. The drain region 7a is connected to the high-side circuit region 12 via a level shift resistor R1. A gate electrode 16a is provided on a part of the isolation region 5a extending parallel to the drain region 7a. The gate electrode 16a has a linear planar shape extending parallel to the drain region 7a.

[0030] The level shift element 10b is surrounded by p - The level shift element 10b has an n-type isolation region 5b. The isolation region 5b surrounds the level shift element 10b in a C- or U-shape, and an end of the isolation region 5b contacts the base region 3. The level shift element 10b has an n-type isolation region 5b. - Drift region 6b, n + n-type drain region 7b + The high-side circuit region 12 includes a source region 8b and a gate electrode 9b. The drift region 6b is formed from a part of the voltage-withstanding region 2 and is electrically isolated from the voltage-withstanding region 2 by the isolation region 5b. The drain region 7b, the source region 8b, and the gate electrode 9b have, for example, linear planar shapes extending parallel to each other. The drain region 7b is connected to the high-side circuit region 12 via a level shift resistor R2. A gate electrode 16b is provided on a part of the isolation region 5b extending parallel to the drain region 7b. The gate electrode 16b has a linear planar shape extending parallel to the drain region 7b.

[0031] In the following explanation, we will focus on one of the two level shift elements 10a, 10b, the level shift element 10a and its surrounding area including the gate electrode 16a, but the configuration of the other level shift element 10b and its surrounding area including the gate electrode 16b also has a similar configuration to that of the level shift element 10a and its surrounding area including the gate electrode 16a.

[0032] 3 is a cross-sectional view taken along line AA′ passing through the level shift element 10a in FIG. 2. As shown in FIG. - An n-type high-side circuit region 12 is provided on the upper portion of the substrate 1. An n-type high-side circuit region 12 having a higher impurity concentration than the high-side circuit region 12 is provided on the upper portion of the substrate 1. + A mold contact region 14 is provided. The contact region 14 is not shown in Fig. 2. The level shift resistor R1 and the VB potential on the positive side of the high potential side power supply 105 are connected to the contact region 14.

[0033] A p-type well region 13 is provided above the high-side circuit region 12, spaced apart from the contact region 14. Above the well region 13, a p-type well region 13 having a higher impurity concentration than the well region 13 is provided. + A contact region 15 is provided on the semiconductor device 10. The contact region 15 is not shown in Fig. 2. The contact region 15 is connected to the VS potential on the negative side of the high-potential power supply 105 and the anode of the protection diode D2.

[0034] p - The upper portion of the mold substrate 1 is in contact with the high side circuit region 12 and has an n-type impurity layer with a lower impurity concentration than the high side circuit region 12. - A pressure-resistant region 2 of the mold is provided. - The upper part of the mold substrate 1 is in contact with the pressure-resistant region 2, and p - A mold separation region 5a is provided.

[0035] p - A level shift element 10a is provided on the upper portion of the mold substrate 1 and is electrically isolated from the high-side circuit region 12 by an isolation region 5a. - The upper part of the mold substrate 1 is in contact with the separation region 5a. - The drift region 6a is selectively provided with an n-type impurity layer. The isolation region 5a electrically isolates the voltage-resistant region 2 from the drift region 6a. An n-type impurity layer having a higher impurity concentration than the drift region 6a is provided above the drift region 6a. +The drain region 7a is connected to a level shift resistor R1 and the cathode of a protection diode D2.

[0036] p - A p-type base region 3 having a higher impurity concentration than the base 1 is selectively provided on the upper part of the base 1 in contact with the drift region 6a. + A p-type source region 8a is selectively provided above the base region 3. A p-type source region 8a is provided above the base region 3 and is in contact with the source region 8a. The p-type source region 8a has a higher impurity concentration than the base region 3. + A base contact region 4 is selectively provided. The source region 8a and the base contact region 4 are connected to the GND potential.

[0037] A gate electrode 9a is provided on the base region 3, extending from above the source region 8a to above the drift region 6a, and is insulated via a gate insulating film 17. The gate insulating film 17 can be formed of various insulating films, such as a silicon oxide film (SiO2 film) or a silicon nitride film (Si3N4 film) other than SiO2 film, or a stacked film of insulating films including SiO2 film, Si3N4 film, etc. The gate electrode 9a is formed of, for example, a polycrystalline silicon film (doped polysilicon) into which impurities have been introduced, a refractory metal, or a silicide of a refractory metal. The gate electrode 9a controls the surface potential of the base region 3 and thus the flow of the main current between the source region 8a and the drain region 7a.

[0038] When the gate of the level shift element 10a is turned off, the drain potential (Dr potential) of the drain region 7a of the level shift element 10a is higher than the VS potential and substantially equal to the VB potential (VB potential ≈ Dr potential > VS potential). On the other hand, when the gate of the level shift element 10a is turned on, the Dr potential of the level shift element 10a is lower than the VB potential and substantially equal to the VS potential (VB potential > Dr potential ≈ VS potential).

[0039] A gate electrode (shield layer) 16a is provided on the isolation region 5a, extending from above the breakdown voltage region 2 to above the drift region 6a, and is insulated via a gate insulating film 18. The gate insulating film 18 may be made of the same material as the gate insulating film 17 below the gate electrode 9a, or may be made of a different material. The gate electrode 16a is made of, for example, a polycrystalline silicon film (doped polysilicon) into which impurities have been introduced, a refractory metal, or a silicide of a refractory metal. The gate electrode 16a may be made of a metal such as aluminum (Al), or may be made of another conductive material. The gate electrode 16a may be made of the same material as the gate electrode 9a, or may be made of a different material.

[0040] A switching circuit S1 is connected to the gate electrode 16a. The potential of the gate electrode 16a can be switched by the switching circuit S1 alternatively between a VS potential (first potential) on the negative side of the high-potential power supply 105 and a VB potential (second potential) on the positive side of the high-potential power supply 105. That is, an n-channel MOSFET 10 is configured with the drain region 7a as a source region, the isolation region 5a as a base region, the contact region 14 as a drain region, and the voltage-resistant region 2 and the high-side circuit region 12 as drift regions, and the gate electrode 16a functions as the gate electrode of the n-channel MOSFET 10. The gate electrode 16a controls the surface potential of the isolation region 5a, and thereby controls the flow of a main current flowing between the source region, which is the drain region 7a of the level shift element 10a, and the drain region, which is the contact region 14.

[0041] By switching the potential of the gate electrode 16a between the VB potential and the VS potential, the n-channel MOSFET 10 can be turned on and off at any timing. As shown in Fig. 3, when the potential of the gate electrode 16a is fixed to the VS potential, the n-channel MOSFET is in the off state, and the VB potential and the Dr potential are connected only by the level shift resistor R1. On the other hand, as shown in Fig. 4, when the connection destination of the gate electrode 16a is switched by the switching circuit S1 and the potential of the gate electrode 16a is fixed to the VB potential, the n-channel MOSFET is in the on state, and the VB potential and the Dr potential are short-circuited.

[0042] During normal operation, when the Dr potential of the level shift element 10a is always equal to or lower than the VB potential (Dr potential≦VB potential), the switching circuit S1 is controlled to fix the potential of the gate electrode 16a to the VS potential. In this case, the n-channel MOSFET is turned off, and the gate electrode 16a functions as a shield (field plate) that prevents an inversion layer from being formed in the isolation region 5a due to surface charges or the like. This prevents the VB potential and the Dr potential from being shorted, thereby preventing malfunction of the level shift element 10a.

[0043] On the other hand, during abnormal operation under specific conditions other than normal operation, the switching circuit S1 detects the abnormal operation and is controlled to temporarily fix the potential of the gate electrode 16a to the VB potential. For example, the switching circuit S1 detects the Dr potential of the level shift element 10a, and when the detected Dr potential of the level shift element 10a becomes higher than the VB potential, the switching circuit S1 is controlled to temporarily fix the potential of the gate electrode 16a to the VB potential. In this case, the n-channel MOSFET is turned on, shorting the VB potential and the Dr potential, thereby preventing malfunction of the level shift element 10a.

[0044] It is known that, as an abnormal operation, for example, when a negative voltage surge is applied to the high-side circuit region 12, the high-voltage diode formed by the pn junction of the voltage-resistant region 2 and the base region 3 is forward biased, and the Dr potential of the level shift element 10a temporarily increases, exceeds the VB potential, and then begins to decrease and approaches the VS potential.

[0045] FIG. 5 shows the potential of the gate electrode 16a. rank The following shows the simulation results when a negative voltage surge is applied when the voltage is fixed. The VB-GND voltage (thick solid line) is temporarily biased negative from +15V and then returned to the original +15V. At this time, the Dr-VS voltage (thin solid line) exceeds the VB potential while the VB-GND voltage is negative, and then drops. If the drop in Dr potential is large, the Dr potential will become approximately the same potential as the VS potential (Dr potential ≈ VS potential) even though the level shift element 10a is not turned on, which may result in erroneous inversion of the output of the level shift element 10a.

[0046] In response to such an abnormal operation mode, the semiconductor device according to the first embodiment detects the abnormal operation using the switching circuit S1, switches the connection destination of the gate electrode 16a to the VB potential, and turns on the n-channel MOSFET 10, thereby shorting the Dr potential to the VB potential and suppressing a drop in the Dr potential. For example, the n-channel MOSFET 10 is temporarily turned on when the Dr potential, which is equal to or lower than the VB potential during normal operation, exceeds the VB potential during abnormal operation.

[0047] Fig. 6 shows an example of the configuration of the switching circuit S1. As shown in Fig. 6, the switching circuit S1 includes, for example, a pnp transistor 31, a resistor 32, a comparator 33, a delay circuit 34, and a latch circuit 35. The emitter of the pnp transistor 31 is connected to the Dr potential. The base of the pnp transistor 31 is connected to the VB potential. The collector of the pnp transistor 31 is connected to the VS potential via a resistor 32.

[0048] A non-inverting input terminal of a comparator 33 is connected to a connection point 30 between the collector of the pnp transistor 31 and the resistor 32. The inverting input terminal of the comparator 33 is connected to the positive side of a reference power supply 36. but Connected 。 During normal operation, the Dr potential is lower than the VB potential (Dr potential≦VB potential), the potential at connection point 30 between the collector of pnp transistor 31 and resistor 32 is lower than the VS potential, and the output of comparator 33 becomes low (VS potential). On the other hand, when a negative voltage surge is applied, the Dr potential momentarily exceeds the VB potential (Dr potential>VB potential), the potential at connection point 30 becomes higher than the VS potential, and the output of comparator 33 becomes high (VB potential).

[0049] The output terminal of the comparator 33 is connected to a delay circuit 34 and a set input terminal S of a latch circuit 35 . Latch circuit 35 The reset output terminal R of the latch circuit 35 is connected to the output terminal of the comparator 33 via a delay circuit 34. The delay circuit 34 delays the output of the comparator 33 by a predetermined time and transmits it to the input terminal R of the latch circuit 35. That is, the same signal as that input to the input terminal S is input to the input terminal R of the latch circuit 35 via the delay circuit 34.

[0050] The output terminal Q of the latch circuit 35 is connected to the gate electrode 16a. The latch circuit 35 outputs a high-level VB potential or a low-level VS potential from the output terminal Q depending on the states of the input terminals S and R, and applies this potential to the gate electrode 16a. During normal operation, the output terminal Q of the latch circuit 35 is low (VS potential). On the other hand, when a negative voltage surge is applied, the output terminal Q of the latch circuit 35 temporarily becomes high (VB potential) in response to the high (VB potential) of the input terminal S. Thereafter, when the input terminal R becomes high (VB potential), the output terminal Q of the latch circuit 35 returns to low (VS potential). Note that the configuration of the switching circuit S1 shown in FIG. 6 is merely an example, and the switching circuit S1 may be realized with other configurations. The switching circuit S1 may be formed, for example, in the high-side circuit region 12 shown in FIG. 2.

[0051] Next, the operation of the switching circuit S1 shown in Fig. 6 will be described with reference to the timing chart of Fig. 7. In the timing chart of Fig. 7, the Dr potential is indicated as "Dr", the input to the input terminal S of the latch circuit 35 is indicated as "S", the input to the input terminal R of the latch circuit 35 is indicated as "R", and the output from the output terminal Q of the latch circuit 35 is indicated as "Q".

[0052] Before time t11, the output of output terminal Q of latch circuit 35 is low (VS potential), and gate electrode 16a is fixed at the VS potential. When a negative voltage surge is applied, the Dr potential momentarily exceeds the VB potential, and at time t11, the output of comparator 33 becomes high (VB potential), and the input of input terminal S of latch circuit 35 switches from low (VS potential) to high (VB potential). Meanwhile, the input of input terminal R of latch circuit 35 remains low (VS potential). As a result, the output of output terminal Q of latch circuit 35 switches from low (VS potential) to high (VB potential), and gate electrode 16a is fixed at the VB potential.

[0053] The timing from when the Dr potential exceeds the VB potential to time t11 can be adjusted as appropriate, and the output of the latch circuit 35 may be set to high (VB potential) immediately after the Dr potential exceeds the VB potential, or the output of the latch circuit 35 may be set to high (VB potential) after the Dr potential exceeds the VB potential by a predetermined threshold voltage.

[0054] From time t11 to t12, the output of output terminal Q of latch circuit 35 is fixed at high (VB potential). At time t12, high (VB potential) is output with a delay from delay circuit 34, and the input of input terminal R of latch circuit 35 switches from low (VS potential) to high (VB potential). The output of output terminal Q of latch circuit 35 returns from high (VB potential) to low (VS potential). The predetermined time (constant time) from time t11 to t12 can be adjusted as appropriate by adjusting the delay time of delay circuit 34, for example, depending on the type of surge voltage, etc.

[0055] Fig. 8 shows the behavior of the Dr potential when a negative voltage surge is applied. The solid line in Fig. 8 shows the behavior of the Dr potential in the conventional case when a negative voltage surge is applied, and the dashed line in Fig. 8 shows the behavior of the Dr potential in the semiconductor device according to the first embodiment when a negative voltage surge is applied. Times t11 and t12 in Fig. 8 correspond to times t11 and t12 shown in Fig. 7.

[0056] 8, during a time T1 before time t11, gate electrode 16a is connected to the VS potential, turning off n-channel MOSFET 10. At time t11, the timing at which the Dr potential exceeds the VB potential is used as a trigger. During a certain period T2 from time t11 to t12, the connection destination of gate electrode 16a is switched from the VS potential to the VB potential, turning on n-channel MOSFET 10. This shorts the Dr potential to the VB potential, and suppresses the drop in Dr potential indicated by the dashed line in FIG. 8 compared to the conventional drop in Dr potential indicated by the solid line in FIG. 8. During a time T3 after time t12, the connection destination of gate electrode 16a is switched from the VB potential to the VS potential, turning off n-channel MOSFET 10, causing gate electrode 16a to function as a shield (field plate).

[0057] Here, semiconductor devices according to first and second comparative examples will be described. As shown in FIG. 9, the semiconductor device according to the first comparative example has a p - 3 in that a shield layer 16x fixed to the Dr potential of the level shift element 10a is provided above the isolation region 5a. - 3 in that a shield layer 16x fixed to the VS potential is provided above the isolation region 5a of the mold. In each of the semiconductor devices according to the first and second comparative examples, the potential of the shield layer 16x is equal to or lower than the Dr potential, and the shield layer 16x is p - It only acts as a shield to prevent the formation of an inversion layer in the mold isolation region 5a.

[0058] In contrast to the semiconductor devices according to the first and second comparative examples, the semiconductor device according to the first embodiment has p - A gate electrode 16a is provided above the isolation region 5a to control the on / off of the n-channel MOSFET 10. Therefore, during normal operation, the gate electrode 16a can function as a shield like the shield layer 16x in the semiconductor devices according to the first and second comparative examples, and during abnormal operation, the gate electrode 16a can temporarily turn on the n-channel MOSFET 10 to suppress malfunction of the level shift element 10a.

[0059] (Second embodiment) As shown in FIG. 11, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that the potential of the gate electrode 16a can be switched between the Dr potential of the level shift element 10a and the VB potential on the positive side of the high potential side power supply 105 by a switching circuit S2, instead of the VS potential on the negative side of the high potential side power supply 105.

[0060] During normal operation, when the Dr potential of the level shift element 10a is equal to or lower than the VB potential (Dr potential≦VB potential), the potential of the gate electrode 16a is fixed to the Dr potential. On the other hand, during abnormal operation, when the Dr potential of the level shift element 10a exceeds the VB potential (Dr potential>VB potential), the switching circuit S2 detects the abnormal operation and temporarily switches the connection destination of the gate electrode 16a to the VB potential, as shown in Fig. 3. The other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0061] According to the semiconductor device of the second embodiment, even when the potential of the gate electrode 16a is switched between the Dr potential of the level shift element 10a and the VB potential on the positive side of the high-potential side power supply 105 by the switching circuit S2, the same effects as those of the semiconductor device of the first embodiment can be achieved.

[0062] (Third embodiment) 12, the semiconductor device according to the third embodiment is similar to the semiconductor device according to the second embodiment shown in Fig. 11 in that the potential of the gate electrode 16a can be switched by a switching circuit S2 between the Dr potential of the level shift element 10a and the VB potential on the positive side of the high-potential power supply 105. However, the semiconductor device according to the third embodiment differs from the semiconductor device according to the second embodiment in that it further includes resistors R3 and R4 connected between one end of the switching circuit S2 and the VB potential and between the other end of the switching circuit S2 and the VS potential and between the other end of the switching circuit S2 and the Dr potential.

[0063] The resistance values ​​of resistors R3, R4, R5, and R6 can be adjusted as appropriate. The potential of gate electrode 16a can be switched between a potential in the range of VS potential or higher and Dr potential or lower when switching circuit S2 is connected to resistors R5 and R6, and a potential in the range of Dr potential or higher and VB potential or lower when switching circuit S2 is connected to resistors R3 and R4. Other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the second embodiment, and therefore, redundant explanations will be omitted.

[0064] The semiconductor device according to the third embodiment has the same effect as the semiconductor device according to the first embodiment, even when the potential of the gate electrode 16a is switched between an intermediate potential between the VS potential and the Dr potential and an intermediate potential between the VB potential and the Dr potential on the positive side of the high-potential power supply 105. Note that the configuration in which the potential of the gate electrode 16a is switched between an intermediate potential between the VS potential and the Dr potential and an intermediate potential between the VB potential and the Dr potential on the positive side of the high-potential power supply 105 can be realized by a configuration other than that further including the resistors R3, R4, R5, and R6.

[0065] (Other embodiments) As described above, the present invention has been described with reference to the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0066] For example, although an HVIC is used as an example of the semiconductor device according to the first to third embodiments, the present invention can also be applied to semiconductor devices other than HVICs as long as the device has a configuration in which a shield layer can be disposed above the isolation region. For example, the present invention is particularly effective for semiconductor devices to which a high voltage of several tens of volts or more is applied.

[0067] Furthermore, the configurations disclosed in the first to third embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0068] 1...Base (semiconductor chip) 2...Voltage range 3...Base area 4...Base contact region 5a,5b…separation area 6a, 6b...Drift region 7a, 7b...Drain region 8a, 8b...Source region 9a, 9b...gate electrodes 10a, 10b...Level shift elements 11a, 11b...contact area 12...High-side circuit area 13...Well area 14,15...Contact area 16a, 16b...gate electrodes (shield layers) 16x...Shield layer 17, 18...Gate insulating film 30...Connection point 31...pnp transistor 32...Resistance 33...Comparator 34...Delay circuit 35...Latch circuit 36…Reference power supply 100...Semiconductor device 101…Low potential side circuit (low side circuit) 102...High-side circuit 103...Level shift circuit 104...Low potential side power supply 105…High potential side power supply 106...Connection point 200...Power conversion section D1, D2: Protection diodes R1, R2...Level shift resistors R3,R4,R5,R6…Resistance S1, S2...Switching circuit T11, T12...Level shift elements T21: High-potential side switching element T22…low potential side switching element

Claims

1. a substrate of a first conductivity type; a second conductivity type well region provided on the substrate, in which a high potential side circuit is formed; a second conductivity type breakdown voltage region that is provided to surround the well region and has a lower impurity concentration than the well region; a level shift element including: a drift region of a second conductivity type provided on the substrate; a carrier receiving region of the second conductivity type provided above the drift region and having a higher impurity concentration than the drift region; a base region of a first conductivity type provided in contact with the drift region; a first gate electrode provided on and insulated from the base region; and a carrier supply region of the second conductivity type provided above the base region; an isolation region of a first conductivity type provided between the voltage-withstanding region and the drift region on the substrate; a second gate electrode provided on the isolation region in an insulated manner, the second gate electrode being selectively applied with a first potential or a second potential higher than the first potential; A semiconductor device comprising:

2. the first potential is equal to or higher than the potential of the negative electrode of a power source connected to the high potential side circuit and equal to or lower than the potential of the carrier receiving area, The second potential is equal to or higher than the potential of the carrier receiving area and equal to or lower than the potential of the positive electrode of the power supply.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. the first potential is a potential on the negative side of a power supply connected to the high potential side circuit, The second potential is a potential on the positive side of a power supply connected to the high potential side circuit.

3. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

4. the first potential is a potential of the carrier receiving region; The second potential is a potential on the positive side of a power supply connected to the high potential side circuit.

3. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

5. During normal operation, the first potential is applied to the second gate electrode, During an abnormal operation, the second gate electrode is fixed to the second potential.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

6. the first potential is applied to the second gate electrode when the potential of the carrier receiving region is equal to or lower than the potential of a positive electrode of a power supply connected to the high potential side circuit; When the potential of the carrier receiving region exceeds the potential of the positive electrode of a power supply connected to the high-potential side circuit, the second potential is temporarily applied to the second gate electrode.

6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

7. The semiconductor device according to any one of claims 1 to 6, further comprising a switching circuit that detects the potential of the carrier receiving region and switches the first potential or the second potential applied to the second gate electrode in accordance with the detected potential of the carrier receiving region.

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