Audio circuitry and DSD signal playback methods

Abstract

An audio circuit 100 is provided with a volume circuit 110 that processes a DSD signal including DSD data and a DSD clock. The volume circuit 110 is provided with a first shift register 112 and a replacement circuit 114. The first shift register 112 holds N bits of the DSD data. The replacement circuit 114 replaces (N - M) bits (0 ≤ M ≤ N) corresponding to a gain set value among the N bits stored in the first shift register 112, with a bit string for muting having a mark rate of substantially 50%.

Description

[Technical Field]

[0001] The present disclosure relates to audio signal processing, and in particular to a technique for reproducing DSD signals. [Background technology]

[0002] In recent years, the audio industry has seen a trend toward high-resolution audio sources. In response to this trend, a format called DSD (Direct Stream Digital) is becoming increasingly popular for network distribution of audio sources, creating a demand for playback devices that support this format. The DSD format itself has existed for some time, and was also used in formats such as SACD (Super Audio CD).

[0003] The DSD method is a type of PDM (pulse density modulation) in which the audio waveform is recorded as a 1-bit pulse density modulated bit stream, and in principle the original audio waveform can be reproduced by passing it through a low-pass filter.

[0004] There are two methods for playing DSD format audio signals: non-native playback and native playback. In non-native playback, the DSD signal is first converted into a PCM (Pulse Code Modulation) signal, and then converted into an analog audio signal by a D / A converter.

[0005] On the other hand, with native playback, the DSD signal is not converted to a PCM signal, but is instead directly converted to an analog audio signal through D / A conversion. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 9,875,750 Summary of the Invention [Problem to be solved by the invention]

[0007] With non-native playback, a DSP (Digital Signal Processor or Digital Sound Processor) can perform various digital signal processing on the PCM signal, such as volume control and equalization. However, PCM conversion causes delays and makes the signal more susceptible to jitter, so native playback is superior in terms of sound quality.

[0008] On the other hand, although native playback offers superior sound quality, it has the limitation of not being able to control volume in the digital domain.

[0009] The present disclosure has been made in this situation, and one exemplary purpose of an embodiment thereof is to provide an audio circuit capable of controlling volume natively in DSD. [Means for solving the problem]

[0010] One aspect of the present disclosure relates to an audio circuit. The audio circuit includes a volume circuit that processes a DSD (Direct Stream Digital) signal including DSD data and a DSD clock. The volume circuit includes a first shift register with N bits (N≧2) that stores the DSD data, and a substitution circuit that substitutes (NM) bits (0≦M≦N) corresponding to a gain setting value among the N bits stored in the first shift register with a mute bit string having a mark ratio of substantially 50%.

[0011] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, etc. are also valid aspects of the present disclosure. [Effects of the Invention]

[0012] According to an embodiment of the present disclosure, volume control is possible natively in DSD. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a circuit diagram of an audio circuit according to an embodiment; [Figure 2] 2 is an operational waveform diagram of the audio circuit of FIG. 1. [Figure 3] FIG. 2 is a diagram illustrating volume control in the audio circuit of FIG. [Figure 4] FIG. 2 is a circuit diagram of a volume circuit according to an embodiment. [Figure 5] FIG. 2 is a circuit diagram of a volume circuit according to an embodiment. [Figure 6] 5 is an operational waveform diagram of the volume circuit of FIG. 4. [Figure 7] FIG. 5 is a diagram illustrating the internal operation of the volume circuit of FIG. [Figure 8] FIG. 1 is a block diagram of a D / A converter IC. DETAILED DESCRIPTION OF THE INVENTION

[0014] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0015] One embodiment disclosed in this specification relates to an audio circuit. The audio circuit includes a volume circuit. The volume circuit includes an N-bit (N≧2) first shift register that holds DSD data of a DSD (Direct Stream Digital) signal, and a substitution circuit that substitutes (NM) bits (0≦M≦N) corresponding to a gain setting value among the N bits stored in the first shift register with a mute bit string having a mark ratio of substantially 50%.

[0016] The smaller the gain setting, the closer the mark rate of the N bits after substitution by the substitution circuit approaches 50%, approaching the mute state. This allows for volume control in DSD native format.

[0017] If a fixed pattern is used as the mute bit string, when the gain setting value is fixed so that (NM) is an odd number, the mute bit string will deviate from 50%, resulting in deterioration of sound quality. Therefore, in one embodiment, the mute bit string may be inverted every DSD clock cycle. This brings the time average mark rate of the mute bit string closer to 50%, thereby suppressing deterioration of sound quality.

[0018] In one embodiment, a pseudo-random bit sequence (PRBS) with a mark rate of 50% may be used as the muting bit sequence, which makes the time average mark rate of the muting bit sequence approach 50%, thereby suppressing deterioration of sound quality.

[0019] In one embodiment, the substitution circuit may include an N-bit second shift register that receives data that is inverted every cycle of the DSD clock, and a combiner that combines M bits from one end of the first shift register and (NM) bits from the other end of the second shift register. The second shift register can generate a muting bit string that is inverted every cycle of the DSD clock.

[0020] In one embodiment, the volume circuit may further include a counter that, when the volume setting value is changed, changes the gain setting value from an initial value before the volume is changed toward a target value after the volume is changed.

[0021] In one embodiment, the time or slope for the gain setting to reach the target value from the initial value may be configurable.

[0022] In one embodiment, the audio circuit may further comprise a current segment D / A converter that receives as an input the N bits generated by the substitution circuit.

[0023] (Embodiment) The present disclosure will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the disclosure, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure.

[0024] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected, and a case in which component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the function or effect achieved by their combination.

[0025] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0026] 1 is a circuit diagram of an audio circuit 100 according to an embodiment. The audio circuit 100 is an IC (Integrated Circuit) integrated on a single semiconductor substrate. For example, the audio circuit 100 is a DAC chip in which a D / A converter 102 and a volume circuit 110 are integrated.

[0027] The audio circuit 100 has a data pin DATA and a clock pin CLK, and receives a DSD signal containing DSD data D1 and a DSD clock CLK. The volume circuit 110 receives the DSD signal containing the DSD data D1 and the DSD clock CLK, and performs volume control according to the volume setting value VOL. In the muted state, the DSD data D1 has a 50% probability of appearing as 0 or 1, and deviations from 50% represent audio signal components.

[0028] The volume circuit 110 includes a first shift register 112 and a substitution circuit 114. The first shift register 112 holds N bits (N≧2) of DSD data. For example, N=128, although this is not limited thereto.

[0029] The substitution circuit 114 substitutes (NM) bits (0≦M≦N) corresponding to the gain setting value from the N-bit bit string D2 stored in the first shift register 112 with a mute bit string MB having a mark ratio of substantially 50%, and outputs the bit string D3 after substitution. The number of bits M is N at the maximum gain and 0 at the minimum gain.

[0030] The above is the configuration of the audio circuit 100. Next, a description will be given of the operation of the audio circuit 100. Fig. 2 is a waveform diagram showing the operation of the audio circuit 100 of Fig. 1.

[0031] D1 indicates DSD data. DSD data is a bit stream of 1s and 0s that have been pulse density modulated. In a given clock cycle, N bits of data D2 from the DSD data D1 are stored in the first shift register 112.

[0032] The replacement circuit 114 replaces (N - M) bits of the N-bit data D2 with the mute bit sequence MB having a mark rate of 50%. Among the N-bit data D2, the M bits are the original bits that are preserved. In this example, the mute bit sequence MB is a bit sequence in which 1s and 0s alternate. The data D3 after replacement is input to the subsequent D / A converter and is converted into an analog signal.

[0033] The audio circuit 100 repeats the same process while shifting the bit sequence D2 to be stored in the first shift register 112 from the DSD data D1 to the right for each clock cycle.

[0034] FIG. 3 is a diagram for explaining the volume control in the audio circuit 100 of FIG. 1. When the volume setting value VOL is the maximum value MAX, M = N, and the DSD data D2 (i.e., D1) is output as the DSD data D3 as it is.

[0035] When the volume setting value VOL is the minimum value MIN, M = 0, and all bits of the input DSD data D2 are replaced with the mute bit sequence MB. In this state, since the mark rate of the DSD data to be reproduced is 50%, it is in the mute state.

[0036] When the volume setting value VOL takes an intermediate value between the minimum value MIN and the maximum value MAX, 0 < M < N, and a part of the input DSD data D2 is replaced with the mute bit sequence MB. In this state, the effective volume of the DSD data to be reproduced is M / N times that when the volume setting value is maximum.

[0037] The above is the operation of the audio circuit 100. According to this audio circuit 100, volume control in DSD native is possible. Since volume control in DSD native does not require PCM conversion, the delay time during audio reproduction can be reduced, and the power consumption of the circuit can also be lowered. Furthermore, since the volume circuit 110 can be composed of a combination of a shift register and a bit replacement circuit, it is simple and the circuit area can be small.

[0038] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the disclosure.

[0039] FIG. 4 is a circuit diagram of a volume circuit 110 according to one embodiment. In this embodiment, the mute bit string MB is inverted every cycle of the DSD clock CLK. The substitution circuit 114 includes a second shift register 116 and a combiner 118. The second shift register 116 has N bits, similar to the first shift register 112, and receives data D4 (referred to as clock-inverted data) that is inverted every cycle of the DSD clock CLK at its input. The bit string stored in the second shift register 116 is inverted every cycle of the DSD clock CLK. For example, the clock-inverted data D4 can be configured using a flip-flop 115 and an inverter 117.

[0040] The combiner 118 combines M bits from one end of the first shift register 112 with (NM) bits from the other end of the second shift register 116, and outputs N-bit DSD data D3.

[0041] The substitution circuit 114 further includes a counter 120. When the volume setting value VOL is changed, the counter 120 changes the gain setting value, that is, M, from the initial value before the volume is changed toward the target value after the volume is changed.

[0042] It is preferable that the time or slope required for the gain setting value M to reach the target value from the initial value can be set using a register.

[0043] 5 is a circuit diagram of a volume circuit 110 according to a modified example. The inverted clock data D4 is generated by inverting the output of the second shift register 116 using an inverter 116. Alternatively, a signal obtained by delaying the DSD clock by about 1 / 4 of its cycle may be used as the inverted clock data D4.

[0044] The above is an example of the configuration of the volume circuit 110. Next, its operation will be described. Fig. 6 is an operational waveform diagram of the volume circuit 110 of Fig. 4 or 5. Before time t0, the volume setting value VOL is a certain value V1, and the gain setting value M is a value M1 corresponding to the volume setting value V1.

[0045] At time t0, the user changes the volume setting value VOL to a value V2. In response to this, the counter 120 decreases the gain setting value M from an initial value M1 corresponding to the volume setting value V1 before the change to a target value M2 corresponding to the volume setting value V2 after the change over a transition time τ. This causes the amplitude of the audio signal output from the D / A converter, i.e., the volume, to gradually decrease.

[0046] At time t1, the user changes the volume setting value VOL to a value V3. In response to this, the counter 120 increases the gain setting value M from an initial value M2 corresponding to the volume setting value V2 before the change toward a target value M3 corresponding to the volume setting value V3 after the change over a transition time τ. This causes the amplitude of the audio signal output from the D / A converter, i.e., the volume, to increase gradually.

[0047] 6, counter 120 operates so that the transition time τ of gain setting value M is constant, but this is not limited thereto, and counter 120 may operate so that the slope of gain setting value M is constant. The transition time τ is on the order of several tens to several hundreds of milliseconds.

[0048] FIG. 7 is a diagram for explaining the internal operation of the volume circuit 110 in FIG. 4. Consider a situation where the gain setting value M is fixed at a value where 0 < M < N. In this case, the mute bit string MB included in the DSD data D3 after volume control alternates between 1 and 0 at the period of the DSD clock CLK. Note that the audio component D2 included in the DSD data D3 is shifted by 1 bit for each period of the DSD clock CLK.

[0049] The above is the internal operation of the volume circuit 110. When using a fixed pattern for the mute bit MB, if N - M is odd, the mark rate of the mute bit string MB deviates from 50%, resulting in a DC offset, which is a factor in sound quality degradation. According to the volume circuit 110 in FIG. 6, even when N - M is odd, the time-average value of the mark rate of the mute bit string MB is 50%, so the influence of the DC offset can be suppressed.

[0050] Also, when a current segment type D / A converter is provided at the subsequent stage of the volume circuit 110, if the mute bit string MB is fixed, the state of the segment corresponding to the mute bit string MB will be fixed. On the other hand, if it is inverted at the clock cycle of the mute bit string MB, the current segments that turn on will be switched at the clock cycle, so the effect of so-called direct element matching can be obtained.

[0051] The above is an explanation of the present disclosure based on the embodiments. It is understood by those skilled in the art that these embodiments are examples, and various modifications are possible for the combination of each component and each processing process, and such modifications are also within the scope of the present disclosure. Hereinafter, such modifications will be described.

[0052] (Modification Example 1) A pseudo-random signal PRBS with a mark rate of 50% may be used as the muting bit string. In this case, the second shift register 116 in Fig. 4 can be replaced with an N-bit PRBS generator. Even when a PRBS is used, the time average value of the mark rate of the muting bit string MB can approach 50%.

[0053] (Variation 2) A fixed pattern may be used as the muting bit string. In this case, a DC offset occurs, but the circuit configuration can be further simplified. When using a fixed pattern, the gain setting value M may be changed so that (MN) is an even number, in which case a DC offset does not occur.

[0054] Finally, a specific example of the audio circuit 100 will be described. Figure 8 is a block diagram of a D / A converter IC 200. The D / A converter IC 200 is configured using the architecture of the audio circuit 100 described above.

[0055] The D / A converter IC200 receives audio signals in PCM format or DSD format, converts them into analog audio signals, and outputs them.

[0056] In one platform (called a PCM platform), a PCM sound source is connected to the BCLK, LRCLK, and DIN pins of the D / A converter IC200, and two-channel (e.g., L channel and R channel) audio signals are input to the I 2 On another platform (DSD platform), a DSD sound source is connected to the DSDCLK, DSD1, and DSD2 pins of the D / A converter IC200, and two-channel audio signals are input in DSD format.

[0057] In this embodiment, the BCLK pin and DSDCLK ​​pin, the LRCLK pin and DSDCL2 pin, and the DIN pin and DSDCL1 pin are shared.

[0058] The PCM interface 210, audio function controller 214, oversampling digital filter 216, and delta-sigma modulator 218 are active in the PCM platform. The audio function controller 214 performs signal processing, such as volume control, on the PCM signal received by the PCM interface 210. The oversampling digital filter 216 oversamples the output of the audio function controller 214 and controls the frequency characteristics using a digital filter. The delta-sigma modulator 218 delta-sigma modulates the output of the oversampling digital filter 216. The delta-sigma modulator 218 outputs two channels, each of which is an N-bit PDM signal. The N-bit × 2-channel PDM signal is input to current segment DACs 224 and 226 for each channel via a selector 220. The current segment DACs 224 and 226 correspond to the D / A converter 102 in Figure 1. A reference voltage source 228 supplies a reference voltage to the current segment DACs 224 and 226. In FIG. 8, the current segment DACs 224, 226 have differential current outputs, but are not limited to this and may have single-ended or voltage outputs.

[0059] The DSD interface 212 is active on a DSD platform and receives a DSD signal, specifically a DSD clock and two channels of DSD data, from an external DSD sound source. The first shift register 112 of the volume circuit 110 may be configured as part of the DSD interface 212.

[0060] The audio function controller 214 includes the above-mentioned volume circuit 110. The volume circuit 110 performs volume control on the two-channel DSD signals received by the DSD interface 212.

[0061] The volume-controlled DSD signal (the above-mentioned DSD data D3) output from the volume circuit 110 passes through a selector 220 and is input to current segment DACs 224 and 226 for each channel.

[0062] The clock generator 230 multiplies the reference clock to generate a master clock.

[0063] The serial interface 232 is 2 The serial interface 232 is an I / O (Interface Card) or SPI interface, and an external host processor is connected to the data pin SDA and clock pin SCK. The serial interface 232 receives the volume setting value and various parameters from the host processor. These parameters include the time constant and slope when softly transitioning the volume. The volume setting value received by the serial interface 232 is supplied to the audio function controller 214.

[0064] The system controller 234 comprehensively controls the entire D / A converter IC 200. A reset signal is input to the system controller 234.

[0065] The present disclosure has been described using specific terms based on the embodiments, but the embodiments merely illustrate the principles and applications of the present disclosure, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present disclosure as defined in the claims. [Industrial Applicability]

[0066] The present disclosure can be used in audio signal processing. [Explanation of symbols]

[0067] 100 Audio Circuit 102 D / A converter 110 Volume circuit 112 First shift register 114 Replacement circuit 116 Second shift register 118 Combiner 120 counters 200 D / A converter ICs 210 PCM interface 212 DSD interface 214 Audio Function Controller 216 Oversampling Digital Filter 218 Delta-Sigma Modulator 220 Selector 224,226 Current Segment DAC 228 Reference Voltage Source 230 Clock Generator 232 serial interface 234 System Controller

Claims

1. a volume circuit for processing a DSD signal including DSD (Direct Stream Digital) data and a DSD clock; The volume circuit is a first shift register of N bits (N≧2) for storing the DSD data; a substitution circuit that generates a mute bit string in which 1s and 0s are alternately arranged, and substitutes (N-M) bits (0≦M≦N) corresponding to a gain setting value among the N bits stored in the first shift register with the mute bit string; Including, The audio circuit is characterized in that the substitution circuit inverts each bit included in the mute bit string for each cycle of the DSD clock.

2. The substitution circuit includes an N-bit second shift register that receives as input data that is inverted every period of the DSD clock; 2. The audio circuit according to claim 1, wherein (N-M) bits stored in the first shift register are replaced with (N-M) bits of the N bits stored in the second shift register.

3. The substitution circuit 3. The audio circuit of claim 2, further comprising a combiner that combines M bits from one end of the first shift register and (N-M) bits from the other end of the second shift register.

4. 4. The audio circuit according to claim 1, wherein the volume circuit further includes a counter that, when the volume setting value is changed, changes the gain setting value from an initial value before the change toward a target value after the change.

5. 5. The audio circuit according to claim 4, wherein the time or slope required for the gain setting value to reach the target value from the initial value is configurable.

6. 6. The audio circuit according to claim 1, further comprising a current segment D / A converter that receives as an input the N bits generated by the substitution circuit.

7. A method for reproducing a DSD (Direct Stream Digital) signal including DSD data and a DSD clock, comprising: storing the DSD data in a first shift register of N bits (N≧2); generating a muting bit string in which 1s and 0s alternate, with each bit inverting every cycle of the DSD clock; replacing (N-M) bits (0≦M≦N) corresponding to a gain setting value among the N bits stored in the first shift register with the mute bit string; A reproducing method comprising:

8. The step of generating the muting bit string includes a step of inputting data that is inverted every period of the DSD clock into an N-bit second shift register; The reproduction method according to claim 7, wherein the replacing step replaces (N-M) bits stored in the first shift register with (N-M) bits of the N bits stored in the second shift register.

9. The reproduction method described in Claim 8, characterized in that the replacement step includes a step of combining M bits from one end of the first shift register and (N-M) bits from the other end of the second shift register.

10. 10. The playback method according to claim 7, further comprising the step of, when a volume setting value is changed, changing the gain setting value from an initial value before the change toward a target value after the change.

11. 11. The reproducing method according to claim 10, wherein the time or slope required for the gain setting value to reach the target value from the initial value is configurable.

12. 12. The reproducing method according to claim 7, further comprising the step of converting the N bits generated in the replacing step into an analog signal by a current segment D / A converter.

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