Apparatus and method for ion current compensation

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating a waveform for plasma processing a substrate in a processing chamber. Embodiments herein include apparatus and methods for generating a pulsed voltage waveform, the methods including coupling a main voltage source to an electrode disposed in a processing chamber during a first phase of a process for generating a pulsed voltage waveform, coupling a ground node to the electrode during a second phase of the process for generating a pulsed voltage waveform, coupling a first compensation voltage source to the electrode during a third phase of the process for generating a pulsed voltage waveform, and coupling a second compensation voltage source to the electrode during a fourth phase of the process for generating a pulsed voltage waveform.

Description

[Technical Field]

[0001] background Field

[0001] Embodiments of the present disclosure generally relate to systems used in the manufacture of semiconductor devices. More particularly, embodiments of the present disclosure relate to plasma processing systems used to process substrates. [Background technology]

[0002] 2. Description of Related Art

[0002] Reliably fabricating high aspect ratio features is one of the key technological challenges for next generation semiconductor devices. One method for forming high aspect ratio features is to use a plasma-assisted etching process in which a plasma is formed in a processing chamber and ions from the plasma are accelerated toward the surface of a substrate to form openings in a layer of material located below a mask layer formed on the surface of the substrate.

[0003]

[0003] In a typical plasma-assisted etching process, a substrate is placed on a substrate support located in a processing chamber, a plasma is formed above the substrate, and ions are accelerated from the plasma toward the substrate through a plasma sheath, i.e., an electron-depleted region, formed between the plasma and the surface of the substrate.

[0004]

[0004] Conventional RF plasma-assisted etching processes simply transmit a sinusoidal waveform containing an RF signal to one or more electrodes in a plasma processing chamber, and have been found to lack adequate or desirable control over sheath characteristics and generated ion energy, which can result in undesirable plasma processing results, including excessive sputtering of mask layers and the creation of sidewall defects in high aspect ratio features.

[0005]

[0005] Therefore, there is a need in the art for a method for plasma processing and biasing that can provide desirable plasma assisted etch process results. Summary of the Invention

[0006]

[0006] Embodiments provided herein generally include an apparatus, plasma processing system, and method for generating a waveform for plasma processing a substrate in a processing chamber.

[0007]

[0007] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, as other equally effective embodiments may be permitted. [Brief explanation of the drawings]

[0008] [Figure 1] 8 is a schematic cross-sectional view of a processing system according to one or more embodiments configured to perform the methods described herein. [Figure 2A]

[0009] 1 illustrates a voltage waveform that may be applied to electrodes of a processing chamber according to one or more embodiments. [Figure 2B]

[0010] 3 shows a voltage waveform established on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 3A]

[0011] A typical ion energy distribution (IED) is shown when using a single frequency excitation waveform. [Figure 3B]

[0012] 1 is a graph illustrating an IED function (IEDF) in accordance with certain embodiments of the present disclosure. [Figure 4A]

[0013] 5B illustrates a pulse voltage (PV) waveform generated using the waveform generator of FIG. 5A in accordance with certain embodiments of the present disclosure. [Figure 4B]

[0014] 5D illustrates a PV waveform generated using the waveform generator of FIG. 5C in accordance with certain embodiments of the present disclosure. [Figure 4C]

[0015] 5B illustrates a measurement waveform generated using the waveform generator of FIG. 5A in accordance with certain embodiments of the present disclosure. [Figure 5A]

[0016] 1 illustrates an example implementation of a waveform generator for biasing a substrate to achieve IED control in accordance with certain aspects of the present disclosure. [Figure 5B]

[0017] 1 illustrates an example implementation of a waveform generator for biasing a substrate to achieve IED control in accordance with certain aspects of the present disclosure. [Figure 5C]

[0018] 1 illustrates an example implementation of a waveform generator for biasing a substrate to achieve IED control in accordance with certain aspects of the present disclosure. [Figure 6]

[0019] 5D illustrates an exemplary filter topology for use with the waveform generator of FIG. 5C, in accordance with certain embodiments of the present disclosure. [Figure 7]

[0020] FIG. 5C is a timing diagram illustrating the states of the switches of the waveform generator of FIG. 5A, FIG. 5B, or FIG. 5C in accordance with certain aspects of the present disclosure. [Figure 8]

[0021] FIG. 1 is a process flow diagram illustrating a waveform generation method. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0022] As technology nodes advance toward 2 nm, the fabrication of smaller features with larger aspect ratios requires atomic precision in plasma processing. In etching processes where plasma ions play a key role, controlling ion energy has become a challenge for the semiconductor equipment industry. Conventional RF bias technology uses a sinusoidal wave to excite the plasma and accelerate the ions.

[0010]

[0023] Some embodiments of the present disclosure generally relate to techniques for generating pulsed voltage (PV) waveforms to control ion energy distribution (IED). For example, a pulsed voltage waveform and a radio frequency (RF) waveform may be applied to the same node in a plasma chamber to implement low- and high-energy peaks for IED functionality, with little or no intermediate energies between the low- and high-energy peaks, as described in more detail herein. Ions associated with the high-energy peaks have the energy and directionality to reach the bottom of high-aspect-ratio features being etched and enable the etching reaction. While low-energy ions cannot reach the bottom of the features during etching, they are still important to the etching process. Intermediate-energy ions are not beneficial to the etching process because they do not have the desired directionality and impinge on the sidewalls of the features being etched, often resulting in undesirable bowing of the sidewalls of the etched features. Some embodiments relate to techniques for generating PV waveforms with high- and low-energy peaks and few or no intermediate-energy ions.

[0011] Plasma Processing System Example

[0024] 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etch process, such as a reactive ion etch (RIE) plasma process. However, it should be noted that the embodiments described herein may also be used in processing systems configured for use with other plasma-assisted processes, such as plasma-enhanced deposition processes, e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processes, e.g., plasma doping (PLAD), or plasma-based ion implantation processes.

[0012]

[0025] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP), and the processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed in a processing region 129 facing a lower electrode (e.g., substrate support assembly 136) disposed within the processing region 129. In a typical CCP processing system, a radio frequency (RF) source is electrically coupled to one of the upper or lower electrodes and sends an RF signal configured to ignite and sustain a plasma (e.g., plasma 101) that is capacitively coupled to each of the upper and lower electrodes and disposed in the processing region therebetween. Typically, the opposing electrode of the upper or lower electrode is coupled to ground or to a second RF power source for additional plasma excitation. As shown, the processing system 10 includes the processing chamber 100, the substrate support assembly 136, and a system controller 126.

[0013]

[0026] The processing chamber 100 typically includes a chamber body 113 that includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define a processing region 129. The one or more sidewalls 122 and the chamber base 124 are generally sized and shaped to provide structural support for the elements of the processing chamber 100 and comprise materials configured to withstand pressures and additional energy applied thereto, while the plasma 101 is generated within a reduced pressure environment maintained within the processing region 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0014]

[0027] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases from a process gas source 119 in fluid communication with the process region 129. The substrate 103 is loaded into and removed from the process region 129 through an opening (not shown) in one or more sidewalls 122, which opening is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0015]

[0028] In some embodiments, a plurality of lift pins 20 movably disposed through openings formed in the substrate support assembly 136 are used to facilitate transfer of substrates to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are disposed above and coupled to and / or engageable with a lift pin hoop (not shown) disposed within the processing region 129. The lift pin hoop may be coupled to a shaft (not shown) that extends sealingly through the chamber base 124. The shaft may be coupled to an actuator (not shown) that is used to raise and lower the lift pin hoop. When the lift pin hoop is in the raised position, it engages the plurality of lift pins 20, elevating the upper surfaces of the lift pins above the substrate support surface 105A and lifting the substrate 103 therefrom to allow access to the inactive (backside) surface of the substrate 103 by a robotic handler (not shown). When the lift pin hoop is in the lowered position, the plurality of lift pins 20 are flush with or recessed below the substrate support surface 105A, upon which the substrate 103 rests.

[0016]

[0029] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate bias method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated sub-processors. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 135 are conventionally coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are performable by components in the processing system 10.

[0017]

[0030] Typically, a program readable by the CPU 133 of the system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing schemes described herein. The program may include instructions used to control various hardware and electrical components within the processing system 10 to perform various process tasks and various process sequences used to carry out the methods described herein. In one embodiment, the program includes instructions used to perform one or more of the processes described below in connection with FIG. 8.

[0018]

[0031] The plasma control system generally includes a first source assembly 196 for establishing at least a first pulsed voltage (PV) waveform at the bias electrode 104 and a second source assembly 197 for establishing at least a second PV waveform at the edge control electrode 115. The first PV waveform or the second PV waveform may be generated using one or more components in a waveform generator assembly 150, which may correspond to the waveform generators described in more detail herein with respect to FIGS. 4A-5C. In one embodiment, the waveform generator assembly 150 includes a waveform generator 500, shown in FIG. 5A, configured to generate a PV waveform at the bias electrode 104 and the edge control electrode 115 similar to the PV waveform 400 shown in FIG. 4A.

[0019]

[0032] In some embodiments, the waveform generator assembly 150 includes a PV waveform source and an RF source, such as the waveform generator 550 illustrated in FIG. 5C , configured to generate a PV waveform similar to the PV waveform 450 shown in FIG. 4B at the bias electrode 104, the edge control electrode 115, and / or the support base 107 (e.g., a powered electrode or cathode). The waveform generator 550 of the waveform generator assembly 150 of the first source assembly 196 can be configured to send a PV waveform and an RF signal to the support base 107 (e.g., a powered electrode or cathode) or the bias electrode 104. In some embodiments, as shown in FIG. 1 , a separate waveform generator assembly 150 in the third source assembly 198 includes at least an RF source configured to send an RF signal to the support base 107 (e.g., a powered electrode or cathode).

[0020]

[0033] An applied RF signal provided from the first source assembly 196, the second source assembly 197, or the third source assembly 198 can be configured to generate (sustain and / or ignite) a plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF signal is used to ignite and sustain the plasma 101 using a process gas disposed in the processing space 129 and an electric field generated by RF power (RF signal) delivered to the support base 107 and / or the bias electrode 104. The processing region 129 is fluidly coupled to one or more dedicated vacuum pumps (not shown) via a vacuum outlet 120, which maintain the processing region 129 at subatmospheric pressure conditions and evacuate the processing gas and / or other gases from the processing region 129. In some embodiments, the substrate support assembly 136 disposed in the processing region 129 is grounded and disposed on a support shaft 138 extending through the chamber base 124. In some embodiments, the applied RF signal provided from waveform generator assembly 150 in first source assembly 196, second source assembly 197, or third source assembly 198 is provided by RF generator 506 (FIG. 5C) implemented using RF signal source 581 and RF matching network 582. In some embodiments, as described further below, RF generator 506 is configured to send an RF signal having a frequency greater than 40 MHz, such as between about 40 MHz and about 200 MHz.

[0021]

[0034] Referring back to FIG. 1 , the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) having a substrate support surface 105A and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a grounded plate 112, as described further below. The support base 107 is electrically isolated from the chamber base 124 by the insulating plate 111, and the grounded plate 112 is interposed between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. In some embodiments, the support base 107 has one or more cooling channels (not shown) disposed therein, which are fluidly coupled to and in fluid communication with a coolant source (not shown) (e.g., a refrigerant source or a water source having a relatively high electrical resistance). In some embodiments, the substrate support 105 includes a heater (not shown), e.g., a resistive heating element embedded in its dielectric material, where the support base 107 is formed of a corrosion-resistant, heat-conducting material, such as a corrosion-resistant metal (e.g., aluminum, an aluminum alloy, or stainless steel), and is coupled to the substrate support by adhesive or mechanical means.

[0022]

[0035] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk-sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (YO3), mixtures thereof, or combinations thereof, etc. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material.

[0023]

[0036] In one configuration, the bias electrode 104 is used as a chucking pole to secure (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and bias the substrate 103 relative to the plasma 101 using one or more pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed from one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof. In some embodiments, the substrate surface and the bias electrode 104 are coupled to a capacitive element (e.g., an electrostatic chuck capacitor (C esc ), which in some embodiments comprises a dielectric material layer of the substrate support 105 disposed between the bias electrode 104 and the substrate support surface 105A, as shown in FIG.

[0024]

[0037] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network, which uses an electrical conductor such as a coaxial power supply 106 (e.g., a coaxial cable) to supply a chucking voltage, such as a static DC voltage between about −5000 V and about 5000 V. The clamping network includes a DC power supply 155 (e.g., a high-voltage DC power supply) and a filter 151 (e.g., a low-pass filter).

[0025]

[0038] The substrate support assembly 136 further includes an edge control electrode 115 located below the edge ring 114, surrounding the bias electrode 104, and / or spaced a distance from the center of the bias electrode 104. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made from a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in FIG. 1, the edge control electrode 115 is located within the region of the substrate support 105. In some embodiments, as shown in FIG. 1, the edge control electrode 115 comprises a conductive mesh, foil, and / or plate located a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 as the bias electrode 104.

[0026]

[0039] The edge control electrode 115 can be biased by using a waveform generator assembly 150 that is different from the waveform generator assembly 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased by using a waveform generator assembly 150 that is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, the waveform generator assembly 150 of the first source assembly 196 is configured to bias the bias electrode 104, and the waveform generator assembly 150 of the second source assembly 197 is configured to bias the edge control electrode 115.

[0027]

[0040] A power feed line 157 electrically connects the output of the waveform generator assembly 150 of the first power supply assembly 196 to the bias electrode 104. The following description will primarily focus on the power feed line 157 of the first power supply assembly 196, which is used to couple the waveform generator assembly 150 of the first source assembly 196 to the bias electrode 104, while a power feed line 158 of the second power supply assembly 197 couples the waveform generator assembly 150 of the second source assembly 197 to the edge control electrode 115 and will include the same or similar components. The conductors in the various parts of the power feed line 157 may include (a) a coaxial cable or combination such as a flexible coaxial cable coupled in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hook-up wire, (c) bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements of (a)-(e).

[0028]

[0041] In some embodiments, the processing chamber 100 further includes a quartz pipe 110 or collar that at least partially surrounds a portion of the substrate support assembly 136 to prevent contact of the substrate support 105 and / or support base 107 with corrosive process gases or plasma, cleaning gases or plasma, or their by-products. Typically, the quartz pipe 110, the insulating plate 111, and the grounded plate 112 are surrounded by a cathode liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewalls 122 to prevent plasma from forming in the region below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0029]

[0042] FIG. 2A shows a voltage waveform that can be established at an electrode in a processing chamber. FIG. 2B shows examples of different types of voltage waveforms 225 and 230 established at the substrate surface by different voltage waveforms, which, like the voltage waveform shown in FIG. 2A, are separately installed at electrodes in the processing chamber. As shown, the waveform includes two stages: an ion current stage and a sheath collapse stage. At the start of the ion current stage, a drop in the substrate voltage creates a high-voltage sheath over the substrate, accelerating positive ions toward the substrate. Positive ions impinging on the substrate surface during the ion current stage deposit a positive charge on the substrate surface, which, if uncompensated, causes the substrate voltage to gradually increase positive during the ion current stage, as shown by voltage waveform 225 in FIG. 2B. However, uncontrolled accumulation of positive charge on the substrate surface can undesirably gradually discharge the sheath and chuck capacitors, slowly decreasing the sheath voltage drop and driving the substrate potential toward zero, as shown by voltage waveform 225. The accumulation of positive charge results in a voltage drop in the voltage waveform established at the substrate surface (FIG. 2B). However, as shown in FIG. 2A, a voltage waveform established at the electrode during the ion current stage with a negative slope can be generated to establish a square region (e.g., a near-zero slope) for the established substrate voltage waveform, as shown in curve 230 of FIG. 2B. Achieving a slope for the waveform established at the electrode during the ion current stage is sometimes referred to as current compensation. The voltage difference at the beginning and end of the ion current phase determines the ion energy distribution function (IEDF) width. The larger the voltage difference, the wider the IEDF width. To achieve monoenergetic ions and a narrower IEDF width, current compensation is used to flatten the substrate voltage waveform during the ion current phase. In some embodiments of the present disclosure, an RF signal is overlaid on the voltage waveform shown in FIG. 2A.

[0030] Waveform Generation Techniques

[0043] Certain embodiments of the present invention generally relate to techniques for waveform generation that simultaneously utilizes plasma generation and ion energy distribution (IED) control to facilitate plasma processing of a substrate and reduce undesirable IED bowing profiles formed in etched high aspect ratio features. For example, a pulsed voltage (PV) waveform can be generated by overlaying an RF signal on the PV waveform. In some embodiments, the generated waveform can also include a ramp signal to facilitate current compensation, as described herein.

[0031]

[0044] FIG. 3A shows a typical IED using a single RF frequency excitation waveform. As shown, the IED has a bimodal shape with a high-energy peak 306, a low-energy peak 302, and intermediate-energy ions (e.g., associated with the intermediate-energy region 304). From the perspective of the plasma etching process, only ions at or near the high-energy peak have the energy and directionality to overcome the ion-generating charging effects created within the material being etched and reach the bottom of the feature to enable the etching reaction. Intermediate-energy ions are directionless and not beneficial to the etching process; they tend to strike the sidewalls of the feature, often resulting in an undesirable curved IED profile. Low-energy ions are important for the etching process because they clean the mask surface and maintain the shape of the mask layer, preventing hole clogging. Some embodiments of the present disclosure aim to create an energy profile with high and low energy peaks, with little or no intermediate energy between the high and low energy peaks.

[0032]

[0045] FIG. 3B is a graph illustrating an IED function (IEDF) in accordance with certain embodiments of the present disclosure. As shown, the IEDF includes a low-energy peak 301 and a high-energy peak 303. The energy associated with the low-energy peak can be less than a few hundred eV (e.g., less than 1 keV), while the energy associated with the high-energy peak can be from a few hundred eV to tens of thousands of eV, depending on the aspect ratio of the feature being formed on the substrate. For example, in some cases, the energy associated with the high-energy peak can be between 4 keV and 10 keV. As shown, there are no ions (or at least fewer than in conventional embodiments) between the lower-energy peak 301 and the higher-energy peak 303. Some embodiments relate to techniques for achieving the ion energy distribution shown in FIG. 3B using PV waveform tuning techniques, as described in more detail herein.

[0033]

[0046] 4A illustrates a PV waveform 400 generated using a waveform generator in accordance with certain embodiments of the present disclosure. As shown, the PV waveform 400 includes waveform regions 401 and 405. Waveform region 401 includes a direct current (DC) signal, and waveform region 405 includes a voltage step that can be used for ion current compensation.

[0034]

[0047] During a portion of the waveform region 401 within a pulse waveform cycle, plasma bulk electrons are attracted to the surface of a substrate (e.g., substrate 103) by the rising edge 402 of the PV waveform 400. As explained above, the substrate surface and the electrode (e.g., bias electrode 104) are coupled to a capacitive element (e.g., an electrostatic chuck capacitor (C esc ), which creates an equal amount of positive charge on the pole (compared to the negative charge on the substrate, for example) to counteract the electric field created by the accumulation of electrons provided by the bulk plasma.

[0035]

[0048] At the falling edge 403 of the PV waveform 400, the application of the PV waveform 400 to the electrodes causes the ions to be neutralized by electrons. Thus, a negative voltage V is established at the electrodes, creating a negative DC sheath potential Vdc is established at the substrate surface. This is the origin of the higher energy peak 303. The DC sheath potential (V dc ), or higher ion energy, is determined by the voltage drop (ΔV) at the falling edge 403 and C according to the following equation: esc and sheath capacitance (C sheath ) can be approximated using the ratio Thus, the waveform region 401 sustains a plasma in the chamber (e.g., while generating the lower energy peak 301) and creates a DC sheath potential V relative to the higher energy peak 303. dc It functions to establish

[0036]

[0049] Without ion compensation measures, the DC sheath potential V dc Therefore, the ions incident on the substrate surface are no longer monoenergetic due to the change in DC sheath potential. To compensate for the collection of positive charge on the substrate during the ion current stage found in waveform region 405, in some embodiments, the sheath potential V dc A voltage step is applied to the electrodes to compensate for changes in the sheath potential V dc In some embodiments, the voltage step applied to the bias electrode 104 in the waveform region 405 is divided into two or more substeps, each of which may have a constant duration Δt or may vary between substeps. In the first substep 406, which has a duration Δt, the total amount of positive charge ΔQ=I ion × Δt accumulates on the substrate surface, where the ion current (I ion ) is the electrode voltage (V) and sheath capacitance (C sheath )of TIFF0007736820000002.tif9170 can be calculated based on the time derivative as follows, and therefore the DC sheath potential V dc is ΔQ / C sheath The DC sheath potential V dcTo compensate for this change in C applies, where the voltage drop ΔV C teeth, Selected as TIFF0007736820000003.tif11170. The voltage drop ΔV applied during one or more substeps of the voltage step C The required quantity of is calculated using the known or measured ion current I ion can be determined from

[0037]

[0050] In some embodiments, the voltage drop ΔV of one or more substeps of the voltage step C The ion current I is used to determine ion is pre-measured by applying measurement waveform 399 (FIG. 4C) to the electrode. As shown in FIG. 4C, measurement waveform 399 includes waveform region 401 and measurement region 419. Measurement waveform 399 is first measured as it is provided to an electrode (e.g., bias electrode 104) by applying a voltage pulse to form waveform region 401. After falling edge 403 is formed, the time decay of the electrode voltage is measured during measurement region 419. Measurement waveform 399 may include one or more cycles that are used to calculate or estimate the uncompensated ion current due to the voltage decay (i.e., rate dV / dt) measured during at least a portion of the duration of measurement region 419, as shown by curve 418. The output voltage at the end of falling edge 403 is typically measured during this process so that it can be used as a reference voltage for the subsequent ion compensation stage seen in PV waveform 400 or 450.

[0038]

[0051] Therefore, the ionic current I ion Once determined, the duration Δt and voltage drop ΔV of each substep are calculated to compensate for the voltage decay produced by the ion current during the ion current stage of the PV waveform 400 or 450. Cis determined. Typically, the substeps formed approximate a linear compensation curve, such as curve 411 of FIG. 4A, during the ion current stage of the PV waveform 400 or 450, such that the portion of the waveform established at the substrate during plasma processing includes the square region shown by curve 230 of FIG. 2B. One or more software algorithms within the system controller 126 are used to measure and determine the ion current based on the measured waveform 399 and also to calculate the characteristics of each substep (e.g., duration Δt and voltage drop ΔV) used within the PV waveform 400 or 450 to compensate for the ion current. C ) can also be determined.

[0039]

[0052] In the first substep 406, the desired voltage drop ΔV C Once is determined, the voltage drop ΔV C is V1=V0−ΔV at the end of the first sub-step 406 (i.e., at the falling edge 407 of the waveform region 405). C In some embodiments, the voltage drop ΔV C The output of the first voltage source used to generate ΔV is a fixed voltage. In other embodiments, the output voltage of the first voltage source is determined by the determined voltage drop ΔV C to the desired set point by a command signal provided by the system controller 126 based on

[0040]

[0053] Similarly, in the second substep 408, the desired voltage drop ΔV C Once is determined, the voltage drop ΔV C At the end of the second sub-step 408 (i.e., at the falling edge 409 of the waveform region 405), V2=V1-ΔV C In one embodiment, the voltage drop ΔV applied at the falling edge 409 may be C is the voltage drop ΔV applied at the falling edge 407 C Therefore, voltage V2=V1-ΔV C=V0-2ΔV C However, in some embodiments, the voltage drop ΔV applied at the falling edge 409 C The magnitude of the voltage drop ΔV applied at the falling edge 407 C In some embodiments, the output of the second voltage source may be different from the voltage drop ΔV C In another embodiment, the output voltage of the first voltage source is set to a fixed voltage used to achieve the determined voltage drop ΔV C to the desired set point by a command signal provided by the system controller 126 based on

[0041]

[0054] 4A, two substeps 406 and 408 of equal duration Δt are included within the waveform region 405, and it should be noted that the number of substeps n within the waveform region 405 is not limited to two substeps. In some embodiments, the PV waveform 400 has n substeps within the waveform region 405, such that the electrodes receive V during the i-th substep (i=1, 2, ..., n). i =V0-(i-1)ΔV C In some embodiments, the number of substeps n in the waveform region 405 is 5 or less. i may be different for each substep (i=1, 2, ..., n), in which case the voltage drop at the end of the i-th substep is Determined by TIFF0007736820000004.tif13170.

[0042]

[0055] Voltage drop ΔV C The above equation used to determine ΔV does not include the effects of parasitic and stray capacitances, transmission line inductance, etc. Therefore, when modifying the coefficients based on different chamber designs and plasma conditions, it is necessary to consider the voltage drop ΔV to compensate for the change in DC sheath potential due to the positive charge accumulated on the substrate surface. C It should also be noted that the

[0043]

[0056] 5A illustrates an embodiment of a waveform generator 500 for biasing a substrate to achieve IED control in accordance with certain aspects of the present disclosure. In some embodiments, the waveform generator 500 is configured to generate a PV waveform 400 (FIG. 4A) that can be established at the bias electrode 104 or the support base 107. However, the waveform generator 500 may also be used to implement one or more of the waveform generator assemblies 150 described above with respect to FIG. 1.

[0044]

[0057] The waveform generator 500 includes a main voltage source 502 (e.g., a DC voltage source) for implementing a positive voltage during waveform region 401, a first compensation voltage source 505A (e.g., a first voltage source), and a second compensation voltage source 505B (e.g., a second voltage source) connected in parallel to implement a voltage step during waveform region 405. The waveform generator 500 generates the PV waveform 400 at an output node 504. In one example, the output node 504 is coupled to a bias electrode 104 in a substrate support 105 (e.g., a ceramic puck) or support base 107. When the output node 504 is coupled to the support base 107, the total capacitance C between the output node 504 and the substrate 103 is total (for example, TIFF0007736820000005.tif10170, where C SB is the capacitance of a dielectric layer disposed between the support base 107 and the bias electrode 104) is determined by the capacitance of the output node 504 relative to the bias electrode 104 (e.g., C esc ), resulting in a C esc The voltage drop across the wires may be small and the sheath voltage drop may be large.

[0045]

[0058] As shown in FIG. 5A , switch 520 (e.g., a high-voltage solid-state relay) is coupled between main voltage source 502 and output node 504, and switch 522 (e.g., a high-voltage solid-state relay) is coupled between ground node 508 and output node 504. Switch 523A and switch 523B are coupled between first compensation voltage source 505A and output node 504 and between second compensation voltage source 505B and output node 504, respectively. While FIG. 5A shows a configuration including two compensation voltage sources used to form the voltage steps, this configuration is not intended to limit the scope of the disclosure provided herein, as waveform generator 500 can include three or more waveform generators connected in parallel to form three or more sub-steps in the voltage steps. As described further below, the timing of the opening and closing of the various switches can be controlled by commands sent from system controller 126.

[0046]

[0059] 5B illustrates an implementation of a waveform generator 580 for biasing a substrate to achieve IED control in accordance with certain aspects of the present disclosure. In one embodiment, the waveform generator 580 is configured to generate a PV waveform 400 (FIG. 4A) that can be established at the bias electrode 104 or the support base 107. The waveform generator 580 may also be used to implement one or more of the waveform generator assemblies 150 described above with respect to FIG. 1.

[0047]

[0060] Waveform generator 580 includes a main voltage source 502 (e.g., a DC voltage source) for implementing a positive voltage during waveform region 401, a first compensation voltage source 505A (e.g., a first voltage source), and a second compensation voltage source 505B (e.g., a second voltage source) connected in series to enable the realization of voltage steps during waveform region 405. Waveform generator 580 generates PV waveform 400 at output node 504. Output node 504 may be coupled to substrate support 105 (e.g., a ceramic puck) or bias electrode 104 in support base 107. As shown in FIG. 5B , switch 520 (e.g., a high-voltage solid-state relay) is coupled between main voltage source 502 and output node 504, and switch 522 (e.g., a high-voltage solid-state relay) is coupled between ground node 508 and output node 504. Switch 523A is coupled between a first port of first compensation voltage source 505A and output node 504. Second compensation voltage source 505B is coupled between ground and switch 523B. Switch 523B is configured to selectively couple the second port of first compensation voltage source 505A to the ground node during the formation of falling edge 407, and then serially connects the first port of second compensation voltage source 505B to the second port of first compensation voltage source 505A, thereby coupling second compensation voltage source 505B and first compensation voltage source 505A during the formation of falling edge 409. As described further below, the timing of the opening and closing of the various switches can be controlled by commands sent from system controller 126. While FIG. 5B depicts two series-connected voltage sources forming a voltage step, this configuration is not intended to limit the scope of the disclosure provided herein, as waveform generator 580 can include three or more waveform generators connected in parallel to form three or more substeps in a voltage step. In a system configuration including three or more waveform generators, the connection between each adjacent pair of waveform generators would include a two-position switch, similar to switch 523B shown in FIG. 5B, allowing the series connection of each waveform generator to form each substep of the voltage staircase.

[0048] RF Overlay Configuration Example

[0061] FIG. 4B illustrates a PV waveform 450 generated using a waveform generator in accordance with certain embodiments of the present disclosure. As illustrated, the PV waveform 450 includes waveform regions 451 and 455. Waveform region 451 includes a direct current (DC) signal superimposed with an RF signal 454, and waveform region 455 includes a voltage step (e.g., for current compensation) overlaid with the RF signal 454. The RF signal 454 may also be overlaid on the voltage step signal during waveform region 455 to continue to maintain the plasma in the chamber (e.g., while generating the lower energy peak 301) and establish a DC sheath potential for the higher energy peak 303. While the example illustrated in FIG. 4B includes two substeps 456 and 458 having an equal duration Δt within waveform region 455, it should be noted that the number of substeps n within waveform region 455 is not limited to two substeps and may therefore include more or fewer substeps.

[0049]

[0062] The RF signal 454 is typically used to maintain the plasma in the chamber, producing the lower energy peak 301 described with respect to FIG. 3B. In some embodiments, the RF signal 454 can have a frequency between 40 MHz and 200 MHz. The frequency of the RF signal 454 may be higher than the ion sheath transition frequency, such as a frequency >40 MHz. In this case, the average ion transit time across the sheath thickness is longer than the period of the RF signal 454. As a result, ions experience multiple cycles of the RF signal 454 and acquire the average energy associated with the multiple cycles, producing the lower energy peak 301. Thus, ions are accelerated by the average sheath potential induced by the RF signal 454 such that a single ion energy peak is achieved. High-frequency RF excitation produces ions with a single energy peak. In other words, ions moving across the sheath are subjected to an average sheath potential driven by the RF signal 454, producing a single ion energy peak rather than a continuous energy distribution.

[0050]

[0063] 5C illustrates an embodiment of a waveform generator 550 for biasing a substrate to achieve IED control in accordance with certain aspects of the present disclosure. In some embodiments, the waveform generator 550 is configured to generate a PV waveform 450 (FIG. 4B) that can be established at the bias electrode 104 or the support base 107. The waveform generator 550 may be used to implement one or more of the waveform generator assemblies 150 described above with respect to FIG. 1.

[0051]

[0064] The waveform generator 550 includes a main voltage source 502 (e.g., a DC voltage source) for implementing a positive voltage during waveform region 401, a first compensation voltage source 505A (e.g., a DC voltage source) and a second compensation voltage source 505B (e.g., a DC voltage source) for implementing voltage steps during waveform region 405, and an RF generator 506 (also referred to as an RF signal generator) for providing an RF signal 454. The waveform generator 550 generates the PV waveform 450 at an output node 504. The output node 504 may be coupled to a bias electrode 104 in the substrate support 105 (e.g., a ceramic puck) or support base 107.

[0052]

[0065] 5C, RF filter 540 may be implemented in a path between main voltage supply 502 and switch 520, RF filter 542 may be implemented in a path between ground node 508 and switch 522, RF filter 544A may be implemented between first compensation voltage source 505A and output node 504, and RF filter 544B may be implemented between second compensation voltage source 505B and output node 504. RF filters 540, 542, 544A, 544B may be implemented as low-pass filters configured to block the RF signal provided from RF generator 506. Main voltage supply 502, first compensation voltage source 505A, and second compensation voltage source 505B are protected by respective RF filters 540, 544A, 544B from the output of RF generator 506. In other words, RF filters 540, 544A, 544B are configured to block the high frequency RF signal provided from RF generator 506. Ground node 508 is isolated from RF generator 506 by RF filter 542 (e.g., a low pass filter) when switch 522 is closed. In some embodiments, each of RF filters 540, 542, 544A, 544B may be implemented as a parallel LC topology, as shown in FIG.

[0053]

[0066] 6 shows a parallel LC filter topology 600 having a capacitive element 602 and an inductive element 604. As shown, capacitive element 602 may be coupled in parallel to inductive element 604 between nodes 610 and 612. Each of RF filters 540, 542, and 544 may be implemented using the parallel LC filter topology 600. For example, for RF filter 542, node 610 may be coupled to ground node 508, and node 612 may be coupled to switch 522. As an example, for a 40 MHz RF signal, capacitive element 602 may be 100 picofarads (pF) and inductive element 604 may be 158 nanohenries (nH) to reject the 40 MHz RF signal. In other words, the parallel LC filter topology 600 is a resonant circuit that effectively acts as an open circuit to the 40 MHz signal, isolating the main voltage source 502, the ground node 508, the first compensation voltage source 505A, or the second compensation voltage source 505B from the 40 MHz RF signal.

[0054] Waveform generation example

[0067] 7 is a timing diagram 700 illustrating the states of switch 520 (labeled “S1”), switch 522 (labeled “S2”), switch 523A (labeled “S3”), and switch 523B (labeled “S4”) in accordance with certain embodiments of the present disclosure. Generally, during operation, switches 520, 523A, 523B are not closed at the same time as switch 522 (S2) to avoid electrically shorting primary voltage source 502, first compensation voltage source 505A, and / or second compensation voltage source 505B to ground node 508. While the following description primarily discloses a switch timing process performed on a system including waveform generator 500 that forms PV waveform 400, this configuration is not intended to limit the scope of the disclosure provided herein, as the switch timing process may also be implemented on a system including waveform generator 550 that forms PV waveform 450.

[0055]

[0068] 4A, 5A, and 7, in some embodiments, during phase 1 of a waveform cycle (e.g., a cycle of the PV waveform 400), the switch 520 (S1) can be closed to generate the rising edge 402 as shown in FIG. 4A. The switch 520 (S1) can be closed for a period ranging from 20 ns to 2000 ns to allow a sufficient number of electrons to collect at the substrate surface. After the period associated with the waveform region 401, the switch 520 (S1) can be opened and the switch 522 (S2) can be closed to connect the output node 504 to ground and generate the falling edge 403 during phase 2 of the waveform cycle. After the switch 520 (S1) is opened, the switch 522 (S2) can be closed for a period ranging from 10 ns to 100 ns.

[0056]

[0069] In some embodiments, during phase 1 when switch 520 (S1) is closed, negative charge accumulates on substrate 103 shown in FIG. 1 . The voltage drop across the capacitor formed by bias electrode 104 on substrate 103 and substrate 103 cannot change instantaneously due to capacitive effects. Therefore, in phase 2, when switch 520 (S1) opens and switch 522 (S2) closes, the voltage at output node 504 (e.g., bias electrode 104 shown in FIG. 1 ) drops from a positive voltage to zero (ground potential) as switch 522 grounds bias electrode 104, as shown in FIG. 4A . In other words, the positive charge on bias electrode 104 attracts electrons from ground, causing a drop to a negative voltage V0 at the substrate surface of output node 504 when switch S2 closes.

[0057]

[0070] After reaching the time period associated with the first substep 406 of the waveform region 405 (i.e., duration Δt), switch 522 (S2) can be opened and switch 523A (S3) can be closed to generate the falling edge 407 during phase 3 of the waveform cycle. After opening switch 522 (S2), switch 523A (S3) can be closed for a period ranging from 100 ns to 1000 ns. During phase 3 of the waveform cycle, both switches 520, 522 remain open and switch 523A is closed, allowing the first compensation voltage source 505A to be connected to the output node 504 (e.g., the chamber).

[0058]

[0071] After reaching the time period associated with substep 408 of waveform region 405 (i.e., duration Δt), switch 523A (S3) can be opened and switch 523B (S4) can be closed to generate falling edge 409 during phase 4 of the waveform cycle, as shown in FIG. 4. In one embodiment, the magnitude of the output of second compensation module 502B is multiplied by the voltage applied at falling edge 407 to generate falling edge 409 (i.e., V = V - ΔV C1 -ΔV C2 ) the additional voltage drop ΔV that will be applied during C After opening switch 523A (S3), switch 523B (S4) may be closed for a period ranging from 100 ns to 2000 ns. During phase 4 of the waveform cycle, switches 520 and 522 both remain open and switch 523B is closed.

[0059]

[0072] 7 is modified so that switch 523A (S3) remains closed, while switch 523B (S4) is used to couple the first compensation voltage source 505A and the second compensation voltage source 505B together during phase 4 of the waveform cycle. At the end of phase 4, switch 523A is open and switch 523B is switched to a position that grounds the first compensation voltage source 505A, either for or in preparation for the waveform cycle to repeat.

[0060]

[0073] Embodiments of the present disclosure provide advantageous process dual-peak IEDs and methods for simultaneously exciting and sustaining a plasma and achieving such an IED at a substrate surface in a plasma processing chamber. One advantage of embodiments of the present disclosure over conventional ion energy control techniques is the ability to simultaneously generate plasma and control the IED. After one cycle of the PV waveform is completed, multiple additional PV waveform cycles are repeated consecutively, as shown in FIGS. 4A-4C by partial views of a repeating second voltage waveform cycle. In some embodiments, the voltage waveform established at the electrodes has an on-time, which is the time period between the ion current (e.g., the length of the waveform region 405) and the waveform period T P (e.g., the length of waveform region 401 plus the length of waveform region 405), and is greater than 50%, or greater than 70%, such as between 80% and 95%. In some embodiments, the period T P A PV waveform having a waveform cycle having a .times. ...

[0061]

[0074] 8 is a process flow diagram illustrating a method 800 of waveform generation. Method 800 may be performed by a waveform generation system including a waveform generator, such as waveform generator 500, and / or a system controller, such as system controller 126.

[0062]

[0075] In operation 802, the waveform generation system couples a primary voltage source (e.g., primary voltage source 502) to an output node (e.g., output node 504) (e.g., by closing switch 520) for about 20 ns to about 2000 ns during a first phase (e.g., phase 1 shown in FIG. 7) of a PV waveform (e.g., PV waveform 400). The output node may be coupled to an electrode disposed within a processing chamber (e.g., processing chamber 100). For example, the output node may be coupled to bias electrode 104 or support base 107.

[0063]

[0076] In operation 804, the waveform generation system couples a ground node (e.g., ground node 508) to an output node (e.g., by closing switch 522) for between about 10 ns and about 100 ns during a second phase of the waveform (e.g., phase 2 shown in FIG. 7). As described above, closing switch 522 creates falling edge 403.

[0064]

[0077] In operation 806, the waveform generation system couples the first compensation voltage source (e.g., first compensation voltage source 505A) to the output node (e.g., by closing switch 523A) for between about 100 ns and about 2000 ns during the third phase of the waveform (e.g., phase 3 shown in FIG. 7). Thus, when switch 523A is closed and switch 522 is open, falling edge 407 is formed.

[0065]

[0078] In operation 808, the waveform generation system couples the second compensation voltage source (e.g., second compensation voltage source 505B) to the output node (e.g., by closing switch 523B) for between about 100 ns and about 2000 ns during the fourth phase of the waveform (e.g., phase 4 shown in FIG. 7). When using the configuration of waveform generator 500 or waveform generator 550 shown in FIG. 5A or 5C, therefore, falling edge 407 is formed when switch 523B is closed and switch 523A is open.

[0066]

[0079] In some embodiments including waveform generator 550, an RF signal generator (e.g., RF generator 506) is coupled to the output node through a filter (e.g., high-pass filter 546) during the first stage. The RF signal generator may be coupled to the output node during the first, second, third, and fourth phases of the waveform. The main voltage supply and ground node are decoupled from the output node (e.g., by opening switches 520, 522) during the third and fourth phases. In some embodiments, the main voltage supply is coupled to the output node through a filter (e.g., RF filter 540) and the ground node is coupled to the output node through a filter (e.g., RF filter 542).

[0067]

[0080] In some embodiments, two or more compensation voltage sources (e.g., first compensation voltage source 505A and second compensation voltage source 505B) are coupled to the output node during the third and fourth phases of the waveform, respectively, and the main voltage supply and ground nodes are decoupled from the output node during the third and fourth phases. The first and second compensation voltage sources may each be coupled to the output node through a filter (e.g., RF filter 544).

[0068]

[0081] The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B physically contacts object C, objects A and C can still be considered to be coupled to each other even if they are not in direct physical contact with each other. For example, a first object can be coupled to a second object even if the first object is not in direct physical contact with the second object.

[0069]

[0082] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A waveform generator for generating a pulse voltage waveform for plasma processing, comprising: a main voltage source selectively coupled to the output node during a first phase to generate a pulsed voltage waveform, the output node is configured to be coupled to an electrode disposed within a processing chamber; the primary voltage source, the output node being selectively coupled to a ground node during a second phase of the generated pulsed voltage waveform following the first phase; a first compensation voltage source selectively coupled to the output node during a third phase of the generated pulsed voltage waveform following the second phase; a second compensation voltage source selectively coupled to the output node during a fourth phase of the generated pulsed voltage waveform following the third phase; 1. A waveform generator comprising:

2. a first switch configured to couple the main voltage source to the output node during the first phase of the generated pulsed voltage waveform; a second switch configured to couple the ground node to the output node during the second phase of the generated pulsed voltage waveform; and a third switch configured to couple the first compensation voltage source to the output node during the third phase of the generated pulsed voltage waveform.

10. The waveform generator of claim 1, further comprising:

3. 3. The waveform generator of claim 2, further comprising a fourth switch configured to couple the second compensation voltage source to the output node during the fourth phase of the generated pulsed voltage waveform.

4. 3. The waveform generator of claim 2, further comprising a fourth switch configured to selectively couple the first compensation voltage source to ground during the third phase of the generated pulsed voltage waveform and to selectively couple the second compensation voltage source to the output node during the fourth phase of the generated pulsed voltage waveform.

5. a radio frequency (RF) signal generator; and 10. The waveform generator of claim 1, further comprising a first filter coupled between the RF signal generator and the output node.

6. a second filter coupled between the ground node and the output node; a third filter coupled between the main voltage source and the output node; a fourth filter coupled between the first compensation voltage source and the output node; and 6. The waveform generator of claim 5, further comprising a fifth filter coupled between the second compensation voltage source and the output node.

7. 2. The waveform generator of claim 1, wherein the main voltage source, the first compensation voltage source, and the second compensation voltage source each comprise a direct current (DC) voltage source.

8. 1. A method for generating a pulsed voltage waveform, comprising: coupling a main voltage source to an output node coupled to an electrode disposed within the processing chamber during a first phase of generating a pulsed voltage waveform; coupling a ground node to the output node during a second phase of the generated pulsed voltage waveform following the first phase; coupling a first compensation voltage source to the output node during a third phase of the generated pulsed voltage waveform following the second phase; coupling a second compensation voltage source to the output node during a fourth phase of the generated pulsed voltage waveform following the third phase; A method comprising:

9. coupling a first port of the first compensation voltage source to the ground node and a second port of the output node during the third phase; and coupling the first port of the first compensation voltage source to the second compensation voltage source during the fourth phase; The method of claim 8 further comprising:

10. the first phase of the generated pulsed voltage waveform is between 20 ns and 2000 ns; the second phase of the generated pulsed voltage waveform is between 10 ns and 100 ns; the third phase of the generated pulsed voltage waveform is between 100 ns and 2000 ns; 9. The method of claim 8, wherein the fourth phase of the generated pulsed voltage waveform is between 100 ns and 2000 ns.

11. 9. The method of claim 8, wherein an RF signal generator is coupled to the output node during the first phase, the second phase, the third phase, and a fourth phase of the generated pulsed voltage waveform.

12. the RF signal generator is coupled to the output node through a first filter; the ground node is coupled to the output node through a second filter; the main voltage source is coupled to the output node through a third filter; the first compensation voltage source is coupled to the output node through a fourth filter; and 12. The method of claim 11, wherein the second compensation voltage source is coupled to the output node through a fifth filter.

13. The method of claim 11 , wherein the main voltage source, the first compensation voltage source, and the second compensation voltage source each comprise a direct current (DC) voltage source.

14. 1. An apparatus for waveform generation, comprising: an electrode in the processing chamber; a main voltage source; a first compensation voltage source; a second compensation voltage source; When executed by a processor, the apparatus coupling the main voltage source to the electrodes during a first phase of a process for forming a pulsed voltage waveform; coupling the electrode to a ground node during a second phase of the pulsed voltage waveform following the first phase; coupling the first compensating voltage source to the electrode during a third phase of the pulsed voltage waveform following the second phase; and Following the third phase, coupling the second compensating voltage source to the electrode during a fourth phase of the pulsed voltage waveform. a non-volatile memory in which program information containing instructions for causing the 1. An apparatus comprising:

15. The instructions, when executed by a processor, coupling the first compensation voltage source to the ground node during the third phase; and coupling the first compensation voltage source to the second compensation voltage source during the fourth phase; The apparatus of claim 14 , further comprising:

16. the first phase of the pulse voltage waveform is between 20 ns and 2000 ns; the second phase of the pulse voltage waveform is between 10 ns and 100 ns; the third phase of the pulse voltage waveform is between 100 ns and 2000 ns; 15. The apparatus of claim 14, wherein the fourth phase of the pulsed voltage waveform is between 100 ns and 2000 ns.

17. 15. The apparatus of claim 14, further comprising an RF signal generator coupled to the electrodes during the first phase, the second phase, the third phase, and the fourth phase of the pulsed voltage waveform.

18. the RF signal generator is coupled to the electrode through a first filter; the ground node is coupled to the electrode through a second filter; the main voltage source is coupled to the electrode through a third filter; the first compensation voltage source is coupled to the electrode through a fourth filter; and 18. The apparatus of claim 17, wherein the second compensation voltage source is coupled to the electrode through a fifth filter.

19. 15. The apparatus of claim 14, wherein the main voltage source, the first compensation voltage source, and the second compensation voltage source each comprise a direct current (DC) voltage source.

20. A waveform generator for generating a pulsed voltage waveform for plasma processing, comprising: a primary voltage source selectively coupled to the output node, the output node is configured to be coupled to an electrode disposed within a processing chamber; the primary voltage source, the output node of which is selectively coupled to a ground node; a first compensation voltage source selectively coupled to the output node; a second compensation voltage source selectively coupled to the output node; a radio frequency (RF) signal generator; a first filter coupled between the RF signal generator and the output node; a second filter coupled between the ground node and the output node; a third filter coupled between the main voltage supply and the output node; a fourth filter coupled between the first compensation voltage source and the output node; a fifth filter coupled between the second compensation voltage source and the output node; 1. A waveform generator comprising:

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