Comparator Integration Time Stabilization Technique Using Common-Mode Mitigation

Abstract

Aspects of the disclosure provide a method for adjusting an integrated current (Im at node 122) of a sense amplifier (110). The sense amplifier (110) includes a first input transistor (120) and a second input transistor (125), with a source of the first input transistor and a source of the second input transistor coupled to a source node (122). The method includes sinking a current (Is) from or sourcing a current to the source node (122), measuring (305) the integrated current (Im), comparing (310) the measured integrated current (node ​​312) to a reference signal (node ​​314), and adjusting (315) the current drawn from or sourced to the source node based on the comparison (signal 318).

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Nonprovisional Patent Application No. 17 / 453,967, filed with the U.S. Patent and Trademark Office on November 8, 2021, the entire contents of which are incorporated herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to amplifiers, and more particularly to sense amplifiers. [Background technology]

[0003] Sense amplifiers are used in a wide range of applications, including in high-speed serializers / deserializers (SerDes), memories, analog-to-digital converters, and data samplers. In a system, a sense amplifier may be used in conjunction with a comparator to determine (i.e., recover) a bit from a differential signal including a first input signal (e.g., a first input voltage) and a second input signal (e.g., a second input voltage). For each bit, the sense amplifier may integrate the first input signal and the second input signal during a sensing phase, and the comparator may determine (i.e., make) the bit based on the integrated signal. As data rates increase, it is desirable for the sense amplifier and comparator to determine data bits at a stable rate over varying conditions (e.g., varying common-mode voltage) to meet stringent timing constraints (e.g., hold time and / or setup time) in the system. Summary of the Invention

[0004] SUMMARY OF THE INVENTION The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] A first aspect relates to an apparatus. The apparatus includes an error amplifier having a first input, a second input, and an output. The apparatus also includes a sense amplifier including a first transistor and a second transistor, where the source of the first transistor and the source of the second transistor are coupled to a common source node. The apparatus also includes a first current control device coupled to the common source node, where the first current control device has a control input coupled to the output of the error amplifier. The apparatus also includes a replica circuit coupled to the first input of the error amplifier, where the replica circuit includes a third transistor replicating one of the first transistor and the second transistor. The apparatus also includes a second current control device coupled to the source of the third transistor, where the second current control device has a control input coupled to the output of the error amplifier. The apparatus further includes a reference circuit coupled to the second input of the error amplifier, where the reference circuit is configured to output a reference signal.

[0006] A second aspect relates to a method for adjusting an integration current of a sense amplifier, the sense amplifier including a first input transistor and a second input transistor, the source of the first input transistor and the source of the second input transistor coupled to a source node, the method including sinking or sourcing a current from or to the source node, measuring the integration current, comparing the measured integration current to a reference signal, and adjusting the current drawn from or sourced to the source node based on the comparison. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 illustrates an example of a sense amplifier in accordance with certain aspects of the present disclosure. [Figure 2] FIG. 4 is a timing diagram illustrating an example of voltages at a sense amplifier during an integration phase, in accordance with certain aspects of the present disclosure. [Figure 3] FIG. 2 illustrates an example of a feedback circuit coupled to a sense amplifier in accordance with certain aspects of the present disclosure. [Figure 4] FIG. 2 illustrates an exemplary implementation of a reference circuit in accordance with certain aspects of the present disclosure. [Figure 5] FIG. 2 illustrates an example of a feedback circuit coupled to a sense amplifier in accordance with certain aspects of the present disclosure. [Figure 6] FIG. 2 illustrates an example circuit configured to apply a common-mode voltage to the gates of input transistors, in accordance with certain aspects of the present disclosure. [Figure 7A] FIG. 2 illustrates an example of multiple sense amplifiers coupled to a feedback circuit, in accordance with certain aspects of the present disclosure. [Figure 7B] FIG. 10 illustrates another example of multiple sense amplifiers coupled to a feedback circuit in accordance with certain aspects of the present disclosure. [Figure 7C] FIG. 2 illustrates an example of a receiver coupled to multiple sense amplifiers in accordance with certain aspects of the present disclosure. [Figure 8] FIG. 1 illustrates an example of a system in which aspects of the present disclosure may be used in accordance with certain aspects of the present disclosure. [Figure 9] 4 is a flowchart illustrating an exemplary method for adjusting an integration current of a sense amplifier, in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0009] FIG. 1 illustrates an example of a sense amplifier 110 according to certain embodiments of the present disclosure. The sense amplifier 110 may also be referred to as a sense amplifier, a sensing stage, or other terminology. The sense amplifier 110 includes a first input transistor 120, a second input transistor 125, a first switch 115, a second switch 130, and a third switch 135. In the example of FIG. 1, each of the input transistors 120 and 125 is implemented with a respective p-type field effect transistor (PFET). However, it should be understood that each of the input transistors 120 and 125 may be implemented using another type of transistor.

[0010] In the example shown in FIG. 1, the sources of input transistors 120 and 125 are coupled at a common source node 122, and a first switch 115 couples the common source node 122 to a supply voltage V DDA second switch 130 is coupled between the drain of the first input transistor 120 and ground, and a third switch 135 is coupled between the drain of the second input transistor 125 and ground. The sense amplifier 110 has a first input 112 coupled to the gate of the first input transistor 120 and a second input 114 coupled to the gate of the second input transistor 125. The sense amplifier 110 also has a first integration node 140 located at the drain of the first input transistor 120 and a second integration node 145 located at the drain of the second input transistor 125. The first integration node 140 is coupled to a first output 146 of the sense amplifier 110, and the second integration node 145 is coupled to a second output 148 of the sense amplifier 110.

[0011] First switch 115 has control input 116, second switch 130 has control input 132, and third switch 135 has control input 136. As used herein, a "control input" of a switch is an input that controls the on / off state of the switch based on a signal (e.g., the voltage of the signal) applied to the control input. In examples where the switches are implemented with transistors, the control input is located at the gate of the transistor. In the example shown in FIG. 1 , first switch 115 is implemented with a PFET 118, second switch 130 is implemented with an n-type field effect transistor (NFET) 134, and third switch 135 is implemented with an NFET 138. However, it should be understood that the present disclosure is not limited to this example, and each of switches 115, 130, and 135 may be implemented using another type of switch (e.g., a transmission gate). 1, the control input 116 of the first switch 115, the control input 132 of the second switch 130, and the control input 136 of the third switch 135 are driven by a clock signal (labeled "clk") from a timing circuit 190. The timing circuit 190 may include a clock generator (e.g., a phase-locked loop (PLL)), a clock recovery circuit configured to recover a clock signal from a data signal or a control signal, or another type of timing circuit.

[0012] 1, sense amplifier 110 is coupled to a comparator 150 (also called a latch circuit) configured to resolve a bit value based on the voltage at a first integration node 140 (labeled "vintegn") and a voltage at a second integration node 145 (labeled "vintegp") of sense amplifier 110. In this example, comparator 150 has a first input 152 coupled to first integration node 140 and a second input 154 coupled to second integration node 145.

[0013] Comparator 150 includes a first inverter circuit 170 and a second inverter circuit 175 that are cross-coupled to each other to provide a regenerative gain that enables comparator 150 to quickly resolve bit values, as described further below. More specifically, an output 174 of first inverter circuit 170 is coupled to an input 176 of second inverter circuit 175, and an output 178 of second inverter circuit 175 is coupled to an input 172 of first inverter circuit 170.

[0014] 1, each of the drive transistors 160 and 165 is implemented with a PFET. However, it should be understood that the drive transistors 160 and 165 are not limited to this example. In this example, the source of the first drive transistor 160 is coupled to the supply rail, the gate of the first drive transistor 160 is coupled to the first input 152 of the comparator 150 (and thus the first integration node 140), and the drain of the first drive transistor 160 is coupled between the output 174 of the first inverter circuit 170 and the input 176 of the second inverter circuit 175. The source of the second drive transistor 165 is coupled to the supply rail, the gate of the second drive transistor 165 is coupled to the second input 154 of the comparator 150 (and therefore the second integration node 145), and the drain of the second drive transistor 165 is coupled between the output 178 of the second inverting circuit 175 and the input 172 of the first inverting circuit 170.

[0015] Comparator 150 has a first output 180 and a second output 185. In one example, first output 180 outputs a resolved bit and second output 185 outputs the complement of the resolved bit, or vice versa. First output 180 and second output 185 are coupled to subsequent stages (e.g., set-reset (SR) latches), as described further below.

[0016] An exemplary operation of the sense amplifier 110 and the comparator 150 according to certain aspects will now be discussed.

[0017] The first input 112 and the second input 114 of the sense amplifier 110 receive a differential input voltage from a previous stage (not shown), such as an equalizer. The differential input voltage includes an input voltage v p applied to the gate of the first input transistor 120 and an input voltage v i n applied to the gate of the second input transistor 125. In certain embodiments, the polarity of the differential input voltage represents a bit value. For example, the differential input voltage may represent a bit value of 1 when the input voltage v i p is greater than the input voltage v i n and a bit value of 0 when the input voltage v i p is less than the input voltage v i n. The gates of the input transistors 120 and 125 may also be biased by a common-mode voltage, which may be a DC voltage that is common to both inputs 112 and 114 of the sense amplifier 110. The common-mode voltage may originate from the output of the previous stage (e.g., an equalizer).

[0018] In this example, the sense amplifier 110 is in the reset phase when the clock signal is high. During the reset phase, the first switch 115 is turned off, and the second switch 130 and the third switch 135 are turned on. As a result, the second switch 130 pulls the first integration node 140 to ground, and the third switch 135 pulls the second integration node 145 to ground. During the reset phase, the first drive transistor 160 and the second drive transistor 165 in the comparator 150 are turned on. This is because the integration nodes 140 and 145 are pulled low (i.e., to ground) during the reset phase, and the drive transistors 160 and 165 are implemented with PFETs in this example.

[0019] The sense amplifier 110 enters the integration phase (also called the sensing phase) when the clock signal transitions low. During the integration phase, the first switch 115 is turned on, and the second switch 130 and the third switch 135 are turned off. By turning on the first switch 115, the integration current I M is allowed to flow from the supply rail through the first switch 115 via the common source node 122 to the sources of the input transistors 120 and 125. M is divided between the first input transistor 120 and the second input transistor 125, resulting in an integrated current I M A portion of flows through the first input transistor 120 to the first integration node 140, resulting in an integrated current I M Another portion of flows through the second input transistor 125 to the second integration node 145, increasing the voltages vintegn and vintegp at the integration nodes 140 and 145, respectively.

[0020] In this regard, Figure 2 shows an example of the rise of voltages Vintegn and Vinteggp at integration nodes 140 and 145, respectively, during the integration phase. In this example, the input voltage Vinn is lower than the input voltage Vinp. As a result, the source-to-gate voltage of the second input transistor 125 is greater than the source-to-gate voltage of the first input transistor 120, and in this example, the integration current IM A larger portion of the integrated current I flows through the second input transistor 125 to the second integration node 145. M flows to the second integration node 145, so that in this example, the voltage vintegp at the second integration node 145 rises faster than the voltage vintegn at the first integration node 140, as shown in FIG.

[0021] At the beginning of the integration phase at time t1, both drive transistors 160 and 165 are turned on because integration voltages Vintegn and Vintegp are initially less than the turn-off voltage 210 to turn off drive transistors 160 and 165. Because drive transistors 160 and 165 are implemented with PFETs in this example, the turn-off voltage 210 to turn off drive transistors 160 and 165 is given by Vdd-Vt, where Vdd is the power source voltage and Vt is the threshold voltage of each of drive transistors 160 and 165. When integration voltage Vintegp rises above turn-off voltage 210 at time t2, second drive transistor 165 turns off. At this time, as shown in FIG. 2, first drive transistor 160 is still turned on because integration voltage Vintegn is still less than turn-off voltage 210. By turning off second drive transistor 165, cross-coupled first inverter circuit 170 and second inverter circuit 175 in comparator 150 latch a 1 at first output 180 and a 0 at second output 185. Thus, comparator 150 determines a bit value of 1 at first output 180 when integrated voltage vintegp rises to turn-off voltage 210 before integrated voltage vintegn. In this example, the integration time of comparator 150 is given by the time it takes for integrated voltage vintegp to reach turn-off voltage 210, as shown in FIG. 2.

[0022] In the example shown in FIG. 2, the input voltage vinn is lower than the input voltage vinp. In the example where the input voltage vinp is lower than the input voltage vinn, the integral current I MA larger portion of flows to the first integration node 140 during the integration phase, causing the voltage vintegn at the first integration node 140 to rise faster. In this example, the integration voltage vintegn rises to the turn-off voltage 210 before the integration voltage vintegp, causing the comparator 150 to determine a bit value of 0 at the first output 180.

[0023] In the above example, the integration time is the time it takes for either the integrated voltage Vintegp or the integrated voltage Vintegn to reach the turn-off voltage 210, depending on which of the input voltages Vintegp and Vintegn is lower. Once one of the integrated voltages Vintegp and Vintegn reaches the turn-off voltage 210, the comparator 150 determines a bit value of 1 or 0 (i.e., makes a bit decision) at the first output 180, depending on which of the integrated voltages Vintegp and Vintegn rises to the turn-off voltage 210 faster. Thus, the integration time determines how long it takes before the comparator 150 determines a bit value (i.e., makes a bit decision), and therefore determines the speed at which the bit decision is made.

[0024] The integration time is determined by the integration current I M This is because the integral current I M This is because the integral current I M The higher the integral current I, the faster the rise time and therefore the shorter the integral time. M The lower the , the slower the rise time and therefore the longer the integration time.

[0025] The problem is the integral current I MThe problem with this is that the integration time depends on the transconductance of the input transistors 120 and 125, which varies with the common-mode voltage (e.g., from a previous stage) applied to the gates of the input transistors 120 and 125. As a result, the integration time varies with changes in the common-mode voltage, making it difficult to stabilize the integration time against variations in the common-mode voltage. Therefore, in order to maintain a stable integration time over various conditions (e.g., variations in the common-mode voltage), the integration current I of the sense amplifier 110 is M It is desirable to design a method for adjusting the

[0026] 3 illustrates an exemplary feedback circuit 305 according to certain aspects of the present disclosure. The feedback circuit 305 is coupled to the common source node 122 (i.e., the sources of the input transistors 120 and 125 of the sense amplifier 110). The feedback circuit 305 controls the integrated current I of the sense amplifier 110, as will be described further below. M to stabilize the integration time over variations in common mode voltage.

[0027] The feedback circuit 305 includes an error amplifier 310, a replica circuit 330, a reference circuit 350, a first current control device 315, a second current control device 325, and a switch 320. In the example shown in FIG. 3 , the switch 320 is coupled between the common source node 122 and the first current control device 315, and a control input 322 of the switch 320 is driven by a clock signal clk. In this example, the switch 320 is configured to couple the first current control device 315 to the common source node 122 during the integration phase and to decouple the first current control device 315 from the common source node 122 during the reset phase. In the example shown in FIG. 3 , the switch 320 is implemented with a PFET 324, and the gate of the PFET 324 is coupled to the timing circuit 190 and driven by the clock signal clk. However, it should be understood that the switch 320 is not limited to this example and that the switch 320 may be implemented using another type of switch.

[0028] The first current control device 315 receives a current (I S 3. The first current control device 315 is configured to sink a current (e.g., a differential amplifier) ​​from the common source node 122 based on a signal (e.g., a voltage) input to the control input 318. In the example of FIG. 3, the control input 318 is coupled to the output 316 of the error amplifier 310. Thus, in this example, the amount of current that the first current control device 315 draws from the common source node 122 is controlled by the output 316 of the error amplifier 310. It should be understood that the first current control device 315 may also be referred to as an adjustable current source or by another term.

[0029] The current I that the first current control device 315 draws from the common source node 122 S The amount of current that flows from the common source node 122 to the integrating nodes 140 and 145 affects the amount of current that flows from the common source node 122 to the integrating nodes 140 and 145, and therefore the amount of integrated current I M (This integrated current is approximately equal to the sum of the currents flowing through the integration nodes 140 and 145). Based on this relationship, the first current control device 315 controls the integrated current I M For example, the integral current I M To decrease , the error amplifier 310 may increase the amount of current that the first current control device 315 draws from the common source node 122. This decreases the integrated current I by drawing more current away from the integrating nodes 140 and 145. M Decrease the integral current I M To increase , the error amplifier 310 may decrease the amount of current that the first current control device 315 draws from the common source node 122.

[0030] The replica circuit 330 outputs an integral current I M Replica current (I cm ” (labeled “I”), the integrated current I of the sense amplifier 110M As explained further below, the replica current I cm is the integrated current I caused by changes in the common-mode voltage at the inputs 112 and 114 of the sense amplifier 110. M This allows you to track changes in

[0031] In this example, replica circuit 330 includes a switch 335, a third input transistor 340, and a current sensing resistor 345. Switch 335 is connected to a supply rail V DD and the source of a third input transistor 340 (eg, a PFET), and a current sense resistor 345 is coupled between the drain of the third input transistor 340 and ground.

[0032] Switch 335 corresponds to the first switch 115 in sense amplifier 110. In the example shown in Figure 3, switch 335 is implemented with a PFET 338 that is always on by coupling the control input 336 of switch 335 (and therefore the gate of PFET 338) to ground.

[0033] The third input transistor 340 may be a replica of one of the first input transistor 120 and the second input transistor 125 of the sense amplifier 110. In particular aspects, the third input transistor 340 may be a scaled-down version of one of the first input transistor 120 and the second input transistor 125. For example, the third input transistor 340 may have one or more dimensions (e.g., gate width and / or gate length) that are scaled down (i.e., reduced) from one or more dimensions of one of the first input transistor 120 and the second input transistor 125.

[0034] The gate of third input transistor 340 is biased by the same common-mode voltage (labeled "Vcm") as the gates of input transistors 120 and 125 of sense amplifier 110. Exemplary techniques for coupling the common-mode voltage Vcm to the gate of third input transistor 340, according to certain embodiments, are described below. Because third input transistor 340 is biased by the same common-mode voltage Vcm as input transistors 120 and 125 of sense amplifier 110, replica current I cm is the integrated current I of the sense amplifier 110 M is equal to or proportional to the integral current I M This allows the replica current I cm Using the integral current I M In an example where the third input transistor 340 is a scaled down version of one of the first input transistor 120 and the second input transistor 125, the replica current I cm is the integral current I M (i.e., the integral current I M (Approximately equal to multiplied by a proportionality factor less than 1).

[0035] In this example, the third input transistor 340 in the replica circuit 330 replicates one of the first input transistor 120 and the second input transistor 125. This is possible because the replica circuit 330 replicates the integrated current I caused by changes in the common-mode voltage. M , and the common-mode voltage is common to both input transistors 120 and 125 (i.e., the common-mode voltage is applied to the gates of both input transistors 120 and 125). However, it should be understood that replica circuit 330 is not limited to this example. For example, in other implementations, replica circuit 330 may include two input transistors that replicate both input transistors 120 and 125.

[0036] Replica current Icm flows through a current sense resistor 345 coupled between the drain of the third input transistor 340 and ground. The current sense resistor 345 detects the replica current I flowing through the third input transistor 340. cm into a corresponding measurement signal. In this example, the measurement signal is the replica current I cm is a voltage approximately equal to the resistance of the current sense resistor 345 multiplied by the resistance of the current sense resistor 345.

[0037] The second current control device 325 is coupled to a source node 342 of the replica circuit 330, which in turn is coupled to the source of the third input transistor 340. The second current control device 325 couples a current ("I") from the source node 342 of the replica circuit 330. R 3 , the control input 328 is coupled to the output 316 of the error amplifier 310. Thus, in this example, the amount of current that the second current control device 325 draws from the source node 342 of the replica circuit 330 is controlled by the output 316 of the error amplifier 310. It should be understood that the second current control device 325 may also be referred to as an adjustable current source or by another term.

[0038] As will be further explained below, the error amplifier 310 uses a second current control device 325 to control the replica current I cm For example, adjust the replica current I cm To decrease replica current I, the error amplifier 310 may increase the amount of current that the second current control device 325 draws from the source node 342 of the third input transistor 340. This may increase replica current I by drawing more current from the source node 342. cm, causing less current to flow through the third input transistor 340 to the current sense resistor 345. cm To increase , the error amplifier 310 may decrease the amount of current that the second current control device 325 draws from the source node 342.

[0039] Reference circuit 350, as described further below, is configured to generate a reference signal (e.g., a reference voltage) that represents a target integration current for sense amplifier 110. Reference circuit 350 outputs the reference signal at output 352 of reference circuit 350. An exemplary implementation of reference circuit 350 is further described below with reference to FIG.

[0040] 3, a current sense resistor 345 is coupled between the first input 312 of the error amplifier 310 and ground. Thus, in this example, the measurement signal from the replica circuit 330 is provided by the voltage across the current sense resistor 345, which is a voltage proportional to the replica current I cm multiplied by the resistance of current sense resistor 345. A second input 314 of error amplifier 310 is coupled to an output 352 of reference circuit 350 to receive a reference signal from reference circuit 350.

[0041] As will be further described below, the error amplifier 310 controls the integrated current I of the sense amplifier 110 based on the reference signal and the measurement signal using a first current control device 315. M and the error amplifier 310 adjusts the replica current I of the replica circuit 330 based on the reference signal and the measurement signal using a second current control device 325. cm The error amplifier 310 adjusts the integrated current I of the sense amplifier 110 using a first current control device 315. MSimilar to adjusting the replica current I of the replica circuit 330 using the second current control device 325, cm As will be explained further below, this is achieved by the error amplifier 310 using the measurement signal to adjust the replica current I by the second current control device 325. cm By following a similar adjustment to the integrated current I by the first current control device 315, M This allows you to track adjustments to

[0042] Exemplary operations of the feedback circuit 305 according to certain aspects are discussed below.

[0043] The error amplifier 310 receives a measurement signal from the replica circuit 330 at a first input 312 and a reference signal representing a target integral current from the reference circuit 350 at a second input 314. The error amplifier 310 is configured to generate an output signal (e.g., a voltage) at an output 316 of the error amplifier 310 based on the error (i.e., difference) between the measurement signal and the reference signal. The output signal of the error amplifier 310 is output to a control input 318 of a first current control device 315 and a control input 328 of a second current control device 325, and the first current control device 315 controls the integral current I of the sense amplifier 110 based on the output signal. M and the second current control device 325 adjusts the replica current I of the replica circuit 330 based on the output signal. cm Adjust.

[0044] The error amplifier 310 adjusts its output signal in a direction that reduces the error (i.e., difference) based on the detected error (i.e., difference) between the measurement signal and the reference signal. The output signal of the error amplifier 310 is then adjusted to generate a replica current I in the replica circuit 330 using a second current control device 325. cm , the error amplifier 310 uses its output signal to generate a replica current I cmto keep the measurement signal approximately equal to the reference signal, which represents the target integrated current (i.e., make the measurement signal approximately equal to the reference signal). The output signal of the error amplifier 310 is also adjusted to control the integrated current I using a first current control device 315. M This involves having the error amplifier 310 control the integral current I using a first current control device 315. M and adjusts the integrated current I of the sense amplifier 110. M approximately equal to the target integral current represented by the reference signal.

[0045] The integral current I M deviates from the target integral current, the feedback circuit 305 uses the measurement signal to adjust the replica current I cm By detecting a similar change in the integrated current I M The replica current I cm In response to detecting a change in , the error amplifier 310 adjusts its output signal (i.e., voltage) in a direction that reduces the error (i.e., difference) between the measurement signal and the reference signal. Because the output signal also controls the first current control device 315, this adjustment in the output signal reduces the integrated current I M and the target integral current represented by the reference signal. M Using this feedback mechanism, the feedback circuit 305 adjusts the integrated current I across variations in the common-mode voltage Vcm. M can be maintained at approximately the target integral current.

[0046] The feedback circuit 305 responds to either an increase or a decrease in the common-mode voltage Vcm by increasing or decreasing the integrated current I M can be maintained at approximately the target integral current. Exemplary feedback operations of the feedback circuit 305 according to certain embodiments when the common-mode voltage Vcm decreases and when the common-mode voltage Vcm increases are described below with reference to FIG.

[0047] For example, when the common-mode voltage Vcm decreases, the integrated current I M increases compared to the target integral current. This is because the decrease in the common-mode voltage Vcm increases the transconductance of the input transistors 120 and 125, which in turn decreases the integral current I M The decrease in the common-mode voltage Vcm also increases the replica current I cm (and therefore, increase the measurement signal). This is because the third input transistor 340 of replica circuit 330 is biased by the same common-mode voltage Vcm as input transistors 120 and 125. The corresponding increase in the measurement signal increases the error (i.e., difference) between the measurement signal and the reference signal. In this example, in response to the increase in error, error amplifier 310 causes second current control device 325 to increase replica current I in replica circuit 330. cm Since the error amplifier 310 also controls the first current control device 315, the error amplifier 310 controls the first current control device 315 to provide an integral current I M In this case, the integral current I M and the target integral current.

[0048] An increase in the common-mode voltage Vcm increases the integral current I M This is because an increase in the common-mode voltage Vcm reduces the transconductance of the input transistors 120 and 125, which reduces the integral current I M The increase in the common-mode voltage Vcm also reduces the replica current I cm (and therefore, a decrease in the measurement signal). This is because the third input transistor 340 of replica circuit 330 is biased by the same common-mode voltage Vcm as input transistors 120 and 125. The corresponding decrease in the measurement signal increases the error (i.e., the difference) between the measurement signal and the reference signal. In this example, in response to the increase in error, error amplifier 310 causes second current control device 325 to increase replica current I in replica circuit 330. cmThe error amplifier 310 also controls the first current control device 315, so that the error amplifier 310 causes the first current control device 315 to increase the integral current I M In this case, the integral current I M and the target integral current.

[0049] integral current I M may also vary due to changes in the transconductance of the input transistors 120 and 125 caused by process, voltage, and temperature (PVT) variations. In this case, the third input transistor 340 of the replica circuit 330 is configured to detect the integrated current I due to the changes in the transconductance of the input transistors 120 and 125 caused by the PVT variations. M For example, the third input transistor 340 of the replica circuit 330 may be integrated on the same chip (i.e., die) as the input transistors 120 and 125, such that the third input transistor 340 experiences the same or similar PVT as the input transistors 120 and 125. As a result, the transconductance of the third input transistor 340 varies in the same way as the input transistors 120 and 125 over PVT variations. This allows the replica current I cm is the integral current due to PVT fluctuations, I M Since the replica current I cm is the integral current due to PVT fluctuations, I M This allows the feedback circuit 305 to track changes in the integrated current I over PVT variations. M can be maintained at approximately the target integral current.

[0050] 4 illustrates an exemplary implementation of a first current control device 315 and a second current control device 325 according to certain aspects. In this example, the first current control device 315 includes a first transistor 415 (e.g., an NFET). A switch 320 is coupled between the common source node 122 and the drain of the first transistor 415, the gate of the first transistor 415 is coupled to the output 316 of the error amplifier 310, and the source of the first transistor 415 is coupled to ground. In this example, the output voltage at the output 316 of the error amplifier 310 is applied to the gate of the first transistor 415 and controls the current I of the first current control device 315 by controlling the channel conductance of the first transistor 415. S In this example, the error amplifier 310 controls the current I of the first current control device 315. S , increasing the voltage at the output 316 to increase the current I of the first current control device 315. S The voltage at output 316 is decreased to decrease .

[0051] In this example, the second current control device 325 includes a second transistor 425 (e.g., an NFET). The drain of the second transistor 425 is coupled to the source node 342 of the replica circuit 330, the gate of the second transistor 425 is coupled to the output 316 of the error amplifier 310, and the source of the second transistor 425 is coupled to ground. In this example, the output voltage at the output 316 of the error amplifier 310 is applied to the gate of the second transistor 425 and controls the current I of the second current control device 325 by controlling the channel conductance of the second transistor 425. R In this example, the error amplifier 310 controls the current I of the second current control device 325. R , increasing the voltage at the output 316 to increase the I R The voltage at output 316 is decreased to decrease .

[0052] In this example, the first input 312 of the error amplifier 310 may be a positive input (i.e., a non-inverting input) and the second input 314 of the error amplifier 310 may be a negative input (i.e., an inverting input), as shown in the example of FIG.

[0053] It should be understood that the first current control device 315 and the second current control device 325 are not limited to the exemplary implementation shown in Figure 4. For example, in other implementations, each of the current control devices 315 and 325 may be implemented using another type of transistor or another type of device that can control current flow based on the output signal (e.g., voltage) of the error amplifier 310.

[0054] Furthermore, it should be understood that the first current control device 315 is not limited to drawing current from the common source node 122. For example, in some implementations, the first current control device 315 may be configured to source current to the common source node 122, where the amount of current sourced by the first current control device 315 is controlled by a signal at the control input 318 (e.g., the output signal of the error amplifier 310). In this example, the error amplifier 310 increases the amount of current that the first current control device 315 sources to the common source node 122, thereby increasing the integrated current I M , and the amount of current that the first current control device 315 supplies to the common source node 122, thereby reducing the integrated current I M can be reduced.

[0055] Similarly, in some implementations, the second current control device 325 may be configured to source a current to the source node 342 of the replica circuit 330, where the amount of current sourced by the second current control device 325 is controlled by a signal at the control input 328 (e.g., the output signal of the error amplifier 310). In this example, the error amplifier 310 increases the amount of current that the second current control device 325 sources to the source node 342, thereby increasing the replica current I cmand decreases the amount of current that the second current control device 325 sources to the source node 342, thereby decreasing the replica current I cm can be reduced.

[0056] In the above example, each of the current control devices 315 and 325 may be implemented with a respective PFET that receives current from the supply rail. More specifically, the first current control device 315 may be implemented with a first PFET coupled between the supply rail and the common source node 122, with the gate of the first PFET coupled to the output 316 of the error amplifier 310. In a particular aspect, the first PFET and switch 320 may be coupled in series between the supply rail and the common source node 122. The second current control device 325 may be implemented with a second PFET coupled between the supply rail and the source node 342, with the gate of the second PFET coupled to the output 316 of the error amplifier 310. Also, in this example, the second input 314 of the error amplifier 310 may be a positive input (i.e., a non-inverting input), and the first input 312 of the error amplifier 310 may be a negative input (i.e., an inverting input).

[0057] 4 illustrates an exemplary implementation of a reference circuit 350 according to certain aspects. In this example, the reference circuit 350 includes a second replica circuit 430. In the example illustrated in FIG. 4, the second replica circuit 430 replicates a branch of the sense amplifier 110. For example, the second replica circuit 430 may replicate either branch of the sense amplifier 110.

[0058] The second replica circuit 430 includes a switch 435, a fourth input transistor 440, and a current sensing resistor 445. The switch 435 is connected to the supply rail V DDand the source of fourth input transistor 440, and current sense resistor 445 is coupled between the drain of fourth input transistor 440 and ground. Switch 435 corresponds to first switch 115 in sense amplifier 110. In the example shown in FIG. 4 , switch 435 is implemented with a PFET 438 that is always on by coupling a control input 436 of switch 435 (and therefore the gate of PFET 438) to ground. In this example, output 352 of reference circuit 350 is coupled between the drain of fourth input transistor 440 and current sense resistor 445.

[0059] The gate of the fourth input transistor 440 is biased by a reference voltage (labeled "Vref"). In particular embodiments, the reference voltage is generated by a voltage source 450 that is coupled to the gate of the fourth input transistor 440. The voltage Vref causes a reference current I ref flows through the fourth input transistor 440. The reference current I ref flows through a current sense resistor 445 coupled between the drain of the fourth input transistor 440 and ground. The current sense resistor 445 senses a reference current I ref is converted into the reference signal mentioned above. In this example, the reference signal is the reference current I ref multiplied by the resistance of current sense resistor 445. This reference signal is output at an output 352 of reference circuit 350, which is coupled to the second input 314 of error amplifier 310.

[0060] In this example, the reference voltage Vref output by the voltage source 450 controls the reference signal, and therefore the target integral current. Thus, in this example, the reference signal (and therefore the target integral current) can be set to a desired value by setting the reference voltage Vref output by the voltage source 450 accordingly. For example, the reference signal (and therefore the target integral current) can be increased by decreasing the reference voltage Vref. This is because decreasing the reference voltage Vref decreases the reference current I flowing through the fourth input transistor 440 (implemented with a PFET in this example).ref This is because the reference current I ref An increase in increases the reference signal, and in this example, the reference current I ref is approximately equal to multiplied by the resistance of the current sense resistor 445.

[0061] In particular aspects, voltage source 450 is a programmable voltage source that allows the reference voltage Vref to be programmed to set the reference signal (and therefore the target integral current). In one example, voltage source 450 may include a digital-to-analog converter (DAC) configured to receive a digital code and convert the digital code to one of a plurality of different voltages. In this example, reference voltage Vref may be programmed to any one of the different voltages by inputting a corresponding digital code into the DAC.

[0062] It should be understood that the example implementation of the reference circuit 350 shown in FIG. 4 is not limited to being used with the example implementation of the first current control device 315 and the example implementation of the second current control device 325 shown in FIG.

[0063] FIG. 5 illustrates an example of a feedback circuit 305 in which the switch 320 is omitted, according to certain embodiments. In the example illustrated in FIG. 5, the drain of the first transistor 415 is directly coupled to the common source node 122, and the source of the first transistor 415 is coupled to the timing circuit 190. Because the source of the first transistor 415 is coupled to the timing circuit 190, a clock signal from the timing circuit 190 is applied to the source of the first transistor 415. In this example, the first transistor 415 is implemented using an NFET, and the clock signal is high during the reset phase and low during the integrate phase. The high clock signal during the reset phase turns the first transistor 415 off during the reset phase, and the low clock signal during the integrate phase turns the first transistor 415 on during the integrate phase. Because the first transistor 415 is off during the reset phase, the first transistor 415 does not draw current from the common source node 122 during the reset phase. In the exemplary implementation shown in FIG. 4, the first transistor 415 is prevented from drawing current from the common source node 122 during the reset phase by turning off the switch 320 during the reset phase, thereby decoupling the first transistor 415 from the common source node 122 during the reset phase.

[0064] 6 illustrates an example of a circuit 605 configured to apply a common-mode voltage Vcm to the gate of the third input transistor 340 in the replica circuit 330, according to certain embodiments. In this example, the circuit 605 includes a first resistor 610 and a second resistor 620 having approximately equal resistances. The first resistor 610 and the second resistor 620 are coupled in series between the first input 112 and the second input 114 of the sense amplifier 110, and the gate of the third input transistor 340 is coupled to a node 625 between the first resistor 610 and the second resistor 620.

[0065] In this example, the voltage at node 625 is approximately equal to the average of the voltages at the first input 112 and the second input 114 of the sense amplifier 110. The average voltage developed at node 625 is approximately equal to the common-mode voltage, assuming that the input voltages VINp and VINn have equal and opposite amplitudes relative to the common-mode voltage Vcm. Thus, in this example, node 625 provides the common-mode voltage Vcm to the gate of the third input transistor 340. It should be understood that the present disclosure is not limited to this example and that other techniques may be used to apply the common-mode voltage to the gate of the third input transistor 340.

[0066] Although switch 320 is shown in the example of FIG. 6, it should be understood that circuit 605 may also be used in the exemplary implementation shown in FIG. 5, in which switch 320 is omitted.

[0067] 3, 5, and 6 illustrate examples in which the feedback circuit 305 is coupled to one sense amplifier 110, it should be understood that the feedback circuit 305 is not limited to one sense amplifier 110. In certain aspects, the feedback circuit 305 may be coupled to multiple sense amplifiers to adjust the integration currents of the multiple sense amplifiers. In this regard, FIG. 7A illustrates an example in which a first sense amplifier 110-1 and a second sense amplifier 110-2 are coupled to the feedback circuit 305. In this example, each of the sense amplifiers 110-1 and 110-2 may be a copy (i.e., a separate instance) of the sense amplifier 110 described above in accordance with various aspects. Thus, the discussion of the sense amplifier 110 above also applies to each of the first sense amplifier 110-1 and the second sense amplifier 110-2. In this example, feedback circuit 305 includes current control devices 315-1 and 315-2 and switches 320-1 to 320-2, each of which is a separate instance of first current control device 315 described above, and each of which is a separate instance of switch 320 described above.

[0068] In this example, each of switches 320-1 through 320-2 is coupled between a respective common source node of first sense amplifier 110-1 and second sense amplifier 110-2 and a respective one of current control devices 315-1 and 315-2. Control inputs 322-1 and 322-2 of each of switches 320-1 through 320-2 are coupled to timing circuit 190 and driven by a clock signal. Control inputs 318-1 and 318-2 of each of current control devices 315-1 through 315-2 are coupled to output 316 of error amplifier 310. In this example, feedback circuit 305 uses each of current control devices 315-1 and 315-2 to adjust the respective integration currents of first sense amplifier 110-1 and second sense amplifier 110-2 based on the error between the measurement signal and the reference signal.

[0069] 7A illustrates an example in which the same clock signal is input to each of the first sense amplifier 110-1 and the second sense amplifier 110-2, but it should be understood that the present disclosure is not limited to this example. In this regard, FIG. 7B illustrates an example in which a first clock signal clk1 is input to the first sense amplifier 110-1 and a second clock signal clk2 is input to the second sense amplifier 110-2. More specifically, the first clock signal clk1 is used to clock the switches in the first sense amplifier 110-1 (e.g., the respective switches 115, 130, and 135 in the first sense amplifier 110-1), and the second clock signal clk2 is used to clock the switches in the second sense amplifier 110-2 (e.g., the respective switches 115, 130, and 135 in the second sense amplifier 110-2).

[0070] In this example, a first clock signal clk1 is input to the control input 322-1 of switch 320-1, and a second clock signal clk2 is input to the control input 322-2 of switch 320-2. In one example, the second clock signal clk2 may be the complement (i.e., the inverse) of the first clock signal clk. In this example, the first sense amplifier 110-1 and the second sense amplifier 110-2 may be coupled to the same data channel and used to receive alternating data bits from the data channel. In this regard, FIG. 7C shows an example in which the first sense amplifier 110-1 and the second sense amplifier 110-2 are coupled to a receiver 720. In this example, the receiver 720 has a first input 722, a second input 724, a first output 726, and a second output 728. A first output 726 of the receiver 720 is coupled to the first input 112-1 of the first sense amplifier 110-1 and the first input 112-2 of the second sense amplifier 110-2. A second output 728 of the receiver 720 is coupled to the second input 114-1 of the first sense amplifier 110-1 and the second input 114-2 of the second sense amplifier 110-2. The receiver 720 may include at least one of an amplifier and an equalizer.

[0071] In operation, the receiver 720 is configured to receive input differential signals (e.g., from a differential serial link) at a first input 722 and a second input 724. The receiver 720 may amplify and / or equalize the input differential signals into differential voltages including the input voltages v p and v n described above, and output the input voltages v p and v n at a first output 726 and a second output 728, respectively. In one example, the differential voltages may carry data bits at a data rate equal to twice the frequency of the clock signals clk1 and clk2 (i.e., the data rate may be twice the data rate for the clock signals clk1 and clk2). Here, the first sense amplifier 110-1 may be configured to receive odd-numbered data bits using the first clock signal clk1, and the second sense amplifier 110-2 may be configured to receive even-numbered data bits using the second clock signal clk2, or vice versa.

[0072] 7C, the common-mode voltage Vcm may be obtained using exemplary circuit 605. In this example, circuit 605 is coupled between a first output 726 and a second output 728 of receiver 720, and the common-mode voltage Vcm is provided at a node 625 between a first resistor 610 and a second resistor 620. Node 625 may be coupled to the gate of a third input transistor 340 in replica circuit 330 (shown in FIG. 7B).

[0073] It should be understood that the first clock signal clk and the second clock signal clk2 are not limited to the above example. In general, the first clock signal clk1 and the second clock signal clk2 may have the same frequency but may be offset from each other by a certain phase (e.g., 180 degrees, 90 degrees, etc.).

[0074] 7A and 7B, two sense amplifiers 110-1 and 110-2 are shown, it should be understood that the feedback circuit 305 may be expanded to adjust the integration current of more than two sense amplifiers. Thus, one feedback circuit may be used to adjust the integration current of multiple sense amplifiers.

[0075] 8 illustrates an example of a system 805 in which aspects of the present disclosure may be used. In this example, the system 805 includes a first chip 810 and a second chip 815, and SerDes may be used for communication between the first chip 810 and the second chip 815. The first chip 810 includes a serializer 820, a driver 830, a first output pin 840, and a second output pin 842. The second chip 815 includes a first receive pin 850, a second receive pin 852, a receiver 860, a sense amplifier 110, a comparator 150, a latch 870, and a deserializer 880.

[0076] In this example, a first chip 810 and a second chip 815 are coupled via a differential serial link including a first line 844 and a second line 846. The first line 844 is coupled between a first output pin 840 and a first receive pin 850, and the second line 846 is coupled between a second output pin 842 and a second receive pin 852. Each of the first line 844 and the second line 846 may be implemented as a metal line, wire, or the like on a substrate (e.g., a printed circuit board).

[0077] On the first chip 810, a serializer 820 is configured to receive a parallel data stream (e.g., from a processor on the first chip 810) and convert the parallel data stream to a serial data stream, which is output at an output 825 of the serializer 820. A driver 830 has an input 832 coupled to the output 825 of the serializer 820, a first output 834 coupled to a first output pin 840, and a second output 836 coupled to a second output pin 842. The driver 830 is configured to receive the serial data stream, convert the serial data stream to a differential signal, and drive a first wire 844 and a second wire 846 of the differential serial link with the differential data signal to transmit the differential signal to the second chip 815. It should be understood that the first chip 810 may include additional components not shown in FIG. 8 (e.g., an impedance matching network coupled to the first output pin 840 and / or the second output pin 842, a pre-driver coupled between the serializer 820 and the driver 830, etc.).

[0078] On the second chip 815, a receiver 860 (e.g., receiver 720) has a first input 862 coupled to the first receive pin 850, a second input 864 coupled to the second receive pin 852, a first output 866 coupled to the first input 112 of the sense amplifier 110, and a second output 868 coupled to the second input 114 of the sense amplifier 110. The receiver 860 may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip 810 and the second chip 815). The sense amplifier 110 receives a differential input voltage from the receiver 860. As described above, the differential input voltage includes an input voltage Vinp and an input voltage Vinn. The receiver 860 may also bias each of the inputs 112 and 114 with a common-mode voltage Vcm. The first output 146 and the second output 148 of the sense amplifier 110 are coupled to the first input 152 and the second input 154, respectively, of the comparator 150. The comparator 150 outputs the determined bit at the first output 180 and the complement of the determined bit at the second output 185, as described above. The second chip 815 may also include a feedback circuit 305 coupled to the sense amplifier 110 to adjust the integration current of the sense amplifier 110, as described above.

[0079] 8 , the first output 180 of the comparator 150 is coupled to a first input 872 of a latch 870, and the second output 185 of the comparator 150 is coupled to a second input 874 of the latch 870. The latch 870 has an output 876 coupled to an input 882 of a deserializer 880. The latch 870 (e.g., an SR latch or another type of latch) is configured to latch the bit decision from the comparator 150 and output the latched bits to the deserializer 880. The deserializer 880 is configured to convert the bits into a parallel data stream, which may be output to one or more components (not shown) on the second chip 815 for further processing. It should be understood that the second chip 815 may include additional components not shown in FIG. 8 (e.g., an impedance matching network coupled to the first receive pin 850 and / or the second receive pin 852, a clock recovery circuit, etc.).

[0080] 9 illustrates a method 900 for adjusting an integration current of a sense amplifier according to a particular embodiment. The sense amplifier (e.g., sense amplifier 110) includes a first input transistor (e.g., first input transistor 120) and a second input transistor (e.g., second input transistor 125), where the source of the first input transistor and the source of the second input transistor are coupled to a source node (e.g., common source node 122).

[0081] In block 910, a current is sunk from or sourced to a source node. For example, a current (e.g., current I S ) may be drawn from or supplied to the source node by the first current control device 315.

[0082] In block 920, the integrated current is measured. For example, the integrated current may be measured indirectly using a replica circuit (e.g., replica circuit 330). In this example, measuring the integrated current involves using a replica circuit to generate a replica current proportional to the integrated current (e.g., replica current I cm) and generating a measurement signal based on the replica current.

[0083] In block 930, the measured integrated current is compared to a reference signal. For example, the error amplifier 310 may compare the measured integrated current (e.g., a measurement signal) to a reference signal. For example, this reference signal may be generated by the reference circuit 350.

[0084] At block 940, the current drawn from or provided to the source node is adjusted based on the comparison. For example, the current drawn from or provided to the source node may be adjusted by the error amplifier 310 and the first current control device 315. In this example, the error amplifier 310 may adjust the current drawn from or provided to the source node by adjusting the output signal (e.g., voltage) of the error amplifier 310 input to the control input 318 of the first current control device 315 based on the comparison. In certain aspects, adjusting the current drawn from or provided to the source node includes adjusting the current drawn from or provided to the source node in a direction that reduces the difference between the measured integrated current (e.g., measurement signal) and the reference signal.

[0085] It is to be understood that this disclosure is not limited to the exemplary terminology used above to describe aspects of the disclosure.

[0086] Any reference herein to an element using a designation such as "first," "second," etc. generally does not limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element. Also, it should be understood that the numerical designations used to distinguish elements (e.g., transistors) in the description do not necessarily correspond to the numerical designations used for corresponding elements (e.g., transistors) in the claims.

[0087] It should be understood that the first input transistor 120, the second input transistor 125, the third input transistor 340, and the fourth input transistor 440 may be referred to simply as the first transistor, the second transistor, the third transistor, and the fourth transistor, respectively. In this example, the first transistor 415 and the second transistor 425 may be referred to as the fifth transistor and the sixth transistor, respectively, or may be referred to using other numerical designations. In another example, the first transistor 415 may be referred to as the first current control transistor, and the second transistor 425 may be referred to as the second current control transistor.

[0088] The following numbered clauses describe example implementations. 1. an error amplifier having a first input, a second input, and an output; a sense amplifier including a first transistor and a second transistor, the source of the first transistor and the source of the second transistor being coupled to a common source node; a first current control device coupled to the common source node, the first current control device having a control input coupled to the output of the error amplifier; a replica circuit coupled to a first input of the error amplifier, the replica circuit including a third transistor replicating one of the first transistor and the second transistor; a second current control device coupled to the source of the third transistor, the second current control device having a control input coupled to the output of the error amplifier; a reference circuit coupled to a second input of the error amplifier, the reference circuit configured to output a reference signal; An apparatus comprising: 2. The replica circuit is a switch coupled between the supply rail and the third transistor; a resistor coupled between the third transistor and ground; 10. The apparatus of claim 1, wherein the first input of the error amplifier is coupled between the third transistor and the resistor. 3. The apparatus of clause 2, wherein the switch comprises a p-type field effect transistor (PFET) having a gate coupled to ground. 4. The apparatus of clause 2 or 3, wherein the third transistor comprises a p-type field effect transistor (PFET). 5. The device of any one of clauses 2 to 4, wherein the gate of the third transistor is biased by the common-mode voltage of the sense amplifier. 6. The reference circuit is a fourth transistor having a gate coupled to the voltage source; a switch coupled between the supply rail and the fourth transistor; a resistor coupled between the fourth transistor and ground; 6. The apparatus of any one of clauses 1-5, wherein a second input of the error amplifier is coupled between the fourth transistor and the resistor. 7. The apparatus of clause 6, wherein the switch comprises a p-type field effect transistor (PFET) having a gate coupled to ground. 8. The apparatus of clause 6 or 7, wherein the fourth transistor comprises a p-type field effect transistor (PFET). 9. The apparatus of any one of clauses 6 to 8, wherein the voltage source comprises a digital-to-analog converter. 10. The apparatus of any one of clauses 1-9, further comprising a switch coupled between the first current control device and the common source node, the control input of the switch being coupled to the timing circuit. 11. The apparatus of clause 10, wherein the timing circuit is configured to drive the control input of the switch with a clock signal. 12. The apparatus of any one of clauses 1-9, wherein the first current control device comprises a fourth transistor having a gate coupled to the output of the error amplifier. 13. The apparatus of clause 12, wherein the drain of the fourth transistor is coupled to the common source node and the source of the fourth transistor is coupled to the timing circuit. 14. The apparatus of clause 13, wherein the timing circuit is configured to drive the source of the fourth transistor with a clock signal. 15. A first current control device comprising: sinking or sourcing current from the common source node; receiving an output signal from the output of the error amplifier at a control input of the first current control device; 15. The apparatus of any one of clauses 1-14, configured to adjust the current drawn from or supplied to the common source node based on the received output signal. 16. the first current control device comprises a fourth transistor having a gate coupled to the output of the error amplifier; 16. The apparatus of any one of clauses 1-15, wherein the second current control device comprises a fifth transistor having a gate coupled to the output of the error amplifier. 17. The apparatus of clause 16, wherein the fourth transistor and the fifth transistor each comprise a respective n-type field effect transistor (NFET). 18. The apparatus of clause 16, wherein the fourth transistor and the fifth transistor each comprise a respective p-type field effect transistor (PFET). 19. a first transistor having a gate coupled to a first input of the sense amplifier; a second transistor having a gate coupled to a second input of the sense amplifier; 19. The apparatus of any one of clauses 1-18, wherein a first input of the sense amplifier is configured to receive a first input voltage and a second input of the sense amplifier is configured to receive a second input voltage. 20. a first transistor having a drain coupled to a first output of the sense amplifier; 20. The apparatus of clause 19, wherein the second transistor has a drain coupled to a second output of the sense amplifier. 21. The apparatus of clause 20, further comprising a comparator having a first input and a second input, the first input of the comparator coupled to the first output of the sense amplifier and the second input of the comparator coupled to the second output of the sense amplifier. 22. The apparatus of any one of clauses 1-21, further comprising a receiver coupled to the sense amplifier. 23. The apparatus of any one of clauses 1-22, further comprising a comparator coupled to the sense amplifier. twenty four. a latch coupled to the comparator; a deserializer coupled to the latch; 24. The apparatus of clause 23, further comprising: 25. A method for adjusting an integration current of a sense amplifier, the sense amplifier including a first input transistor and a second input transistor, a source of the first input transistor and a source of the second input transistor coupled to a source node, the method comprising: sinking or sourcing current from a source node; measuring an integrated current; comparing the measured integrated current to a reference signal; adjusting a current drawn from or supplied to the source node based on the comparison; and A method comprising: 26. The method of clause 25, wherein adjusting the current drawn from or supplied to the source node includes adjusting the current drawn from or supplied to the source node in a direction that reduces a difference between the measured integrated current and a reference signal. 27. Measuring the integral current generating a replica current proportional to the integrated current; generating a measurement signal based on the replica current; 27. The method according to clause 25 or 26, comprising: 28. The method of clause 27, wherein comparing the measured integrated current to a reference signal includes comparing the measured signal to the reference signal. 29. The method of clause 28, wherein adjusting the current drawn from or supplied to the source node includes adjusting the current drawn from or supplied to the source node in a direction that reduces a difference between the measurement signal and the reference signal. 30. The method of any one of clauses 27 to 29, wherein generating the measurement signal includes passing a replica current through a resistor. 31. an error amplifier having a first input, a second input, and an output; a sense amplifier including a first input transistor and a second input transistor, the source of the first input transistor and the source of the second input transistor being coupled to a common source node, and an integrated current flowing from a supply rail to the common source node; a first current control device coupled to the common source node for adjusting the integral current, the first current control device having a control input coupled to the output of the error amplifier; a replica circuit configured to generate a replica current that tracks the integrated current and configured to couple the replica current to a first input of the error amplifier, the replica circuit including a third input transistor replicating one of the first input transistor and the second input transistor; a second current control device coupled to the source of the third input transistor, the second current control device having a control input coupled to the output of the error amplifier; a reference circuit coupled to a second input of the error amplifier, the reference circuit configured to output a reference signal to the second input of the error amplifier; An apparatus comprising: 32. A replica circuit is a switch coupled between the supply rail and the third input transistor; a resistor coupled between the third input transistor and ground; 32. The apparatus of claim 31, wherein the first input of the error amplifier is coupled between the third input transistor and the resistor. 33. The apparatus of clause 32, wherein the switch comprises a p-type field effect transistor (PFET) having a gate coupled to ground. 34. The apparatus of clause 32 or 33, wherein the third input transistor comprises a p-type field effect transistor (PFET). 35. The apparatus of any one of clauses 32 to 34, wherein the gate of the third input transistor is biased by the common-mode voltage of the sense amplifier. 36. The apparatus of clause 35, further comprising a first resistor and a second resistor coupled in series between the first input and the second input of the sense amplifier, wherein a gate of the third input transistor is coupled to a node between the first resistor and the second resistor, the first input of the sense amplifier is coupled to the gate of the first input transistor, and the second input of the sense amplifier is coupled to the gate of the second input transistor. 37. A reference circuit is a fourth input transistor having a gate coupled to the voltage source; a switch coupled between the supply rail and the fourth input transistor; a resistor coupled between the fourth input transistor and ground; 37. The apparatus of any one of clauses 31-36, comprising: a second input of the error amplifier coupled between the fourth input transistor and the resistor. 38. The apparatus of clause 37, wherein the switch comprises a p-type field effect transistor (PFET) having a gate coupled to ground. 39. The apparatus of clause 37 or 38, wherein the fourth input transistor comprises a p-type field effect transistor (PFET). 40. The apparatus of any one of clauses 37 to 39, wherein the voltage source comprises a digital-to-analog converter. 41. The apparatus of any one of clauses 31-40, further comprising a switch coupled between the first current control device and the common source node, the control input of the switch being coupled to the timing circuit. 42. The apparatus of clause 41, wherein the timing circuit is configured to drive the control input of the switch with a clock signal. 43. The apparatus of any one of clauses 31-40, wherein the first current control device comprises a current control transistor having a gate coupled to the output of the error amplifier. 44. The apparatus of clause 43, wherein the drain of the current control transistor is coupled to the common source node and the source of the current control transistor is coupled to the timing circuit. 45. The apparatus of clause 44, wherein the timing circuit is configured to drive the source of the current control transistor with a clock signal. 46. ​​A first current control device sinking or sourcing current from the common source node; receiving an output signal from the output of the error amplifier at a control input of the first current control device; 46. ​​The apparatus of any one of clauses 31 to 45, configured to adjust the current drawn from or supplied to the common source node based on the received output signal. 47. the first current control device comprises a first current control transistor having a gate coupled to the output of the error amplifier; 47. The apparatus of any one of clauses 31-46, wherein the second current control device comprises a second current control transistor having a gate coupled to the output of the error amplifier. 48. The apparatus of clause 47, wherein the first current control transistor and the second current control transistor each comprise a respective n-type field effect transistor (NFET). 49. The apparatus of clause 46, wherein the first current control transistor and the second current control transistor each comprise a respective p-type field effect transistor (PFET). 50. a first input transistor having a gate coupled to the first input of the sense amplifier; a second input transistor having a gate coupled to a second input of the sense amplifier; 49. The apparatus of any one of clauses 31 to 49, wherein a first input of the sense amplifier is configured to receive a first input voltage and a second input of the sense amplifier is configured to receive a second input voltage. 51. a first input transistor having a drain coupled to a first output of the sense amplifier; 51. The apparatus of clause 50, wherein the second input transistor has a drain coupled to a second output of the sense amplifier. 52. The apparatus of clause 51, further comprising a comparator having a first input and a second input, the first input of the comparator coupled to the first output of the sense amplifier and the second input of the comparator coupled to the second output of the sense amplifier. 53. The apparatus of any one of clauses 31-52, further comprising a receiver coupled to the sense amplifier. 54. The apparatus of any one of clauses 31-53, further comprising a comparator coupled to the sense amplifier. 55. a latch coupled to the comparator; a deserializer coupled to the latch; 55. The apparatus of clause 54, further comprising: 56. A method for adjusting an integration current of a sense amplifier, the sense amplifier including a first input transistor and a second input transistor, a source of the first input transistor and a source of the second input transistor coupled to a source node, an integration current flowing from a supply rail to the source node, the method comprising: sinking or sourcing current from or to a source node with a current control device; measuring the integrated current in the replica circuit; comparing the measured integrated current with a reference signal in an error amplifier; adjusting a current drawn from or supplied to the source node by a current control device based on the comparison; A method comprising: 57. The method of clause 56, wherein adjusting the current drawn from or supplied to the source node includes adjusting the current drawn from or supplied to the source node in a direction that reduces a difference between the measured integrated current and a reference signal. 58. Measuring the integrated current in the replica circuit generating a replica current proportional to the integrated current; generating a measurement signal based on the replica current; 58. The method according to clause 56 or 57, comprising: 59. The method of clause 58, wherein comparing the measured integrated current in the error amplifier with a reference signal includes comparing the measured signal with the reference signal. 60. The method of clause 59, wherein adjusting the current drawn from or supplied to the source node by the current control device includes adjusting the current drawn from or supplied to the source node in a direction that reduces a difference between the measurement signal and the reference signal. 61. The method of any one of clauses 58 to 60, wherein generating the measurement signal includes passing a replica current through a resistor. 62. The method of clause 58, wherein generating the replica current includes generating the replica current with a third input transistor having a gate that receives the common-mode voltage of the sense amplifier. 63. The method of clause 27, wherein generating the replica current includes generating the replica current using a third input transistor having a gate that receives the common-mode voltage of the sense amplifier. 64. a sense amplifier including a first transistor and a second transistor, the source of the first transistor and the source of the second transistor being coupled to a common source node, and an integration current flowing from a supply rail to the common source node; A feedback circuit, sinking or sourcing current from the common source node; Measure the integrated current, comparing the measured integrated current to a reference signal; adjusting the current drawn from or supplied to the source node based on the comparison; a feedback circuit configured to An apparatus comprising: 65.A feedback circuit is 65. The apparatus of clause 64, configured to adjust the current drawn from or supplied to the source node in a direction that reduces a difference between the measured integrated current and a reference signal. 66. a first transistor having a gate coupled to a first input of the sense amplifier; a second transistor having a gate coupled to a second input of the sense amplifier; 66. The apparatus of clause 64 or 65, wherein a first input of the sense amplifier is configured to receive a first input voltage and a second input of the sense amplifier is configured to receive a second input voltage. 67. a first transistor having a drain coupled to a first output of the sense amplifier; 67. The apparatus of clause 66, wherein the second transistor has a drain coupled to a second output of the sense amplifier. 68. The apparatus of clause 67, further comprising a comparator having a first input and a second input, the first input of the comparator coupled to the first output of the sense amplifier and the second input of the comparator coupled to the second output of the sense amplifier. 69. the feedback circuit comprises a third transistor configured to generate a replica current proportional to the integrated current; 69. The apparatus of any one of clauses 64 to 68, wherein the feedback circuit is configured to measure the integrated current based on the replica current. 70. The apparatus of clause 69, wherein the gate of the third transistor is configured to receive the common-mode voltage of the sense amplifier. 71. The apparatus of clause 70, further comprising a first resistor and a second resistor coupled in series between a gate of the first transistor and a gate of the second transistor, wherein a gate of the third transistor is coupled to a node between the first resistor and the second resistor.

[0089] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "approximately," as used herein with respect to a stated value or property, is intended to indicate within 10% of the stated value or property.

[0090] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. an error amplifier having a first input, a second input, and an output; an error amplifier, the first input of which is configured to receive a measurement signal from a replica circuit, the second input of which is configured to receive a reference signal from a reference circuit, and the output of which is configured to output an output signal to a first current control device and a second current control device based on an error between the measurement signal and the reference signal; A sense amplifier including a first transistor and a second transistor, a source of the first transistor and a source of the second transistor coupled to a common source node; a gate of the first transistor coupled to a first input of the sense amplifier, and a gate of the second transistor coupled to a second input of the sense amplifier; the first input of the sense amplifier is configured to receive a first input voltage and the second input of the sense amplifier is configured to receive a second input voltage, the first input voltage and the second input voltage being a differential input voltage; a drain of the first transistor coupled to a first output of the sense amplifier via a first integration node, and a drain of the second transistor coupled to a second output of the sense amplifier via a second integration node; the first output of the sense amplifier is configured to output a voltage at the first integration node, and the second output of the sense amplifier is configured to output a voltage at the second integration node; a sense amplifier, wherein an integrating current flows from a supply rail through a first switch coupled between the common source node and a supply voltage to the common source node, raising the voltage at the first integrating node and the voltage at the second integrating node, respectively; a first current control device coupled to the common source node for adjusting the integral current, the first current control device having a control input coupled to the output of the error amplifier; the replica circuit configured to generate a replica current that tracks the integrated current, and configured to output the measurement signal corresponding to the replica current to the first input of the error amplifier; a third transistor that replicates one of the first transistor and the second transistor; a second switch coupled between the supply rail and the third transistor; the replica circuit including a first resistor coupled between the third transistor and ground, wherein the first input of the error amplifier is coupled between the third transistor and the first resistor; the second current control device coupled to the source of the third transistor, the second current control device having a control input coupled to the output of the error amplifier; the reference circuit coupled to the second input of the error amplifier, the reference circuit configured to output the reference signal to the second input of the error amplifier; a third switch coupled between the first current control device and the common source node, the control input of the third switch being coupled to a timing circuit; A circuit including a second resistor and a third resistor, the second resistor and the third resistor are coupled in series between the first input and the second input of the sense amplifier; a circuit in which the second resistor and the third resistor have equal resistances, and a voltage at a node between the second resistor and the third resistor is equal to an average voltage of the first input voltage and a second input voltage of the sense amplifier, the average voltage being equal to a common mode voltage of the sense amplifier; a gate of the third transistor coupled to the node between the second resistor and the third resistor and biased by the common-mode voltage of the sense amplifier.

2. 2. The apparatus of claim 1, wherein the second switch comprises a p-type field effect transistor (PFET) having a gate coupled to the ground.

3. The apparatus of claim 1 , wherein the third transistor comprises a p-type field effect transistor (PFET).

4. The reference circuit a fourth transistor having a gate coupled to the voltage source; a fourth switch coupled between the supply rail and the fourth transistor; a fourth resistor coupled between the fourth transistor and ground; 2. The apparatus of claim 1, wherein the second input of the error amplifier is coupled between the fourth transistor and the fourth resistor.

5. 5. The apparatus of claim 4, wherein the fourth switch comprises a p-type field effect transistor (PFET) having a gate coupled to the ground.

6. The apparatus of claim 4 , wherein the fourth transistor comprises a p-type field effect transistor (PFET).

7. The apparatus of claim 4 , wherein the voltage source comprises a digital-to-analog converter.

8. 2. The apparatus of claim 1, wherein the timing circuit is configured to drive the control input of the third switch with a clock signal.

9. 2. The apparatus of claim 1, wherein the first current control device comprises a fourth transistor having a gate coupled to the output of the error amplifier.

10. the first current control device comprising: sinking or sourcing current from the common source node; receiving an output signal from the output of the error amplifier at the control input of the first current control device; adjusting the current drawn from or supplied to the common source node based on the received output signal; The device of claim 1 configured to:

11. the first current control device comprises a fourth transistor having a gate coupled to the output of the error amplifier; 2. The apparatus of claim 1, wherein the second current control device comprises a fifth transistor having a gate coupled to the output of the error amplifier.

12. 12. The apparatus of claim 11, wherein the fourth transistor and the fifth transistor each comprise a respective n-type field effect transistor (NFET).

13. 12. The apparatus of claim 11, wherein the fourth transistor and the fifth transistor each comprise a respective p-type field effect transistor (PFET).

14. the first transistor having a drain coupled to a first output of the sense amplifier; 2. The apparatus of claim 1, wherein the second transistor has a drain coupled to a second output of the sense amplifier.

15. 15. The apparatus of claim 14, further comprising a comparator having a first input and a second input, the first input of the comparator coupled to the first output of the sense amplifier and the second input of the comparator coupled to the second output of the sense amplifier.

16. The apparatus of claim 1 , further comprising a receiver coupled to the sense amplifier.

17. The apparatus of claim 1 , further comprising a comparator coupled to the sense amplifier.

18. a latch coupled to the comparator; a deserializer coupled to the latch; 20. The apparatus of claim 17, further comprising:

19. an error amplifier having a first input, a second input, and an output; an error amplifier, the first input of which is configured to receive a measurement signal from a replica circuit, the second input of which is configured to receive a reference signal from a reference circuit, and the output of which is configured to output an output signal to a first current control device and a second current control device based on an error between the measurement signal and the reference signal; A sense amplifier including a first transistor and a second transistor, a source of the first transistor and a source of the second transistor coupled to a common source node; a gate of the first transistor coupled to a first input of the sense amplifier, and a gate of the second transistor coupled to a second input of the sense amplifier; the first input of the sense amplifier is configured to receive a first input voltage and the second input of the sense amplifier is configured to receive a second input voltage, the first input voltage and the second input voltage being a differential input voltage; a drain of the first transistor coupled to a first output of the sense amplifier via a first integration node, and a drain of the second transistor coupled to a second output of the sense amplifier via a second integration node; the first output of the sense amplifier is configured to output a voltage at the first integration node, and the second output of the sense amplifier is configured to output a voltage at the second integration node; a sense amplifier, wherein an integrating current flows from a supply rail through a first switch coupled between the common source node and a supply voltage to the common source node, raising the voltage at the first integrating node and the voltage at the second integrating node, respectively; the first current control device coupled to the common source node to adjust the integrating current, the first current control device having a control input coupled to the output of the error amplifier and a fourth transistor having a gate coupled to the output of the error amplifier, the drain of the fourth transistor being coupled to the common source node and the source of the fourth transistor being coupled to a timing circuit; the replica circuit configured to generate a replica current that tracks the integrated current, and configured to output the measurement signal corresponding to the replica current to the first input of the error amplifier; a third transistor that replicates one of the first transistor and the second transistor; a second switch coupled between the supply rail and the third transistor; the replica circuit including a first resistor coupled between the third transistor and ground, wherein the first input of the error amplifier is coupled between the third transistor and the first resistor; the second current control device coupled to the source of the third transistor, the second current control device having a control input coupled to the output of the error amplifier; the reference circuit coupled to the second input of the error amplifier, the reference circuit configured to output the reference signal to the second input of the error amplifier; a third switch coupled between the first current control device and the common source node, the control input of the third switch being coupled to a timing circuit; A circuit including a second resistor and a third resistor, the second resistor and the third resistor are coupled in series between the first input and the second input of the sense amplifier; a circuit in which the second resistor and the third resistor have equal resistances, and a voltage at a node between the second resistor and the third resistor is equal to an average voltage of the first input voltage and a second input voltage of the sense amplifier, the average voltage being equal to a common mode voltage of the sense amplifier; a gate of the third transistor coupled to the node between the second resistor and the third resistor and biased by the common-mode voltage of the sense amplifier.

20. 20. The apparatus of claim 19, wherein the timing circuit is configured to drive the source of the fourth transistor with a clock signal.

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