Semiconductor device with electrical components in a circuit board

Abstract

To provide a semiconductor device incorporating an electric component in a circuit board, and having improved thermal conductivity and mechanical characteristic in a substrate main body while keeping insulating of the electric component.SOLUTION: A semiconductor device includes a substrate main body 12 having a first surface 12a and a second surface 12b, electric components 21, 22, 31, and 32 disposed in the substrate main body, a surface conductor pattern 70 provided in a circuit layer L6 present on the second surface, a first internal conductor pattern 68 and a second internal conductor pattern 69 provided in a circuit layer L5 existing between the electric component and the second surface and insulated from each other, at least one first heat conductive veer 77 extending from the electric component to the first internal conductor pattern, and at least one second heat conductive veer 78a, 78b extending from the surface conductor pattern to the second internal conductor pattern.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device that incorporates electrical components in a circuit board.

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes a substrate body and an electric component (core substrate) disposed within the substrate body. A surface conductor pattern is provided on the lower surface of the substrate body, and an internal conductor pattern is provided between the electric component and the second surface. The electric component and the first internal conductor pattern are connected by a plurality of heat transfer vias. With this configuration, heat from the electric component is transferred to the internal conductor pattern via the plurality of heat transfer vias, and further transferred from the internal conductor pattern to the surface conductor pattern, and then dissipated to the outside of the substrate body. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-9879 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, an insulating layer made of the material of the substrate body is provided between the internal conductor pattern and the surface conductor pattern. This configuration provides electrical insulation between the internal conductor pattern and the surface conductor pattern. However, there is a problem in that the insulating layer inhibits heat conduction from the internal conductor pattern to the surface conductor pattern. Furthermore, while the layer located on one side of the internal conductor pattern has multiple heat transfer vias, the insulating layer located on the other side of the internal conductor pattern does not have such heat transfer vias, resulting in significant differences in mechanical properties between the two layers adjacent to the internal conductor pattern. As a result, when the temperature of the substrate body rises, this may result in uneven thermal deformation of the substrate body, such as warping or undulation.

[0005] In view of the above, this specification provides a technique for improving the thermal conductivity and mechanical properties of a substrate body in a semiconductor device having electrical components built into a circuit board while maintaining the insulation properties of the electrical components. [Means for solving the problem]

[0006] The semiconductor device disclosed in this specification comprises a substrate body (12) having a first surface (12a) and a second surface (12b), electrical components (21, 22, 31, 32) arranged within the substrate body, a surface conductor pattern (70) provided on a circuit layer (L6) located on the second surface, a first internal conductor pattern (68) and a second internal conductor pattern (69) insulated from each other and provided on a circuit layer (L5) located between the electrical components and the second surface, at least one first heat transfer via (77) extending from the electrical components to the first internal conductor pattern, and at least one second heat transfer via (78a, 78b) extending from the surface conductor pattern to the second internal conductor pattern.

[0007] In the above-described configuration, a first internal conductor pattern and a second internal conductor pattern, which are insulated from each other, are provided on a circuit layer located between the electrical component and the second surface. The first internal conductor pattern is connected to the electrical component through at least one first heat transfer via. The second internal conductor pattern is connected to a surface conductor pattern on the second surface through at least one second heat transfer via. As a result, heat generated in the electrical component is transferred to the first internal conductor pattern through the first heat transfer via and then to the second internal conductor pattern. Heat from the second internal conductor pattern is transferred to the surface conductor pattern through the second heat transfer via and dissipated from the surface conductor pattern to the outside of the board body. Although the first internal conductor pattern and the second internal conductor pattern are insulated from each other, since they are located on the same circuit layer, heat transfer between them is relatively high. Furthermore, the presence of the first heat transfer via and the second heat transfer via in two layers adjacent to the circuit layer prevents significant differences in mechanical properties between the two layers. As a result, the thermal conductivity and mechanical properties of the substrate body can be improved while maintaining the insulation properties of the electrical components. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a semiconductor device 10 according to a first embodiment. [Figure 2] 1 is a circuit diagram showing a circuit structure of a semiconductor device 10 according to a first embodiment. [Figure 3] 1. For clarity, hatching of the substrate body 12 has been omitted. Also, some overlapping components have been intentionally shown at different positions. [Figure 4] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 110 according to a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 210 according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In one embodiment of the present technology, the at least one second heat-transfer via may include an inner heat-transfer via (78a) located in a region where the electrical component and the second surface face each other, and an outer heat-transfer via (78b) located outside the facing region. With this configuration, the second heat-transfer via can be effectively arranged in accordance with the range through which heat generated by the electrical component passes while diffusing within the board body.

[0010] In one embodiment of the present technology, the semiconductor device may further include a third internal conductor pattern (66) provided in a circuit layer (L4) located in the same depth range as the electrical component and electrically insulated from the electrical component, and at least one third via (79) extending from the second conductor pattern to the third internal conductor pattern. With this configuration, heat generated in the electrical component can be conducted to the second surface of the substrate body from more directions relative to the electrical component.

[0011] In one embodiment of the present technology, the substrate body may have a first layer (13) made of a first material and a second layer (15) made of a second material having higher thermal conductivity than the first material. In this case, the second layer may be located between the electrical component and the second surface. With this configuration, heat generated by the electrical component can be diffused over a wide area of ​​the substrate body through the second layer.

[0012] In the above-described embodiment, the second layer may be exposed to the second surface. With this configuration, heat diffused into the substrate body through the second layer can be dissipated from the second surface of the substrate body to the outside of the substrate body.

[0013] In the above-described embodiment, the second material may include at least one selected from the group including paper, glass cloth, nonwoven glass cloth, woven glass cloth, and glass fiber, and at least one selected from the group including phenolic resin, epoxy resin, polyimide resin, and Teflon (registered trademark) resin. This configuration can effectively increase the thermal conductivity of the second layer while maintaining the original properties required for the substrate body.

[0014] In one embodiment of the present technology, the semiconductor device may further include a surface electric component provided on the first surface and controlling the operation of the electric component. According to the configuration of the present technology, most of the heat generated by the electric component can be guided to the second surface of the substrate body, thereby suppressing a temperature rise on the first surface of the substrate body. By arranging the surface electric component on the first surface, a temperature rise of the surface electric component can also be suppressed.

[0015] In one embodiment of the present technology, the material constituting the first heat-transfer via may be the same as the material constituting the first internal conductor pattern. With this configuration, for example, the first heat-transfer via and the first internal conductor pattern can be formed simultaneously or successively in the process of manufacturing the semiconductor device.

[0016] In one embodiment of the present technology, the material constituting the second heat-transfer via may be the same as the material constituting the surface conductor pattern. With this configuration, for example, the second heat-transfer via and the surface conductor pattern can be formed simultaneously or successively in the process of manufacturing the semiconductor device.

[0017] In one embodiment of the present technology, the electrical component may include a power semiconductor element (21, 22) and a heat sink plate (31, 32) to which the power semiconductor element is joined. A relatively large current flows through the power semiconductor element, and therefore the amount of heat generated therefrom is also relatively large. The configuration disclosed in this specification can be suitably adopted for a semiconductor device including such a power semiconductor element. [Example]

[0018] (Example 1) A semiconductor device 10 of Example 1 will be described with reference to the drawings. The semiconductor device 10 of this example can be employed, for example, in a power control unit of an electric vehicle, and can constitute part of a power conversion circuit for converting power between a power source and a traction motor. The term "electric vehicle" as used herein broadly refers to a vehicle having a traction motor that drives the wheels, and includes, for example, an electric vehicle that is charged by external power, a hybrid vehicle that has an engine in addition to a traction motor, and a fuel cell vehicle that uses a fuel cell as its power source. However, the application of the semiconductor device 10 of this example is not limited to electric vehicles, and it can be employed in various electrical devices.

[0019] As shown in FIGS. 1 to 3 , a semiconductor device 10 includes a substrate body 12, two semiconductor elements 21 and 22, and two heat sink plates 31 and 32. The substrate body 12 has a plate-like shape and includes an upper surface 12a and a lower surface 12b opposite the upper surface 12a. The substrate body 12 is made of an insulating material such as epoxy resin or other resin material. From the upper surface 12a to the lower surface 12b, the substrate body 12 includes an upper layer 14, an intermediate layer 16, and a lower layer 18. The upper layer 14 includes the upper surface 12a of the substrate body 12. The lower layer 18 includes the lower surface 12b of the substrate body 12. The intermediate layer 16 is located between the upper layer 14 and the lower layer 18.

[0020] Here, the X direction and Y direction in the drawing are directions parallel to the upper surface 12a and lower surface 12b of the substrate body 12 and are perpendicular to each other. The Z direction is a direction perpendicular to the upper surface 12a and lower surface 12b of the substrate body 12 and is a direction perpendicular to both the X direction and the Y direction. That is, the above-mentioned upper layer 14, intermediate layer 16, and lower layer 18 are stacked along the Z direction.

[0021] The semiconductor elements 21 and 22 and the heat sink plates 31 and 32 are each electrical components that constitute part of an electrical circuit in the semiconductor device 10. The two semiconductor elements 21 and 22 are disposed on the intermediate layer 16 of the substrate body 12 together with the two heat sink plates 31 and 32. Each of the semiconductor elements 21 and 22 is a power semiconductor element, particularly a switching element. This switching element may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Each of the semiconductor elements 21 and 22 has an upper electrode 21 a and a lower electrode 21 b and a lower electrode 22 b, and can establish or interrupt electrical conduction between the upper electrode 21 a and the lower electrode 21 b.

[0022] As an example, the two semiconductor elements 21, 22 include a first semiconductor element 21 and a second semiconductor element 22. The first semiconductor element 21 and the second semiconductor element 22 are electrically connected in series inside the substrate body 12. As described above, the two semiconductor elements 21, 22 are switching elements such as IGBTs or MOSFETs. The semiconductor device 10 of this embodiment can constitute, for example, a part of an inverter circuit or a DC-DC converter circuit. The number of semiconductor elements 21, 22 is not limited to two. Furthermore, the semiconductor device 10 may include at least one other electrical component instead of the semiconductor elements 21, 22 and the heat sink plates 31, 32.

[0023] The two heat sink plates 31, 32 each have a plate-like shape and are arranged parallel to the substrate body 12. Each of the heat sink plates 31, 32 is made of a conductor, such as copper or another metal. As an example, the two heat sink plates 31, 32 are arranged along the X direction. The two heat sink plates 31, 32 include a first heat sink plate 31 and a second heat sink plate 32. The first semiconductor element 21 is arranged on the first heat sink plate 31, and the lower surface electrodes 21b of the first semiconductor element 21 are electrically connected to the first heat sink plate 31. The first semiconductor element 21 and the first heat sink plate 31 are integrally joined and can be considered as a single electrical component. Similarly, the second semiconductor element 22 is arranged on the second heat sink plate 32, and the lower surface electrodes 21b, 22b of the second semiconductor element 22 are electrically connected to the second heat sink plate 32. The second semiconductor element 22 and the second heat sink plate 32 are also integrally joined together and can be considered as one electrical component.

[0024] The semiconductor device 10 includes a plurality of terminals 40, 42, and 44. These terminals 40, 42, and 44 are external connection terminals for connecting to an external circuit. The plurality of terminals 40, 42, and 44 are made of a conductor such as copper or another metal. As an example, the plurality of terminals 40, 42, and 44 include a P terminal 40, an N terminal 42, and an O terminal 44. The plurality of terminals 40, 42, and 44 are located on the lower surface 12b of the substrate body 12. However, some or all of the plurality of terminals 40, 42, and 44 may be located on the upper surface 12a of the substrate body 12.

[0025] The P terminal 40 is electrically connected to the first heat sink plate 31 inside the substrate body 12 and is electrically connected to the lower electrode 21b of the first semiconductor element 21 via the first heat sink plate 31. The N terminal 42 is electrically connected to the upper electrode 22a of the second semiconductor element 22 inside the substrate body 12. The O terminal 44 is electrically connected to the upper electrode 21a of the first semiconductor element 21 and the second heat sink plate 32 inside the substrate body 12. That is, the O terminal 44 is electrically connected to each of the upper electrode 21a of the first semiconductor element 21 and the lower electrode 22b of the second semiconductor element 22. As a result, when the first semiconductor element 21 is turned on, the P terminal 40 and the O terminal 44 are electrically connected. On the other hand, when the second semiconductor element 22 is turned on, the N terminal 42 and the O terminal 44 are electrically connected.

[0026] The substrate body 12 is provided with multiple circuit layers L1-L6, forming a multilayer substrate structure. The multiple circuit layers L1-L6 include a first circuit layer L1, a second circuit layer L2, a third circuit layer L3, a fourth circuit layer L4, a fifth circuit layer L5, and a sixth circuit layer L6. The first circuit layer L1 is located on the top surface 12a of the substrate body 12. The second circuit layer L2 is located within the upper layer 14 of the substrate body 12. The third circuit layer L3 is located at the boundary between the upper layer 14 and the middle layer 16 of the substrate body 12. The fourth circuit layer L4 is located at the boundary between the substrate body 12, the middle layer 16, and the lower layer 18. The fifth circuit layer L5 is located within the lower layer 18 of the substrate body 12. The sixth circuit layer L6 is located on the bottom surface 12b of the substrate body 12.

[0027] The first circuit layer L1 has a first conductor pattern 61. The first conductor pattern 61 is made of a conductor such as copper or another metal. The first conductor pattern 61 constitutes a control circuit 50 that controls the two semiconductor elements 21 and 22. To this end, a plurality of surface electrical components 52 are mounted on the first conductor pattern 61. The plurality of surface electrical components 52 includes, for example, a gate drive circuit that controls the switching of the semiconductor elements 21 and 22.

[0028] The first conductor pattern 61 here is a general term for one or more conductor patterns required to configure the control circuit 50. In other words, the first conductor pattern 61 may be a single conductor pattern or a combination of multiple conductor patterns. The same applies to the second conductor pattern 62 to the tenth conductor pattern 70 described below. Each of the second conductor pattern 62 to the tenth conductor pattern 70 is a general term for one or more conductor patterns having a common function, and may be a single conductor pattern or a combination of multiple conductor patterns.

[0029] The second circuit layer L2 has a plurality of conductor patterns 62, 63, and 64. Each of the conductor patterns 62, 63, and 64 is made of a conductor such as copper or another metal. The plurality of conductor patterns 62, 63, and 64 includes a second conductor pattern 62, a third conductor pattern 63, and a fourth conductor pattern 64. Although the plurality of conductor patterns 62, 63, and 64 are actually located on the same plane, in FIG. 3 , the second conductor pattern 62 is intentionally displaced relative to the third conductor pattern 63 and the fourth conductor pattern 64 for the purpose of clarity of illustration.

[0030] The second conductor pattern 62 extends over most of the second circuit layer L2 and faces the multiple semiconductor elements 21 and 22. This allows heat generated in the semiconductor elements 21 and 22 to be diffused over a wide area of ​​the board body 12 through the second conductor pattern 62. The second conductor pattern 62 also functions as a shielding layer that blocks electromagnetic noise radiated from the semiconductor elements 21 and 22. Although not particularly limited, the second conductor pattern 62 may be connected to a ground potential, thereby improving the function of the second conductor pattern 62 as a shielding layer.

[0031] The third conductor pattern 63 is connected to the O terminal 44 via the first via 71. In addition, the third conductor pattern 63 is connected to the upper surface electrode 21a of the first semiconductor element 21 and the second heat sink plate 32 via two second vias 72. The first via 71 and the second via 72 are made of a conductor such as copper or another metal. As a result, the two semiconductor elements 21, 22 are electrically connected in series by the second conductor pattern 62, and are also electrically connected to the O terminal 44 via the second conductor pattern 62.

[0032] The fourth conductor pattern 64 is connected to the upper surface electrode 22a of the second semiconductor element 22 via the third via 73. In addition, the fourth conductor pattern 64 is connected to the N terminal 42 via the fourth via 74. The third via 73 and the fourth via 74 are made of a conductor such as copper or another metal. As a result, the upper surface electrode 22a of the second semiconductor element 22 is electrically connected to the N terminal 42 via the fourth conductor pattern 64.

[0033] The semiconductor elements 21, 22 and heat sink plates 31, 32 are arranged on the third circuit layer L3 and the fourth circuit layer L4. The heat sink plates 31, 32 have a thickness equal to the distance from the third circuit layer L3 to the fourth circuit layer L4. The semiconductor elements 21, 22 arranged on the heat sink plates 31, 32 are located on the third circuit layer L3. In addition, a fifth conductor pattern 65 and a sixth conductor pattern 66 are provided on the third circuit layer L3 and the fourth circuit layer L4, respectively. The uses of the fifth conductor pattern 65 and the sixth conductor pattern 66 are not particularly limited. The fifth conductor pattern 65 and the sixth conductor pattern 66 may be connected to a ground potential, for example.

[0034] The fifth circuit layer L5 has a plurality of conductor patterns 67, 68, and 69. Each of the conductor patterns 67, 68, and 69 is made of a conductor such as copper or another metal. The plurality of conductor patterns 67, 68, and 69 includes a seventh conductor pattern 67, an eighth conductor pattern 68, and a ninth conductor pattern 69. Although the plurality of conductor patterns 67, 68, and 69 are actually located on the same plane, in FIG. 3 , the seventh conductor pattern 67 is intentionally displaced relative to the eighth conductor pattern 68 and the ninth conductor pattern 69 for the purpose of clarity of illustration.

[0035] The seventh conductor pattern 67 is connected to the first heat sink plate 31 via a fifth via 75. In addition, the seventh conductor pattern 67 is connected to the P terminal 40 via a sixth via 76. The fifth via 75 and the sixth via 76 are made of a conductor such as copper or another metal. As a result, the bottom electrode 21b of the first semiconductor element 21 is electrically connected to the P terminal 40 via the first heat sink plate 31 and the seventh conductor pattern 67.

[0036] The eighth conductor pattern 68 is provided in an area facing the first heat sink plate 31 or the second heat sink plate 32. The eighth conductor pattern 68 is connected to the first heat sink plate 31 and the second heat sink plate 32 via a plurality of seventh vias 77. The plurality of seventh vias 77 are made of a conductor such as copper or another metal. As a result, the eighth conductor pattern 68 is electrically and thermally connected to the first heat sink plate 31 and the seventh conductor pattern 67 via the plurality of seventh vias 77. Although not particularly limited, the material constituting the plurality of seventh vias 77 may be the same as the material constituting the eighth conductor pattern 68, and may be, for example, copper or aluminum.

[0037] The ninth conductor pattern 69 is provided adjacent to the eighth conductor pattern 68 and is configured so that heat from the eighth conductor pattern 68 is efficiently transferred to the ninth conductor pattern 69. However, the eighth conductor pattern 68 and the ninth conductor pattern 69 are separated by the material that constitutes the substrate body 12, and are electrically insulated from each other. A portion of the ninth conductor pattern 69 is located in a range that faces the first heat sink plate 31 or the second heat sink plate 32, and another portion of the ninth conductor pattern 69 is located outside the facing range.

[0038] A plurality of eighth vias 78a, 78b are connected to the ninth conductor pattern 69. The plurality of eighth vias 78a, 78b extend from the ninth conductor pattern 69 to the sixth circuit layer L6 located on the lower surface 12b of the substrate body 12. The plurality of eighth vias 78a, 78b are made of a conductor such as copper or other metal. As a result, the ninth conductor pattern 69 is electrically and thermally connected to the sixth circuit layer L6 via the plurality of eighth vias 78a, 78b.

[0039] The multiple eighth vias 78a, 78b include at least one inner via 78a and at least one outer via 78b. The inner via 78a is located in an area where the first heat sink plate 31 or the second heat sink plate 32 faces the underside 12b of the substrate main body 12. On the other hand, the outer via 78b is located outside the facing area. The range in which the multiple eighth vias 78a, 78b are arranged is designed to match the range in which heat from the first heat sink plate 31 or the second heat sink plate 32 passes through the substrate main body 12 while diffusing.

[0040] The sixth circuit layer L6 has a tenth conductor pattern 70. The tenth conductor pattern 70 extends over most of the sixth circuit layer L6 and faces the ninth conductor pattern 69 of the fifth circuit layer L5. The tenth conductor pattern 70 is made of a conductor such as copper or another metal. A plurality of eighth vias 78a, 78b are connected to the tenth conductor pattern 70. This allows the tenth conductor pattern 70 to be electrically and thermally connected to the ninth conductor pattern 69 of the fifth circuit layer L5 through the plurality of eighth vias 78a, 78b. Although not particularly limited, the material constituting the tenth conductor pattern 70 may be the same as the material constituting the plurality of eighth vias 78a, 78b, and may be, for example, copper or aluminum.

[0041] As described above, in the semiconductor device 10 of this embodiment, the tenth conductor pattern 70 is provided on the circuit layer L6 located on the lower surface 12b of the substrate main body 12. The eighth conductor pattern 68 and the ninth conductor pattern 69, which are insulated from each other, are provided on the circuit layer L5 located between the heat sink plates 31, 32 and the lower surface 12b of the substrate main body 12. The heat sink plates 31, 32 and the eighth conductor pattern 68 are connected via at least one seventh via 77. The ninth conductor pattern 69 and the tenth conductor pattern 70 are connected via at least one eighth via 78a, 78b.

[0042] With the above-described configuration, heat generated in the semiconductor elements 21, 22 and the heat sink plates 31, 32 is transferred to the eighth conductor pattern 68 via the seventh via 77 and then to the ninth conductor pattern 69 adjacent to the eighth conductor pattern 68. The heat from the ninth conductor pattern 69 is then transferred to the tenth conductor pattern 70 via the eighth vias 78a, 78b and dissipated from the tenth conductor pattern 70 to the outside of the substrate main body 12. Although the eighth conductor pattern 68 and the ninth conductor pattern 69 are insulated from each other, because they are located on the same fifth circuit layer L5, the heat transfer between them is relatively high. Furthermore, because the seventh via 77 and the eighth vias 78a, 78b are present on the two layers above and below the fifth circuit layer L5, there is no significant difference in mechanical properties between the two layers. As a result, the thermal conductivity and mechanical properties of the substrate main body 12 can be improved while maintaining the insulation of the semiconductor elements 21, 22 and the heat sink plates 31, 32.

[0043] The semiconductor device 10 according to the first embodiment is an example of the technology disclosed in the present specification and does not particularly limit the content of the technology. The substrate body 12 in the present embodiment is an example of the substrate body in the present technology. The upper surface 12a and the lower surface 12b of the substrate body 12 in the present embodiment are examples of the first surface and the second surface of the substrate body in the present technology, respectively. The combination of the first semiconductor element 21 and the first heat sink plate 31 and the combination of the second semiconductor element 22 and the second heat sink plate 32 in the present embodiment are examples of the electrical component in the present technology. The tenth conductor pattern 70 in the present embodiment is an example of the surface conductor pattern in the present technology. The eighth conductor pattern 68 in the present embodiment is an example of the first internal conductor pattern in the present technology. The ninth conductor pattern 69 in the present embodiment is an example of the second internal conductor pattern in the present technology. The ninth via in the present embodiment is an example of the heat transfer via in the present technology. The seventh via 77 in the present embodiment is an example of the first heat transfer via in the present technology. The eighth vias 78a and 78b in this embodiment are an example of the second heat transfer vias in the present technology. Of the eighth vias 78a and 78b in this embodiment, the inner via 78a is an example of the inner heat transfer vias in the present technology, and the outer via 78b is an example of the outer heat transfer vias in the present technology. The seventh via 77 in this embodiment is an example of the first heat transfer via in the present technology. And the surface electrical component 52 in this embodiment is an example of the surface electrical component in the present technology.

[0044] (Example 2) A semiconductor device 110 of Example 2 will be described with reference to Fig. 4. The semiconductor device 110 of Example 2 has a plurality of ninth vias 79 added thereto, which is a point where it differs from the semiconductor device 10 of Example 1. Below, differences from Example 1 will be mainly described, and the same reference numerals will be used to denote components common to Example 1, and description thereof will be omitted.

[0045] The plurality of ninth vias 79 extend from the fourth circuit layer L4 to the fifth circuit layer L5, connecting the sixth conductor pattern 66 on the fourth circuit layer L4 and the ninth conductor pattern 69 on the fifth circuit layer L5 to each other. The plurality of ninth vias 79 are made of a conductor such as copper or another metal. As a result, the sixth conductor pattern 66 is electrically and thermally connected to the ninth conductor pattern 69 via the plurality of ninth vias 79.

[0046] The sixth conductor pattern 66 located on the fourth circuit layer L4 is located in the same depth range as the heat sink plates 31 and 32. Therefore, the sixth conductor pattern 66 receives heat diffusing from the heat sink plates 31 and 32 in a direction parallel to the substrate main body 12 (i.e., the X direction or the Y direction). The heat from the sixth conductor pattern 66 is transferred to the ninth conductor pattern through the ninth via 79, and further transferred to the tenth conductor pattern 70 through the outer via 78b of the eighth vias 78a and 78b. This allows heat from the semiconductor elements 21 and 22 and the heat sink plates 31 and 32 to be dissipated from the tenth conductor pattern 70 to the outside of the substrate main body 12. The sixth conductor pattern 66 is electrically insulated from the semiconductor elements 21 and 22 and the heat sink plates 31 and 32.

[0047] The semiconductor device 110 according to this embodiment is also an illustrative embodiment of the technology disclosed in this specification and does not particularly limit the content of the technology. The sixth conductor pattern 66 in this embodiment is an example of the third inner conductor pattern in the technology. The ninth via 79 in this embodiment is an example of the third via in the technology.

[0048] (Example 3) A semiconductor device 210 of Example 3 will be described with reference to Figure 5. The semiconductor device 210 of this example differs from the semiconductor device 110 of Example 2 in that the substrate body 12 has two layers 13 and 15 made of different materials. Below, differences from Example 2 will be mainly described, and components common to Examples 1 and 2 will be denoted by the same reference numerals and will not be described again.

[0049] In this embodiment, the substrate body 12 includes a first layer 13 made of a first material and a second layer 15 made of a second material. The first layer 13 includes the upper layer 14, the middle layer 16, and a portion of the lower layer 18. The second layer 15 is the remaining portion of the lower layer 18, particularly the portion that fills the gap between the fifth circuit layer L5 and the sixth circuit layer L6. That is, the second layer 15 is located at the bottom, including the lower surface 12b of the substrate body 12. The second material constituting the second layer 15 has higher thermal conductivity than the first material constituting the first layer 13. By positioning the second layer 15, which has excellent thermal conductivity, between the heat sink plates 31 and 32 and the lower surface 12b of the substrate body 12, temperature increases in the semiconductor elements 21 and 22 and the heat sink plates 31 and 32 are further suppressed.

[0050] The first material and the second material are not particularly limited. For example, the second material may be a composite material containing fibers, such as at least one selected from the group including paper, glass cloth, nonwoven glass cloth, woven glass cloth, and glass fiber, and at least one selected from the group including phenolic resin, epoxy resin, polyimide resin, and Teflon (registered trademark) resin. The first material may also be, for example, one of the resin materials exemplified herein, and may further contain fibers, as with the second material. The combination of the first material and the second material is not particularly limited, as long as the thermal conductivity of the second material is higher than that of the first material.

[0051] Although specific examples of the technology disclosed in this specification have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or in the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0052] 10, 110, 210: Semiconductor device 12: Board body 12a:Top surface 12b: Bottom surface 21, 22: Semiconductor elements 31, 32: Heat sink plate 40, 42, 44: Terminals 50: Control circuit 52: Surface electrical components 61-70: Conductor pattern 71-79:Beer L1-L6:Circuit layer

Claims

1. A substrate body (12) having a first surface (12a) and a second surface (12b); Electrical components (21, 22, 31, 32) disposed within the substrate body; a surface conductor pattern (70) provided on a circuit layer (L6) located on the second surface; a first internal conductor pattern (68) and a second internal conductor pattern (69) provided on a circuit layer (L5) located between the electrical component and the second surface, insulated from each other, and each having an opposing portion located in a region where the electrical component and the second surface face each other; at least one first heat transfer via (77) extending from the electrical component to the facing portion of the first internal conductor pattern; at least one second heat transfer via (78a, 78b) extending from the surface conductor pattern to the second internal conductor pattern; Equipped with the at least one second heat transfer via includes an inner heat transfer via (78a) located in the region where the electrical component and the second surface face each other; Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the at least one second heat transfer via further includes an outer heat transfer via (78 b) located outside the region where the electrical component and the second surface face each other.

3. a third internal conductor pattern (66) provided on a circuit layer (L4) located in the same depth range as the electrical component and electrically insulated from the electrical component; 3. The semiconductor device according to claim 1, further comprising at least one third via extending from said second internal conductor pattern to said third internal conductor pattern.

4. The substrate body has a first layer (13) made of a first material and a second layer (15) made of a second material having a higher thermal conductivity than the first material, The semiconductor device according to claim 1 , wherein the second layer is located between the electrical component and the second surface.

5. The semiconductor device according to claim 4 , wherein said second layer is exposed at said second surface.

6. The second material is At least one selected from the group consisting of paper, glass cloth, glass nonwoven fabric, glass woven fabric, and glass fiber; 6. The semiconductor device according to claim 4, further comprising at least one selected from the group consisting of phenolic resin, epoxy resin, polyimide resin and Teflon (registered trademark) resin.

7. The semiconductor device according to claim 1 , further comprising a surface electrical component (52) provided on the first surface and controlling the operation of the electrical component.

8. The semiconductor device according to claim 1 , wherein the material forming the first heat transfer via is the same as the material forming the first internal conductor pattern.

9. The semiconductor device according to claim 1 , wherein the second heat transfer vias are made of the same material as the surface conductor pattern.

10. 10. The semiconductor device according to claim 1, wherein the electrical components include a power semiconductor element (21, 22) and a heat sink plate (31, 32) to which the power semiconductor element is joined.

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