Array substrate and display panel

Abstract

SOLUTION: An embodiment of the present disclosure provide an array substrate and a display panel. The array substrate includes a base substrate, a first electrode layer, an insulation layer, and a second electrode layer arranged in order. The base substrate includes a display area and a non-display area. The first electrode layer includes a first common electrode positioned in the display area. The second electrode layer includes a plurality of pixel electrodes and a plurality of common electrode wirings positioned in the display area, and the plurality of pixel electrodes is spaced apart from each other and the common electrode wiring is arranged between at least two adjacent pixel electrodes, and an extension direction of the common electrode wiring is consistent with an extension direction of an edge of adjacent pixel electrode.EFFECT: In the present invention, a common electrode wiring is arranged between at least two adjacent pixel electrodes, and when a signal is input, the common electrode wiring reacts with an adjacent pixel electrode so that an electric field intensity of a corresponding pixel electrode edge increases, thereby a state of dark stripes of the pixel electrode edge is improved, and transmissivity of an array substrate is improved.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to the display field, and in particular to an array substrate and a display panel. [Background technology]

[0002] With the development of display technology, the current mainstream display technologies include liquid crystal display, organic semiconductor display, and quantum dot display. Furthermore, as people's demands increase, high refresh rates and high image quality have become essential elements of high-end electronic display products on the market. Liquid crystal display panels have become increasingly popular due to their advantages of low power consumption and high image quality. However, in the array substrate of a conventional liquid crystal display panel, the electric field at the edge of the pixel electrode gradually weakens, resulting in dark stripes at the edge of the pixel electrode, which reduces the transmittance of the entire array substrate and further affects the display quality of the display panel. Summary of the Invention

[0003] The embodiments of the present application provide an array substrate and a display panel that can solve the problem of a conventional array substrate in which the electric field at the edge of a pixel electrode is weakened, resulting in dark stripes and a decrease in transmittance.

[0004] An embodiment of the present application provides an array substrate, the array substrate comprising: a base substrate including a display area and a non-display area; a first electrode layer disposed on the base substrate and including a first common electrode located in the display area; an insulating layer disposed on a side of the first electrode layer that faces away from the base substrate; a second electrode layer disposed on a side of the insulating layer away from the first electrode layer, the second electrode layer including a plurality of pixel electrodes and a common electrode wiring located in the display area, the plurality of pixel electrodes being disposed at intervals, the common electrode wiring being disposed between at least two adjacent pixel electrodes, and the extension direction of the common electrode wiring being the same as the extension direction of the adjacent pixel electrode edges.

[0005] Preferably, in some embodiments of the present application, the common electrode wiring is provided between any two adjacent pixel electrodes.

[0006] Preferably, in some embodiments of the present application, the second electrode layer includes a plurality of pixel electrode groups arranged in parallel along a first direction, each of the pixel electrode groups includes a plurality of the pixel electrodes arranged in parallel along a second direction, the second direction and the first direction form an included angle, at least one common electrode wiring is installed between two adjacent pixel electrode groups, and the extension direction of the common electrode wiring coincides with the extension direction of the edges of the adjacent pixel electrode groups.

[0007] Preferably, in some embodiments of the present application, the distances between the common electrode wiring and two adjacent edges of the pixel electrode group are equal.

[0008] Preferably, in some embodiments of the present application, the pixel electrode includes a plurality of branch electrodes spaced apart along the first direction, the extension direction of the branch electrodes coincides with the extension direction of the common electrode wiring, there is a first gap between the edge of the pixel electrode group and the adjacent common electrode wiring, there is a second gap between two adjacent branch electrodes of the pixel electrode, and the first gap and the second gap are equal.

[0009] Preferably, in some embodiments of the present application, the width of the common electrode wiring in the first direction is not less than 4 microns and not more than 5 microns.

[0010] Preferably, in some embodiments of the present application, the array substrate includes a first signal line installed in the display area, a first opening is opened on the insulating layer at a position corresponding to the first signal line, and the common electrode wiring is electrically connected to the first signal line through the first opening.

[0011] Preferably, in some embodiments of the present application, the array substrate includes a second signal line arranged in the non-display area, the second signal line being arranged in the same layer as the first signal line, the first electrode layer including a second common electrode located in the non-display area, the second common electrode being electrically connected to the first common electrode, the second electrode layer including a connection electrode located in the non-display area, a second opening being opened in the insulating layer at a position corresponding to the second signal line, the connection electrode being electrically connected to the second signal line through the second opening, a third opening being opened on the insulating layer at a position corresponding to the second common electrode, the connection electrode being electrically connected to the second common electrode through the third opening.

[0012] Preferably, in some embodiments of the present application, the array substrate further includes data lines arranged within the display area, and the orthogonal projection of the common electrode wiring on the base substrate at least partially overlaps with the orthogonal projection of the data lines on the base substrate.

[0013] Accordingly, an embodiment of the present application further provides a display panel, which includes the array substrate according to any one of the above claims.

[0014] In an embodiment of the present application, the array substrate includes a base substrate, a first electrode layer, an insulating layer, and a second electrode layer, which are arranged in sequence, the base substrate including a display area and a non-display area, the first electrode layer including a first common electrode located in the display area, and the second electrode layer including a plurality of pixel electrodes and a common electrode wiring located in the display area, the plurality of pixel electrodes being spaced apart, and the common electrode wiring being arranged between at least two adjacent pixel electrodes, and the extension direction of the common electrode wiring is aligned with the extension direction of the edges of the adjacent pixel electrodes. In the present application, the common electrode wiring is arranged between at least two adjacent pixel electrodes, and when a signal is input, the common electrode wiring reacts with the adjacent pixel electrode to increase the electric field strength of the corresponding pixel electrode edge, thereby improving the dark stripe situation at the pixel electrode edge and improving the transmittance of the array substrate. [Brief explanation of the drawings]

[0015] In order to more clearly explain the technical solutions in the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without exerting any creative efforts. [Figure 1] 3 is a structural schematic diagram of a corresponding display area of ​​an array substrate according to an embodiment of the present application; [Figure 2] 10 is a structural schematic diagram of a corresponding display area of ​​another array substrate according to an embodiment of the present application; [Figure 3] 3 is a structural schematic diagram of a corresponding non-display area of ​​an array substrate according to an embodiment of the present application; [Figure 4] 3 is a schematic diagram of the distribution of pixel electrodes on an array substrate according to an embodiment of the present application; [Figure 5] FIG. 5 is an enlarged structural schematic diagram of region A in FIG. 4 according to an embodiment of the present application. [Figure 6] 2 is a structural schematic diagram of one row of pixel electrodes on an array substrate according to an embodiment of the present application; [Figure 7] 10A and 10B are comparative schematic diagrams of electric field distributions at pixel electrode edges on array substrates according to embodiments of the present application; [Figure 8] 1 is a structural schematic diagram of a display panel according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present application without any creative effort fall within the scope of protection of the present application. It should be understood that the specific embodiments described herein are only intended to explain and interpret the present application, and are not intended to limit the present application. In this application, unless otherwise specified, the terms "up" and "down" used in the directions generally refer to the up and down of the device in its actual use or operating state, specifically in the direction of the paper in the drawings, and "inside" and "outside" refer to the directions relative to the contour of the device.

[0017] The embodiments of the present application provide an array substrate and a display panel, which will be described in detail below. Note that the order of description of the embodiments below does not limit the preferred order of the embodiments.

[0018] First, an embodiment of the present application provides an array substrate, and as shown in Figures 1 to 3, the array substrate 100 includes a base substrate 110, which serves as a support structure for the array substrate 100, supporting other functional structural layers of the array substrate 100 and ensuring the structural stability of the array substrate 100. Here, the base substrate 110 includes a display area S1 and a non-display area S2, and the non-display area S2 serves as a signal input area, used to input control signals to the display area S1 to control the screen display of the display area S1.

[0019] As shown in FIG. 1, the array substrate 100 includes a first electrode layer 140, which is disposed on a base substrate 110. The first electrode layer 140 includes a first common electrode 141 located in the display area S1. The first common electrode 141 is coupled with a pixel electrode 161 to form an electric field and control the deflection of the liquid crystal, thereby realizing the control function of the array substrate 100.

[0020] The array substrate 100 includes an insulating layer 150, which is disposed on the side of the first electrode layer 140 away from the base substrate 110. The insulating layer 150 is used to isolate the first electrode layer 140 from subsequent functional layers to avoid interference between them and further affecting the normal use of the array substrate 100.

[0021] The array substrate 100 includes a second electrode layer 160, which is disposed on a side of the insulating layer 150 away from the first electrode layer 140. The second electrode layer 160 includes a plurality of pixel electrodes 161 and a common electrode line 162 located in the display area S1. The pixel electrodes 161 are spaced apart, and the common electrode line 162 is disposed between at least two adjacent pixel electrodes 161. When a signal is input, the electric field at the edge of the pixel electrode 161 gradually weakens, resulting in a dark stripe region. The formation of the dark stripe region directly affects the transmittance of the entire array substrate 100 and thus the display quality. The common electrode line 162 is disposed between two adjacent pixel electrodes 161. When a signal is input, the common electrode line 162 interacts with the adjacent pixel electrode 161, increasing the electric field strength at the edge of the corresponding pixel electrode 161. This reduces the dark stripe at the edge of the pixel electrode 161 and improves the transmittance of the array substrate 100.

[0022] In the embodiment of the present application, the common electrode wiring 162 and the pixel electrode 161 are disposed on the same film layer, and the common electrode wiring 162 and the first common electrode 141 are disposed on different film layers, but the input signals on the first common electrode 141 and the common electrode wiring 162 are the same. That is, during use of the array substrate 100, the input signal on the first common electrode 141 is used to control the display mode, and the signal on the common electrode wiring 162 is used to strengthen the gradually weakening edge electric field of the adjacent pixel electrode 161, so that two functions can be achieved with the same signal, which further simplifies the signal input method on the array substrate 100.

[0023] Here, the extension direction of the common electrode wiring 162 coincides with the extension direction of the edge of the adjacent pixel electrode 161, i.e., when a signal is input, the electric field reaction between the common electrode wiring 162 and the edge of the adjacent pixel electrode 161 can maintain the same extension direction, thereby improving the uniformity of the electric field strength change at the edge of the pixel electrode 161 and further improving the transmittance of the array substrate 100.

[0024] As shown in FIG. 6, the pixel electrode 161 has a first bent region, and the common electrode wiring 162 between two adjacent pixel electrodes 161 has a second bent region at a position corresponding to the first bent region, and the structural shape of the second bent region matches the structural shape of the first bent region, i.e., the extension direction of the common electrode wiring 162 matches the extension direction of the edge of the adjacent pixel electrode 161. As can be understood, the alignment of the extension directions described in the embodiments of the present application means that the extension directions of the common electrode wiring 162 and the contours of the adjacent edges of the pixel electrodes 161 are aligned, so that the distance between the common electrode wiring 162 and the adjacent pixel electrodes 161 in the extension direction is always equal. As a result, when a signal is input, the electric field reaction between the common electrode wiring 162 and the edges of the adjacent pixel electrodes 161 can maintain alignment of the extension direction, and further improve the uniformity of the change in electric field strength at the edges of the pixel electrodes 161, effectively reducing the dark stripe areas and improving the distribution uniformity of the dark stripe areas, thereby improving the transmittance of the entire array substrate 100.

[0025] In the embodiment of the present application, the array substrate 100 includes a base substrate 110, a first electrode layer 140, an insulating layer 150, and a second electrode layer 160, which are arranged in this order. The base substrate 110 includes a display area S1 and a non-display area S2. The first electrode layer 140 includes a first common electrode 141 located in the display area S1. The second electrode layer 160 includes a plurality of pixel electrodes 161 and common electrode wirings 162 located in the display area S1. The plurality of pixel electrodes 161 are arranged at intervals, and the common electrode wirings 162 are arranged between at least two adjacent pixel electrodes 161. The extension direction of the common electrode wirings 162 coincides with the extension direction of the edges of the adjacent pixel electrodes 161. In the present application, a common electrode wiring 162 is installed between at least two adjacent pixel electrodes 161. When a signal is input, the common electrode wiring 162 reacts with the adjacent pixel electrode 161, thereby increasing the electric field strength at the edge of the corresponding pixel electrode 161, thereby improving the dark stripe situation at the edge of the pixel electrode 161 and improving the transmittance of the array substrate 100.

[0026] In some embodiments, a common electrode wiring 162 is installed between any two adjacent pixel electrodes 161. That is, when a plurality of pixel electrodes 161 are distributed in an array, the common electrode wiring 162 is also distributed in an array like a mesh structure, and a common electrode wiring 162 is installed between every two pixel electrodes 161. This can increase the electric field strength at at least both edges of each pixel electrode 161 when a signal is input, thereby further improving the overall dark stripe situation and further improving the transmittance of the array substrate 100.

[0027] 4, the second electrode layer 160 preferably includes a plurality of pixel electrode groups 164 arranged in parallel along a first direction X, each pixel electrode group 164 including a plurality of pixel electrodes 161 arranged in parallel along a second direction Y, and the second direction and the first direction form an included angle. That is, when the first direction X is the row direction and the second direction Y is the column direction, the plurality of pixel electrodes 161 are distributed in an array, the plurality of pixel electrodes 161 in each column constitute one pixel electrode group 164, and the plurality of pixel electrode groups 164 are distributed in a row.

[0028] Here, at least one common electrode wiring 162 is installed between two adjacent pixel electrode groups 164, and the extension direction of the common electrode wiring 162 coincides with the extension direction of the edges of the adjacent pixel electrode groups 164. That is, the common electrode wiring 162 is installed between two adjacent columns of pixel electrodes 161, and the extension direction of the common electrode wiring 162 coincides with the extension direction of the edges of the pixel electrodes 161 in the adjacent columns, so that one common electrode wiring 162 can simultaneously improve the uniformity of the electric field strength change at the edges of the pixel electrodes 161 in the entire adjacent columns, and effectively reduce the dark stripe areas at the edges of the pixel electrodes 161 in the entire column, thereby improving the transmittance of the entire array substrate 100.

[0029] In some embodiments, common electrode wirings 162 are provided on both opposing sides of any one pixel electrode group 164 in the first direction X. That is, a plurality of pixel electrode groups 164 are grouped together, and common electrode wirings 162 are provided on both opposing sides of the group in the first direction X, thereby improving the dark stripes in the edge regions of the display area S1 of the array substrate 100 in the first direction X, and further improving the transmittance of the array substrate 100 and display quality.

[0030] The positions where the common electrode wiring 162 and the pixel electrode 161 are disposed opposite each other can be adjusted according to the actual situation and are not particularly limited here. The common electrode wiring 162 can be disposed only in the areas where there are no noticeable dark stripes, and the number of common electrode wirings 162 can be reduced, which can reduce the difficulty of the manufacturing process and save costs.

[0031] Preferably, the distance between the common electrode wiring 162 and the edges of two adjacent pixel electrode groups 164 is equal, i.e., the common electrode wiring 162 is located in the central region of the gap between the two adjacent pixel electrode groups 164, so that when a signal is input, the electric field response between the common electrode wiring 162 and the two adjacent pixel electrode groups 164 is consistent, thereby improving the uniformity of the electric field strength change at the edges of the pixel electrode groups 164, further improving the uniformity of the transmittance of the array substrate 100, and further improving the display quality.

[0032] 6 , in some embodiments, the pixel electrode 161 includes a plurality of branch electrodes 1611 spaced apart along the first direction X, and the extension direction of the branch electrodes 1611 coincides with the extension direction of the common electrode wiring 162, i.e., the distribution direction of the plurality of branch electrodes 1611 of each pixel electrode 161 coincides with the distribution direction of the plurality of pixel electrode groups 164, and the extension direction of the branch electrodes 1611 coincides with the extension direction of the edges of the pixel electrode groups 164. The plurality of branch electrodes 1611 are electrically connected to each other, thereby constituting one pixel electrode 161.

[0033] Here, there is a first gap between the edge of the pixel electrode group 164 and the adjacent common electrode wiring 162, and there is a second gap between two adjacent branch electrodes 1611 of the pixel electrode 161, and the first gap and the second gap are equal. That is, the gaps in the first direction X are all equal. On the one hand, because the common electrode wiring 162 and the pixel electrode 161 are located on the same film layer and are formed using the same photomask, all gaps can be set to the same distance, which is advantageous for simplifying the photomask design for the second electrode layer 160 and improving production efficiency. On the other hand, if the branch electrode 1611 and the common electrode wiring 162 are both regarded as a single signal line and the first distance is set to be equal to the second distance, the distance between any two signal lines will be equal, and when a signal is input, the electric field response between any two signal lines will be consistent, thereby ensuring a consistent distribution of electric field strength. This effectively reduces the dark stripe areas and improves the uniformity of the distribution of the dark stripe areas, further improving the uniformity of the transmittance and improving display quality.

[0034] In some other embodiments, as shown in FIG. 2 , two common electrode wirings 162 are spaced apart along the first direction X between two adjacent pixel electrode groups 164. When a signal is input, an electric field reaction occurs between each of the two adjacent pixel electrode groups 164 and the adjacent common electrode wiring 162, thereby strengthening the gradually weakening electric field between the two adjacent pixel electrode groups 164 and preventing mutual interference. Furthermore, the dark stripe areas around the pixel electrode groups 164 are reduced, which effectively reduces the transmittance loss caused by the dark stripe areas and improves display quality.

[0035] In some embodiments, there is a third gap between the two common electrode wirings 162 between two adjacent pixel electrode groups 164, and the third gap is equal to the first gap. That is, the first gap, the second gap, and the third gap are equal, that is, the gaps in the first direction X are all equal.

[0036] On the one hand, because the common electrode wiring 162 and the pixel electrode 161 are located on the same film layer and are formed using the same photomask, all gaps can be set to the same interval, which is advantageous for simplifying the photomask design for the second electrode layer 160 and improving production efficiency. On the other hand, if the branch electrode 1611 and the common electrode wiring 162 are all regarded as a single signal line and the first interval, second interval, and third interval are set to be equal, the intervals between any two signal lines will be equal, and when a signal is input, the electric field response between any two signal lines will be consistent, thereby making the distribution of electric field strength consistent. This effectively reduces the dark stripe areas and improves the uniformity of the distribution of the dark stripe areas, further improving the uniformity of the transmittance and improving display quality.

[0037] Preferably, when manufacturing the common electrode wiring 162, the width of the common electrode wiring 162 in the first direction X can be set to be 4 microns or more and 5 microns or less. If the width of the common electrode wiring 162 in the first direction X is too small, the manufacturing process for the common electrode wiring 162 will require higher precision, which will increase the difficulty and cost of manufacturing. If the width of the common electrode wiring 162 in the first direction X is too large, the gap between the common electrode wiring 162 and the adjacent pixel electrode group 164 will be too small, which will increase the risk of contact between the common electrode wiring 162 and the adjacent pixel electrode group 164 and be detrimental to the electric field reaction between the common electrode wiring 162 and the adjacent pixel electrode group 164.

[0038] During actual manufacturing, the width of the common electrode wiring 162 in the first direction X can be set to 4 microns, 4.2 microns, 4.5 microns, 4.8 microns, 5 microns, or the like. The specific value of the width can be adjusted according to design requirements. As long as the installation of the common electrode wiring 162 can effectively improve the dark stripe situation at the edges of the adjacent pixel electrode groups 164 and can ensure the improvement of the transmittance of the array substrate 100, there is no particular limitation here.

[0039] Furthermore, during the manufacturing of the common electrode wiring 162, the number and width of the common electrode wiring 162 between two adjacent pixel electrode groups 164 can be adjusted based on the distance between two adjacent pixel electrode groups 164, the distance between two adjacent branch electrodes 1611 in one pixel electrode 161, and the manufacturing accuracy of the common electrode wiring 162, so that the installation of the common electrode wiring 162 can effectively improve the dark stripe situation at the edges of the adjacent pixel electrode groups 164, and ensure the improvement of the transmittance of the array substrate 100.

[0040] 1 and 5, the array substrate 100 preferably includes a first signal line 121 disposed in the display area S1, a first opening 151 formed on the insulating layer 150 at a position corresponding to the first signal line 121, and a common electrode line 162 electrically connected to the first signal line 121 through the first opening 151. The array substrate 100 further includes a source and a drain disposed in the display area S1, and the pixel electrode 161 is electrically connected to the drain. That is, during use of the array substrate 100, the first signal line 121 in the display area S1 inputs a signal to the common electrode line 162, and controls the signal conduction between the source and drain to input a signal to the pixel electrode 161, thereby generating an electric field reaction between the common electrode line 162 and the adjacent pixel electrode 161, thereby effectively improving the dark stripes at the edges of the adjacent pixel electrodes 161 and improving the transmittance of the array substrate 100.

[0041] 3, the array substrate 100 includes a second signal line 122 disposed in the non-display area S2, the second signal line 122 being disposed in the same layer as the first signal line 121, the first electrode layer 140 including a second common electrode 142 disposed in the non-display area S2, the second common electrode 142 being electrically connected to the first common electrode 141, and the second electrode layer 160 including a connecting electrode 163 disposed in the non-display area S2. That is, when manufacturing the array substrate 100, the first signal line 121 and the second signal line 122 are simultaneously formed using one photomask manufacturing process, the first common electrode 141 and the second common electrode 142, which are electrically connected to each other, are simultaneously formed using one photomask, and the pixel electrode 161, the common electrode wiring 162, and the connecting electrode 163 are simultaneously formed using one photomask.

[0042] Here, a second opening 152 is formed on the insulating layer 150 at a position corresponding to the second signal line 122, and the connecting electrode 163 is electrically connected to the second signal line 122 through the second opening 152. A third opening 153 is formed on the insulating layer 150 at a position corresponding to the second common electrode 142, and the connecting electrode 163 is electrically connected to the second common electrode 142 through the third opening 153. That is, the first common electrode 141 is electrically connected to the second signal line 122 through the second common electrode 142 and the connecting electrode 163. Therefore, when the array substrate 100 is used, an input signal is transmitted to the connecting electrode 163 through the second signal line 122 in the non-display area S2, from the connecting electrode 163 to the second common electrode 142, and then transmitted to the first common electrode in the display area S1 by the second common electrode 142, thereby controlling the display mode of the display area S1.

[0043] As can be seen, the base substrate 110 includes, in order, a base layer, a signal layer (including a first signal line 121 and a second signal line 122), a gate insulating layer 133, a data line 123, a passivation layer 131, and a planarization layer 132. Accordingly, the first opening 151 and the second opening 152 pass through the insulating layer, the planarization layer 132, the passivation layer 131, and the gate insulating layer 133, in order, and the third opening 153 passes through the insulating layer.

[0044] When the array substrate 100 is used, input signals on the first common electrode 141 and the common electrode wiring 162 located in the display area S1 are both transmitted by signal lines (not shown) in the non-display area S2. Here, the input signal on the common electrode wiring 162 is transmitted directly to the first signal line 121 by the signal line in the non-display area S2, and then transmitted to the common electrode wiring 162 by the first signal line 121. The input signal on the first common electrode 141 is first transmitted to the second signal line 122 by the signal line in the non-display area S2, then transmitted to the connecting electrode 163 by the second signal line 122, then transmitted to the second common electrode 142 by the connecting electrode 163, and then transmitted to the first common electrode 141 by the second common electrode 142.

[0045] Specifically, Figure 7 is a comparative schematic diagram of the electric field distribution at the edge of the pixel electrode 161 in the array substrate 100 according to an embodiment of the present application, where the solid line a represents the electric field distribution state at the edge of the pixel electrode 161 corresponding to when no common electrode wiring 162 is installed between two adjacent pixel electrodes 161, and the dashed line b represents the electric field distribution state at the edge of the pixel electrode 161 corresponding to when a common electrode wiring 162 is installed between two adjacent pixel electrodes 161.

[0046] FFS (Fringe Field Switching) is a liquid crystal display technology in which the pixel electrode 161 and the first common electrode 141 are coupled to form an electric field, and the oriented liquid crystal molecules are deflected in a direction parallel to the plane of the array substrate 100 under the action of the electric field, thereby improving the light transmission efficiency, i.e., the transmittance, of the liquid crystal layer 300.

[0047] 7, when a common electrode wiring 162 is not installed between two adjacent pixel electrodes 161, the electric field strength between the two adjacent pixel electrodes 161 gradually weakens, restricting the deflection of the oriented liquid crystal molecules, resulting in many dark stripes at the edges of the pixel electrodes 161 and reducing the transmittance of the array substrate 100. When a common electrode wiring 162 is installed between two adjacent pixel electrodes 161, an electric field reaction occurs between the common electrode wiring 162 and the adjacent pixel electrode 161 during signal input, which increases the gradually weakening electric field strength, helping the oriented liquid crystal molecules deflect under the action of the electric field, thereby improving the light transmittance of the liquid crystal layer 300.

[0048] Here, as shown in FIG. 7, the array substrate 100 further includes a data line 123 arranged in the display area S1, and the orthogonal projection of the common electrode wiring 162 on the base substrate 110 at least partially overlaps with the orthogonal projection of the data line 123 on the base substrate 110. That is, the common electrode wiring 162 and the data line 123 are arranged in a stacked manner in the thickness direction of the array substrate 100, but the common electrode wiring 162 is located between two adjacent pixel electrodes 161, so that the common electrode wiring 162 can shield the capacitive coupling between the data line 123 and the pixel electrode 161, and further improve the display effect of the entire array substrate 100.

[0049] Next, an embodiment of the present application provides a display panel, which includes an array substrate, and the specific structure of the array substrate can be referred to the above embodiments. The display panel adopts all the technical solutions of all the above embodiments, and therefore has at least all the beneficial effects brought by the technical solutions of the above embodiments, and the description thereof will be omitted here.

[0050] 8, the display panel 10 includes an array substrate 100, a color film substrate 200, and a liquid crystal layer 300. The color film substrate 200 is located on the side of the second electrode layer 160 of the array substrate 100 that is farther from the base substrate 110 of the array substrate 100, and is disposed opposite the array substrate 100. When assembling the display panel 10, the array substrate 100 and the color film substrate 200 are mated to form an accommodating cavity, and the liquid crystal layer 300 is filled in the accommodating cavity between the color film substrate 200 and the array substrate 100. During operation of the display panel 10, by controlling the driving signals on the array substrate 100, the liquid crystal molecules in the liquid crystal layer 300 can be rotated to change the angle of the emitted light and form different display screens.

[0051] FFS (Fringe Field Switching) is a liquid crystal display technology in which the pixel electrode 161 and the first common electrode 141 are coupled to form an electric field, and the oriented liquid crystal molecules are deflected in a direction parallel to the plane of the array substrate 100 under the action of the electric field, thereby improving the light transmission efficiency of the liquid crystal layer 300.

[0052] Specifically, the array substrate 100 includes a base substrate 110, a first electrode layer 140, an insulating layer 150, and a second electrode layer 160, which are arranged in this order. The base substrate 110 includes a display area S1 and a non-display area S2. The first electrode layer 140 includes a first common electrode 141 located in the display area S1. The second electrode layer 160 includes a plurality of pixel electrodes 161 and common electrode wirings 162 located in the display area S1. The plurality of pixel electrodes 161 are arranged at intervals, and the common electrode wirings 162 are arranged between at least two adjacent pixel electrodes 161. The extension direction of the common electrode wirings 162 coincides with the extension direction of the edges of the adjacent pixel electrodes 161. In the present application, a common electrode wiring 162 is installed between at least two adjacent pixel electrodes 161. When a signal is input, the common electrode wiring 162 reacts with the adjacent pixel electrode 161, thereby increasing the electric field strength at the edge of the corresponding pixel electrode 161, thereby improving the dark stripe situation at the edge of the pixel electrode 161, improving the transmittance of the array substrate 100, and further improving the display quality of the display panel 10.

[0053] It should be noted that the application range of the display panel 10 in the embodiments of the present application is very wide, and various display and lighting related display devices such as televisions, computers, mobile phones, foldable and rollable displays, and wearable devices such as smart bracelets and smart watches are all within the scope of application of the display panel 10 in the embodiments of the present application.

[0054] Finally, the embodiments of the present application further provide a display device, which includes a display panel, and the specific structure of the display panel can be referred to the above embodiments. The display device adopts all the technical solutions of all the above embodiments, and therefore has at least all the beneficial effects brought by the technical solutions of the above embodiments, and the description thereof will be omitted here.

[0055] The display device includes a display panel 10, a control circuit, and a case, where the case is connected to the display panel 10 to support and fix the display panel 10, and the control circuit is installed in the case and electrically connected to the display panel 10 to control the screen display of the display panel 10.

[0056] Here, the display panel 10 can be fixed on a case to form a single unit with the case, and the display panel 10 and the case form a sealed space to accommodate a control circuit. The control circuit can be a motherboard of the display device, and one or more functional assemblies such as a battery, an antenna structure, a microphone, a speaker, an earphone interface, a universal serial bus interface, a camera, a distance sensor, an ambient light sensor, and a processor can be integrated on the control circuit, thereby enabling the display device to be adapted to various application fields.

[0057] It should be noted that the display device is not limited to the above content and may further include other devices, such as a camera, an antenna structure, a fingerprint unlocking module, etc., thereby expanding its range of use, and is not particularly limited here.

[0058] The above has introduced in detail the array substrate and display panel according to the embodiments of the present application, and in this specification, the principles and embodiments of the present application have been described using specific examples. However, the explanation of the above examples is only for understanding the method and core idea of ​​the present application, and those skilled in the art can modify the specific embodiments and application scope based on the idea of ​​the present application. In short, the contents of this specification should not be construed as limiting the present application.

Claims

1. An array substrate, a base substrate including a display area and a non-display area; a first electrode layer disposed on the base substrate and including a first common electrode located in the display area; an insulating layer disposed on a side of the first electrode layer that faces away from the base substrate; a second electrode layer disposed on a side of the insulating layer away from the first electrode layer, the second electrode layer including a plurality of pixel electrode groups disposed in parallel along a first direction, each of the pixel electrode groups including a plurality of pixel electrodes disposed in parallel along a second direction and located in the display area, the second electrode layer further including common electrode wirings located in the display area, the plurality of pixel electrodes being disposed at intervals, two common electrode wirings having a third interval in the first direction being disposed between two of the pixel electrode groups adjacent to each other in the first direction and being insulated from the pixel electrodes, and the contours of the common electrode wirings and edges of the adjacent pixel electrode groups being consistent so that a distance in the first direction between the common electrode wirings and edges of the adjacent pixel electrodes is constant; the second direction and the first direction form an included angle; the pixel electrode includes a plurality of branch electrodes spaced apart along the first direction, the extending direction of the branch electrodes coincides with the extending direction of the common electrode wiring, a first distance is provided between an edge of the pixel electrode group and an adjacent one of the common electrode wirings in the first direction, and a second distance is provided between two adjacent branch electrodes of the pixel electrode in the first direction; An array substrate, wherein the first interval, the second interval, and the third interval are equal to each other.

2. 2. The array substrate according to claim 1, wherein the width of the common electrode wiring in the first direction is not less than 4 microns and not more than 5 microns.

3. 2. The array substrate according to claim 1, wherein the array substrate includes a first signal line installed in the display area, a first opening is formed on the insulating layer at a position corresponding to the first signal line, and the common electrode wiring is electrically connected to the first signal line through the first opening.

4. 4. The array substrate of claim 3, wherein the array substrate includes a second signal line disposed in the non-display area, the second signal line being disposed in the same layer as the first signal line, the first electrode layer including a second common electrode disposed in the non-display area, the second common electrode being electrically connected to the first common electrode, the second electrode layer including a connection electrode disposed in the non-display area, a second opening being formed in the insulating layer at a position corresponding to the second signal line, the connection electrode being electrically connected to the second signal line through the second opening, and a third opening being formed in the insulating layer at a position corresponding to the second common electrode, the connection electrode being electrically connected to the second common electrode through the third opening.

5. 2. The array substrate according to claim 1, wherein the array substrate further includes data lines disposed within the display area, and the orthogonal projection of the common electrode wiring on the base substrate at least partially overlaps with the orthogonal projection of the data lines on the base substrate.

6. A display panel comprising the array substrate according to any one of claims 1 to 5.

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