Antenna device and camera system

Abstract

To provide an antenna device that operates satisfactorily with reduced parasitic oscillation.SOLUTION: An antenna device of the present disclosure has: an antenna array in which a plurality of antennas is arranged each consisting of a negative differential resistance element and a resonance circuit; a voltage bias circuit that applies a voltage to the antenna array; a first shunt element that is connected in parallel with the negative differential resistance elements and the voltage bias circuit between the antenna array and the voltage bias circuit and has a first resistance and a first capacity connected in series thereto; and a second shunt element that is connected in parallel with the negative differential resistance elements and the voltage bias circuit between the first shunt element and the voltage bias circuit and has a second resistance and a second capacity connected in series thereto. The first shunt element and the second shunt element have a lower impedance with reference to a value of resistance of the negative differential resistance elements.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an antenna device and a camera system that transmits or receives electromagnetic waves. [Background technology]

[0002] An antenna consisting of a negative differential resistance element and a resonant circuit can generate electromagnetic waves (hereinafter simply referred to as "terahertz waves") that include at least a part of the frequency band from millimeter waves to terahertz waves (30 GHz or more and 30 THz or less). As an example, Patent Document 1 discloses an antenna that emits terahertz waves by integrating a negative differential resistance element and a resonant circuit on a semiconductor chip.

[0003] In Patent Document 1, a resonant tunneling diode (RTD) is used as the negative differential resistance element, and a power supply is provided that supplies a bias voltage to the negative differential resistance element. The bias voltage from the power supply is supplied to the negative differential resistance element via a bias supply unit that includes an electric wire and a conductor. Parasitic low-frequency oscillation (parasitic oscillation) other than the terahertz waves emitted by the antenna is often generated by the structure associated with the bias supply unit. Therefore, Patent Document 1 discloses a technology for suppressing parasitic oscillation by arranging a shunt element in the bias supply unit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-180049 Summary of the Invention [Problem to be solved by the invention]

[0005] One way to increase antenna output is to create an antenna array by arranging multiple antennas, each consisting of a negative differential resistance element and a resonant circuit. When mounting a chip integrating this antenna array on a separate substrate such as a ceramic package or printed circuit board, the chip and substrate are connected with bonding wires, and a shunt element is placed on the substrate to suppress parasitic oscillation.

[0006] The resistances and capacitances that make up these bonding wires and shunt elements have parasitic inductance. This parasitic inductance cannot be ignored in order to properly generate terahertz waves, and it is the cause of parasitic oscillations at frequencies lower than terahertz waves (less than 30 GHz). This parasitic inductance is particularly likely to cause parasitic oscillations in the 10 MHz to 10 GHz range. In such an antenna array, the circuit parameters and placement of the shunt elements on the substrate must be optimized to properly oscillate terahertz waves, but this is not fully considered in Patent Document 1.

[0007] Therefore, an object of the present disclosure is to provide a technique for suppressing parasitic oscillation in an antenna device having an antenna array made up of a negative differential resistance element and a resonant circuit. [Means for solving the problem]

[0008] In order to achieve the above object, an antenna device according to the present disclosure includes: An antenna device for transmitting or receiving electromagnetic waves, an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and The first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element. And, The antenna device is characterized by satisfying the following formulas (1) to (3): Rp +1 / (2π×f×Cp) < r ···(1) Rc +1 / (2π×f×Cc) < r ···(2) L / (Cc×r) <Rc ···(3) Here, r is the absolute value of the resistance value of the negative differential resistance element, Rp is the resistance value of the second resistor, Cp is the capacitance value of the second capacitor, Rc is the resistance value of the first resistor, Cc is the capacitance value of the first capacitor, L is the inductance of the path connecting the first shunt element and the second shunt element, and f is a frequency less than the resonant frequency of the resonant circuit. In order to achieve the above object, the antenna device according to the present disclosure comprises: An antenna device for transmitting or receiving electromagnetic waves, an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element, The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4): L≦5nH (4) When the path is divided into a first portion whose cross section can be approximated to a circle and a second portion whose cross section can be approximated to a rectangle, the inductance L1 of the first portion is calculated by the following formula (5), and the inductance L2 of the second portion is calculated by the following formula (6). L1=0.2×l1×[ln(4×l1 / d)- 0.75] ···(5) L2=0.2×l2×[ln{2×l2 / (w + h)}+0.2235×(w+h) / l2+0.5] ···(6) where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion. In order to achieve the above object, the antenna device according to the present disclosure comprises: An antenna device for transmitting or receiving electromagnetic waves, an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element, The antenna array includes an antenna device having a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance. In order to achieve the above object, the antenna device according to the present disclosure comprises: An antenna device for transmitting or receiving electromagnetic waves, a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged; a substrate on which the chip is disposed; a voltage bias circuit for applying a voltage to the antenna array; The chip is a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit and including at least a first capacitance; a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array; The substrate is a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate; the antenna array is located between the first pad and the second pad; The antenna array includes an antenna device having a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance. In order to achieve the above object, the antenna device according to the present disclosure comprises: An antenna device for transmitting or receiving electromagnetic waves, an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element, a plurality of pairs of the first shunt element and the second shunt element are arranged; The antenna device includes at least two pairs of the first shunt element and the second shunt element, which are arranged symmetrically with respect to an axis passing through the center of the antenna array.

[0009] Moreover, the antenna device according to the present disclosure includes: An antenna device for transmitting or receiving electromagnetic waves, a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged; a substrate on which the chip is disposed; a voltage bias circuit for applying a voltage to the antenna array; The chip is a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit and including at least a first capacitance; a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array; The substrate is a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate; The antenna device includes an antenna array located between the first pad and the second pad. In addition, the camera system according to the present disclosure includes: The antenna device; a detection device for detecting electromagnetic waves transmitted from the antenna device; and a processing unit for processing signals from the detection device. [Effects of the Invention]

[0010] According to the technology of the present disclosure, it is possible to provide an antenna device and a camera system in which the configuration of the shunt element is optimized, parasitic oscillation is suppressed, and the antenna device and camera system operate well. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view illustrating an example of an antenna device according to a first embodiment; [Figure 2] 1 is a cross-sectional view of an example of an antenna device according to a first embodiment; [Figure 3] 1 is a cross-sectional view of an example of an antenna device according to a first embodiment; [Figure 4] FIG. 1 is an explanatory diagram showing an antenna array according to a first embodiment; [Figure 5] 1 is an equivalent circuit diagram of an antenna device according to a first embodiment; [Figure 6] Graph illustrating the antenna device according to the first embodiment [Figure 7] Graph illustrating the antenna device according to the first embodiment [Figure 8] FIG. 1 is a diagram illustrating an antenna device according to a first embodiment. [Figure 9] FIG. 1 is a diagram illustrating an antenna device according to a first embodiment. [Figure 10] 10 is a plan view of an antenna device according to a second embodiment of the present invention; [Figure 11]10 is a plan view of an antenna device according to a third embodiment of the present invention; [Figure 12] 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; [Figure 13] 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; [Figure 14] 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; [Figure 15] 10 is a plan view illustrating an example of an antenna device according to a fifth embodiment. [Figure 16] 10 is a plan view illustrating an example of an antenna device according to a fifth embodiment. [Figure 17] FIG. 10 is an equivalent circuit diagram of an antenna device according to a sixth embodiment. [Figure 18] FIG. 10 is an explanatory diagram showing an antenna array according to a sixth embodiment. [Figure 19] 13 is a cross-sectional view of an antenna device according to a sixth embodiment of the present invention; [Figure 20] FIG. 13 is an explanatory diagram showing an antenna array according to a modification of the sixth embodiment. [Figure 21] 13 is an example of a cross-sectional view of an antenna device according to a modification of the sixth embodiment. [Figure 22] 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; [Figure 23] FIG. 13 is a schematic diagram illustrating a camera system according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to the following embodiments and can be modified as appropriate without departing from the spirit of the present disclosure. In addition, in the drawings described below, parts having the same functions are designated by the same reference numerals, and their description may be omitted or simplified.

[0013] (First embodiment) An antenna device according to a first embodiment will be described with reference to Fig. 1 to Fig. 9. Fig. 1 is a plan view showing a schematic configuration of the antenna device according to this embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1.

[0014] As shown in FIGS. 1 and 2, the antenna device 100 according to this embodiment has a rectangular chip 11 mounted on a substrate 10, on which an antenna array 12 consisting of a plurality of antennas 121 is arranged. FIG. 1 shows the configuration on the surface of the chip 11. The details of the antenna 121 will be described later; the antenna 121 is composed of a negative differential resistance element and a resonant circuit, and transmits or receives electromagnetic waves in the terahertz frequency band. The antenna 121 generates electromagnetic waves (hereinafter simply referred to as "terahertz waves") including at least a portion of the frequency band from millimeter waves to terahertz waves (30 GHz or higher and 30 THz or lower). Adjacent antennas 121 are capacitively coupled via a microstrip line (described later using FIG. 4).

[0015] In addition to the antenna array 12, the chip 11 includes a resistive element 131 and a capacitive element 132 that constitute a first shunt element 1300, a pad 141 that applies a bias voltage to the chip 11, and a pad 142 that applies a ground voltage to the chip 11. The pads 141 and 142 are used for electrical connection with an external circuit of the chip 11, for example, for supplying a predetermined voltage from the outside. The pads 141 and 142 are made of a conductor. Hereinafter, the term "pad" refers to a pad for electrical connection with the outside. Specifically, the pad is used to receive a predetermined voltage from the outside, and may be used to supply a predetermined voltage to the outside. In this embodiment, the predetermined voltage may be a ground voltage, a power supply voltage, a voltage from a voltage bias circuit, or the like.

[0016] The antenna array 12 is disposed approximately in the center of the chip 11, and the capacitive element 132 is disposed adjacent to the antenna array 12. Furthermore, by disposing the capacitive element 132 so as to surround the antenna array 12, the arrangement area of ​​the capacitive element on the chip 11 can be expanded, thereby ensuring a large capacitance. Furthermore, the capacitive elements 132 are disposed separately on each of two opposing sides of the chip 11 (on the right and left sides of the chip 11 in the figure) so that the antenna array 12 is sandwiched between the capacitive elements 132. This allows the resistive element 131, wiring, pads, etc. to be disposed in the portion where the capacitive element 132 is not disposed (on the upper side of the chip 11 in the figure), thereby enabling the chip size of the chip 11 to be reduced.

[0017] 2, one terminal of the resistive element 131 is connected to one terminal of the capacitive element 132 via a wiring 133 and a via 134. The resistive element 131 and the capacitive element 132 are connected in series, and it is preferable to arrange the resistive element 131 near the capacitive element 132 to facilitate the connection. Alternatively, the resistive element 131 may be arranged so as to overlap the capacitive element 132. The other terminal of the resistive element 131 is connected to a pad 141 via a bias voltage line 130. The bias voltage line 130 is also arranged between the antennas 121 of the antenna array 12 and is connected in common to each antenna 121, thereby applying a bias voltage to each antenna 121. The other terminal of the capacitive element 132 is connected to the pad 142 via a wiring and a via (not shown).

[0018] The capacitance element 132 is a MIM (Metal-Insulator-Metal) capacitor in which an insulating layer is sandwiched between metal layers. The metal layer can be a wiring layer in the chip 11, and the insulating layer can be an insulating layer or a dielectric layer that forms an antenna. According to this embodiment, as shown in FIG. 2, the ground metal layer 124 is used as one electrode of the MIM capacitor, and the ground metal layer 124 is connected to a pad 142 that applies a ground voltage. The other electrode of the MIM capacitor is connected to the metal layer 13 via an insulating layer. 9 The metal layer 13 is formed. 9is connected to wiring 133 through via 134. By configuring the MIM capacitor in this way, it is possible to form the capacitor within the chip using a simple manufacturing process.

[0019] In addition to the above configuration, it is also possible to form a capacitor on a substrate separate from chip 11 and attach it to the front or back surface of chip 11. With this configuration, it is possible to provide a capacitive element with a larger capacity.

[0020] In the first shunt element 1300, the resistive element 131 is connected to a pad 141 that applies a bias voltage, and the capacitive element 132 is connected to a pad 142 that applies a ground voltage. However, the connections may be reversed so that the resistive element 131 is connected to the pad 142 that applies the ground voltage, and the capacitive element 132 is connected to the pad 141 that applies the bias voltage.

[0021] Preferably, 20 to 40 antennas are arranged on the chip 11 as the antennas 121 of the antenna array 12. Furthermore, the number of pads 141 for applying a bias voltage and the number of pads 142 for applying a ground voltage are made smaller than the number of antennas. This allows the space on the chip 11 to be used effectively and the chip 11 to be made smaller. Furthermore, if the number of pairs of resistive elements 131 and capacitive elements 132 is equal to or less than the number of pads 141 for applying a bias voltage or the number of pads 142 for applying a ground voltage, the space on the chip 11 can be used effectively and the chip 11 can be made smaller.

[0022] The substrate 10 also includes a resistive element 151 and a capacitive element 152 that constitute the second shunt element 1500, a pad 161 for connecting to the pad 141 of the chip 11, and a pad 162 for connecting to the pad 142 of the chip 11. The pads 161 and 162 are for electrically connecting the chip 11 to an external circuit. The pads 161 and 162 are made of a conductor. In this case, the external circuit is the chip 11. The substrate 10 also includes a connection terminal 181 to which a bias voltage is supplied from the voltage bias circuit 17 and a connection terminal 182 to which a ground voltage is applied. To reduce the size of the substrate 10, it is preferable to use surface mount devices (SMDs) as the resistive element 151 and the capacitive element 152. Because wiring arranged on the substrate 10 also has resistance, the resistance of the wiring on the substrate 10 included in the path connecting the first shunt element 1300 and the second shunt element 1500 may be used as the resistive element 151. This reduces the number of components used in chip 11, thereby achieving a smaller chip 11. Here, connection terminals 181 and 182 may be pads.

[0023] The voltage bias circuit 17 is connected from the outside of the substrate 10 via connection terminals 181 and 182. Instead of this configuration, the voltage bias circuit 17 may be arranged on the substrate 10 or on the chip 11.

[0024] Pad 141 of chip 11 and pad 161 of substrate 10 are connected by bonding wire 191. Pad 142 of chip 11 and pad 162 of substrate 10 are connected by bonding wire 192. In order to reduce the inductance of bonding wires 191 and 192, it is preferable to arrange pads 141 and 161, and pads 142 and 162 close to each other and shorten the lengths of bonding wires 191 and 192.

[0025] To shorten the bonding wires 191 and 192, it is preferable to arrange the pads 141 and 142 at the ends of the chip 11. It is also preferable to arrange the pads 141 and 161 opposite each other with a side of the chip 11 in between. It is also preferable to arrange the pads 142 and 162 opposite each other with a side of the chip 11 in between.

[0026] One terminal 1512 of the resistance element 151 is connected to one terminal 1521 of the capacitance element 152 via a wiring 157. That is, the resistance element 151 and the capacitance element 152 are connected in series. Therefore, it is preferable that the resistance element 151 and the capacitance element 152 are arranged in the vicinity of each other. More preferably, one terminal 1512 of the resistance element 151 is arranged adjacent to one terminal 1521 of the capacitance element 152. This makes it possible to shorten the length of the wiring 157 and reduce inductance.

[0027] The other terminal 1511 of the resistive element 151 is connected to the pad 161 via the wiring 153, and to the connection terminal 181 via the wiring 154. The other terminal 1522 of the capacitive element 152 is connected to the pad 162 via the wiring 155, and to the connection terminal 182 via the wiring 156. It is preferable that the direction in which the terminals 1511 and 1512 of the resistive element 151 and the terminals 1521 and 1522 of the capacitive element 152 are aligned is the same as the direction in which the pads 161 and 162 are aligned. This arrangement allows the connecting wiring to be short, thereby reducing inductance.

[0028] In the second shunt element 1500, the resistive element 151 is connected to a connection terminal 181 that applies a bias voltage, and the capacitive element 132 is connected to a connection terminal 182 that applies a ground voltage. However, the connections may be reversed so that the resistive element 131 is connected to the connection terminal 182 that applies the ground voltage, and the capacitive element 132 is connected to the connection terminal 181 that applies a bias voltage.

[0029] In this embodiment, an example is assumed in which the first shunt element 1300 and the second shunt element 1500 are respectively composed of resistive elements 131 and 151 and capacitive elements 132 and 152. However, the first shunt element and the second shunt element may be composed of either a resistive element or a capacitive element. When the shunt element includes a capacitive element, it is possible to suppress not only parasitic oscillation but also power consumption by, for example, cutting DC current using the frequency characteristics of impedance.

[0030] The positional relationship of the components of the antenna device 100 is such that the first shunt element 1300 is arranged between the antenna array 12 and the voltage bias circuit 17, and the second shunt element 1500 is arranged between the first shunt element 1300 and the voltage bias circuit 17.

[0031] FIG. 3 is a partial cross-sectional view of an antenna device 100 illustrating a configuration in which a pad is formed on the back surface of the chip 11 and the chip 11 is connected to the substrate 10 without using a bonding wire 19. 3, the wiring on the front surface of the chip 11 is connected to the pad 141 on the back surface of the chip 11 via the through electrode 135.

[0032] The through electrode 135 is formed by forming a through hole in the chip 11, forming an insulating film on the inner wall of the through hole for electrical isolation, and filling the through hole with copper or the like, which has low electrical resistance and allows for easy electrode formation by electrolytic plating or the like. The through electrode 135 is also smoothed using a CMP (Chemical Mechanical Polishing) process or the like. After forming the through electrode 135, a pad 141 is formed on the back surface of the chip 11 so as to be electrically connected to the through electrode 135.

[0033] Pads 141 on the back surface of chip 11 and pads 161 on substrate 10 are arranged to overlap and are connected by solder or the like. When electrical connection is made using through electrodes 135, no bonding wire is used, so inductance is reduced and parasitic oscillation in antenna device 100 can be easily suppressed.

[0034] Fig. 4 is an explanatory diagram showing the antenna array 12 in this embodiment. Fig. 4A is a top view of the antenna array 12, and Fig. 4B is a cross-sectional view of the antenna array 12 taken along line B-B' in Fig. 4A. In the figure, two antennas 121 and 122 included in the antenna array 12 are shown as an example.

[0035] Typically, in an antenna array intended for power combining, the spacing between individual antennas is set to be equal to or less than the wavelength of the oscillating electromagnetic wave converted to its wavelength in vacuum, or an integral multiple of the wavelength, and more preferably equal to or less than half the wavelength. In this embodiment, the antennas 121 and 122 are arranged so that the spacing between the antennas is equal to or less than half the wavelength of the transmitted electromagnetic wave.

[0036] In the antenna array 12, a resonant circuit 1200 is formed by a microstrip resonator that includes a metal layer 123, which is a first conductor that forms part of the antenna, a dielectric layer 128, and a grounded metal layer 124, which is a second conductor that forms part of the antenna. The antennas 121 and 122 are each formed by this resonant circuit 1200 and a negative differential resistance element 127. The metal layer 123 has a via 13. 4 A bias voltage line 130 is connected via the negative differential resistance element 127, and a bias voltage is applied to the negative differential resistance element 127. The negative differential resistance element 127 generates electromagnetic wave gain to maintain oscillation. The individual antennas 121 and 122 oscillate synchronously in phase, so they are designed to have an oscillation frequency close to ω0. Therefore, it is preferable that the shapes of the individual antennas including the half-wave resonators are similar to each other. It is also preferable that the shape and characteristics of the negative differential resistance element 127 are similar. The microstrip line 125 is an inter-element structure that allows the individual antennas described above to oscillate synchronously in phase with each other.

[0037] The microstrip line 125, which is the transmission line of the metal portion of the link structure, is preferably selected so that the length along the microstrip line 125 from one end to the other is 2π in electrical length at the oscillation frequency ω0 after synchronization. The 2π electrical length corresponds to the effective oscillation wavelength λ0 converted by the effective dielectric constant of the surrounding structure. The electrical length of 2π is selected so that the antennas 121 and 122 oscillate in phase. If the antennas 121 and 122 are synchronized in phase, the electrical length may be π or 3π. The length of the microstrip line 125 does not need to be exactly 2π to synchronize the antennas 121 and 122. Although it depends on the magnitude of coupling between the elements formed by the microstrip line 125, a typical allowable range is approximately 2π ±10% of the electrical length. This allowable range is wider than when coupling is achieved without the microstrip line 125. The electrical length of the microstrip line can be easily confirmed using an electromagnetic field simulator or the like.

[0038] A portion of the oscillation output of antenna 121 is input in approximately the same phase to adjacent antenna 122 via microstrip line 125. On the other hand, a portion of the oscillation output of antenna 122 is input in approximately the same phase to adjacent antenna 121 via microstrip line 125. In the antenna array of this embodiment, microstrip line 125 is introduced to realize such a mutual injection locking phenomenon between antennas 121 and 122.

[0039] The microstrip line 125 of this embodiment is characterized by being capacitively coupled to the metal layer 123 of the resonant structure. They only form a capacitance via the insulating layer 129 in the metal-insulator-metal (MIM) region 126, and are DC-open. This allows the magnitude of coupling between the antennas to be as large as direct coupling in the oscillation frequency band ω0. Furthermore, in the low-frequency region below ω0, the magnitude of coupling is small, ensuring isolation between the antennas. The microstrip line 125 of this embodiment is preferable because it has these properties. Furthermore, in the low-frequency region below ω0, the open-ended microstrip line 125 becomes a capacitive element. From the perspective of the negative differential resistance element 127 on the antenna 121 side, the microstrip line 125 is a capacitive element, and the metal layer 123 of the resonant structure on the antenna 122 side is also a capacitor. Therefore, the resonant frequency itself, which is a concern in the low-frequency region, is not generated. Therefore, parasitic oscillation in the low-frequency region can be suppressed.

[0040] 4A and 4B illustrate two individual antennas 121 and 122. However, in the antenna array 12, each antenna can be arrayed by arranging it in the same configuration as the antennas 121 and 122. Furthermore, a plurality of metal layers 123 corresponding to the number of arrays are arranged on the ground metal layer 124, with a dielectric layer 128 interposed therebetween, and negative differential resistance elements 127 corresponding to the metal layers 123 are further arranged. Adjacent antennas are capacitively coupled by microstrip lines 125. Furthermore, the electrical length of each microstrip line 125 is approximately 2π. Therefore, all negative differential resistance elements 127 can be synchronized in phase. Arranging antennas in this manner is preferable because it not only increases the combined power but also provides sharp directivity.

[0041] Furthermore, the plurality of metal layers 123 are connected in common via a strip conductor (not shown) inside the chip 11 and are connected to a pad 141 to which a bias voltage is applied, and the ground metal layer 124 is connected to a pad 142 inside the chip 11. With this configuration, when a voltage is applied to the pads 141 and 142, a bias voltage is applied to the negative differential resistance element 127.

[0042] A resonant tunneling diode lattice-matched to the InP substrate can be used as the negative differential resistance element 127. Note that the negative differential resistance element 127 is not limited to a resonant tunneling diode, and an Esaki diode or a Gunn diode may also be used. The resonant tunneling diode is configured, for example, with a multiple quantum well structure of InGaAs / InAlAs or InGaAs / AlAs on an InP substrate and an electrical contact layer of n-InGaAs. For example, a triple barrier structure is used as the multiple quantum well structure. More specifically, a triple barrier structure of AlAs (1.3 nm) / InGaAs(7.6nm) / InAlAs(2.6nm) / InGaAs(5. It is composed of a semiconductor multilayer structure of InGa (6 nm) / AlAs (1.3 nm). As is the well layer, and lattice-matched InAlAs and non-matched AlAs are the barrier layers. These layers are intentionally left undoped. This type of multiple quantum well structure has an electron concentration of 2×10 18 cm -3 The current-voltage (I / V) characteristics of the structure between these electrical contact layers show a peak current density of 280 kA / cm 2 The negative resistance region is from about 0.7V to about 0.9V. In the case of a mesa structure with a diameter of 2μm, the peak current is 10mA and the negative resistance is 10mA. Considering the reactance associated with the junction capacitance of the resonant tunneling diode with a diameter of 2 μm connected to the bottom of the metal layer 123, the oscillation frequency is about 0.55 THz. become.

[0043] 5 shows an equivalent circuit diagram of the antenna device according to this embodiment. The equivalent circuit of the chip 11 has a resistance r (r indicates the absolute value of the resistance of the negative differential resistance element) of the negative differential resistance element that constitutes the antenna array 12. The equivalent circuit of the chip 11 also has an impedance Z of the resonant circuit 1200 that constitutes the antenna array 12 and a resistance Rc of the resistive element 131 that constitutes the first shunt element 1300. The equivalent circuit of the chip 11 also has a capacitance Cc of the capacitive element 132 that constitutes the first shunt element 1300.

[0044] The first shunt element 1300 is configured by connecting a resistance Rc and a capacitance Cc in series. Furthermore, the resistance r, the impedance Z of the resonant circuit 1200, and the first shunt element 1300 are connected in parallel with each other. More specifically, one terminal of the resistance r, one terminal of the impedance Z of the resonant circuit 1200, and one terminal of the resistance Rc are each connected to a first node n1. The other terminal of the resistance Rc is connected to one terminal of the capacitance Cc. The other terminal of the resistance r, the other terminal of the impedance Z of the resonant circuit 1200, and the other terminal of the capacitance Cc are connected to a ground voltage. The first node n1 is connected to a pad 141 of the chip 11, and the ground voltage is applied via a pad 142 of the chip 11.

[0045] The equivalent circuit of the substrate 10 is composed of the resistance Rp of the resistive element 151 and the capacitance Cp of the capacitive element 152 that constitute the second shunt element 1500, and the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500. The inductance L includes the parasitic inductance of the wiring connecting the first shunt element 1300 and the pad 141, the bonding wire connecting the chip and the substrate, the wiring connecting the bonding wire and the second shunt element 1500, the pad, etc.

[0046] The second shunt element 1500 is configured by connecting a resistance Rp and a capacitance Cp in series. Furthermore, the chip 11 and the second shunt element 1500 are connected via an inductance L. More specifically, one terminal of the inductance L is connected to a first node n1 in the equivalent circuit of the chip 11, and the other terminal of the inductance L and one terminal of the resistance Rp are connected to a second node n2. Furthermore, the other terminal of the resistance Rp is connected to one terminal of the capacitance Cp. Furthermore, a ground voltage is applied to the other terminal of the capacitance Cp. Furthermore, the second node n2 is connected to the terminal 181, and a voltage bias circuit V is connected thereto. Therefore, a bias voltage is applied to the second node n2, and the bias voltage is applied to the resistance r via the inductance L.

[0047] The first shunt element 1300 (resistance Rc and capacitance Cc) is connected in parallel with a negative differential resistance element (resistance r), and is also connected in parallel with the second shunt element 1500 (resistance Rp and capacitance Cp) via an inductance L. Furthermore, the first shunt element 1300 is also connected in parallel with a voltage bias circuit V.

[0048] In such an antenna device, to suppress parasitic oscillation, it is preferable that first shunt element 1300 and second shunt element 1500 have low impedance with reference to resistance r of negative differential resistance element 127. That is, it is preferable to set them so that they have low impedance as seen from negative differential resistance element 127 in a frequency band shorter than the terahertz frequency band. In this case, the following conditional expressions (1) and (2) hold true. Rp +1 / (2π×f×Cp) < r···(1) Rc +1 / (2π×f×Cc) < r···(2) Here, r is the absolute value of the resistance of the negative differential resistance element, Rc is the resistance of the resistor Rc which is the first resistor, and Cc is the capacitance of the capacitor Cc which is the first capacitor. where R is the resistance value of resistor Rp, Cp is the capacitance value of capacitor Cp, which is the second capacitor, and L is the inductance of the path connecting the first shunt element 1300 and the second shunt element 1500. Furthermore, f is the frequency of the parasitic oscillation in question, and indicates a frequency lower than the resonant frequency of the resonant circuit that constitutes the antenna array 12. Furthermore, the frequency f is specifically lower than 30 GHz, but when the chip 11 is mounted on the substrate 10 as in this embodiment, it is particularly a frequency in the range of 10 MHz to 10 GHz.

[0049] However, even if equations (1) and (2) hold, LC resonance may occur between the inductance L and capacitance Cc. To suppress this LC resonance, it is necessary to ensure Rc in order to dissipate the oscillation energy, and it is preferable to reduce L and increase Cc. Therefore, to suppress parasitic oscillation, the following conditional equation (3) also holds. L / (Cc×r) <Rc···(3)

[0050] Fig. 6 is a graph showing the frequency characteristics of the impedance seen from negative differential resistance element 127 when the value of inductance L is changed based on the equivalent circuit of Fig. 5. The dashed line shows the characteristics for L = 1 nH, the solid line shows the characteristics for L = 5 nH, and the dashed-dotted line shows the characteristics for L = 10 nH, and the impedance has peak values ​​at specific frequencies. Specifically, for L = 1 nH, the peak value is 1.8 Ω at 160 MHz, for L = 5 nH, the peak value is 16.8 Ω at 50 MHz, and for L = 10 nH, the peak value is 8.5 Ω at 71 MHz.

[0051] Fig. 7 is a graph showing the relationship between the inductance L and the peak value of the impedance seen from the negative differential resistance element 127, based on the frequency characteristics of Fig. 6. According to Fig. 7, as the inductance L increases, the peak value of the impedance increases.

[0052] At the frequency f of the parasitic oscillation to be suppressed, the line seen from the negative differential resistance element 127 If the impedance of is 10 times or less the absolute value of the negative differential resistance, the magnitude of the loss due to the line cannot be ignored compared to the gain of the negative differential resistance element 127. This makes it possible to suppress LC resonance oscillation. As an example, in an antenna array with a chip size of 3 mm square to 4 mm square, 20 to 40 antennas can be arranged, and the combined resistance value of the negative differential resistance 127 is at most 1 Ω, i.e., 1 Ω or less. Therefore, if the combined resistance value is 10 times this resistance value, i.e., 10 Ω or less, parasitic oscillation can be suppressed. In other words, according to the graph of FIG. 7, it is sufficient if L≦5 nH.

[0053] The inductance L includes the parasitic inductance of the wiring connecting the first shunt element 1300 and the pad 141, the bonding wire connecting the chip and the substrate, the wiring connecting the bonding wire and the second shunt element 1500, the pad, etc. The inductances of the path connecting the first shunt element 1300 and the second shunt element 1500 can be calculated using the following formulas (4) and (5), respectively. In the path connecting the first shunt element 1300 and the second shunt element 1500, the part whose cross section can be approximated to a nearly circle is calculated using formula (4), and the part whose cross section can be approximated to a square is calculated using formula (5). L1=0.2×l1×[ln(4×l1 / d)- 0.75] [nH]...(4) L2=0.2×l2×[ln{2×l2 / (w + h)}+0.2235×(w+h) / l2+0.5] [nH]...(5) Here, l1 is the length (mm) of the portion of the path whose cross section can be approximated as a circle, d is the diameter (mm) of the cross section, l2 is the length (mm) of the portion of the path whose cross section can be approximated as a rectangle, w is the width (mm), and h is the thickness (mm).

[0054] FIG. 8 shows a first shunt element 1300 and a second shunt element 1500 in this embodiment. 1 is a diagram illustrating the inductance of a connecting path. The path connecting the first shunt element 1300 and the second shunt element 1500 includes a wiring (first portion P1) that connects the resistive element 131 constituting the first shunt element 1300 to the pad 141, and the pad 141 (second portion P2). The path further includes a bonding wire 19 (third portion P3), a pad 161 (fourth portion P4), and a wiring (fifth portion P5) that connects the pad 161 to the resistive element 151 constituting the second shunt element 1500.

[0055] The length of the path connecting the first shunt element 1300 and the second shunt element 1500 is preferably 4 mm or less, which is suitable for reducing parasitic inductance and suppressing parasitic oscillation, and more preferably 2 mm or less.

[0056] The following describes an example of the dimensions of each part in the path and the inductance calculated by equation (4) or equation (5).

[0057] The first portion P1 has a length of 0.3 mm, a width of 0.2 mm, and a thickness of 0.5 μm, and the inductance L1 of this region is calculated by equation (5) to be 0.1 nH.

[0058] The inductance L2 of the second portion P2 is calculated as the region from the end of the pad 141 to approximately the center of the pad 141 to which the bonding wire 19 is connected. This region has a length of 0.1 mm, a width of 0.2 mm, and a thickness of 0.5 μm, and the inductance L2 is calculated using equation (5) to be 0.02 nH.

[0059] The third portion P3 is a bonding wire having a length of 1.0 mm and a cross-sectional diameter of 20 μm, and the inductance L3 of this region is calculated by equation (4) to be 0.91 nH.

[0060] The inductance L4 of the fourth portion P4 is calculated as the region from the end of the pad 161 to approximately the center of the pad 161 to which the bonding wire 19 is connected. This region has a length of 0.6 mm, a width of 1.2 mm, and a thickness of 35 μm, and the inductance L4 is calculated using equation (5) to be 0.11 nH.

[0061] The fifth portion P5 has a length of 0.8 mm, a width of 0.6 mm, and a thickness of 35 μm, and the inductance L5 of this region is calculated by equation (5) to be 0.26 nH.

[0062] Therefore, the inductance of the path connecting the first shunt element 1300 and the second shunt element 1500 can be calculated as the sum of the inductances L1, L2, L3, L4, and L5, which is 1.4 nH.

[0063] In this embodiment, the inductance was calculated using equation (4) assuming that the cross section of the bonding wire 19 is circular, but a ribbon-shaped bonding wire with a square cross section may also be used. In the case of a ribbon-shaped bonding wire, the inductance can be calculated using equation (5). A ribbon-shaped bonding wire can have a large cross-sectional area, which can reduce the inductance.

[0064] 9A and 9B are diagrams for explaining calculation of wiring inductance. Here, explanation will be given using wiring 153 connecting pad 161 and resistive element 151 constituting second shunt element 1500. The same can be applied to the wiring connecting resistive element 131 constituting first shunt element 1300 and pad 141.

[0065] 9A is a diagram showing an example of a configuration in which the wiring 153 has a bent portion. In the example shown in FIG. 9A, the wiring 153 is configured with a bent portion having two 90-degree bent portions. 9A, the inductance of the wiring 153 can be calculated by dividing it into three rectangular portions. The three rectangular portions are a first rectangular portion RS1 connected to the pad 161, a second rectangular portion RS2 connected to the first rectangular portion, and a third rectangular portion RS3 connected to the second rectangular portion. The third rectangular portion RS3 is connected to the resistor element 151. The first rectangular portion RS1 has a length l21, a width w1, and a thickness h1. The second rectangular portion RS2 has a length l22, a width w2, and a thickness h2. The third rectangular portion RS3 has a length l23, a width w3, and a thickness h3. The inductance of each rectangular portion is calculated using equation (5), and the sum of the calculated inductances is the inductance of the wiring 153.

[0066] Here, an example of a method for determining lengths l21, l22, and l23 will be described. Point A is the intersection of line X, which passes through the center of the width direction of first rectangular portion RS1 and extends in the length direction, and line Y, which passes through the center of the width direction of second rectangular portion RS2 and extends in the length direction. Point B is the intersection of line Y and line Z, which passes through the center of the width direction of third rectangular portion RS3 and extends in the length direction. The distance between the end of pad 161 and point A is the length l21 of the first rectangular portion, the distance between points A and B is the length l22 of second rectangular portion RS2, and the distance between point B and the end of resistor element 151 is the length l23 of third rectangular portion RS3.

[0067] As a method for determining the lengths l21, l22, and l23, any method other than the above may be used as long as it is possible to divide the wiring 153 and identify rectangular portions.

[0068] 9B shows an example in which wiring 153 is configured to extend linearly from resistor element 151 toward pad 161 while its width gradually increases. Even with this type of wiring 153, the inductance of wiring 153 can be calculated using equation (5) by replacing wiring 153 with a rectangular portion RS4 as shown in the figure. Rectangular portion RS4 has a length l24, a width w4, and a thickness h4.

[0069] Next, an example of how to determine the length l24 and width w4 of rectangular portion RS4 will be described. A center point C of portion V-V' where wiring 153 and pad 161 contact is defined, and a point D that contacts resistor element 151 at the shortest distance from point C is defined. The distance between points C and D is defined as length l24. Furthermore, the distance between the ends of the wiring in the direction perpendicular to line segment CD, passing through center E between points C and D, is defined as width w4.

[0070] In this way, the inductance of the wiring can be calculated by the determination method described with reference to FIGS. 9A and 9B.

[0071] According to this embodiment, it is possible to suppress parasitic oscillation by configuring the shunt element so as to satisfy the formulas (1), (2), and (3). In addition, when calculating the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500 used in the formula (3), the calculation method described using the formulas (4), (5), FIGS. 8, and 9 can be applied.

[0072] (Second embodiment) An antenna device according to a second embodiment of the present disclosure will be described with reference to Fig. 10. The second embodiment differs from the first embodiment in that pads are connected to each other by a plurality of bonding wires. Note that in this embodiment, a description of the same configuration as in the first embodiment will be omitted.

[0073] 10 includes a pad 241 for applying a bias voltage and a pad 242 for applying a ground voltage to the chip 21. The substrate 20 includes a pad 261 for connecting to the pad 241 of the chip 21 and a pad 262 for connecting to the pad 242 of the chip 21. The pads 241 and 261 are connected to the substrate 20. The antenna device 200 includes a plurality of bonding wires 291 for connecting the pad 242 and the pad 262, and a plurality of bonding wires 292 for connecting the pad 242 and the pad 262. The other elements of the antenna device 200, such as the antenna array, the first shunt element, and the second shunt element, are the same as those of the antenna device 100 according to the first embodiment.

[0074] In order to reduce the inductance of the bonding wires 291 and 292, it is preferable to arrange the pads 241 and 261, and the pads 242 and 262 close to each other and shorten the bonding wires 291 and 292.

[0075] To shorten the bonding wires 291, 292, it is preferable to arrange the pads 241 and 242 at the ends of the chip 21. If one side of the chip 21 across which the multiple bonding wires 291, 292 cross is defined as a first side 271, the pads 241 and 261 are arranged to face each other with the first side 271 in between. The pads 242 and 262 are also arranged to face each other with the first side 271 in between. Furthermore, the multiple bonding wires 291, 292 are arranged side by side at intervals in a direction parallel to the first side 271.

[0076] The multiple bonding wires 291, 292 are electrically connected in parallel. The combined inductance Lm of the M bonding wires connected in parallel can be calculated by the following equation (6). 1 / Lm=Σ(1 / Li)(i=1,2,3,...,M)...(6) Here, Li is the inductance of the ith bonding wire out of M wires, and is calculated using equation (4) if the cross section of the bonding wire is circular, and is calculated using equation (5) if the cross section of the bonding wire is rectangular. Whether the cross section of the bonding wire is circular or rectangular may be determined appropriately, and the combined inductance Lm of the bonding wire may be calculated using equations (4) and (5).

[0077] By electrically connecting the bonding wires 291 and 292 in parallel in this way, the combined inductance of the bonding wires 291 and 292 can be reduced, which makes it easier to suppress parasitic oscillation.

[0078] In this embodiment, the areas of pads 241 and 242 are made larger than the areas of pads 141 and 142 in the first embodiment, and the areas of pads 261 and 262 are made larger than the areas of pads 161 and 162 in the first embodiment. This increases the number of bonding wires connecting the pads, thereby reducing the combined inductance of multiple bonding wires.

[0079] Furthermore, the pads 241, 242, 261, and 262 are configured so that the dimension in the direction parallel to the first side 271 of the chip 21 is larger than the dimension in the direction perpendicular to the first side 271. This allows the number of bonding wires that can be placed to be increased, and the combined inductance of the bonding wires to be reduced.

[0080] It is also possible to divide the pads 241, 242, 261, and 262 into individual bonding wires, as in the first embodiment. In this case, the pads can be connected in a wiring layer below the metal layer on which they are formed. However, a configuration in which multiple bonding wires are arranged on one pad, as shown in FIG. 10, does not require space to separate the pads, making pattern formation easier. Therefore, by adopting the configuration shown in FIG. 10, an inexpensive printed circuit board or ceramic package can be used as the substrate 20, thereby reducing costs.

[0081] (Third embodiment) An antenna device according to a third embodiment of the present disclosure will be described with reference to Fig. 11. The third embodiment differs from the first embodiment in that resistive elements and capacitive elements constituting the first shunt element and the second shunt element are added and connected in parallel. In this embodiment, descriptions of the same configuration as the first and second embodiments will be omitted.

[0082] 11, an antenna device 300 according to this embodiment includes, on a chip 31, a first shunt element including a resistive element 331 and a capacitive element 332, and another first shunt element including a resistive element 333 and a capacitive element 332. The antenna device 300 further includes, on the chip 31, pads 341 and 343 for applying a bias voltage and a pad 342 for applying a ground voltage. The substrate 30 also includes, on the chip 30, a second shunt element including a resistive element 351 and a capacitive element 352, and another second shunt element including a resistive element 353 and a capacitive element 354.

[0083] The substrate 30 also includes a pad 361 for connection to a pad 341 of the chip 31, a pad 362 for connection to a pad 342 of the chip 31, and a pad 363 for connection to a pad 343 of the chip 31. The pads 341 and 361 are connected by a bonding wire 391, the pads 342 and 362 are connected by a bonding wire 392, and the pads 343 and 363 are connected by a bonding wire 393. The substrate 30 also includes connection terminals 381 and 383 to which a bias voltage is supplied from a voltage bias circuit 37, and a connection terminal 383 to which a ground voltage is applied. 3 Equipped with 82.

[0084] 11, pads 341, 342, and 343 of chip 31 are connected to pads 361, 362, and 363 of substrate 30 by single bonding wires 391, 392, and 393, respectively. However, two pads may be connected by multiple bonding wires as in the second embodiment. Alternatively, two pads may be connected by through electrodes without using bonding wires 391, 392, and 393 as in FIG. 3.

[0085] As in the first embodiment, the antenna array 32 is disposed approximately in the center of the chip 31, and a capacitance element 332 is disposed adjacent to the antenna array 32. One terminal of the resistance element 331 is connected to one terminal of the capacitance element 332 via a wiring and a via (not shown). One terminal of the resistance element 333 is connected to one terminal of the capacitance element 332 via a wiring and a via (not shown). The resistance elements 331 and 333 are preferably disposed near the capacitance element 332. Alternatively, the resistance elements 331 and 333 may be disposed on top of and overlapping the capacitance element 332. The other terminal of the resistance element 331 is connected to a pad 341 via a bias voltage line 330. The bias voltage line 330 is also disposed between the antennas 321 of the antenna array 32 and connected to each antenna 321. This applies a bias voltage to each antenna 321. The other terminal of the capacitance element 332 is connected to a pad 342 via a wiring and a via (not shown). The other terminal of the resistor element 333 is connected to the pad 343 via the bias voltage line 330 .

[0086] One terminal 3512 of resistor 351 is connected to one terminal 3521 of capacitor 352 via a wiring. That is, resistor 351 and capacitor 352 are connected in series. Therefore, it is preferable to arrange resistor 351 and capacitor 352 adjacent to each other. More preferably, if one terminal 3512 of resistor 351 is arranged adjacent to one terminal 3521 of capacitor 352, the wiring can be shortened, thereby reducing inductance.

[0087] The other terminal 3511 of the resistive element 351 is connected to the pad 361 via a wire and also connected to the connection terminal 381 via a wire. The other terminal 3522 of the capacitive element 352 is connected to the pad 362 via a wire and also connected to the connection terminal 382 via a wire.

[0088] One terminal 3532 of resistor 353 is connected to one terminal 3541 of capacitor 354 via a wiring. That is, resistor 353 and capacitor 354 are connected in series. Therefore, it is preferable to arrange resistor 353 and capacitor 354 adjacent to each other. More preferably, if one terminal 3532 of resistor 353 is arranged adjacent to one terminal 3541 of capacitor 354, the wiring can be shortened, thereby reducing inductance.

[0089] The other terminal 3531 of the resistive element 353 is connected to the pad 363 via a wire and also connected to the connection terminal 383 via a wire. The other terminal 3542 of the capacitive element 354 is connected to the pad 362 via a wire and also connected to the connection terminal 382 via a wire.

[0090] 11, terminals 3511 and 3512 of resistor element 351, terminals 3521 and 3522 of capacitor element 352, terminals 3531 and 3532 of resistor element 353, and terminals 3541 and 3542 of capacitor element 354 are arranged to line up in one direction (the left-right direction in the figure) on substrate 30. In this embodiment, pads 361, 362, and 363 are also arranged to line up in the same direction as the direction in which terminals 3511, 3512, 3521, 3522, 3531, 3532, 3541, and 3542 are arranged. By arranging the terminals and pads in this manner, the connecting wiring can be shortened, thereby reducing inductance.

[0091] Because a bias voltage is supplied from the voltage bias circuit 37 to both connection terminals 381 and 383, the other terminal 3511 of the resistive element 351 and the other terminal 3531 of the resistive element 353 are electrically connected. Furthermore, the other terminal 3522 of the capacitive element 352 and the other terminal 3542 of the capacitive element 354 are commonly connected by wiring. Therefore, the resistive element 351 and the capacitive element 352 constituting the second shunt element are electrically connected in parallel with the resistive element 353 and the capacitive element 354 constituting another second shunt element. For example, SMDs (Surface Mount Devices) are used as the resistive elements 351 and 353 and the capacitive elements 352 and 354, but such components have not only resistive and capacitive components but also parasitic inductance. Therefore, for each pair of first and second shunt elements, the second shunt elements (resistive element 351 and capacitive element 352 and resistive element 353 and capacitive element 354) of each pair are connected in parallel. This reduces the parasitic inductance and suppresses the parasitic oscillation.

[0092] Furthermore, since the bonding wires 391 and 393, which are paths for supplying the bias voltage, are connected in parallel, the combined inductance of the bonding wires is also reduced.

[0093] Furthermore, since the wiring arranged on the substrate 30 also has a resistance value, the resistance of the wiring on the substrate 30 connecting the first shunt element and the second shunt element may be used as the resistance elements 351 and 353. This makes it possible to reduce the number of components arranged on the substrate 30, which is advantageous for miniaturization.

[0094] Furthermore, in the chip 31, the elements and pads arranged on the chip 31, and the elements, pads, wiring, etc. arranged on the substrate 30 are arranged symmetrically with respect to an axis passing through the center of the antenna array 32. The axis passing through the center of the antenna array 32 may be, for example, an axis AX extending in a direction perpendicular to the surface of the substrate 30, or an axis extending in a direction parallel to the surface of the substrate 30. Here, symmetry is determined based on the axis extending in a direction parallel to the surface of the substrate. The center of the antenna array 32 can be determined based on the planar shape of the conductors of the antenna array 32. The center of the antenna array 32 may also be the center of gravity of the conductors of the antenna array 32. The center of gravity can be determined based on the cross-sectional shape and planar shape. Therefore, on the substrate 30, multiple pairs of first shunt and second shunt elements connected to each other are arranged, and at least two pairs of first shunt and second shunt elements are arranged symmetrically with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 32, and increases the frontal intensity of the terahertz waves.

[0095] In this embodiment, a configuration is adopted in which bias voltages are supplied from two paths using connection terminals 381 and 383, and ground voltage is supplied from one path using connection terminal 182. However, a configuration in which ground voltages are supplied from two paths using connection terminals 381 and 383, and bias voltages are supplied from one path using connection terminal 182 may also be used.

[0096] (Fourth embodiment) An antenna device according to a fourth embodiment of the present disclosure will be described with reference to Figures 12 to 14. The antenna device according to the fourth embodiment differs from the antenna device according to the first embodiment in that pads are arranged on both sides of the chip, i.e., the pads and chip are arranged so that the chip is sandwiched between the pads. In this embodiment, a description of the same configuration as in the above embodiments will be omitted.

[0097] 12 according to this embodiment, similar to the first embodiment, the chip 41 includes a pad 441 for applying a bias voltage and a pad 442 for applying a ground voltage. Unlike the first embodiment, the antenna device 400 also includes a pad 443 for applying a bias voltage and a pad 444 for applying a ground voltage.

[0098] Moreover, in the chip 41, the pads 441 and 442 are arranged on the side of the first side 411 of the chip 41 as viewed from the antenna array 42. Moreover, in the chip 41, the pads 443 and 444 are arranged on the side of the second side 412 of the chip 41 that faces the first side 411 as viewed from the antenna array 42. As a result, the antenna array 4 is formed between the pads 441 and 442 and the pads 443 and 444. 2 is In this way, the pairs of first shunt elements and second shunt elements are arranged so that the antenna array is sandwiched between the two pairs of first shunt elements and second shunt elements.

[0099] Furthermore, on the chip 41, a resistive element 431, a capacitive element 432, and a resistive element 433 that constitute a first shunt element are arranged.

[0100] One terminal of the resistive element 431 is connected to one terminal of the capacitive element 432 via a wiring and a via (not shown). The resistive element 431 is preferably arranged in the vicinity of the capacitive element 432. Alternatively, the resistive element 431 may be arranged so as to overlap the capacitive element 432. The other terminal of the resistive element 431 is connected to a pad 441 via a bias voltage line 430. The bias voltage line 430 is also arranged between the antennas 421 of the antenna array 42 and is commonly connected to each of the antennas 421, so that a bias voltage is applied to each of the antennas 421.

[0101] One terminal of the resistive element 433 is connected to one terminal of the capacitive element 432 via a wiring and a via (not shown). The resistive element 433 is preferably arranged in the vicinity of the capacitive element 432. Alternatively, the resistive element 433 may be arranged on top of the capacitive element 432 so as to overlap it. The other terminal of the resistive element 433 is connected to a pad 443 via a bias voltage line 430. The other terminal of the capacitive element 432 is connected to pads 442 and 444 via a wiring and a via (not shown).

[0102] In the chip 41, the resistive element 431 and the resistive element 433 are arranged between the pads 441, 442 and the pads 443, 444. The antenna array 42, around which the capacitive element 432 is arranged, is arranged between the resistive element 431 and the resistive element 433. In this way, the pads and the first shunt element are aligned along an axis passing through the center of the antenna array 42 (in the figure, the axis is aligned along the surface of the substrate 40). stretches vertically The terahertz waves are arranged symmetrically with respect to the axis BX. Therefore, on the substrate 40, a plurality of pairs of first shunt and second shunt elements connected to each other are arranged, and at least two pairs of first shunt and second shunt elements are arranged in positions symmetrical with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 42, and increases the frontal intensity of the terahertz waves.

[0103] In the substrate 40, a resistive element 451 and a capacitive element 452 constituting a second shunt element are arranged in a first region 413 (region surrounded by a dotted line in the figure) on the side of a first side 411 of a chip 41, as in the first embodiment. Furthermore, in the first region 413, a pad 461 connected to a pad 441 of the chip 41 by a bonding wire 491, and a pad 462 connected to a pad 442 of the chip 41 by a bonding wire 492 are arranged. Furthermore, in the first region 413, a connection terminal 481 to which a bias voltage is supplied from a voltage bias circuit 471, and a connection terminal 482 to which a ground voltage is applied are arranged.

[0104] Furthermore, in substrate 40, a resistive element 453 and a capacitive element 454 constituting a second shunt element are arranged in a second region 414 (the region surrounded by a dotted line in the figure) on the side of second side 412 of chip 41. Furthermore, in second region 414, a pad 463 connected to pad 443 of chip 41 by a bonding wire 493, and a pad 464 connected to pad 444 of chip 41 by a bonding wire 494 are arranged. Furthermore, in second region 414, a connection terminal 483 to which a bias voltage is supplied from voltage bias circuit 472, and a connection terminal 484 to which a ground voltage is applied are arranged.

[0105] In the above description, the voltage bias circuits 471 and 472 are separate circuits, but the substrate 40 may be configured so that the bias voltage and the ground voltage are supplied by a single voltage bias circuit.

[0106] In this way, the substrate 40 has a configuration in which the chip 41 is disposed between the first region 413 and the second region 414. According to this configuration, the pads 441 and 442 and the pads 443 and 444 are electrically connected to each other. 4 In other words, in the direction along the line segment connecting the side 411 and the side 412, the first region 413, the chip 41, and the second region 414 are The elements are arranged in this order. This configuration reduces the impedance of the wiring that supplies the bias voltage. The chip 41 is also arranged between the resistive element 451 or the capacitive element 452 and the resistive element 453 or the capacitive element 454. Therefore, as with the first shunt element, the pads and the second shunt elements are arranged symmetrically with respect to an axis passing through the center of the antenna array 42. The axis passing through the center of the antenna array 42 can be, for example, an axis BX extending perpendicular to the surface of the substrate 40 or an axis extending parallel to the surface of the substrate 40. Here, symmetry is determined based on the axis extending parallel to the surface of the substrate. Therefore, multiple pairs of first and second shunt elements connected to each other are arranged on the substrate 40, and at least two pairs of the first and second shunt elements are arranged symmetrically with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 42 and increases the frontal intensity of the terahertz waves.

[0107] Furthermore, according to this embodiment, the bias voltage applied to the antenna array 42 is supplied from the two opposing sides 411 and 412 of the chip 41. This reduces the impedance of the wiring that supplies the bias voltage compared to when the bias voltage is supplied from one side of the chip 41, thereby reducing the voltage drop. As a result, the variation between the antennas in the bias voltage applied to the negative differential resistance element of each antenna is reduced, and the antenna Improved output uniformity.

[0108] Furthermore, resistive element 451 and capacitive element 452, which constitute the second shunt element, are connected in parallel with resistive element 453 and capacitive element 454. Resistive elements 451 and 453 and capacitive elements 452 and 454 are, for example, SMDs, but such components have not only resistive and capacitive components but also parasitic inductance. Therefore, by connecting resistive element 451 and capacitive element 452 in parallel with resistive element 453 and capacitive element 454, the parasitic inductance can be reduced and parasitic oscillation can be suppressed.

[0109] Furthermore, since the wiring arranged on the substrate 40 also has a resistance value, the resistance of the wiring may be used as the resistance elements 451 and 453, which allows the number of components arranged on the substrate 40 to be reduced, which is advantageous for miniaturization.

[0110] Fig. 13 is a diagram illustrating an antenna device according to a modified example of this embodiment. Note that in this modified example, explanations of configurations similar to those in the above-described embodiment will be omitted. The configuration of antenna device 500 shown in Fig. 13 is a configuration in which the features of this embodiment are further applied to the configuration described in the third embodiment. In this modified example, configurations similar to those in the third embodiment will be assigned the same reference numerals, and explanations will be omitted.

[0111] In the antenna device 500, resistor elements 531 and 533 and pads 541, 542, and 543 are arranged on a chip 51 on the side where a first side 511 of the chip 51 is located, as in the third embodiment. Furthermore, resistor elements 534 and 535 and pads 544, 545, and 546 are arranged on the side where a second side 512 opposite to the first side 511 of the chip 51 is located.

[0112] An antenna array 52 having a plurality of antennas 521 is disposed between a first side 511 and a second side 512 of a chip 51. A capacitance element 532 is disposed around the antenna array 52. ​​The capacitance element 532 is connected to resistance elements 531, 533, 534, and 535, respectively, to form a first shunt element.

[0113] One terminal of each of the resistive elements 531, 533, 534, and 535 is connected to one terminal of the capacitive element 532 via wiring and vias (not shown). The resistive elements 531, 533, 534, and 535 are preferably arranged near the capacitive element 532. Alternatively, the resistive elements 531, 533, 534, and 535 may be arranged on top of the capacitive element 532 so as to overlap each other. The other terminal of each of the resistive elements 531, 533, 534, and 535 is connected to a pad 541 via a bias voltage line 530. The bias voltage line 530 is also arranged between the antennas 521 of the antenna array 52 and connected in common to each antenna 521, thereby applying a bias voltage to each antenna 521. The other terminal of the capacitive element 532 is connected to pads 542 and 545 via wiring and vias (not shown).

[0114] In the chip 51, resistive elements 531, 533 and resistive elements 534, 535 are arranged between pads 541, 542, 543 and pads 544, 545, 546. Furthermore, an antenna array 52, with a capacitive element 532 arranged around it, is arranged between the resistive elements 531, 533 and the resistive elements 534, 535. In this manner, the pads and first shunt elements are arranged symmetrically with respect to an axis passing through the center of the antenna array 52. ​​The axis passing through the center of the antenna array 52 may be, for example, an axis CX extending in a direction perpendicular to the surface of the substrate 50 or an axis extending in a direction parallel to the surface of the substrate 50. Here, symmetry is determined based on the axis extending in a direction parallel to the surface of the substrate. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 50, and at least two pairs of first shunt and second shunt elements are arranged in positions symmetrical with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 52, The frontal strength of the Hertzian wave increases.

[0115] In the substrate 50, a pad 561 connected to a pad 541 of the chip 51 by a bonding wire 591 is arranged in a first region 513 (the region surrounded by a dotted line in the figure) on the side of a first side 511 of the chip 51, as in the third embodiment. Furthermore, in the first region 513, a pad 562 connected to a pad 542 by a bonding wire 592 and a pad 563 connected to a pad 543 by a bonding wire 593 are arranged. Furthermore, in the first region 513, resistive elements 551 and 553 and capacitive elements 552 and 554 constituting a second shunt element are arranged. Furthermore, in the first region 513, connection terminals 581 and 583 to which a bias voltage is supplied from a voltage bias circuit 571 and a connection terminal 582 to which a ground voltage is applied are arranged. The mutual connection relationships among the pads, the second shunt elements, and the connection terminals are the same as those described in the third embodiment.

[0116] In the above description, the voltage bias circuits 571 and 572 are separate circuits, but the substrate 50 may be configured so that the bias voltage and the ground voltage are supplied by a single voltage bias circuit.

[0117] In addition, in the substrate 50, a pad 564 connected to a pad 544 of the chip 51 by a bonding wire 594 is arranged in a second region 514 (the region surrounded by a dotted line in the figure) on the side of the second side 512 of the chip 51. Furthermore, in the second region 514, a pad 565 connected to a pad 545 by a bonding wire 595 and a pad 566 connected to a pad 546 by a bonding wire 596 are arranged. Furthermore, in the second region 514, resistive elements 555 and 557 and capacitive elements 556 and 558 constituting a second shunt element are arranged. Furthermore, in the second region 514, connection terminals 584 and 586 to which a bias voltage is supplied from a voltage bias circuit 572 and a connection terminal 585 to which a ground voltage is applied are arranged. Note that the connection relationships among the pads, second shunt elements, and connection terminals in the second region 514 are also the same as those described in the third embodiment.

[0118] In this manner, the chip 51 is disposed between the first region 513 and the second region 514 on the substrate 50. According to this configuration, the antenna array 52 is disposed between the pads 541 and 544, between the pads 542 and 545, or between the pads 543 and 546. The chip 51 is disposed between the resistive elements 551 and 553 and the capacitive elements 552 and 554, and between the resistive elements 555 and 557 and the capacitive elements 556 and 558. Therefore, the pads and the second shunt elements are disposed symmetrically with respect to an axis passing through the center of the antenna array 52. ​​The axis passing through the center of the antenna array 52 may be, for example, an axis CX extending in a direction perpendicular to the surface of the substrate 50 or an axis extending in a direction parallel to the surface of the substrate 50. Here, symmetry is determined based on the axis extending in a direction parallel to the surface of the substrate. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 50, and at least two pairs of first shunt and second shunt elements are arranged at positions symmetrical with respect to an axis passing through the center of the antenna array, thereby improving the directivity of the terahertz waves generated from the antenna array 52 and increasing the frontal intensity of the terahertz waves.

[0119] Furthermore, by supplying the bias voltage from two opposing sides 511 and 512 of the chip 51, the impedance of the wiring supplying the bias voltage is reduced, thereby reducing voltage drop. As a result, the variation between antennas in the bias voltage applied to the negative differential resistance element of each antenna is reduced, improving the uniformity of the antenna output.

[0120] Furthermore, a resistive element 551 and a capacitive element 552 that constitute a second shunt element, A resistor 553 and a capacitor 554 that constitute a second shunt element are connected in parallel. Similarly, a resistor 555 and a capacitor 556 that constitute a second shunt element are connected in parallel to a resistor 557 and a capacitor 558. As a result, the number of resistors and capacitors connected in parallel in the antenna device 500 is greater than that in the antenna device 400. This makes it possible to further reduce the parasitic inductance contained in the resistors and capacitors, and to suppress parasitic oscillation.

[0121] Furthermore, since the wiring arranged on the substrate 50 also has a resistance value, the resistance of the wiring may be used as the resistance elements 551, 553, 555, and 557, which allows the number of components arranged on the substrate 50 to be reduced, which is advantageous for miniaturization.

[0122] Fig. 14 is a diagram illustrating an antenna device according to a modified example of this embodiment. The configuration of antenna device 600 shown in Fig. 14 is a configuration in which the features of the second embodiment are further applied to the configuration of antenna device 500 shown in Fig. 13. Therefore, the antenna device according to this modified example is characterized in that the number of bonding wires connecting the pads in the above-mentioned antenna device is different. In the configuration of the antenna device shown in Fig. 14, the description of the same configuration as the configuration of antenna device 500 shown in Fig. 13 will be omitted.

[0123] 14, in antenna device 600, pads 641, 642, and 643 are arranged on chip 61 on the side where first side 611 of chip 61 is located. Furthermore, pads 644, 645, and 646 are arranged on the side where second side 612 opposite first side 611 of chip 61 is located.

[0124] In addition, in the substrate 60, pads 661, 662, and 663 are arranged in a first region 613 (region surrounded by a dotted line in the figure) on the side of a first side 611 of the chip 61, similar to the configuration shown in Fig. 13. In addition, pads 664, 665, and 666 are arranged in a second region 614 (region surrounded by a dotted line in the figure) on the side of a second side 612 of the chip 61.

[0125] Pads 641 and 661 are connected by multiple bonding wires 691, pads 642 and 662 are connected by multiple bonding wires 692, and pads 643 and 663 are connected by multiple bonding wires 693. Pads 644 and 664 are connected by multiple bonding wires 694, pads 645 and 665 are connected by multiple bonding wires 695, and pads 646 and 666 are connected by multiple bonding wires 696.

[0126] In this modification, similarly to the second embodiment, the combined inductance of the bonding wires can be reduced by electrically connecting a plurality of bonding wires in parallel, and parasitic oscillation can be suppressed.

[0127] (Fifth embodiment) Next, an antenna device according to a fifth embodiment of the present disclosure will be described with reference to Figures 15 and 16. The antenna device according to the fifth embodiment is characterized in that pads are arranged near each side of the chip. In this embodiment, descriptions of configurations that are the same as those in other embodiments will be omitted.

[0128] 15 includes pads 741 and 743 for applying a bias voltage and a pad 742 for applying a ground voltage on a chip 71. The antenna device 700 further includes a pad 741 for applying a bias voltage and a pad 742 for applying a ground voltage.

[0129] In the antenna device 700 according to this embodiment, in the chip 71, A pad 741 is arranged near the first side 711, and a pad 742 is arranged near the second side 712. Furthermore, on the chip 71, a pad 743 is arranged near a third side 713 opposite the first side 711, and a pad 744 is arranged near a fourth side 714 opposite the second side 712. A bias voltage is applied to the pads 741 and 743, and a ground voltage is applied to the pads 742 and 744. The pads 741, 742, 743, and 744 are arranged around the antenna array 72 so as to surround the antenna array 72.

[0130] Resistive elements 731 and 733 and a capacitive element 732 that constitute a first shunt element are arranged on the chip 71. One terminal of the resistive element 731 and one terminal of the resistive element 733 are connected to the capacitive element 7 32 via wiring and a via (not shown). The resistive element 731 and the resistive element 733 are preferably arranged adjacent to the capacitive element 732. Alternatively, the resistive element 731 may be arranged overlapping on the capacitive element 732. The other terminal of the resistive element 731 is connected to the pad 741 via the bias voltage line 730, and the other terminal of the resistive element 733 is connected to the pad 743 via the bias voltage line 730. The bias voltage line 730 is also arranged between the antennas 721 of the antenna array 72 and is commonly connected to each antenna 721, and a bias voltage is applied to the antennas 721. element The other terminal of 732 is connected to pads 742 and 744 via wiring and vias (not shown).

[0131] In the substrate 70, a first region 715 on the side of the first side 711 of the chip 71 is provided with a resistor element 751 and a resistor element 752 which constitute a second shunt element. capacity The element 758 is provided with a pad 761 connected to the pad 741 of the chip 71 by a bonding wire 791. The first region 715 is also provided with a connection terminal 781 to which a bias voltage is supplied from a voltage bias circuit 771. The first region 715 is also provided with a terminal of the resistor element 751 and a capacity One terminal of the element 758 is connected to a pad 761 , and the pad 761 is connected to a connection terminal 781 .

[0132] Similarly, a second region 716 on the second side 712 of the chip 71 includes a second shunt. A capacitance element 752 constituting the element and resistance The element 753 is provided with a pad 762 connected to the pad 742 of the chip 71 by a bonding wire 792. The second region 716 is also provided with a connection terminal 782 to which a ground voltage is supplied from a voltage bias circuit 772. One terminal of the capacitance element 752 is connected to a ground terminal 782. resistance One terminal of the element 753 is connected to a pad 762 , and the pad 762 is connected to a connection terminal 782 .

[0133] Similarly, a third region 717 on the third side 713 of the chip 71 is provided with a second shunt element. capacity Arranged are an element 754, a resistor element 755, and a pad 763 connected to a pad 743 of the chip 71 by a bonding wire 793. Also arranged in the third region 717 is a connection terminal 783 to which a bias voltage is supplied from a voltage bias circuit 773. capacity One terminal of the element 754 and one terminal of the resistance element 755 are connected to a pad 763 , and the pad 763 is connected to a connection terminal 783 .

[0134] Similarly, a fourth region 718 on the fourth side 714 of the chip 71 is provided with a second shunt element. capacity Arranged in the fourth region 718 are an element 756, a resistor element 757, and a pad 764 connected to a pad 744 of the chip 71 by a bonding wire 794. Also arranged in the fourth region 718 is a connection terminal 784 to which a ground voltage is supplied from a voltage bias circuit 774. capacity One terminal of the element 756 and one terminal of the resistor element 757 are connected to a pad 764 , and the pad 764 is connected to a connection terminal 784 .

[0135] A resistive element 751 and a capacitive element 752 are arranged near a first corner 726 formed by a first side 711 and a second side 712 of the chip 71, and the other terminal of the resistive element 751 and the other terminal of the capacitive element 752 are connected. Also, a resistive element 753 and a capacitive element 754 are arranged near a second corner 727 formed by a second side 712 and a third side 713 of the chip 71, and The other terminal of the resistor 753 is connected to the other terminal of the capacitor 754. Furthermore, in the vicinity of a third corner 728 formed by the third side 713 and the fourth side 714 of the chip 71, a resistor 755 and a capacitor 756 are arranged, and the other terminal of the resistor 755 is connected to the other terminal of the capacitor 756. Furthermore, in the vicinity of a fourth corner 729 formed by the fourth side 714 and the first side 711 of the chip 71, a resistor 757 and a capacitor 758 are arranged, and the other terminal of the resistor 757 is connected to the other terminal of the capacitor 758.

[0136] Due to this connection relationship between the resistance element and the capacitance element, the resistance element 751 and capacitance element 752, the resistance element 753 and capacitance element 754, the resistance element 755 and capacitance element 756, and the resistance element 757 and capacitance element 758 that constitute the second shunt element are electrically connected in parallel with each other. This makes it possible to further reduce the parasitic inductance contained in each element, thereby suppressing parasitic oscillation.

[0137] In FIG. 15, the voltage bias circuits 771, 772, 773, and 774 are shown as separate circuits, but the substrate 70 may be configured so that the bias voltage and the ground voltage are supplied by a single voltage bias circuit.

[0138] 15, the resistive element 751 and the capacitive element 752 constituting the second shunt element are arranged so that the direction in which the two terminals of the resistive element 751 are aligned is perpendicular to the direction in which the two terminals of the capacitive element 752 are aligned. The resistive element 753 and the capacitive element 754, the resistive element 755 and the capacitive element 756, and the resistive element 757 and the capacitive element 758 are also arranged in a similar manner.

[0139] Furthermore, since the wiring arranged on the substrate 70 also has a resistance value, the resistance of the wiring may be used as the resistance elements 751, 753, 755, and 757. 7 This reduces the number of components placed on the board, which is advantageous for miniaturization.

[0140] As described above, in this embodiment, a pad is disposed on each of the four sides of the chip 71, and a bias voltage or ground voltage is supplied from each side. This configuration can be expressed as follows: A pad, the chip 71, and a pad are arranged in this order along a line segment connecting two opposing sides, and a pad, the chip 71, and a pad are arranged in this order along a line segment connecting another two opposing sides. The direction along the line segment connecting two opposing sides intersects with the direction along the line segment connecting the other two opposing sides. With the configuration of this embodiment, the impedance of the wiring supplying the bias voltage is smaller than when the bias voltage or ground voltage is supplied from one or two sides of the chip 71, thereby reducing voltage drop. As a result, the variation between antennas in the bias voltage applied to the negative differential resistance elements of each antenna is reduced, improving the uniformity of the antenna output.

[0141] Furthermore, since the pads are located on each side of the chip 71, the pads can be made larger and multiple bonding wires can be electrically connected in parallel, thereby reducing the combined inductance of the bonding wires and further suppressing parasitic oscillation.

[0142] Furthermore, by arranging the resistive and capacitive elements of the second shunt element near each of the four corners 726 to 729 of the chip 71 on the substrate 70, the space on the substrate can be effectively utilized, the substrate size can be reduced, and manufacturing costs can be kept down.

[0143] The pads and second shunt elements are arranged symmetrically with respect to an axis passing through the center of the antenna array 72. The axis passing through the center of the antenna array 72 includes, for example, an axis DX extending in a direction perpendicular to the surface of the substrate 70 and an axis extending in a direction parallel to the surface of the substrate 70. determines whether the symmetry is based on an axis extending in a direction parallel to the surface of the substrate. Therefore, on substrate 70, multiple pairs of first shunt and second shunt elements connected to each other are arranged, and at least two pairs of first shunt and second shunt elements are arranged in positions symmetrical with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from antenna array 72, and increases the frontal intensity of the terahertz waves.

[0144] FIG. 16 is a diagram illustrating an antenna device according to a modified example of this embodiment. Note that in this modified example, a description of the same configuration as in the above embodiment will be omitted. In the antenna device 800 shown in FIG. 16, a resistive element 851 and a capacitive element 852, a resistive element 853 and a capacitive element 854, a resistive element 855 and a capacitive element 856, and a resistive element 857 and a capacitive element 858 are arranged near each of corners 826 to 829 of a chip 81. The resistive elements 851, 853, 855, and 857 and the capacitive elements 852, 854, 856, and 858 are arranged obliquely with respect to the extension direction of each side of the chip. The two terminals of the resistive element 851 and the two terminals of the capacitive element 852 are arranged in the same direction, and the resistive element 853 and the capacitive element 854, the resistive element 855 and the capacitive element 856, and the resistive element 857 and the capacitive element 858 are arranged in a similar manner.

[0145] By arranging each element in this manner, the wiring connecting the resistive element, the capacitive element, and the pad can be shortened, reducing the parasitic inductance contained in the wiring and suppressing parasitic oscillation.

[0146] (Sixth embodiment) Next, an antenna array in an antenna device according to a sixth embodiment of the present disclosure will be described with reference to Fig. 17 to Fig. 22. In this embodiment, a description of the same configuration as in the other embodiments will be omitted.

[0147] FIG. 17 shows an equivalent circuit diagram of an antenna device 900 according to this embodiment. The configuration example of the equivalent circuit diagram shown in FIG. 17 corresponds to the configuration in which the antenna array 12 in the equivalent circuit diagram of the antenna device 100 according to the first embodiment shown in FIG. 5 has antennas 121 arranged in a 3×3 matrix. The antenna array 912 has 3×3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, and r33, resistive elements Rai (i=1, 2, 3..., 12), and capacitive elements Cai (i=1, 2, 3..., 12). The antenna array 912 includes a negative differential resistance element and multiple third shunt elements, each of which is connected in series with a resistive element and a capacitive element. The 3×3 negative differential resistance elements and multiple third shunt elements are connected in parallel with each other. One terminal of each negative differential resistance element, one terminal of the resistance element Rai in the plurality of third shunt elements, and one terminal of the resistance element Rc in the first shunt element are commonly connected. The other terminal of the resistance element Rai is connected to one terminal of the capacitance element Cai. Furthermore, the other terminal of each negative differential resistance element and the other terminal of the capacitance element Cai in the plurality of third shunt elements are connected to ground potential. The other configuration of the antenna array 912 is the same as that in FIG. 5, so a description thereof will be omitted here.

[0148] In the antenna array 912, the combined resistance of 3×3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, and r33 corresponds to the resistance r shown in Fig. 5. Also, the combined impedance of the third shunt element and the parasitic impedance of the wiring corresponds to the impedance Z shown in Fig. 5.

[0149] Fig. 18 is an example of a top view of an antenna array 912 arranged in a 3 x 3 matrix corresponding to the equivalent circuit diagram of Fig. 17. Fig. 19 is a cross-sectional view taken along the line CC' in Fig. 18. The description of the configuration described using Fig. 4 will be omitted, and the same components as those in Fig. 4 will be described in the same manner. As explained with reference to FIG. 4, adjacent antennas are mutually coupled by microstrip lines 125a to 125h, and are mutually injection locked (mutually synchronized) at the oscillation frequency fTHz of the terahertz waves. FIG. 18 illustrates a configuration in which one antenna is provided with two negative differential resistance elements 127a and 127b. In order to improve the directivity of the terahertz waves, it is preferable that the two negative differential resistance elements 127a and 127b be arranged symmetrically with respect to a line passing through the center of one antenna.

[0150] A third shunt element is provided on the bias voltage line 130 to suppress parasitic oscillation in a frequency band lower than the oscillation frequency fTHz. The third shunt element is arranged in parallel with the negative differential resistance element to short out the frequency band lower than fTHz and suppress parasitic oscillation. The third shunt element also has a structure in which a resistance element or an element in which a resistance and a capacitance are connected in series is arranged in parallel with the negative differential resistance element. The resistance and capacitance values ​​of the third shunt element are such that the impedance of the element is equal to or slightly lower than the absolute value of the combined negative differential resistance of multiple negative differential resistance elements arranged nearby.

[0151] In FIG. 18 , the area surrounded by dashed line 137′ in plan view is where conductor layer 137, which is one electrode of the capacitive element constituting the third shunt element, is located. Furthermore, the area surrounded by dashed line 138′ is where resistor 138, which is a resistive element, is located. Conductor layer 137 and resistor 138 are located below the wiring layer constituting bias voltage line 130. The third shunt element is located around each antenna. Bias voltage line 130 is connected to metal layer 123, which is part of each antenna, to supply bias voltage. The third shunt element is preferably located near this connection, preferably between the antennas. This arrangement allows for a configuration in which one third shunt element is shared by adjacent antennas. This improves layout efficiency, enabling chip miniaturization. Furthermore, the increased flexibility in adjusting the size of the shunt element capacitance and resistance facilitates suppression of parasitic oscillation.

[0152] 19, a dielectric layer 136 is disposed on the ground metal layer 124. Since the dielectric layer 136 is used as a dielectric for the capacitance of the third shunt element, it is preferable to use silicon nitride (ε=7), which has a relatively high dielectric constant, in order to reduce the size of the MIM capacitance structure.

[0153] Furthermore, a conductor layer 137 is laminated on the dielectric layer 136. Therefore, the antenna array 912 has a metal-insulator-metal (MIM) capacitance structure in which the ground metal layer 124, the dielectric layer 136, and the conductor layer 137 are laminated in this order, and corresponds to the capacitance element of the third shunt element. This capacitance structure element is disposed below the bias voltage line 130 disposed between the antennas. The conductor layer 137 is disposed in a layer between the bias voltage line 130 and the ground metal layer 124. A resistor 138 is connected to the conductor layer 137, and the resistor 138 is connected to the bias voltage line 130. This resistor 138 corresponds to the resistance element of the third shunt element.

[0154] As described above, in this embodiment, the ground metal layer 124 and the bias voltage line 130 are electrically connected via a capacitance element and a resistance element that constitute the third shunt element. A plurality of third shunt elements are arranged in the array antenna so as to be connected to the bias voltage line 130 at each location between the antennas. In this embodiment, the third shunt element is connected to the ground metal layer 124, but it may be connected to another conductive layer as long as it is connected to a conductive layer at a fixed potential.

[0155] The configuration in which the third shunt element is placed at the node of the high frequency electric field of the oscillation frequency fTHz standing in the antenna has high impedance at the frequency fTHz and is a more suitable configuration for selectively oscillating only the high frequency of the frequency fTHz. However, in the antenna array, As the number of arrays increases and bias voltage lines are shared, there is a risk of unexpected low-frequency multi-mode oscillation. Therefore, in this embodiment, the bias voltage line 130 in the array antenna is configured to have a lower impedance than the negative resistance element in the low-frequency band below the oscillation frequency fTHz. This makes it possible to suppress multi-mode oscillation even when the number of antenna arrays increases, and to obtain stable single-frequency oscillation in the terahertz band. The third shunt element can effectively suppress parasitic oscillation, particularly in the frequency band above 10 GHz and below fTHz.

[0156] Figure 20 is a top view of antenna array 1012, which is a modified example of antenna array 912 shown in Figure 18, and Figure 21 is a cross-sectional view taken along line D-D' in Figure 20. The same components as those in Figures 18 and 19 are designated by the same reference numerals, and their description will be omitted. Antenna array 1012 differs from antenna array 912 shown in Figures 18 and 19 in that the resistive element constituting the third shunt element is composed of resistor 138a and resistor 138b.

[0157] As shown in Figure 20, in the antenna array 1012, resistors 138a and 138b are arranged between antennas 1112 and 1113. These two resistors 138a, 138b corresponds to the resistive element of the third shunt element, and is connected in parallel with the capacitive element With children Resistance elements 138a and 138b are arranged near the connection between antennas 1112 and 1113 and bias voltage line 130, and are arranged in a space formed by patterning and removing the wiring layer that constitutes bias voltage line 130.

[0158] 21, resistors 138a and 138b are arranged at the same height as the bias voltage line 130. One end of each of resistors 138a and 138b is connected to the bias voltage line 130, and the other end is connected to the conductor layer 137 using the same wiring layer as the bias voltage line 130.

[0159] For the antenna 1111 at the end of the antenna array 1012, the third shunt element arranged in the area 137'' that is not sandwiched between other antennas may be configured to have either resistor 138a or resistor 138b (138a in the figure) arranged as a resistive element.

[0160] 20 and 21, the configuration of the antenna array 1012 is achieved by removing the wiring layer that constitutes the bias voltage line 130 by patterning at the positions where the resistors 138a and 138b are to be disposed, and then forming the material that will become the resistors in the resulting space. This makes fabrication easier than conventional antenna arrays, and also reduces the occurrence of defects.

[0161] Here, an additional explanation will be given of the first shunt element, the second shunt element, and the third shunt element using Figure 22. Figure 22 illustrates a configuration in which pads are arranged on two opposing sides of the chip described in the fourth embodiment, and the pads are connected by multiple bonding wires. In the following explanation, the same components as those described in the fourth embodiment are given the same reference numerals, and detailed explanations will be omitted.

[0162] The first shunt element is made up of a resistive element 531 and a capacitive element 532, and is arranged around the antenna array 52 within the chip 51. The capacitive element 532 is preferably an MIM capacitor.

[0163] The second shunt element is made up of a resistive element 551 and a capacitive element 552, and is disposed on the substrate 50 on which the chip 51 is mounted. Surface mount devices (SMD) are preferably used for the resistive element 551 and the capacitive element 552, and a ceramic capacitor, for example, is used for the capacitive element 552.

[0164] The third shunt element is a resistor element (not shown) and a capacitor element 5 4 1, which is arranged in the chip 51 in the same manner as the first shunt element, and is arranged in the antenna array 52. 4 As 1, an MIM capacitor is suitable.

[0165] The areas or capacitance values ​​of the capacitive elements constituting the three shunt elements are preferably increased in the order of the third shunt element, the first shunt element, and the second shunt element (capacitive element 5). 4 1<capacitor 532<capacitor 552). Capacitor 5 4 Capacitor element 1 can be suitably arranged if it is 1 pF or more and less than 100 pF, capacitor element 532 if it is 100 pF or more and less than 10 nF, and capacitor element 552 if it is 10 nF or more and less than 100 μF. In addition, the resistive elements of the first shunt element, second shunt element, and third shunt element can be suitably arranged if it is 0.01 Ω or more and less than 10 Ω.

[0166] The number of third shunt elements is determined depending on the number of antennas in the antenna array 2, but is preferably equal to or greater than the number of first shunt elements and the number of second shunt elements, which makes it possible to suppress parasitic oscillation and improve output.

[0167] When the number of antennas in the antenna array 2 is small, for example, to adjust the output to be small, the number of third shunt elements may be smaller than the number of first shunt elements and second shunt elements.

[0168] If the number of second shunt elements is equal to or greater than the number of first shunt elements, the number of second shunt elements connected in parallel can be increased. As a result, the parasitic inductance of the SMD can be reduced, thereby suppressing parasitic oscillation. Furthermore, reducing the number of first shunt elements reduces the chip area, contributing to lowering the cost of the antenna array.

[0169] If the number of second shunt elements is less than the number of first shunt elements, the number of SMDs that make up the second shunt elements can be reduced. Because the area required to mount an SMD on a board is relatively large, reducing the number of SMDs allows the board size to be made smaller, which contributes to reducing the cost of the antenna array.

[0170] Ta, Ti, Mo, Mn, Al, Ni, Nb, W, Ru, etc. are preferably used as resistors forming the resistance elements of the first shunt element and the third shunt element in the chip. Furthermore, alloy films, oxide films, nitride films, silicide films, etc. of these materials (e.g., TiW, TiN, TaN, WN, WSiN, TaSiN, NbN, MoN, MnO, RuO) are preferably used as the resistors. Furthermore, diffused resistance films in which polysilicon or Si is doped with impurities are preferably used as the resistors.

[0171] The materials used for wiring and conductive layers within the chip have a resistivity of 1×10 -6 Materials with a resistance of Ω·m or less are preferred. Specifically, metals and metal compounds such as Ag, Au, Cu, W, Ni, Cr, Ti, Al, AuIn alloys, and TiN are preferably used as materials.

[0172] The dielectric layer that makes up an MIM capacitor must have insulating properties (the ability to act as an insulator and high-resistance material that does not conduct electricity when subjected to DC voltage), barrier properties (the ability to prevent the diffusion of metal materials used in the electrodes), and processability (the ability to be processed with submicron precision).Specific examples of materials that meet these requirements include inorganic insulating materials such as silicon oxide (ε=4), silicon nitride (ε=7), aluminum oxide, and aluminum nitride.

[0173] The negative resistance element includes an electrode and a semiconductor layer, and if the electrode is a conductor ohmically connected to the semiconductor layer, it is suitable for reducing ohmic loss and RC delay due to series resistance. When an electrode is used as an ohmic electrode, the material can be, for example, Ti / Pd / Au or Ti / Pt / Au. , AuGe / Ni / Au, TiW, Mo, ErAs, etc. are preferably used.

[0174] (Seventh embodiment) The detection system according to this embodiment will be described with reference to Fig. 23. The detection system may be a system capable of capturing images, such as a camera system. In this embodiment, a camera system will be used as an example for description. Fig. 23 is a schematic diagram for explaining the configuration of a camera system 2300 using terahertz waves.

[0175] The camera system 2300 includes an oscillation device 2301, a detection device 2302, and a processing unit 2303. The oscillation device 2301 can be an antenna device described in each embodiment. The detection device 2302 can detect electromagnetic waves transmitted from the antenna device, and may be an antenna device using other semiconductor elements such as a Schottky barrier diode, for example. The terahertz waves emitted from the oscillation device 2301 are reflected by a subject 2305 and detected by the detection device 2302. The processing unit 2303 processes the signal detected by the detection device 2302. The image data generated by the processing unit 2303 is output from an output unit 2304. With this configuration, a terahertz image can be acquired.

[0176] An optical unit may be provided in the oscillator 2301 or the detector 2302. The optical unit may be made of multiple layers and includes at least one material that is transparent to terahertz waves, such as polyethylene, Teflon (registered trademark), high-resistivity silicon, or polyolefin resin.

[0177] The camera system described in this embodiment is merely an example, and other configurations may be used. In particular, the information acquired by the system is not limited to image information, and may be a detection system that detects signals.

[0178] The embodiments are merely examples of specific implementations of the present invention, and should not be construed as limiting the technical scope of the present invention. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0179] 12 antenna array, 17 voltage bias circuit, 100 antenna device, 131, 151 resistive element, 132, 152 capacitive element, 1200 resonant circuit, 1300 first shunt element, 1500 second shunt element

Claims

1. An antenna device for transmitting or receiving electromagnetic waves, an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element, An antenna device characterized in that the following formulas (1) to (3) are satisfied: Rp +1 / (2π×f×Cp) < r...(1) Rc +1 / (2π×f×Cc) < r...(2) L / (Cc×r) <Rc...(3) Here, r is the absolute value of the resistance value of the negative differential resistance element, Rp is the resistance value of the second resistor, Cp is the capacitance value of the second capacitor, Rc is the resistance value of the first resistor, Cc is the capacitance value of the first capacitor, L is the inductance of the path connecting the first shunt element and the second shunt element, and f is a frequency less than the resonant frequency of the resonant circuit.

2. The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4): L≦5nH (4) When the path is divided into a first portion whose cross section can be approximated to a circle and a second portion whose cross section can be approximated to a rectangle, the inductance L1 of the first portion is calculated by the following formula (5), and the inductance L2 of the second portion is calculated by the following formula (6).

2. The antenna device according to claim 1, wherein the calculation is performed by: L1=0.2×l1×[ln(4×l1 / d)-0.75]...(5) L2=0.2×l2×[ln{2×l2 / (w + h)}+0.2235×(w+h) / l2+0.5] ...(6) where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion.

3. An antenna device for transmitting or receiving electromagnetic waves, an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element, The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4): L≦5nH (4) When the path is divided into a first portion whose cross section can be approximated to a circle and a second portion whose cross section can be approximated to a rectangle, an inductance L1 of the first portion is calculated by the following formula (5), and an inductance L2 of the second portion is calculated by the following formula (6), L1=0.2×l1×[ln(4×l1 / d)-0.75]...(5) L2=0.2×l2×[ln{2×l2 / (w + h)}+0.2235×(w+h) / l2+0.5] ...(6) where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion.

4. a plurality of pairs of the first shunt element and the second shunt element are arranged; 4. The antenna device according to claim 1, wherein at least two pairs of the first shunt element and the second shunt element are arranged symmetrically with respect to an axis passing through the center of the antenna array.

5. The antenna device according to claim 4, characterized in that the two pairs of the first shunt element and the second shunt element are arranged so that the antenna array is sandwiched between the two pairs of the first shunt element and the second shunt element.

6. the first shunt element is disposed on a chip on which the antenna array is disposed; The chip is a square chip, 6. The antenna device according to claim 4, wherein the second shunt element of each pair of the first shunt element and the second shunt element is arranged near a corner of the chip.

7. The second shunt of each of the two pairs of the first shunt element and the second shunt element 5. The antenna device according to claim 4, wherein the antenna elements are connected in parallel.

8. the first shunt element is disposed on a chip on which the antenna array is disposed; The second shunt element is disposed on a substrate on which the chip is disposed.

8. The antenna device according to claim 1, wherein the antenna device is a semiconductor integrated circuit.

9. a path connecting the first shunt element and the second shunt element includes a first pad disposed on the chip and a second pad disposed on the substrate; A bias voltage is supplied to the antenna array via the first and second pads.

9. The antenna device according to claim 8.

10. the antenna device further includes a third pad disposed on the chip and a fourth pad disposed on the substrate; a ground voltage is supplied to the antenna array via the third pad and the fourth pad; The chip is a square chip, a bias voltage is supplied to the antenna array from the side of the chip where the first side is located via the first pad and the second pad; A ground voltage is supplied to the antenna array via the third pad and the fourth pad from a side of the chip where a second side different from the first side is located.

10. The antenna device according to claim 9.

11. 11. The antenna device according to claim 9, wherein the first pad and the second pad are connected by a plurality of bonding wires connected in parallel.

12. 11. The antenna device according to claim 8, wherein the second resistor is a wiring disposed on the substrate.

13. An antenna device for transmitting or receiving electromagnetic waves, a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged; a substrate on which the chip is disposed; a voltage bias circuit for applying a voltage to the antenna array; The chip is a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, the first shunt element including at least a first capacitance; a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array; The substrate is a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate; The antenna device is characterized in that the antenna array is located between the first pad and the second pad.

14. 14. The antenna device according to claim 1, wherein a combined resistance value of the negative differential resistance elements of the antenna array is 1 Ω or less.

15. 15. The antenna device according to claim 1, wherein a length of a path connecting the first shunt element and the second shunt element is 4 mm or less.

16. 16. The antenna device according to claim 15, wherein the length of the path connecting the first shunt element and the second shunt element is 2 mm or less.

17. 17. The antenna device according to claim 1, wherein the frequency band of the electromagnetic waves includes at least a part of a frequency band of 30 GHz to 30 THz.

18. 18. The antenna device according to claim 1, wherein the negative differential resistance element is a resonant tunneling diode.

19. The first capacitor is a MIM (Metal-Insulator-Metal) capacitor.

19. The antenna device according to any one of claims 1 to 18.

20. 20. The antenna device according to claim 1, further comprising a third shunt element including at least a third capacitance, connected in parallel to the negative differential resistance element in the antenna array.

21. 21. The antenna device according to claim 20, wherein a plurality of the third shunt elements are arranged between the antennas.

22. 22. The antenna device according to claim 21, wherein the third shunt element is shared by antennas on both sides of the third shunt element.

23. 21. The antenna device according to claim 20, wherein the third capacitor has the largest area or capacitance value, followed by the first capacitor and the second capacitor.

24. 21. The antenna device according to claim 20, wherein the number of the third shunt elements is equal to or greater than the number of the first shunt elements and equal to or greater than the number of the second shunt elements.

25. 21. The antenna device according to claim 20, wherein the number of the third shunt elements is less than the number of the first shunt elements and less than the number of the second shunt elements.

26. 20. The antenna device according to claim 1, wherein the number of the second shunt elements is equal to or greater than the number of the first shunt elements.

27. 20. The antenna device according to claim 1, wherein the number of the second shunt elements is smaller than the number of the first shunt elements.

28. An antenna device for transmitting or receiving electromagnetic waves, comprising: an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and The first shunt element and the second shunt element have a resistance value of the negative differential resistance element. It has low impedance based on The antenna device further comprises a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance, in the antenna array.

29. An antenna device for transmitting or receiving electromagnetic waves, comprising: a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged; a substrate on which the chip is disposed; a voltage bias circuit for applying a voltage to the antenna array; The chip is a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, the first shunt element including at least a first capacitance; a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array; The substrate is a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate; the antenna array is located between the first pad and the second pad; The antenna device further comprises a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance, in the antenna array.

30. An antenna device for transmitting or receiving electromagnetic waves, comprising: an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged; a voltage bias circuit for applying a voltage to the antenna array; a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series; a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series; and the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element, a plurality of pairs of the first shunt element and the second shunt element are arranged; An antenna device, characterized in that at least two pairs of the first shunt element and the second shunt element are arranged at positions symmetrical with respect to an axis passing through the center of the antenna array.

31. an antenna device according to any one of claims 1 to 30; a detection device for detecting electromagnetic waves transmitted from the antenna device; a processing unit for processing signals from the detection device.

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