Information processing device

Abstract

To provide an information processing device capable of reducing abrasion of a non-volatile memory in a memory system.SOLUTION: According to an embodiment, an information processing device comprises a non-volatile memory and a CPU. The CPU stores first data and management data associated with the first data and containing information equivalent to a first write command specifying a first logical address range in the non-volatile memory, and performs first transmission of the first write command to a memory system. If any of writing of second data into a third logical address range including at least a part of a second logical address range of the first logical address range and deallocation of the third logical address range is requested before receiving a second response to the first write command, the CPU transmits a command which cancels data writing into at least the second logical address range in a first data writing into the first logical address range according to the first write command to the memory system.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to techniques for controlling non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memory have become widespread. One such memory system is the solid-state drive (SSD) equipped with NAND flash memory. SSDs are used as the main storage of various computing devices.

[0003] For example, when the memory system receives one write request from the host, it writes the user data received from the host in response to the reception of the write request into the nonvolatile memory and returns a response to the host.

[0004] Alternatively, the memory system may write the user data of a specific data unit to the nonvolatile memory and return responses corresponding to each of the multiple write requests to the host after the total amount of user data requested to be written by multiple write requests received from the host reaches a specific data unit. The specific data unit is, for example, the amount of data that can be written to the nonvolatile memory in one data write operation. In other words, the memory system may use a mechanism that does not immediately execute a write in response to a single received write request, but executes the writes in response to the multiple write requests after the total amount of user data requested to be written by the multiple write requests reaches a specific data unit. Hereinafter, this mechanism is also referred to as Delayed Write Completion.

[0005] In Delayed Write Completion, for example, a write unit of user data including a plurality of user data corresponding to a plurality of write requests is written to the nonvolatile memory, thereby enabling efficient use of the storage area of ​​the nonvolatile memory. In Delayed Write Completion, writing and responses corresponding to each write request may be delayed until the plurality of write requests corresponding to the user data in the write unit are received.

[0006] Furthermore, when multiple write requests specifying the same logical address are sent to the memory system at short intervals, data for that logical address is written to the nonvolatile memory in response to the earlier write request, and data is written to the nonvolatile memory in response to the later write request. In other words, the data written to the nonvolatile memory in response to the earlier write request becomes invalid data when data is written to the nonvolatile memory in response to the later write request.

[0007] Alternatively, if a write request and a trim request specifying the same logical address are issued within a short interval, data is written to the nonvolatile memory for that logical address in response to the earlier write request, and the logical address is deallocated in response to the later trim request. In other words, the data written to the nonvolatile memory in response to the earlier write request becomes invalid data when the logical address is deallocated in response to the later trim request.

[0008] In such a case, data that soon becomes invalid is written to the nonvolatile memory, causing wear on the nonvolatile memory. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2021-114038 [Patent Document 2] U.S. Patent No. 1,101,1243 [Patent Document 3] U.S. Patent No. 1,101,6905 [Patent Document 4] Japanese Patent Application Laid-Open No. 2016-133976 Summary of the Invention [Problem to be solved by the invention]

[0010] An embodiment of the present invention provides an information processing device that can reduce wear of non-volatile memory in a memory system. [Means for solving the problem]

[0011] According to an embodiment, an information processing device is connectable to a memory system. The information processing device includes a nonvolatile memory and a processor. The processor stores first data in the nonvolatile memory. The processor stores first management data in the nonvolatile memory, the first management data being associated with the first data and including information corresponding to a first write command that specifies a first logical address range. The processor transmits the first write command to the memory system a first time. In response to receiving a first response to the first write command transmitted for the first time from the memory system, the processor adds information indicating that the first response to the first write command transmitted for the first time has been received to the first management data. After receiving the first response, in response to receiving a second response to the first write command from the memory system, the processor deletes the first data and the first management data from the nonvolatile memory. If the processor is requested to write second data to a third logical address range including a second logical address range that is at least a part of the first logical address range or to deallocate the third logical address range before receiving a second response to the first write command, the processor sends a command to the memory system to cancel writing of the first data to at least the second logical address range in response to the first write command. If the cancellation of writing to the second logical address range is successful, the processor updates or deletes the first management data. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including an information processing device and a memory system according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a lock data list used in the information processing device according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing an example of mapping between a logical address space and a physical address space used in the information processing device according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of the structure of a Physical Region Page (PRP) entry used in the information processing device according to the first embodiment. [Figure 5] FIG. 2 is a view showing an example of a PRP entry list used in the information processing device according to the first embodiment. [Figure 6] FIG. 2 is a view showing an example of a Scatter Gather List (SGL) used in the information processing device according to the first embodiment. [Figure 7] FIG. 2 is a diagram showing an example of the configuration of range information used in the information processing system including the information processing device according to the first embodiment. [Figure 8] 3 is a diagram showing an example of the configuration of modified command data used in the information processing system including the information processing device according to the first embodiment. [Figure 9] 3 is a diagram showing an example of the configuration of a logical-physical address conversion table used in a memory system that communicates with the information processing device according to the first embodiment. FIG. [Figure 10] FIG. 2 is a diagram showing an example of the configuration of a write management table used in a memory system that communicates with the information processing device according to the first embodiment. [Figure 11] FIG. 2 is a block diagram showing an example of a write operation in the information processing system including the information processing device according to the first embodiment. [Figure 12] 3A and 3B are diagrams showing examples of the states of the logical address space and the physical address space at the time when an application makes a write request in the information processing device according to the first embodiment. [Figure 13] 5 is a diagram showing an example of an operation performed immediately before notifying a write request source of write completion in the information processing device according to the first embodiment. FIG. [Figure 14] FIG. 4 is a view showing a first example of an updated lock data list in the information processing device according to the first embodiment. [Figure 15] FIG. 10 is a view showing a second example of an updated lock data list in the information processing device according to the first embodiment. [Figure 16] FIG. 4 is a block diagram showing another example of a write operation in the information processing system including the information processing device according to the first embodiment. [Figure 17] FIG. 10 is a view showing a third example of an updated lock data list in the information processing device according to the first embodiment. [Figure 18] 5 is a diagram showing an example of the operation after an application attempts to write to a write-protected storage area in the information processing apparatus according to the first embodiment. FIG. [Figure 19] FIG. 10 is a block diagram showing yet another example of a write operation in the information processing system including the information processing device according to the first embodiment. [Figure 20] 3A and 3B are views showing examples of a write request or a trim request (write / trim request) in the information processing apparatus according to the first embodiment. [Figure 21] FIG. 10 is a block diagram showing yet another example of a write operation in the information processing system including the information processing device according to the first embodiment. [Figure 22] FIG. 2 is a block diagram showing an example of an abort operation in the information processing system including the information processing device according to the first embodiment. [Figure 23] FIG. 10 is a view showing a fourth example of an updated lock data list in the information processing system including the information processing device according to the first embodiment. [Figure 24] FIG. 2 is a block diagram showing an example of a trimming operation in the information processing system including the information processing device according to the first embodiment. [Figure 25] FIG. 4 is a block diagram showing another example of a trimming operation in the information processing system including the information processing device according to the first embodiment. [Figure 26] FIG. 10 is a view showing another example of a write / trim request in the information processing device according to the first embodiment. [Figure 27] FIG. 10 is a view showing yet another example of a write / trim request in the information processing device according to the first embodiment. [Figure 28] FIG. 10 is a view showing yet another example of a write / trim request in the information processing device according to the first embodiment. [Figure 29] FIG. 2 is a block diagram showing an example of a correction operation in the information processing system including the information processing device according to the first embodiment. [Figure 30] 4A and 4B are views showing examples of modified command data generated in the information processing system including the information processing device according to the first embodiment. [Figure 31] FIG. 10 is a view showing a fifth example of an updated lock data list in the information processing system including the information processing device according to the first embodiment. [Figure 32] FIG. 10 is a view showing yet another example of a write / trim request in the information processing device according to the first embodiment. [Figure 33] FIG. 3 is a diagram showing an example of a write command issued in the information processing device according to the first embodiment. [Figure 34] FIG. 10 is a diagram showing another example of a write command issued in the information processing device according to the first embodiment. [Figure 35] FIG. 10 is a block diagram showing yet another example of a write operation in the information processing system including the information processing device according to the first embodiment. [Figure 36] FIG. 10 is a view showing a sixth example of an updated lock data list in the information processing system including the information processing device according to the first embodiment. [Figure 37] FIG. 2 is a block diagram showing an example of a recovery operation in the information processing system including the information processing apparatus according to the first embodiment. [Figure 38] 10 is a flowchart showing an example of the procedure of a write request control process executed in the information processing device according to the first embodiment. [Figure 39] 10 is a flowchart showing an example of the procedure of a write request process executed in the information processing device according to the first embodiment. [Figure 40] 10 is a flowchart showing an example of the procedure of a write control process executed in a memory system that communicates with the information processing device according to the first embodiment. [Figure 41] 10 is a flowchart showing an example of the procedure of an abort control process executed in a memory system that communicates with the information processing device according to the first embodiment. [Figure 42] 10 is a flowchart showing an example of the procedure of a correction control process executed in a memory system that communicates with the information processing device according to the first embodiment. [Figure 43] 10 is a flowchart showing an example of the procedure of a write response reception process executed in the information processing device according to the first embodiment. [Figure 44] 10 is a flowchart showing an example of the procedure of an abort response reception process executed in the information processing device according to the first embodiment. [Figure 45] 10 is a flowchart showing an example of the procedure of a corrected response receiving process executed in the information processing device according to the first embodiment. [Figure 46] 10 is a flowchart showing an example of another procedure of the write request control process executed in the information processing device according to the first embodiment. [Figure 47] 10 is a flowchart showing an example of the procedure of a combined write request process executed in the information processing device according to the first embodiment. [Figure 48] 6 is a flowchart showing an example of the procedure of a trim request control process executed in the information processing device according to the first embodiment. [Figure 49] 10 is a flowchart showing an example of the procedure of a trim request process executed in the information processing device according to the first embodiment. [Figure 50] 6 is a flowchart showing an example of the procedure of a trim control process executed in a memory system that communicates with the information processing device according to the first embodiment. [Figure 51] 10 is a flowchart showing an example of the procedure of a trim response receiving process executed in the information processing device according to the first embodiment. [Figure 52]10 is a flowchart showing an example of the procedure of a recovery write request process executed in the information processing device according to the first embodiment. [Figure 53] 10 is a flowchart showing an example of the procedure of a deduplication process executed in the information processing device according to the first embodiment. [Figure 54] 10 is a flowchart showing an example of the procedure of an entry control process executed in the information processing device according to the first embodiment. [Figure 55] FIG. 10 is a block diagram showing an example of the configuration of an information processing system including an information processing device and a memory system according to a second embodiment. [Figure 56] FIG. 10 is a view showing an example of rewriting a memory-mapped file in the information processing device according to the second embodiment. [Figure 57] FIG. 10 is a block diagram showing an example of a write operation in an information processing system including an information processing device according to a second embodiment. [Figure 58] FIG. 10 is a block diagram showing another example of a write operation in the information processing system including the information processing device according to the second embodiment. [Figure 59] FIG. 10 is a view showing a first example of a memory-mapped file in the information processing device according to the second embodiment. [Figure 60] FIG. 10 is a block diagram showing an example of an abort operation in an information processing system including an information processing device according to a second embodiment. [Figure 61] FIG. 10 is a view showing a second example of a memory-mapped file in the information processing device according to the second embodiment. [Figure 62] FIG. 10 is a view showing a third example of a memory-mapped file in the information processing device according to the second embodiment. [Figure 63] FIG. 10 is a block diagram showing an example of a correction operation in an information processing system including an information processing device according to a second embodiment. [Figure 64] 10 is a flowchart showing an example of the procedure of a write request process executed in an information processing device according to the second embodiment. [Figure 65] 10 is a flowchart showing an example of the procedure of a write request control process executed in an information processing device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described with reference to the drawings.

[0014] First, the configuration of an information processing system 1 including an information processing device according to the first embodiment will be described with reference to Fig. 1. The information processing system 1 includes an information processing device 2 and a memory system 3.

[0015] The information processing device 2 may be a storage server that stores a large amount of diverse data in the memory system 3, or may be a server or a personal computer. Hereinafter, the information processing device 2 will also be referred to as a host 2.

[0016] The memory system 3 is a semiconductor storage device configured to write data to and read data from a nonvolatile memory such as a NAND flash memory. The memory system 3 is also referred to as a storage device. The memory system 3 is realized as, for example, a solid-state drive (SSD).

[0017] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2, or may be connected to the host 2 via a cable or a network.

[0018] The interface for connecting the host 2 and the memory system 3 complies with standards such as PCI Express (PCIe) (registered trademark), Ethernet (registered trademark), Fibre channel, and NVM Express (NVMe) (registered trademark).

[0019] Configuration examples of the host 2 and the memory system 3 will be described below.

[0020] (Configuration example for host 2) The host 2 includes, for example, a CPU 21, a random access memory (RAM) 22, a storage interface (storage I / F) 23, a nonvolatile random access memory (NVRAM) 24, a RAM interface (RAM I / F) 25, and an NVRAM interface (NVRAM I / F 26). The CPU 21, the storage I / F 23, the RAM I / F 25, and the NVRAM I / F 26 may be connected via a bus 20.

[0021] The CPU 21 is, for example, at least one processor. The CPU 21 controls the operation of various components within the host 2.

[0022] The RAM 22 is a volatile memory. The RAM 22 is realized as, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). The storage area of ​​the RAM 22 is allocated as a storage area for, for example, an operating system (OS) 221, a driver 222, and various application programs 223. Hereinafter, the application programs 223 will also be simply referred to as applications 223.

[0023] The storage I / F 23 functions as a control circuit that controls communication between the host 2 and the memory system 3. The storage I / F 23 transmits various commands to the memory system 3, such as input / output (I / O) commands and various control commands. The I / O commands include, for example, write commands and read commands. The control commands include, for example, trim commands (unmap commands), abort commands, modify commands, and flush commands.

[0024] The trim command is a command for deallocating a flash memory area that has been allocated to a specified logical address range. For example, the Dataset Management command defined in the NVMe standard is used as the trim command.

[0025] A logical address range includes one or more logical addresses. The logical addresses are used by the host 2 to address the memory system 3. The logical address range provided by the memory system 3 to the host 2 can be divided into multiple namespaces. A namespace is identified by a namespace ID, and each namespace has an independent logical address space. A logical address is, for example, a logical block address (LBA). The following mainly illustrates a case where an LBA is used as a logical address. User data in one namespace is logically stored in sectors of a certain size. A sector is identified by an LBA. The size of a sector does not need to be the same between namespaces.

[0026] The trim command includes, for example, a data pointer indicating a location within the host 2, a value specifying the LBA range deallocation process (trim process), and the number of LBA ranges to be deallocated. Information indicating the LBA ranges to be deallocated is stored in the location within the host 2 indicated by the data pointer. The information indicating the LBA ranges is also referred to as range information. The range information associated with the trim command is information indicating the LBA ranges to be deallocated in response to the trim command.

[0027] The abort command is a command for halting the execution of a command issued to the memory system 3. The abort command is defined, for example, in the NVMe standard. The abort command includes information that can uniquely identify the command to be aborted. The information that can uniquely identify the command includes, for example, identification information (command ID) of the command. The abort command is used, for example, to halt the execution of a write command issued to the memory system 3.

[0028] The modification command is a command for canceling (aborting) part of writing to an LBA range specified by an issued write command. When part of writing to an LBA range specified by an issued write command is canceled, the modification command includes, for example, information that can uniquely identify the write command and information indicating the LBA range to be canceled (range information). The modification command may include information indicating a location in the host 2 where the information indicating the LBA range to be canceled is stored. The information indicating the LBA range to be canceled may indicate multiple LBA ranges within the LBA range specified by the corresponding write command. The range information associated with the modification command is information that indicates the LBA range for which writing should be canceled in accordance with the modification command.

[0029] The flash commands include special flash commands and general flash commands.

[0030] The special flash command is a command that causes the memory system 3 to return a second completion in response to an incomplete write command or trim command for which the memory system 3 has returned a first completion, which will be described later. More specifically, the special flash command is a command that completes write command processing by causing user data that has not been written to the nonvolatile memory of the memory system 3 to be written from the storage area of ​​the host 2 to the nonvolatile memory of the memory system 3. The special flash command is also a command that completes trim command processing.

[0031] The general flush command is a command for writing user data written to a volatile write cache using volatile memory such as DRAM in the memory system 3 to nonvolatile memory in the memory system 3. As will be described later, the IO reception unit 210 of the host 2 provides a virtual power loss protection function (virtual PLP function) to the application 223 and the OS 221. Therefore, when the application 223 or the OS 221 makes an I / O request to the IO reception unit 210, the application 223 or the OS 221 does not need to worry about whether a nonvolatile write cache exists in the IO reception unit 210 or in the destination to which the IO reception unit 210 transmits the I / O request (for example, the memory system 3). For this reason, the IO reception unit 210 does nothing even when it receives a request to issue a general flush command from the application 223 or the OS 221, and always responds to the application 223 or the OS 221 that the request has been successfully completed.

[0032] When a memory system with the PLP function receives a write command from the host, it writes user data to a volatile write cache and returns a completion response to the host before writing the user data to non-volatile memory. This makes it appear to the host that the write is occurring quickly. If power is lost to the memory system, the memory system uses the PLP function to write user data in the volatile write cache that has not yet been written to non-volatile memory to the non-volatile memory. This makes it appear to the host that the volatile write cache does not exist within the memory system. Hereinafter, a volatile write cache in a memory system with such a PLP function will be referred to as a write cache with PLP. Note that the PLP function often utilizes energy stored in a capacitor within the memory system.

[0033] The IO reception unit 210 provides a virtual PLP function to the application 223 and the OS 221. The virtual PLP function is a function that uses data stored in the NVRAM 24 to recover writing of user data to the memory system 3 (more specifically, the non-volatile memory of the memory system 3) that could not be completed due to abnormal termination of the host 2, abnormal termination due to an abnormal power outage or the like of the memory system 3, or unintended restart of the memory system 3. In other words, the IO reception unit 210 uses the NVRAM 24 and the memory system 3 to provide a virtual memory system with the PLP function to the application 223 and the OS 221.

[0034] The NVRAM 24 is a nonvolatile memory. The NVRAM 24 is also referred to as a storage class memory (SCM). For example, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory) is used as the NVRAM 24. The storage areas of the NVRAM 24 are allocated as a buffer area used as a data buffer 241, an area for a submission queue (SQ) 242, an area for a completion queue (CQ) 243, an area for storing a pointer list 244, and an area for storing various data used in processing by the host 2. The various data used in processing by the host 2 include, for example, a locked data list 245 and modified command data 246.

[0035] The data buffer 241 is a storage area that temporarily stores user data to be written to the nonvolatile memory of the memory system 3 and information (range information) indicating the LBA range whose allocation is to be deallocated.

[0036] The submission queue 242 is a queue in which commands are stored in order to be sent from the host 2 to the memory system 3. The submission queue 242 is logically ring-shaped, meaning that the same area is used repeatedly.

[0037] The completion queue 243 is a queue in which responses (completions) are stored in order to be returned from the memory system 3 to the host 2. The memory system 3 can respond with multiple completions in response to one write command. The memory system 3 can respond with multiple completions in response to one trim command. The completion queue 243 is also logically ring-shaped.

[0038] The host 2 may implement separate submission queues 242 and completion queues 243 for each type of command, for example, for management commands and for input / output (I / O) commands such as read commands and write commands, for one memory system 3. The host 2 may also implement multiple pairs of submission queues 242 / completion queues 243 for I / O commands for one memory system 3. In this embodiment, the submission queues 242 / completion queues 243 are provided in the NVRAM 24, but submission queues 242 / completion queues 243 for commands other than write commands and trim commands may be provided in the RAM 22.

[0039] The pointer list 244 is a list of pointers that indicate the location of user data associated with a write command or a read command in the data buffer 241. In this embodiment, the pointer list 244 is stored in the NVRAM 24, but the pointer list 244 may also be stored in the RAM 22.

[0040] The lock data list 245 is a list for managing the processing status of write commands and trim commands issued from the host 2 to the memory system 3. One lock data list 245 corresponds to, for example, one memory system 3. More specifically, one lock data list 245 is associated with, for example, the identification information (drive ID) of the corresponding one memory system 3.

[0041] The modified command data 246 is data for managing information related to modified commands issued from the host 2 to the memory system 3. One modified command data 246 corresponds to, for example, one LBA range for which writing has been canceled.

[0042] The RAM I / F 25 functions as a RAM control circuit configured to control access to the RAM 22 .

[0043] The NVRAM I / F 26 functions as an NVRAM control circuit configured to control access to the NVRAM 24 .

[0044] 2 shows an example of the configuration of a lock data list 245 used in the host 2. The lock data list 245 may include one or more entries corresponding to one or more write commands and trim commands sent from the host 2 to the memory system 3. In the lock data list 245, the one or more entries are stored in the order in which the write requests or trim requests are received from the application 223 or the OS 221. Therefore, the area in which the one or more entries are stored is managed in a format that allows for reuse of released areas, such as a ring buffer format or a list structure linked using pointers.

[0045] Each entry includes, for example, an SQ entry information field, a completion order field, a data area management information field, a completion status field, and a pointer field to modified command data.

[0046] The SQ entry information field indicates information (SQ entry information) that represents the corresponding write command or trim command. The SQ entry information includes information such as the command type, content, and parameters required for execution. Below, we will explain in detail the SQ entry information field corresponding to a write command and the SQ entry information field corresponding to a trim command.

[0047] (SQ entry information field corresponding to the write command) The SQ entry information field corresponding to the write command indicates, for example, a command operation code, a data pointer, a command ID, a namespace ID, an LBA, and a data length.

[0048] The command operation code is a code that indicates the type of the corresponding command (here, a write command). For example, an Opcode defined in the NVMe standard is used as the command operation code.

[0049] The data pointer is information indicating the location in the host 2 where user data to be written in response to a corresponding write command is stored. As the data pointer, for example, a Physical Region Page (PRP) entry or a list thereof, or a Scatter Gather List (SGL) defined in the NVMe standard is used. When a PRP is used, a pointer to the list of PRP entries is stored in the SQ entry information field. When an SGL is used, an address indicating the first SGL segment of the SGL is stored in the SQ entry information field, and this segment stores only the second segment and a descriptor indicating its size. The list of PRP entries and the second and subsequent segments of the SGL are stored in the pointer list 244.

[0050] First, the PRP will be described in detail. The PRP maps a storage area for user data corresponding to a range of consecutive logical addresses in the logical address space to a range of physical addresses in the physical address space.

[0051] FIG. 3 shows an example of mapping between a logical address space 91 and a physical address space 92. The logical address space 91 is a space of logical addresses (e.g., LBA, as described above) used by the host 2 to address the memory system 3. In this example, the physical address space 92 is a space of physical addresses that address storage areas in the data buffer 241. The logical address space 91 and the physical address space 92 are divided, for example, in units of page size. Pages in the logical address space 91 (hereinafter also referred to as logical pages) and pages in the physical address space 92 (hereinafter also referred to as physical pages) are mapped one-to-one. Note that the physical address space 92 is usually smaller than the logical address space 91. Contiguous logical addresses in the logical address space 91 can be mapped to non-contiguous physical addresses in the physical address space 92. The memory system 3 accesses the data buffer 241 of the host 2 using physical addresses. Therefore, the host 2 must convert the logical address range of the logical address space 91, which is indicated only by the first logical address and data length in the write command, into a physical address range of the physical address space 92 and pass it to the memory system 3. This physical address is data called a PRP entry.

[0052] FIG. 4 shows an example of the structure of a PRP entry. The PRP entry as a whole represents one physical address. The data size of a PRP entry is, for example, 8 bytes (=64 bits). The PRP entry includes two areas: a base address and an offset. The base address area represents the physical address of the start of a physical page. The size of the base address area is, for example, 52 bits. The offset area represents the offset from the start of that physical page. The size of the offset area is, for example, 12 bits.

[0053] Hereinafter, a physical page whose base address is physical address N will also be referred to as physical page N. For example, if the data size of one PRP entry is 8 bytes, the offset must match an 8-byte boundary (i.e., the lowest 3 bits of the offset must be zero) so that the last PRP entry in a physical page does not straddle a physical page boundary.

[0054] Figure 5 is an example of a PRP entry list representing the user data area shown in Figure 3. As shown in Figure 5(A), the data pointer area for one I / O command (write command) can include fields 921 and 922 of two PRP entries.

[0055] Field 921 of the first PRP entry contains the base address of the first physical page in which user data is stored and an offset indicating the start of the user data within that physical page.

[0056] Field 922 of the second PRP entry is used when the size of the user data is larger than the size of the storage area of ​​the data buffer 241 indicated by the first PRP entry. If the size of the user data is smaller than the sum of the size of the storage area indicated by the first PRP entry and the capacity of another physical page, field 922 of the second PRP entry contains the base address of the second physical page. In this case, the user data is stored from the beginning of the second physical page, so the offset is zero.

[0057] If the user data spans three or more pages, the field 922 of the second PRP entry contains the physical address where the PRP entry list including the second and subsequent PRP entries is stored. The PRP entry list is the pointer list 244.

[0058] In the examples shown in FIGS. 3 and 5(A), the field 921 of the first PRP entry indicates that the beginning of the user data is stored at the position of offset α in physical page D, that is, physical address D+α.

[0059] In the examples shown in Figures 3 and 5(A), field 922 of the second PRP entry indicates that the second and subsequent PRP entry lists are stored at offset λ in physical page X (not shown), i.e., from physical address X+λ.

[0060] As shown in FIG. 5(B), the second and subsequent PRP entry lists stored at physical address X+λ indicate that user data is stored in physical page A, physical page B, physical page C, physical page (C+1), ..., and physical page (C+n-1), respectively. If physical page X cannot store all the PRP entry lists, the last PRP entry stored in physical page X indicates the physical address of the physical page (page Y in the example shown in FIG. 5(B)) where the next PRP entry list is stored, rather than the physical address where user data is stored. If the data size of a PRP entry is 8 bytes and the size of one physical page is 4 KiB, 512 PRP entries can be stored in one physical page. In the example shown in FIG. 5(B), the PRP entry is stored from the beginning of physical page Y, so the offset of this PRP entry is zero. The area where the PRP entry list is stored is also a continuous area in the logical address space 91. Therefore, among the logical pages where the PRP list is stored, the first logical page may have a PRP list stored partway through. Furthermore, the last logical page may store a PRP list up to the middle. On the other hand, the intermediate logical pages always store PRP lists from the beginning to the end. Therefore, even if the physical pages storing the PRP entry lists are not consecutive in the physical address space 92, the second and subsequent PRP entry lists are always stored from the beginning of the physical pages.

[0061] Specifically, as shown in Figure 5(C), the last part of the PRP entry list stored at physical address Y indicates that user data is stored in physical page (C+n), physical page (C+q), and physical page E. PRP entries indicating user data areas are created for each of the one or more physical pages storing data transferred by an I / O command. Because the size of a physical page is larger than the sector size, there may be cases where user data is stored only partway in the physical page indicated by the last PRP entry.

[0062] Next, we will explain the SGL in detail. The SGL is also called Vectored I / O. The SGL is a data structure that enables user data stored in multiple non-contiguous logical address ranges in the logical address space to be written to a contiguous LBA range with a single I / O command, or to be read from a contiguous LBA range to that non-contiguous logical address range with a single I / O command.

[0063] 6 shows an example of an SGL. The SGL includes one or more SGL segments (pointer lists 244). Each SGL segment is a contiguous area aligned on an 8-byte boundary and includes one or more SGL descriptors.

[0064] All SGL descriptors other than the last SGL descriptor in each SGL segment are SGL data block descriptors. The SGL data block descriptor indicates the size and starting physical address of the area in the data buffer 241 where user data is stored. The size of one area where user data is stored does not need to be an integral multiple of the sector size.

[0065] The last SGL descriptor in each SGL segment is an SGL segment descriptor or an SGL last segment descriptor. The SGL segment descriptor indicates the size of the area where the next SGL segment is stored and the starting physical address. The SGL last segment descriptor (the last SGL descriptor in SGL segment N-1 in the example shown in Figure 6) indicates that the next SGL segment (SGL segment N in the example shown in Figure 6) is the last SGL segment.

[0066] When an SGL is used, the write command includes the address of the first SGL segment. A write command can store only one SGL descriptor. If this first SGL segment cannot specify the entire area of ​​the data buffer 241 where user data is stored, an SGL segment descriptor or an SGL last segment descriptor is stored at the end of this SGL segment.

[0067] Returning to FIG. 2, the description returns to the SQ entry information field corresponding to the write command.

[0068] The command ID is identification information for the corresponding write command.

[0069] The namespace ID is identification information of the namespace in which the corresponding write command should be executed. There may be multiple logical address spaces (LBA spaces) used by the host 2 to access the memory system 3. Each logical address space may be referred to as a namespace. One of the multiple namespaces may be identified by the namespace ID.

[0070] The LBA is the LBA specified by the corresponding write command, and indicates the first LBA of the LBA range where user data should be written in response to the write command.

[0071] The data length is the data length specified by the corresponding write command. This data length indicates the length of the user data in logical blocks to be written in response to the write command (i.e., the number of sectors). Therefore, by specifying the LBA and data length in the write command, it is possible to identify the LBA range into which the user data should be written in response to that write command.

[0072] (SQ entry information field corresponding to the trim command) The SQ entry information field corresponding to the trim command indicates, for example, a command operation code, a data pointer, a range number, a command ID, and a namespace ID.

[0073] The command operation code is a code that indicates the type of the corresponding command (here, a trim command).

[0074] The data pointer is information that indicates the location where range information associated with the corresponding trim command is stored in the host 2. A specific configuration example of the range information associated with the trim command will be described later with reference to FIG.

[0075] The command ID is identification information of the corresponding trim command.

[0076] The namespace ID is the identification of the namespace in which the corresponding trim command should be executed.

[0077] FIG. 7 shows an example of the configuration of range information associated with a trim command. The range information is defined as a list of ranges (i.e., LBA ranges) in the NVMe standard, for example. In the range information, one range is indicated by, for example, a pair of the first LBA and the length in logical block units (i.e., the number of sectors). The range information includes the number of ranges specified in the command.

[0078] 7, the range information may include 256 ranges from Range 0 to Range 255. The range information has fields for Context Attributes, length in logical blocks, and starting LBA for each range. Note that the Context Attributes field is not used in range information associated with a trim command.

[0079] Returning to the description of each field of the lock data list 245 shown in FIG.

[0080] The completion order field indicates the order in which the first completion for the corresponding write command or trim command was received. Each of the one or more completions received by host 2 is assigned a sequence number according to the order in which they were received. The completion order field indicates the sequence number assigned to the first completion for the corresponding write command or trim command.

[0081] The data area management information field indicates information capable of identifying a storage area in the NVRAM 24 in which user data to be written in response to the corresponding write command is stored, or information capable of identifying a storage area in the NVRAM 24 in which range information associated with the corresponding trim command is stored. This information can be used, for example, to lock or unlock the identified storage area (e.g., a page) in the NVRAM 24 using a function of the OS 221.

[0082] The completion status field indicates whether the first completion for the corresponding write command or trim command has been received. Alternatively, the completion status field may be omitted, and the presence of a sequence number in the completion order field indicates that the first completion for the corresponding write command or trim command has been received.

[0083] In an entry corresponding to a write command, the pointer to modified command data field indicates a pointer to modified command data 246 associated with the write command. The modified command data 246 associated with the write command indicates information about the LBA range specified in the write command for which writing has been canceled. The pointer to modified command data 246 associated with the write command indicates the location in the NVRAM 24 where the modified command data 246 is stored. If writing to the LBA range specified in the write command has not been canceled, for example, NULL is set in the pointer to modified command data field. Note that in an entry corresponding to a trim command, for example, NULL is set in the pointer to modified command data field.

[0084] In the following description of the lock data list 245, the value indicated in the SQ entry information field will also be referred to simply as the SQ entry information. The same applies to the values ​​indicated in the other fields of the lock data list 245 and the values ​​indicated in the fields of other tables.

[0085] 8 shows an example of the configuration of the modified command data 246. The modified command data 246 includes the starting LBA of the canceled write, the number of sectors whose write was canceled, and a pointer to the next modified command data.

[0086] The first LBA of the canceled write and the number of sectors for which the write was canceled can be used to identify the LBA range for which the write was canceled (hereinafter referred to as the first canceled LBA range) within the LBA range specified in the associated write command. The pointer to the next modified command data indicates a pointer to another modified command data 246 associated with the same write command. This another modified command data 246 indicates information regarding another LBA range for which the write was canceled (hereinafter referred to as the second canceled LBA range) within the LBA range specified in the write command. In other words, this another modified command data 246 indicates information regarding a second canceled LBA range, different from the first canceled LBA range, within the LBA range specified in the write command. If there is no other modified command data 246 associated with the same write command, then, for example, NULL is set to the pointer to the next modified command data.

[0087] The modified command data 246 corresponding to one or more modified commands that modify the corresponding write command can be managed in a linked list structure using a pointer to the modified command data in an entry of the lock data list 245 and a pointer to the next modified command data in the modified command data 246. In other words, each entry of the lock data list 245 and each entry of the modified command data 246 can be said to constitute a modified command data list. This makes it easy to (1) add, (2) modify, (3) insert, and (4) delete a cancel LBA range.

[0088] More specifically, when a cancel LBA range is added for the first time, a pointer to modified command data 246 indicating the additional cancel LBA range is written to the pointer to modified command data of the corresponding entry in lock data list 245. When a further cancel LBA range is added, a pointer to another modified command data 246 indicating the additional cancel LBA range is written to the pointer to next modified command data of the corresponding entry in modified command data 246.

[0089] When an LBA area contiguous with a cancel LBA range already included in the modified command data list is additionally canceled, the first LBA corresponding to the existing cancel LBA range is made smaller and the length of the data to be canceled (number of sectors) is increased, or only the length of the data to be canceled (number of sectors) is increased.

[0090] When multiple cancel LBA ranges are sorted in ascending or descending order, the pointer (assumed to be pointer A) written in the pointer to the next modified command data of the corresponding entry in the modified command data list is overwritten with the pointer to the newly generated modified command data 246. Then, pointer A is written in the pointer to the next modified command data of the newly generated modified command data 246.

[0091] If two existing modified command data 246 entries can be combined into one, only one of the entries is modified. Specifically, to delete an entry of modified command data 246 that is no longer needed (assuming that pointer B is stored in the pointer to the next modified command data), pointer B is written to the pointer to the next modified command data of another modified command data 246 that had a pointer to that entry written in it. This makes it possible to free up the area in which the entry of modified command data 246 that is no longer needed is stored.

[0092] Hereinafter, such operations as (1) adding, (2) modifying, (3) inserting, and (4) deleting the cancellation LBA range will be referred to as registering the modified command data 246 in the modified command data list.

[0093] By arranging the entries in the modified command data list in ascending or descending order of the cancel LBA range, when registering a new cancel LBA range in the modified command data list, it is possible to easily check for continuity with existing cancel LBA ranges. This makes it easy to keep the size of the modified command data list to a minimum, for example. In other words, it is possible to simplify operations on the modified command data list.

[0094] Returning to Fig. 1, the programs executed by the CPU 21 will now be described.

[0095] The CPU 21 executes various programs loaded from, for example, the NVRAM 24 to the RAM 22. The programs executed by the CPU 21 include an OS 221, a driver 222, and various applications 223.

[0096] The OS 221 is a program for controlling the basic operations of various components within the host 2. The CPU 21 executing the OS 221 controls, for example, input / output, file management, memory management, and communication.

[0097] The driver 222 is a program for controlling devices connected to the host 2. For example, the CPU 21 executing the driver 222 transmits commands and data to the memory system 3 via the storage I / F 23. The CPU 21 executing the driver 222 receives responses to commands and data from the memory system 3 via the storage I / F 23.

[0098] By executing the driver 222, the CPU 21 functions as, for example, an IO reception unit 210, a command issue unit 211, a write / trim management unit 212, and a recovery control unit 213. Specific operations of the IO reception unit 210, the command issue unit 211, the write / trim management unit 212, and the recovery control unit 213 will be described later with reference to Fig. 11 to Fig. 37. The IO reception unit 210, the command issue unit 211, the write / trim management unit 212, and the recovery control unit 213 may be realized by dedicated hardware within the host 2.

[0099] (Configuration example of memory system 3) The memory system 3 includes, for example, a controller 4, a nonvolatile memory 5, and a DRAM 6. The controller 4 can be realized by a circuit such as a System-on-a-chip (SoC). The controller 4 may have an SRAM built in. The DRAM 6 may also be built in the controller 4. The nonvolatile memory 5 is, for example, a NAND flash memory. Hereinafter, the nonvolatile memory 5 will be referred to as the NAND flash memory 5.

[0100] The DRAM 6 is a volatile memory. A RAM such as the DRAM 6 includes, for example, a storage area for firmware (FW) 61, a cache area for a logical-physical address conversion table 62, a storage area for a write management table 63, and a storage area for modified command data 64.

[0101] The FW 61 is a program for controlling the operation of the controller 4. The FW 61 is loaded from the NAND flash memory 5 to the DRAM 6, for example.

[0102] The logical-physical address conversion table 62 manages the mapping between each logical address and each physical address of the NAND flash memory 5.

[0103] The write management table 63 manages information relating to received write commands and trim commands.

[0104] The modified command data 64 is data for managing information related to modified commands issued from the host 2 to the memory system 3. The configuration of the modified command data 64 is similar to the configuration of the modified command data 246 in the host 2 described above with reference to FIG.

[0105] The NAND flash memory 5 includes multiple blocks. Each block includes multiple pages. A block functions as the smallest unit of a data erase operation. A block is also referred to as an "erase block" or a "physical block." Each page includes multiple memory cells connected to a single word line. A page functions as a unit of a data write operation and a data read operation. Note that a word line may also function as a unit of a data write operation and a data read operation.

[0106] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, called the maximum number of P / E cycles. One P / E cycle for a block includes an erase operation to erase all memory cells in the block, and a write operation (program operation) to write data to each page of the block.

[0107] For example, user data and management data can be written to the NAND flash memory 5. The user data is data to be written to the NAND flash memory 5, which is associated with a write command received from the host 2. The management data is data for managing the operation of the memory system 3. The management data includes, for example, information used in the flash translation layer (FTL) and a command log 51. The management data may also include identification information (host ID) of the host 2 and information regarding the mode in which the memory system 3 is operating.

[0108] The command log 51 indicates the command IDs of commands whose corresponding processing has been completed. The command log 51 is used for debugging the memory system 3. The controller 4 stores the command IDs in the command log 51 so that the order in which the processing corresponding to the commands is completed can be managed.

[0109] The controller 4 functions as a memory controller configured to control the NAND flash memory 5 .

[0110] The controller 4 may function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes (1) management of mapping information indicating the correspondence between each LBA and each physical address of the NAND flash memory 5, and (2) processing for concealing the difference between page-based data read / write operations and block-based data erase operations. The block management includes management of bad blocks, wear leveling, and garbage collection.

[0111] The management of the mapping between each LBA and each physical address is performed using a logical-physical address conversion table 62. The controller 4 uses the logical-physical address conversion table 62 to manage the mapping between each LBA and each physical address in specific management size units. A physical address corresponding to a certain LBA indicates the physical storage location in the NAND flash memory 5 where the data of this LBA is written. The controller 4 uses the logical-physical address conversion table 62 to manage multiple storage areas obtained by logically dividing the storage area of ​​the NAND flash memory 5. These multiple storage areas correspond to multiple LBAs, respectively. In other words, each of these multiple storage areas is specified by one LBA. The logical-physical address conversion table 62 may be loaded from the NAND flash memory 5 to the DRAM 6 when the memory system 3 is powered on.

[0112] Data can only be written to one page once per P / E cycle. Therefore, the controller 4 writes updated data corresponding to a certain LBA to a different physical storage location, rather than to the physical storage location where the previous data corresponding to this LBA is stored. The controller 4 then invalidates the previous data by updating the logical-physical address conversion table 62 so that this LBA is associated with this different physical storage location. Data referenced by the logical-physical address conversion table 62 (i.e., data associated with an LBA) is called valid data. Data not associated with any LBA is called invalid data. Valid data is data that may be read by the host 2 later. Invalid data is data that is no longer likely to be read by the host 2.

[0113] The logical-physical address conversion table 62 on the DRAM 6 can function as a write-back cache. That is, when the contents of the logical-physical address conversion table 62 on the DRAM 6 are changed, the logical-physical address conversion table 62 is made nonvolatile in the NAND flash memory 5 at an appropriate time. Furthermore, when certain user data is written to the NAND flash memory 5, the mapping between the LBA and the physical address of the user data is also made nonvolatile in the NAND flash memory 5. As a result, even if the logical-physical address conversion table 62 is lost from the DRAM 6, the logical-physical address conversion table 62 can be reconstructed from the information made nonvolatile in the NAND flash memory 5. In other words, even if the power supply to the memory system 3 is cut off when the writing of the user data to the NAND flash memory 5 is completed, the nonvolatile logical-physical address conversion table 62 and the written user data can be preserved.

[0114] When the controller 4 receives a trim command specifying a certain LBA from the host 2, it deallocates this LBA. That is, the controller 4 updates the logical-physical address conversion table 62 to delete the association between this LBA and the physical storage location. As a result, the controller 4 invalidates the data associated with this LBA.

[0115] The controller 4 may include a host interface (host I / F) 11, a CPU 12, a NAND interface (NAND I / F) 13, a DRAM interface (DRAM I / F) 14, and a timer 15. The host I / F 11, the CPU 12, the NAND I / F 13, the DRAM I / F 14, and the timer 15 may be connected via a bus 10.

[0116] The host I / F 11 functions as a circuit that receives various commands, such as I / O commands, various control commands, and data, from the host 2. The host I / F 11 also functions as a circuit that transmits responses to commands and data to the host 2.

[0117] The NAND I / F 13 electrically connects the controller 4 and the NAND flash memory 5. The NAND I / F 13 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0118] The NAND I / F 13 functions as a NAND control circuit configured to control the NAND flash memory 5. The NAND I / F 13 may be connected to multiple memory chips in the NAND flash memory 5 via multiple channels (Ch). By driving multiple memory chips in parallel, it is possible to widen the bandwidth of access to the entire NAND flash memory 5.

[0119] The DRAM I / F 14 functions as a DRAM control circuit configured to control access to the DRAM 6 .

[0120] The timer 15 measures time. The timer 15 can provide the measured time to each section in the controller 4.

[0121] The CPU 12 is a processor configured to control the host I / F 11, the NAND I / F 13, the DRAM I / F 14, and the timer 15. The CPU 12 performs various processes by executing the FW 61 loaded from the NAND flash memory 5 to the DRAM 6. The FW 61 is a control program including a group of instructions for causing the CPU 12 to perform various processes. The CPU 12 can execute command processing and the like for processing various commands from the host 2. The operation of the CPU 12 is controlled by the FW 61 executed by the CPU 12.

[0122] The functions of the various units in the controller 4 may be realized by dedicated hardware in the controller 4, or may be realized by the CPU 12 executing the FW 61.

[0123] The CPU 12 functions as, for example, a command reception unit 121 and a write / trim control unit 122. The CPU 12 functions as these units by, for example, executing FW 61. Specific operations of the command reception unit 121 and the write / trim control unit 122 will be described later with reference to FIGS. 11 to 37.

[0124] Next, two tables used in the memory system 3 will be described with reference to FIGS.

[0125] 9 shows an example of the configuration of the logical-physical address conversion table 62. The logical-physical address conversion table 62 manages the mapping between each LBA and each physical address of the NAND flash memory 5. The controller 4 can convert an LBA into a physical address using the logical-physical address conversion table 62. The controller 4 can also convert a physical address into an LBA using the logical-physical address conversion table 62.

[0126] In the example shown in FIG. 9, physical address "A" is mapped to LBA "0", physical address "B" is mapped to LBA "1", and physical address "C" is mapped to LBA "2".

[0127] 10 shows an example of the configuration of the write management table 63. The write management table 63 may include one or more entries corresponding to one or more write commands. Each entry may include, for example, a command ID field, an LBA field, a data length field, a data pointer field, and a pointer field to the modified command data.

[0128] The command ID field indicates the command ID of the corresponding write command.

[0129] The LBA field indicates the LBA specified in the corresponding write command, which indicates the first LBA in the LBA range where user data should be written in response to the write command.

[0130] The data length field indicates the data length specified in the corresponding write command. This data length indicates the length of the user data to be written in response to the write command. The LBA and data length specified in the write command can be used to identify the LBA range to which the user data should be written in response to the write command.

[0131] The data pointer field indicates a data pointer specified by the corresponding write command. This data pointer indicates the location in the host 2 where the user data to be written to the NAND flash memory 5 in response to the write command is stored, or the location where the pointer list 244 indicating the location in the host 2 where the user data is stored is stored. In other words, the controller 4 obtains the user data from the location in the host 2 that is directly or indirectly indicated by the data pointer.

[0132] The pointer to modified command data field indicates a pointer to modified command data 64 associated with the corresponding write command. The modified command data 64 associated with the write command indicates information about the LBA range specified in the write command for which writing has been canceled. The pointer to modified command data 64 associated with the write command indicates the location in the DRAM 6 where the modified command data 64 is stored. If writing to the LBA range specified in the write command has not been canceled, for example, NULL is set in the pointer to modified command data field.

[0133] Next, with reference to FIGS. 11 to 37, examples of some operations performed in the information processing system 1 will be described.

[0134] (First example of a write operation) 11 to 18, a first example of a write operation in the information processing system 1 will be described. The write operation is an operation for transmitting a write command from the host 2 to the memory system 3 and writing user data associated with the write command to the NAND flash memory 5.

[0135] Here, we will explain the submission queue 242 and completion queue 243 provided in the NVRAM 24 of the host 2. The host 2 sends a command to the memory system 3 via the submission queue 242. In addition, the memory system 3 returns a completion for the command to the host 2 via the completion queue 243.

[0136] The submission queue 242 includes a number of slots in which the host 2 stores commands issued by the host 2 to the memory system 3. The position (i.e., slot) in the submission queue 242 where the host 2 should store the command is indicated by an SQ Tail pointer. The position in the submission queue 242 where the memory system 3 should fetch the command is indicated by an SQ Head pointer.

[0137] The completion queue 243 includes multiple slots in which the memory system 3 stores a response to a command. The location in the completion queue 243 where the memory system 3 should store the response is indicated by a CQ Tail pointer. The location in the completion queue 243 where the host 2 should fetch the response is indicated by a CQ Head pointer.

[0138] The following describes a specific example of a write operation in the host 2 and the memory system 3. For ease of understanding, the examples shown in Figures 11 to 18 illustrate a case where only a write command is written to the submission queue 242.

[0139] 11 shows an example of a write operation in the information processing system 1. Here, an example is shown in which the IO reception unit 210 of the host 2 receives a write request to write user data 71 to the NAND flash memory 5. This write request is, for example, a write request from the application 223 executed by the CPU 21.

[0140] First, in the host 2, the IO reception unit 210 receives a write request from the application 223 ((1) in FIG. 11). The IO reception unit 210 sends the received write request to the write / trim management unit 212 ((2) in FIG. 11). The write / trim management unit 212 uses a function of the application 223 or the OS 221 to lock the user data 71 that is stored in the data buffer 241 and for which writing is requested ((3) in FIG. 11). More specifically, the write / trim management unit 212 uses a function of the OS 221 to lock a storage area (e.g., a page) in which the user data 71 is stored. This prevents the storage area in which the user data 71 is stored from being unintentionally released or paged out. Furthermore, the write / trim management unit 212 uses a function of the OS 221 to write-protect the storage area in which the user data 71 is stored.

[0141] As will be described later, the completion of the write request is notified to the application 223 before the writing of the user data 71 to the NAND flash memory 5 is completed. After the completion of the write request is notified, the application 223 recognizes that the writing is completed, and therefore there is a possibility that the storage area in which the user data 71 is stored will be used for another purpose or will be overwritten with other data. Therefore, in order to prevent the user data 71, which has not yet actually been written to the NAND flash memory 5, from being lost from the data buffer 241, the storage area in which the user data 71 is stored is locked and further set to write-protected.

[0142] Here, the memory management mechanism of the OS 221 will be explained.

[0143] The CPU 21 of the host 2 may include, for example, a Memory Management Unit (MMU). The MMU manages the mapping between each logical address used by the application 223 executed by the CPU 21 to access the physical memory and each address (physical address) on the physical memory. The physical memory is, for example, the RAM 221 or the NVRAM 24. Access to the physical memory is, for example, reading data from the physical memory or writing data to the physical memory. When the application 223 requests access to the physical memory using a logical address, the MMU converts the logical address into a physical address. Access to the physical memory is performed based on the physical address obtained by the conversion.

[0144] The unit of mapping between logical addresses and physical addresses is, for example, a page. A page accessed using a logical address (i.e., a logical page as described above with reference to FIG. 3) may be assigned a page in memory accessed using a physical address (i.e., a physical page as described above with reference to FIG. 3).

[0145] The MMU can manage multiple logical pages. The storage capacity of a virtual memory (virtual memory) corresponding to multiple logical pages may be larger than the storage capacity of physical memory. The OS 221 executed by the CPU 21 allocates physical pages to only those logical pages that are actually currently in use, for example, out of the multiple logical pages. This allows the application 223 to operate as if it had a memory with a storage capacity larger than the physical memory.

[0146] The MMU manages attribute information for each of a plurality of logical pages. The attribute information includes, for example, information indicating whether a physical page is mapped, information indicating whether a physical page is writable, a bit set in response to access, a dirty bit set in response to writing, a bit that prohibits unmapping of the physical page (i.e., a bit that prohibits page-out), or information indicating the address of the corresponding physical page. When the application 223 requests access to a logical page to which no physical page is mapped or requests writing to a non-writable logical page, an interrupt is generated to the CPU 21 based on the attribute information. The OS 221 can perform appropriate processing in response to the interrupt.

[0147] 12 is a diagram illustrating an example of the state of the logical address space 95 and the physical address space 98 at the time when the application 223 makes a write request. The logical address space 95 is a space of logical addresses managed by the MMU. The physical address space 98 is a space of physical addresses managed by the MMU. The logical address space 95 includes a kernel memory space 96 and a user memory space 97. The application 223 accesses the physical memory via the user memory space 97.

[0148] In FIG. 12, each cell in the logical address space 95 and the physical address space 98 represents a logical page and a physical page, respectively. A logical page 971 is a logical page in which user data 71 is logically stored. A physical page 981 is a physical page in which user data 71 is physically stored. The logical page 971 is mapped to the physical page 981. FIG. 12 shows one mapping between the logical page 971 and the physical page 981, but multiple logical pages may be mapped to multiple physical pages. Although not shown in the figure, physical pages are also mapped to logical pages in the user memory space 97 that do not contain user data 71 used by the application 223. Physical pages are also mapped to logical pages in the kernel memory space 96 that are used.

[0149] The user memory space 97 is independent for each process. On the other hand, the IO reception unit 210 and the like run in kernel mode and can access not only the user memory space 97 but also the virtual kernel memory space 96. This kernel memory space 96 is common to each application 223, but cannot be accessed directly by the application 223. Instead, the application 223 invokes a system call to switch to kernel mode, and then the invoked system call accesses the kernel memory space 96. In addition, the part of the OS 221 that runs in kernel mode accesses the kernel memory space 96.

[0150] FIG. 13 shows an example of an operation performed by the write / trim management unit 212 immediately before the IO reception unit 210 notifies the write request source (e.g., application 223) of the completion of the write request. For example, the write / trim management unit 212 uses the function of the OS 221 to write-protect the logical page 971 including the user data 71 immediately before the IO reception unit 210 notifies the write request source of the completion of the write request. The pointer list 244 describes the location of the user data 71 by physical address (physical page 981). Note that this write protection operation only needs to be performed before the IO reception unit 210 notifies the write request source of the completion of the write request. For example, the write / trim management unit 212 may perform the write protection operation when it receives from the memory system 3 the first completion to the write command corresponding to the write request and the completion is a normal response. Note that while FIG. 13 illustrates an example in which the user data 71 exists only in one logical page, the user data 71 may exist in multiple logical pages. In this case, each logical page is mapped to a different physical page.

[0151] The user data 71 may be stored in the RAM 22 using a function of the application 223 or the OS 221. When the user data 71 is stored in the RAM 22, the IO reception unit 210 copies the user data 71 from the RAM 22 to the data buffer 241 of the NVRAM 24, and then sends a write request to the write / trim management unit 212. In this case, the area in the NVRAM 24 to which the user data 71 has been copied does not need to be write-protected because there is no risk of the area being written to later by the application 223 or the like that is the source of the write request.

[0152] Returning to Fig. 11, the write / trim management unit 212 requests the command issuing unit 211 to issue a write command corresponding to the write request ((4) in Fig. 11). In response to the request from the write / trim management unit 212, the command issuing unit 211 issues a write command for writing the user data 71. In other words, the command issuing unit 211 generates SQ entry information corresponding to the write command for writing the user data 71. The command issuing unit 211 sends the generated SQ entry information to the write / trim management unit 212 ((5) in Fig. 11).

[0153] The write / trim management unit 212 generates an entry for the lock data list 245 using the SQ entry information sent by the command issuer 211. The generated entry includes, for example, SQ entry information corresponding to the issued write command and data area management information. This data area management information is information that can identify the storage area in the data buffer 241 where the user data 71 is stored. The write / trim management unit 212 adds the generated entry to the lock data list 245 ((6) in FIG. 11).

[0154] Fig. 14 shows an example of the lock data list 245 to which an entry has been added in the operation (6) in Fig. 11. The lock data list 245 includes the added entry 81.

[0155] 14, the entry 81 includes SQ entry information "sqentry_info1" corresponding to the issued write command, and data area management information "region_info1" indicating the storage area in the data buffer 241 where the user data 71 associated with this write command is stored. Note that the entry 81 does not yet include the completion order and completion status.

[0156] Returning to FIG. 11 , the command issuing unit 211 then stores the issued write command (SQ entry information) in the submission queue 242 ((7) in FIG. 11 ). The operation of storing a command in the submission queue 242 will be described in more detail. First, the command issuing unit 211 writes a command (here, a write command) to a slot in the submission queue 242 indicated by the SQ Tail pointer. The command issuing unit 211 adds 1 to the SQ Tail pointer. Note that if the value obtained by adding 1 to the SQ Tail pointer reaches the number of slots in the submission queue 242 (i.e., the queue size), the command issuing unit 211 sets the SQ Tail pointer to 0. Then, the command issuing unit 211 writes the updated value of the SQ Tail pointer to the SQ Tail doorbell register of the memory system 3. In this way, the operation of storing a command in the submission queue 242 includes the operation of writing the command to the submission queue 242 and the operation of updating the SQ Tail pointer.

[0157] When the SQ Tail doorbell register is updated, the command reception unit 121 of the memory system 3 receives the update and acquires a write command from the submission queue 242 ((8) in FIG. 11). The command reception unit 121 then sends the acquired write command to the write / trim control unit 122 ((9) in FIG. 11). Here, the operation of acquiring a command from the submission queue 242 will be described in more detail. First, if there is a difference between the SQ Head pointer and the SQ Tail pointer, the command reception unit 121 fetches a command (here, a write command) from the slot indicated by the SQ Head pointer in the submission queue 242. The command reception unit 121 adds 1 to the SQ Head pointer. Note that if the value obtained by adding 1 to the SQ Head pointer reaches the number of slots in the submission queue 242, the command reception unit 121 sets 0 to the SQ Head pointer. Thus, the act of retrieving a command from submission queue 242 includes the acts of fetching the command from submission queue 242 and updating the SQ Head pointer.

[0158] Next, the write / trim control unit 122 updates the write management table 63 using the write command sent by the command reception unit 121 ((10) in FIG. 11). Specifically, the write / trim control unit 122 adds an entry including the command ID, LBA, data length, and data pointer specified in the write command to the write management table 63. Note that the write / trim control unit 122 adds the corresponding entry to the write management table 63 after confirming that the LBA specified in the write command is valid, that data can be written to that LBA, and that the data pointer is valid. The data pointer is considered valid, for example, when the data pointer indicates an accessible area in the host 2 and indicates an area that matches the data length. Then, the write / trim control unit 122 notifies the command reception unit 121 that updating of the write management table 63 based on the write command has been completed ((11) in FIG. 11).

[0159] In response to the notification from the write / trim control unit 122, the command reception unit 121 stores the first completion for the write command (a completion indicating normal completion) in the completion queue 243 ((12) in FIG. 11). This first completion includes the command ID of the write command. This first completion may also include an updated SQ Head pointer.

[0160] The operation of storing a completion in the completion queue 243 will be described in more detail. First, the command reception unit 121 writes a completion to the slot indicated by the CQ Tail pointer in the completion queue 243. At this time, the value of the Phase Tag field of this slot is inverted, thereby completing the writing of the completion. The host 2 can determine the position in the completion queue 243 indicated by the CQ Tail pointer by reading the value of the Phase Tag field. The command reception unit 121 adds 1 to the CQ Tail pointer. If the value obtained by adding 1 to the CQ Tail pointer reaches the number of slots in the completion queue 243, the command reception unit 121 sets the CQ Tail pointer to 0. The command reception unit 121 issues an interrupt. The command reception unit 121 may issue an interrupt after writing multiple completions to the completion queue 243. The command reception unit 121 issues an interrupt to notify the host 2 that a new completion to be processed is in the completion queue 243. In this way, the operation of storing a completion in the completion queue 243 includes the operation of writing the completion to the completion queue 243, the operation of updating the CQ Tail pointer, and the operation of issuing an interrupt. As described above, the operation of updating the CQ Tail pointer may include the operation of notifying the host 2 of the updated SQ Head pointer. Hereinafter, performing this series of operations is also referred to as notifying the host 2 of the completion.

[0161] If the write command acquired from the submission queue 242 is an unexecutable command, the command receiving unit 121 may store a completion indicating an abnormal end in the completion queue 243 as the first completion.

[0162] Next, the command issuing unit 211 of the host 2 acquires the first completion for the write command from the completion queue 243 ((13) in FIG. 11). Then, the command issuing unit 211 sends the acquired first completion to the write / trim management unit 212 ((14) in FIG. 11).

[0163] Here, the operation of retrieving a completion from the completion queue 243 will be described in more detail. First, in response to an interrupt issued by the command reception unit 121 of the memory system 3, the command issuing unit 211 fetches a completion from the slot indicated by the CQ Head pointer in the completion queue 243. The command issuing unit 211 increments the CQ Head pointer by 1. If the value obtained by incrementing the CQ Head pointer by 1 reaches the number of slots in the completion queue 243, the command issuing unit 211 sets the CQ Head pointer to 0. Furthermore, if the Phase Tag value of the slot from which the completion was fetched and the Phase Tag value of the slot indicated by the updated CQ Head pointer (also referred to as the next slot) are the same (or the inverted value if the CQ Head pointer becomes 0), the command issuing unit 211 fetches a completion from the next slot and updates the CQ Head pointer again. Similarly, after fetching all completions from slots with the same Phase Tag value, the command issuing unit 211 writes the updated CQ Head pointer value to the CQ Head doorbell register of the memory system 3. Then, the command issuing unit 211 clears the interrupt received from the memory system 3. In this way, the operation of obtaining a completion from the completion queue 243 includes the operation of fetching the completion from the completion queue 243, the operation of updating the CQ Head pointer, and the operation of clearing the interrupt.

[0164] If the first completion indicates a normal end, the write / trim management unit 212 updates the entry in the lock data list 245 that corresponds to the first completion received from the command issuer 211 ((15) in FIG. 11). Specifically, the write / trim management unit 212 assigns a sequence number indicating the order in which the first completion was received to the received first completion. The sequence number is incremented by 1, for example, each time the first completion for a write command is received from the memory system 3. The write / trim management unit 212 also acquires the command ID included in the received first completion. The write / trim management unit 212 identifies an entry in the lock data list 245 that includes SQ entry information that corresponds to the acquired command ID. The write / trim management unit 212 adds the assigned sequence number (i.e., information indicating the order in which the first completion was received) and information indicating that the first completion has been received to the identified entry.

[0165] If the first completion indicates an abnormal termination, the write / trim management unit 212 unlocks the user data 71 in the data buffer 241 that corresponds to the received first completion ((16) in FIG. 11). Then, the write / trim management unit 212 deletes the entry that corresponds to the received first completion from the lock data list 245 ((17) in FIG. 11).

[0166] More specifically, the write / trim management unit 212 acquires the command ID included in the received first completion. The write / trim management unit 212 identifies an entry in the lock data list 245 that includes SQ entry information corresponding to the acquired command ID. The write / trim management unit 212 unlocks the user data 71 associated with the abnormally terminated write command, using the data area management information in the identified entry. Furthermore, if the write / trim management unit 212 has created a list of PRP entries or the second or subsequent segments of the SGL, it also frees the area of ​​the pointer list 244 in which these are stored. The write / trim management unit 212 then deletes the identified entry from the lock data list 245 (i.e., deletes it from the NVRAM 24). Furthermore, if the storage area in which the user data 71 is stored is locked or write-protected, the write / trim management unit 212 unlocks this.

[0167] If the user data 71 stored in the storage area from which the lock or write protection has been released is data copied by the IO receiving unit 210, the IO receiving unit 210 deletes the data from the data buffer 241. Specifically, other data may be stored in this storage area. If the user data 71 is not data copied by the IO receiving unit 210, the application 223 or the OS 221 decides whether to reuse or release the storage area.

[0168] In the following, for a certain write command, the series of operations described above, including unlocking the associated user data 71, deleting the entry in the corresponding lock data list 245, freeing up the area in the corresponding pointer list 244, unlocking or disabling write protection on the storage area containing the user data 71, and deleting the user data 71, will also be referred to as the entry deletion operation for the write command.

[0169] Fig. 15 shows an example of the lock data list 245 in which the entry has been updated in the operation (15) in Fig. 11. The lock data list 245 includes the updated entry 81.

[0170] 15, entry 81 has been added with a completion order "cseq1" indicating the order in which the first completion was received and a completion status "completed" indicating that the first completion has been received. In other words, entry 81 indicates that the first completion has been received in the completion order "cseq1."

[0171] When the write / trim management unit 212 completes updating the lock data list 245, it returns a response to the write request generated by the application 223 or the OS 221. Specifically, if the first completion indicates normal completion, the write / trim management unit 212 notifies the IO reception unit 210 of the completion of the write (normal completion) ((18) in FIG. 11). Then, the IO reception unit 210 notifies the application 223 or the OS 221 of the completion of the write ((19) in FIG. 11). This write completion notification allows the application 223 or the OS 221 to proceed with the processing even though the write to the NAND flash memory 5 has not actually been completed. As a result, even though the memory system 3 does not have a PLP-attached write cache, it appears to the application 223 or the OS 221 as if it had a PLP-attached write cache.

[0172] On the other hand, if the first completion indicates an abnormal termination (error termination), the write / trim management unit 212 notifies the IO reception unit 210 of the abnormal termination ((20) in FIG. 11). Then, the IO reception unit 210 notifies the application 223 or the OS 221 of the abnormal termination ((21) in FIG. 11). As described above, there is a case where the application 223 or the OS 221 stores the user data 71 in the RAM 22, and the IO reception unit 210 copies the user data 71 from the RAM 22 to the NVRAM 24. In this case, upon receiving the first completion indicating the abnormal termination, the application 223 or the OS 221 can release the area of ​​the RAM 22 in which the user data 71 was stored and use it for another purpose. Furthermore, the IO reception unit 210 can release the area of ​​the NVRAM 24 in which the user data 71 was stored and use it to store other data.

[0173] Fig. 16 shows an example of a write operation subsequent to Fig. 11. Here, an example is shown in which the total amount of user data 71 requested to be written by multiple write commands received by the memory system 3 from the host 2 reaches a specific data unit. The specific data unit is, for example, the amount of data that can be written to the NAND flash memory 5 in one data write operation.

[0174] In the memory system 3, after the total amount of user data 71 requested to be written by multiple write commands received from the host 2 reaches a specific data unit, the command reception unit 121 and the write / trim control unit 122 write the specific data unit of user data 71 to the NAND flash memory 5 and return a second completion corresponding to each of the multiple write commands to the host 2. In other words, the command reception unit 121 and the write / trim control unit 122 do not immediately execute writing in response to one received write command, but operate using a mechanism (Delayed Write Completion) in which writing in response to the multiple write commands is executed after the total amount of user data 71 requested to be written by the multiple write commands reaches a specific data unit.

[0175] Specifically, the write / trim control unit 122 transfers the user data 71 of the write unit from the data buffer 241 to the NAND flash memory 5, and writes (programs) the transferred user data 71 of the write unit to the NAND flash memory 5 ((1) in FIG. 16). Then, when there is a write command that has made it possible to read all of the corresponding user data 71 from the NAND flash memory 5, the write / trim control unit 122 notifies the command reception unit 121 of the completion of processing corresponding to the write command ((2) in FIG. 16). The write / trim control unit 122 notifies the command reception unit 121 of the completion of processing corresponding to each of the multiple write commands corresponding to the user data 71 of the write unit. The write / trim control unit 122 deletes entries corresponding to each of the multiple write commands from the write management table 63 ((3) in FIG. 16). The write / trim control unit 122 updates the logical-physical address conversion table 62 based on the processing corresponding to each of the multiple write commands ((4) in FIG. 16). Specifically, the write / trim control unit 122 updates the logical-physical address conversion table 62 so as to associate the LBA specified in each of the multiple write commands with the physical storage location to which the corresponding user data 71 is written. The write / trim control unit 122 also adds the command ID of each of the multiple write commands to the command log 51 ((5) in FIG. 16).

[0176] Every time the command reception unit 121 receives a notification from the write / trim control unit 122, it sends a second completion indicating that processing according to the corresponding write command has been completed to the host 2 ((6) in FIG. 16). More specifically, in response to the notification from the write / trim control unit 122, the command reception unit 121 stores the second completion for the corresponding write command in the completion queue 243. The notification from the write / trim control unit 122 includes, for example, the command ID of the write command whose processing has been completed.

[0177] If an error occurs in the processing according to the write command, the command reception unit 121 sends a completion indicating the error to the host 2 as a second completion.

[0178] Next, the command issuing unit 211 of the host 2 acquires the second completion from the completion queue 243 ((7) in FIG. 16). Then, the command issuing unit 211 sends the acquired second completion to the write / trim management unit 212 ((8) in FIG. 16).

[0179] The write / trim management unit 212 receives the second completion from the command issuing unit 211 and unlocks the user data 71 in the data buffer 241 that corresponds to the received second completion ((9) in FIG. 16). Then, the write / trim management unit 212 deletes the entry that corresponds to the received second completion from the locked data list 245 ((10) in FIG. 16).

[0180] More specifically, the write / trim management unit 212 acquires the command ID included in the received second completion. The write / trim management unit 212 identifies an entry in the lock data list 245 that includes SQ entry information corresponding to the acquired command ID. The write / trim management unit 212 unlocks the user data 71 for which writing has been completed, using the data area management information in the identified entry. Furthermore, if the write / trim management unit 212 has created a list of PRP entries or the second or subsequent segments of the SGL, it also releases the area of ​​the pointer list 244 in which these are stored. Then, the write / trim management unit 212 deletes the identified entry from the lock data list 245 (i.e., deletes it from the NVRAM 24). Furthermore, if the storage area in which the user data 71 is stored is locked or write-protected, the write / trim management unit 212 unlocks this. Note that if the user data 71 stored in the storage area from which the lock or write protection has been released is data copied by the IO reception unit 210, the IO reception unit 210 deletes it from the data buffer 241. Specifically, other data may be stored in this storage area. If the user data 71 is not data copied by the IO reception unit 210, the application 223 or the OS 221 decides whether to reuse or release the storage area. That is, the write / trim management unit 212 and the IO reception unit 210 perform an entry deletion operation for the corresponding write command in response to the second completion.

[0181] If the second completion indicates an error, the host 2 (specifically, the command issuing unit 211, the write / trim management unit 212, and the IO receiving unit 210) considers the memory system 3 to be faulty. The host 2 stops processing the memory system 3 and performs abnormality processing as the information processing system 1. For example, the write / trim management unit 212 deletes all data related to the memory system 3. The deleted data includes the user data 71 in the data buffer 241 corresponding to the memory system 3 and the locked data list 245 corresponding to the memory system 3. If the storage area in which the user data 71 is stored is locked or write-protected, the write / trim management unit 212 unlocks this lock. The command issuing unit 211 also stops sending at least write commands and trim commands to the memory system 3 considered to be faulty. Furthermore, the IO receiving unit 210 responds with an error to all write requests and trim requests from the application 223 or the OS 221.

[0182] Note that if the memory system 3 cannot be written to but can be read from, the host 2 may protect the data before deleting all data related to that memory system 3. For example, the host 2 copies the data at all addresses in the memory system 3 to another memory system, and then overwrites the user data 71 stored in the data buffer 241 with the copied data. This allows the host 2 to protect all user data that was made nonvolatile in the nonvolatile memory (NVRAM 24) in the host 2 and the nonvolatile memory (NAND flash memory 5) in the memory system 3 at the time of the failure of the memory system 3.

[0183] Figure 17 shows an example of the lock data list 245 from which an entry is deleted in operation (10) in Figure 16. The lock data list 245 includes an entry 81 corresponding to the second completion received.

[0184] 17, entry 81 includes SQ entry information "sqentry_info1", completion order "cseq1", data area management information "region_info1", and completion status "completed". In other words, entry 81 is an entry indicating that the first completion has been received. Entry 81 is deleted in response to receiving the second completion for the corresponding write command (i.e., the write command equivalent to the SQ entry information "sqentry_info1") from the memory system 3.

[0185] It should be noted that the slot of the submission queue 242 in which the write command (SQ entry information) was stored can be overwritten to issue a new command, for example, when the SQ Head pointer advances from this slot in response to receiving the first completion for this write command. In this case, in order to manage the status of processing corresponding to the write command issued by the host 2, the SQ entry information corresponding to the write command is saved in an entry of the lock data list 245.

[0186] Furthermore, the write command stored in the submission queue 242 may be maintained until a second completion for this write command is received. That is, upon receiving the second completion, the host 2 may advance the SQ Head pointer beyond the slot in which the write command is stored. In this case, a pointer indicating an entry in the submission queue 242 is saved in the entry of the lock data list 245 instead of SQ entry information. The write command itself stored in the submission queue 242 is used as the SQ entry information. Note that if the write command is not cleared from the submission queue 242, the SQ Head pointer is not updated, which may make the submission queue 242 more likely to become full, and it may become impossible to issue other commands such as read commands. For this reason, the submission queue 242 may be provided as a submission queue dedicated to issuing write commands.

[0187] With the above write operation, while the memory system 3 writes user data using Delayed Write Completion based on the write command received from the host 2, the host 2 can manage the status of the processing corresponding to the issued write command using the lock data list 245.

[0188] Specifically, when the host 2 sends a write command to the memory system 3, it adds an entry corresponding to the write command to the lock data list 245. The added entry does not include, for example, a completion order or a completion status. Therefore, the host 2 can use the added entry to manage that the first and second completions for the corresponding write command have not been received. In other words, the host 2 can use the added entry to manage that the host 2 has issued (sent) the corresponding write command to the memory system 3 and has not yet received the first completion.

[0189] When the memory system 3 receives a write command from the host 2 and adds a corresponding entry to the write management table 63, it returns a first completion for that write command to the host 2. The host 2 updates the entry in the corresponding lock data list 245 based on the first completion received from the memory system 3. The updated entry may include, for example, the completion order and completion status. Therefore, the host 2 can use the updated entry to manage the state in which the first completion for the corresponding write command has been received but the second completion has not yet been received. In other words, the host 2 can use the updated entry to manage the state in which the memory system 3 has received the corresponding write command.

[0190] Furthermore, when the memory system 3 completes writing of user data corresponding to the write command with Delayed Write Completion, it returns a second completion for the write command to the host 2. Based on the second completion received from the memory system 3, the host 2 deletes the corresponding entry from the lock data list 245. With the entry deleted, the host 2 can terminate management of the corresponding write command.

[0191] Note that the write / trim control unit 122 of the memory system 3 may write user data corresponding to the accepted write command with padding to the NAND flash memory 5 when the time elapsed since accepting the write command exceeds a threshold. Writing user data with padding here means writing data in units of writes, each consisting of user data and padding data. This threshold is based, for example, on the upper limit of the time expected by the host 2 until a second completion for the write command is obtained. The time elapsed since accepting the write command is measured, for example, using the timer 15. More specifically, when the time elapsed since accepting the write command exceeds the threshold, the write / trim control unit 122 transfers the user data corresponding to the accepted write command from the data buffer 241 of the host 2 to the NAND flash memory 5. Then, the write / trim control unit 122 writes the transferred user data with padding to the NAND flash memory 5. This allows the command acceptance unit 121 to notify the host 2 of a second completion for the write command within the time expected by the host 2.

[0192] Here, the operation when the application 233 attempts to write to a locked or write-protected storage area of ​​the data buffer 241 will be described. A locked or write-protected storage area may store data other than the user data 71 used by the application 223 or the like. Furthermore, the storage area storing the user data 71 may itself be rewritten after the IO receiving unit 210 notifies the application 223 or the OS 221 of the completion of the write request. When the application 233 or the OS 211 attempts to write to a locked or write-protected storage area, the write / trim control unit 122 is notified by a function of the OS 221 that a write operation has been performed.

[0193] 18 shows an example of the operation after the application 223 attempts to write to a locked or write-protected storage area. As in the examples shown in FIGS. 12 and 13, each cell in the logical address space 95 and the physical address space 98 represents a logical page and a physical page, respectively. Furthermore, user data 71 is logically stored in a logical page 971. User data 71 is physically stored in a physical page 981. Because the logical page 971 is mapped to the physical page 981, the user data 71 physically stored in the physical page 981 is logically stored in the logical page 971. Here, it is assumed that the application 233 or the OS 221 attempts to write to the locked or write-protected logical page 971, and the write / trim control unit 122 is notified of the write operation.

[0194] Upon receiving the notification, the write / trim control unit 122 maps the physical page 981 to the free logical page 961 in the kernel memory space 96 ((1) in FIG. 18). The write / trim control unit 122 itself does not need to read or write the logical page 961 that includes this user data 71. However, if this mapping is not performed, the mapping between the physical page 981 and the logical page 971 will be released in a subsequent operation, and the OS 211 (more specifically, the MMU) will no longer be able to recognize that the physical page 981 is in use. The reason for mapping the physical page 981 to the free logical page 961 in the kernel memory space 96 is to make the OS 221 aware that the physical page 981 is in use and to prevent the OS 221 from using the physical page 981 for another purpose; therefore, if this can be achieved by another method, this mapping need not be performed.

[0195] This mapping moves the location of the user data 71 in the logical address space 95 from the logical page 971 to the logical page 961 .

[0196] The write / trim control unit 122 copies the user data 71 stored in the physical page 981 to an unused physical page 982 in the NVRAM 24 ((2) in FIG. 18). The write / trim control unit 122 changes the mapping destination of the logical page 971 to this copy destination physical page 982 ((3) in FIG. 18). The logical page 971 mapped to the copy destination physical page 982 is set to be writable ((4) in FIG. 18).

[0197] After this interrupt processing is completed, the write / trim control unit 122 returns control to the application 223 or OS 221 that issued the write request, and the write that caused the interrupt continues normally. That is, the new write is executed to the physical page 982 of the copy destination. This allows the application 223 or OS 221 to continue operating. The application 223 or OS 221 that issued the write request does not perceive that an interrupt has occurred. Therefore, the application 223 or OS 221 that issued the write request simply perceives it as if the response to the write request has been delayed.

[0198] At this time, if the lock data list 245 also uses logical addresses for access within the host 2, the logical page containing the user data 71 has changed from logical page 971 to logical page 961, and the lock data list 245 must be modified accordingly. If the physical page 981 is not mapped to the logical page 961, the lock data list 245 must be modified accordingly.

[0199] On the other hand, the memory system 3 accesses the memory of the host 2 using only addresses in the physical address space 98. Because the physical addresses where the user data 71 are stored remain unchanged, the memory system 3 can continue to access the user data 71 in the source physical page 981.

[0200] After receiving the second completion, the physical page 981 of the copy source separated from the user memory space 97 is released from mapping with the logical page 961 of the kernel memory space 96 and is released.

[0201] A method in which a common memory area is shared by multiple entities, and when one of the entities makes a write request to that memory area, the data stored in that memory area is copied to another memory area and the write request is executed in the copied area is generally called copy-on-write. Copy-on-write can minimize the occurrence of copying and the increase in memory area used.

[0202] In conventional copy-on-write, multiple applications, each with its own independent virtual memory space, share a physical memory area in which the same data is stored. When one application makes a write request to a physical memory area, a separate physical memory area is allocated to that application, and the data in the shared physical memory area is copied to the newly allocated physical memory area. This separate physical memory area is then mapped into the virtual memory space of that application.

[0203] In copy-on-write of this embodiment, a storage area on the data buffer 241 is shared between the memory system 3, which is an external device of the host 2, and the application 223, etc. The memory system 3 accesses the storage area on the data buffer 241 using a physical address rather than a logical address. The memory system 3 does not write to this storage area, while the application 223, etc. does write to this storage area. Then, in response to a write request from the application 223, etc., a copy-on-write operation is performed on that storage area. This differs from conventional copy-on-write.

[0204] (Second example of a write operation) In the first example of the write operation described above, when a request is received to write user data 71 to the NAND flash memory 5, the host 2 issues one write command, and the memory system 3 responds with two completions to the write command. In contrast, in the second example of the write operation, when a request is received to write user data 71 to the NAND flash memory 5, the host 2 sends two write commands, and the memory system 3 responds with two completions to each of the two write commands.

[0205] Specifically, when a write request to write user data 71 to the NAND flash memory 5 is received, the command issuing unit 211 of the host 2 issues a first write command. The memory system 3 accepts the first write command and returns a first completion to the host 2. The host 2 receives the first completion and issues a second write command. Then, the memory system 3 accepts the second write command and returns a second completion to the host 2 after completing the process of writing the user data 71 to the NAND flash memory 5. Both the first write command and the second write command are commands for writing the user data 71 to the NAND flash memory 5. After accepting the first write command and the second write command, the memory system 3 performs a process of writing the user data 71 to the NAND flash memory 5.

[0206] In the second example of the write operation, the operations from when the host 2 issues the first write command to when the memory system 3 returns the first completion to the host 2 are the same as those in the first example of the write operation described above with reference to Figure 11.

[0207] FIG. 19 shows a write operation following FIG. 11 in the second example of the write operation.

[0208] The command issuing unit 211 of the host 2 receives the first completion for the first write command from the memory system 3, updates the corresponding entry in the lock data list 245, and then issues a second write command and stores it in the submission queue 242 ((1) in FIG. 19). The second write command is, for example, a write command requesting writing the same content as the first write command. The second write command includes information (for example, a command ID) that indicates the corresponding first write command.

[0209] The command reception unit 121 of the memory system 3 acquires the second write command from the submission queue 242 ((2) in FIG. 19). Then, the command reception unit 121 sends the acquired second write command to the write / trim control unit 122 ((3) in FIG. 19).

[0210] The write / trim control unit 122 updates the write management table 63 using the second write command sent by the command reception unit 121 ((4) in FIG. 19 ). Specifically, the write / trim control unit 122 identifies an entry in the write management table 63 that corresponds to the first write command. To identify the entry, for example, information indicating the first write command included in the second write command is used. The write / trim control unit 122 updates the identified entry to indicate that the second write command has been received. In addition to the configuration described above with reference to FIG. 10 , each entry in the write management table 63 is further provided with a field indicating, for example, whether the first write command or the second write command has been received. The write / trim control unit 122 further updates the command ID in the write management table 63 to the value of the command ID of the second write command. It can be said that the entry indicating that the second write command has been received corresponds to a set of the first and second write commands. Hereinafter, the set of the first write command and the second write command will also be simply referred to as a set of write commands.

[0211] Here, it is assumed that the total amount of user data 71 requested to be written by a set of write commands corresponding to a plurality of entries in the write management table 63, each of which indicates that a second write command has been received, has reached a specific data unit. The specific data unit is, for example, the amount of data that can be written to the NAND flash memory 5 in one data write operation.

[0212] After the total amount of user data 71 requested to be written by a set of multiple write commands received from the host 2 reaches a specific data unit, the command reception unit 121 and the write / trim control unit 122 write the specific data unit of user data 71 to the NAND flash memory 5 and return second completions corresponding to each of the multiple sets of write commands (more specifically, multiple second write commands) to the host 2. In other words, the command reception unit 121 and the write / trim control unit 122 do not immediately execute writing according to one received set of write commands, but operate using a mechanism (Delayed Write Completion) that executes writing according to the multiple sets of write commands after the total amount of user data 71 requested to be written by the multiple sets of write commands reaches a specific data unit.

[0213] Specifically, the write / trim control unit 122 transfers the user data 71 in units of writes from the data buffer 241 to the NAND flash memory 5, and writes the transferred user data 71 in units of writes to the NAND flash memory 5 ((5) in FIG. 19). Then, when there is a set of write commands that has made it possible to read all of the corresponding user data 71 from the NAND flash memory 5, the write / trim control unit 122 notifies the command reception unit 121 of the completion of processing corresponding to the set of write commands ((6) in FIG. 19). The write / trim control unit 122 notifies the command reception unit 121 of the completion of processing corresponding to each of the sets of multiple write commands corresponding to the user data 71 in units of writes. The write / trim control unit 122 deletes entries corresponding to each of the sets of multiple write commands from the write management table 63 ((7) in FIG. 19). The write / trim control unit 122 updates the logical-physical address conversion table 62 based on the processing corresponding to each set of multiple write commands ((8) in FIG. 19). Specifically, the write / trim control unit 122 updates the logical-physical address conversion table 62 so as to associate the LBA specified in each set of multiple write commands with the physical storage location where the corresponding user data 71 is written. In addition, the write / trim control unit 122 adds the command ID corresponding to each set of multiple write commands to the command log 51 ((9) in FIG. 19).

[0214] Every time the command reception unit 121 receives a notification from the write / trim control unit 122, it sends a second completion indicating that processing according to the corresponding set of write commands has been completed to the host 2 ((10) in FIG. 19). More specifically, in response to the notification from the write / trim control unit 122, the command reception unit 121 stores a completion (second completion) for the second write command that constitutes the corresponding set of write commands in the completion queue 243. The notification from the write / trim control unit 122 includes, for example, the command ID of the set of write commands for which processing has been completed.

[0215] If an error occurs in the processing according to the set of write commands, the command reception unit 121 sends a completion indicating the error to the host 2 as a second completion.

[0216] Next, the command issuing unit 211 of the host 2 acquires the second completion from the completion queue 243 ((11) in FIG. 19). Then, the command issuing unit 211 sends the acquired second completion to the write / trim management unit 212 ((12) in FIG. 19).

[0217] The write / trim management unit 212 receives the second completion from the command issuing unit 211 and unlocks the user data 71 in the data buffer 241 that corresponds to the received second completion ((13) in FIG. 19). Then, the write / trim management unit 212 deletes the entry that corresponds to the received second completion from the locked data list 245 ((14) in FIG. 19). That is, in response to the second completion, the write / trim management unit 212 and the IO receiving unit 210 perform an entry deletion operation for the corresponding write command.

[0218] If the second completion indicates an error, the host 2 (specifically, the command issuing unit 211, the write / trim management unit 212, and the IO receiving unit 210) considers this to be a failure in the memory system 3. The write / trim management unit 212 stops processing the memory system 3, and performs abnormality processing as the information processing system 1.

[0219] In the above description, only the user data for which the second write command has been accepted is the target for writing to the NAND flash memory 5, but the command acceptance unit 121 and the write / trim control unit 122 may write the user data for which only the first write command has been accepted to the NAND flash memory 5. This allows the command acceptance unit 121 and the write / trim control unit 122 to write the user data to the NAND flash memory 5 before accepting the second write command. In this case, the command acceptance unit 121 sends a second completion to the host 2 in response to accepting the second write command. Therefore, the write management table 63 needs a field indicating that writing of the user data to the NAND flash memory 5 has been completed, in addition to a field indicating whether the second write command has been accepted. The command reception unit 121 and the write / trim control unit 122 refer to the entry in the write management table 63 corresponding to the second write command received, and if the user data has already been written to the NAND flash memory 5, they immediately return a completion to the host 2 and delete the entry from the write management table 63.

[0220] As in the second example of the write operation described above, when the information processing system 1 receives a request to write user data 71 to the NAND flash memory 5, the host 2 may issue two write commands, and the memory system 3 may respond with two completions for each of the two write commands. The memory system 3 accepts a set of write commands consisting of two write commands. While the memory system 3 is writing user data using Delayed Write Completion based on the set of write commands accepted from the host 2, the host 2 can manage the status of the processing corresponding to the issued write commands using the lock data list 245.

[0221] The following describes an example of the operation of an information processing system 1 configured such that, when a request to write user data 71 to the NAND flash memory 5 is received, the host 2 issues one write command and the memory system 3 responds with a first completion and a second completion for that one write command. Note that the same operation can also be achieved in an information processing system 1 configured such that, when a request to write user data 71 to the NAND flash memory 5 is received, the host 2 issues two write commands and the memory system 3 responds with two completions for each of the two write commands.

[0222] As described above, the host 2 issues a write command corresponding to a write request from the application 223 or OS 221 to the memory system 3. Below, a case will be described in which, before the processing corresponding to the issued write command is completed (i.e., before the non-volatilization of the user data corresponding to the write command is completed), another write request or trim request for the LBA specified in the write command is further generated from the application 223 or OS 221. Note that a write request or trim request is also referred to as a write / trim request.

[0223] For example, if a write command corresponding to a further generated write request is issued, in the memory system 3, user data is written to one LBA in response to the previously issued write command, and then user data is written in response to the later issued write command. That is, the user data written in response to the previously issued write command is invalidated. That is, even though the data will be immediately invalidated, writing to that LBA in response to the earlier write command is still performed. This wears out the NAND flash memory 5 of the memory system 3.

[0224] Furthermore, for example, if a trim command corresponding to a further generated trim request is issued, in the memory system 3, user data is written to one LBA in response to the previously issued write command, and then the allocation of that LBA is deallocated in response to the later issued trim command. That is, the user data written in response to the previously issued write command is invalidated. That is, even though the data will be immediately invalidated, writing to that LBA in response to the previous write command is still performed. This wears out the NAND flash memory 5 of the memory system 3.

[0225] Therefore, in this embodiment, if a write request to an LBA specified in an issued write command is generated from the application 223 or the OS 221 before the processing corresponding to that write command is completed, the write corresponding to that write command to the LBA specified in the generated write request is canceled. This prevents overwriting of the LBA specified in the same way, thereby reducing wear on the NAND flash memory 5.

[0226] Furthermore, in this embodiment, if a trim request for an LBA specified in an issued write command is generated from the application 223 or the OS 221 before the processing corresponding to that write command is completed, the write corresponding to that write command and the LBA specified in the generated trim request are canceled. This prevents writing to the LBA specified in the same way, thereby reducing wear on the NAND flash memory 5.

[0227] Hereinafter, a write command that has been issued from the host 2 to the memory system 3 and for which processing in the memory system 3 according to the write command has not been completed will also be referred to as an issued but incomplete write command.

[0228] If a write / trim request for the LBA specified in an issued write command is further generated by application 223 or OS 221 before processing according to that write command is completed, the following cases may occur: (1) the LBA range specified in the subsequently generated write / trim request completely includes the LBA range specified in the issued but incomplete write command, and (2) the LBA range specified in the subsequently generated write / trim request includes a portion of the LBA range specified in the issued but incomplete write command.

[0229] The write / trim management unit 212 of the host 2 uses the lock data list 245 to determine whether there is an issued but incomplete write command (hereinafter also referred to as an overlapping write command) that specifies an LBA range that at least partially overlaps with the LBA range specified in a later-generated write / trim request. If there is an overlapping write command, the write / trim management unit 212 also determines the overlapping relationship between the LBA range specified in the later-generated write / trim request and the LBA range specified in the overlapping write command. An overlapping relationship means, for example, that the LBA range specified in the later-generated write / trim request completely includes the LBA range specified in the overlapping write command, or that the LBA range specified in the later-generated write / trim request includes a portion of the LBA range specified in the overlapping write command.

[0230] In order to efficiently search for an entry for a duplicate write command from the lock data list 245, the lock data list 245 may have a data structure other than a simple table structure. For example, a lock data list 245 may be generated for each of a plurality of partial spaces into which the entire LBA space for accessing the memory system 3 is divided. By using the lock data list 245 corresponding to the partial space including the LBA range specified in a write / trim request generated later, the search for the entry for the duplicate write command can be speeded up.

[0231] Below, we will explain the operation of the host 2 and the memory system 3 in each of the following cases: (1) when the LBA range specified in a later-generated write / trim request completely includes the LBA range specified in the issued but incomplete write command, and (2) when the LBA range specified in a later-generated write / trim request includes a portion of the LBA range specified in the issued but incomplete write command.

[0232] ((1) The LBA range specified in the subsequently generated write / trim request completely includes the LBA range specified in the issued but incomplete write command.) FIG. 20 shows an example of write / trim requests #2a-#2d that specify an LBA range that completely includes the LBA range specified in an issued but incomplete write command #1. The "X" shown in FIG. 20 represents the LBA specified in the corresponding write command #1. The "W" shown in FIG. 20 represents the LBA specified in the corresponding write / trim requests #2a-#2d. The LBA specified in the write command indicates the sector to which user data should be written. The LBA specified in the write request indicates the sector to which user data should be written. The LBA specified in the trim request indicates the sector to which allocation should be deallocated. The LBA range specified in each of write / trim requests #2a, #2b, #2c, and #2d is the LBA range to be written or trimmed in accordance with the write / trim request (more specifically, the corresponding write command or trim command).

[0233] Specifically, write command #1 specifies an LBA range from LBA x+1 to LBA x+2. The LBA range specified by write command #1 is an LBA range in which nonvolatilization of user data according to write command #1 has not yet been completed.

[0234] Write / Trim request #2a specifies an LBA range from LBA x+1 to LBA x+2. Write / Trim request #2b specifies an LBA range from LBA x to LBA x+2. Write / Trim request #2c specifies an LBA range from LBA x+1 to LBA x+3. Write / Trim request #2d specifies an LBA range from LBA x to LBA x+3.

[0235] In this way, the LBA ranges specified in each of write / trim requests #2a, #2b, #2c, and #2d completely include the LBA range specified in write command #1. Therefore, the user data written in response to write command #1 becomes invalid in response to the write commands corresponding to write / trim requests #2a, #2b, #2c, and #2d, respectively, or in response to the trim commands corresponding to write / trim requests #2a, #2b, #2c, and #2d, respectively. By canceling such writing in response to write command #1, wear on the NAND flash memory 5 in the memory system 3 can be reduced. The write command (write command #1 in this case) that writes user data that becomes invalid in response to a later-generated write / trim request (more specifically, the corresponding write command or trim command) is a duplicate write command.

[0236] (Operation in response to a write request that completely includes the LBA range specified in an issued but incomplete write command) 21 and 22, the operation will be described when the LBA range specified in a subsequently generated write request completely includes the LBA range specified in the issued but incomplete write command.

[0237] 21 shows an example of an operation in response to a write request that specifies an LBA range that completely includes the LBA range specified in an issued but incomplete write command. The operation shown in FIG. 21 is performed, for example, after the write operation described above with reference to FIG. 11. The issued but incomplete write command is referred to as a first write command. A write request that specifies an LBA range that completely includes the LBA range specified in the first write command is referred to as a second write request. User data to be written in response to the first write command is referred to as first user data 711. Furthermore, user data requested to be written by the second write request is referred to as second user data 712. The first user data 711 and second user data 712 are stored in the data buffer 241.

[0238] First, in the host 2, the IO reception unit 210 receives a second write request from the application 223 or the OS 221 ((1) in FIG. 21). The IO reception unit 210 sends the received second write request to the write / trim management unit 212 ((2) in FIG. 21).

[0239] If the write / trim management unit 212 has not received the first completion for the first write command, it waits for the first completion for the first write command. In the memory system 3, accepted write commands and trim commands may be executed out of order. Therefore, when multiple writes or trims are performed on one LBA, the host 2 must control the memory system 3 in accordance with the order in which the write requests or trim requests were generated by the application 223 or the OS 221. Specifically, the host 2 must control the memory system 3 so that the content corresponding to the most recently generated write request or trim request is ultimately reflected in the NAND flash memory 5 of the memory system 3. Therefore, the command issue unit 211 and the write / trim management unit 212 wait for the first completion for the first write command and then perform an operation according to the second write request. Note that the following describes an example in which the first completion for the first write command is a normal response (i.e., a completion indicating normal termination). If the first completion to the first write command is an abnormal response (i.e., a completion indicating an abnormal end), the write operation described above with reference to FIGS. 11 to 18 is performed in response to the second write request.

[0240] In parallel with the operation of waiting for the first completion for the first write command, the write / trim manager 212 locks the second user data 712 ((3) in FIG. 21).

[0241] After receiving the first completion of a normal response to the first write command, the write / trim management unit 212 requests the command issuing unit 211 to issue a write command corresponding to the second write request (hereinafter referred to as the second write command) ((4) in FIG. 21). In response to the request from the write / trim management unit 212, the command issuing unit 211 issues a second write command for writing the second user data 712. In other words, the command issuing unit 211 generates SQ entry information corresponding to the second write command for writing the second user data 712. The command issuing unit 211 sends the generated SQ entry information to the write / trim management unit 212 ((5) in FIG. 21).

[0242] The write / trim management unit 212 generates an entry for the lock data list 245 using the SQ entry information sent by the command issuer 211. The generated entry is referred to as a second entry. The second entry includes, for example, SQ entry information corresponding to the second write command and data area management information. This data area management information is information that can identify the storage area in the data buffer 241 where the second user data 712 is stored. The write / trim management unit 212 adds the second entry to the lock data list 245 ((6) in FIG. 21).

[0243] Then, the command issuing unit 211 stores the second write command (SQ entry information) in the submission queue 242 ((7) in FIG. 21).

[0244] The subsequent operations in the memory system 3 in response to the second write command ((8) to (12) in FIG. 21) are the same as the operations in the memory system 3 described above with reference to FIG. 11 ((8) to (12) in FIG. 11). In addition, the operations in the host 2 in response to the first completion for the second write command ((13) to (17) in FIG. 21) are the same as the operations in the host 2 described above with reference to FIG. 11 ((13) to (15), (18) and (19) in FIG. 11).

[0245] Next, if the first completion in response to the second write command is a normal response, the information processing system 1 performs an operation to stop the first write command (an abort operation).

[0246] FIG. 22 shows the abort operation that follows FIG.

[0247] First, the command issuing unit 211 issues an abort command for aborting the first write command. That is, the command issuing unit 211 generates SQ entry information corresponding to the abort command for aborting the first write command. The issued abort command includes information (for example, a command ID) that can identify the first write command to be aborted. Then, the command issuing unit 211 stores the issued abort command (SQ entry information) in the submission queue 242 ((1) in FIG. 22).

[0248] Next, the command reception unit 121 of the memory system 3 acquires the abort command from the submission queue 242 ((2) in FIG. 22). Then, the command reception unit 121 sends the acquired abort command to the write / trim control unit 122 ((3) in FIG. 22).

[0249] The write / trim control unit 122 updates the write management table 63 using the abort command sent by the command reception unit 121 ((4) in FIG. 22). Specifically, the write / trim control unit 122 identifies a corresponding entry in the write management table 63 using the command ID of the first write command specified in the abort command. If a write operation based on the identified entry has not started, the write / trim control unit 122 deletes this entry from the write management table 63. This causes the writing in response to the first write command to be aborted. The write / trim control unit 122 notifies the command reception unit 121 that the first write command in response to the abort command has been successfully aborted (abort successful) ((5) in FIG. 22).

[0250] If the write operation based on the identified entry has already started, the write / trim control unit 122 notifies the command reception unit 121 that the abort of the first write command in response to the abort command has failed (abort failure) ((5) in FIG. 22). In other words, the write / trim control unit 122 refuses to abort the first write command in response to the abort command. Also, if there is no entry in the write management table 63 that corresponds to the command ID of the first write command, the write / trim control unit 122 notifies the command reception unit 121 of the abort failure ((5) in FIG. 22).

[0251] In response to the notification from the write / trim control unit 122, the command reception unit 121 stores a completion for the abort command in the completion queue 243 ((6) in FIG. 22). Specifically, when the write / trim control unit 122 notifies the command reception unit 121 that the abort is successful, the command reception unit 121 stores a completion indicating that the abort is successful (i.e., normal completion) in the completion queue 243. When the write / trim control unit 122 notifies the command reception unit 121 that the abort is unsuccessful, the command reception unit 121 stores a completion indicating that the abort is unsuccessful (i.e., abnormal completion) in the completion queue 243.

[0252] Next, the command issuing unit 211 of the host 2 acquires a completion for the abort command from the completion queue 243 ((7) in FIG. 22). Then, the command issuing unit 211 sends the acquired completion to the write / trim management unit 212 ((8) in FIG. 22).

[0253] If the completion indicates a successful abort, the first write command has been canceled, and so the write / trim management unit 212 unlocks the first user data 711 in the data buffer 241 that was to be written in response to the first write command ((9) in FIG. 22). Furthermore, if the write / trim management unit 212 has created a list of PRP entries or the second or subsequent segment of the SGL, it also releases the area of ​​the pointer list 244 in which these are stored. Then, the write / trim management unit 212 deletes the first entry corresponding to the first write command from the lock data list 245 ((10) in FIG. 22). That is, the write / trim management unit 212 and the IO reception unit 210 perform an entry deletion operation for the first write command.

[0254] If the completion indicates an abort failure, the first write command has not been stopped, and the write operation according to the first write command continues. In other words, the write / trim manager 212 does not unlock the first user data 711 in the data buffer 241, and does not delete the first entry from the locked data list 245.

[0255] Fig. 23 shows an example of the lock data list 245 from which an entry is deleted by the operation (10) in Fig. 22. The lock data list 245 includes an entry 81 corresponding to the first write command and an entry 82 corresponding to the second write command.

[0256] Entry 81 is an entry indicating that the first completion for the first write command has been received, similar to entry 81 shown in Fig. 17. Entry 81 is deleted in response to receiving a completion from memory system 3 indicating that the first write command has been successfully aborted.

[0257] Entry 82 includes SQ entry information “sqentry_info2,” completion order “cseq2,” data region management information “region_info2,” and completion status “completed.” Entry 82 is an entry indicating that the first completion for the second write command has been received.

[0258] As a result of the above write and abort operations, if the LBA range specified in the second write request generated later completely includes the LBA range specified in the first write command that has been issued but not yet completed, the write in response to the first write command in the memory system 3 can be aborted.

[0259] Specifically, the host 2 transmits a second write command corresponding to the second write request to the memory system 3. When the host 2 receives a first completion indicating successful completion for the second write command from the memory system 3, the host 2 transmits an abort command to the memory system 3 to stop the first write command.

[0260] The memory system 3 receives an abort command from the host 2, and if writing in response to the first write command has not started, it aborts the first write command. Then, the memory system 3 returns a completion indicating successful abort of the first write command to the host 2. The host 2 performs an entry deletion operation for the first write command based on the completion indicating successful abort.

[0261] As a result, in the memory system 3, writing to the NAND flash memory 5 in response to the first write command is not performed. In other words, writing to the LBA range that is to be overwritten by the second write request is not performed. Therefore, wear on the NAND flash memory 5 can be reduced.

[0262] Here, a case will be described in which the second example of the write operation described above is used, that is, when a request to write user data 71 to the NAND flash memory 5 is received, the command issuing unit 211 of the host 2 sends a write command twice, and the memory system 3 responds with two completions for each of the two write commands. In this case, if the host 2 has not received the first completion for the first first write command, or if the host 2 has received the first completion for the first first write command but has not yet sent a second first write command to the memory system 3, the host 2 does not send the second first write command to the memory system 3. Furthermore, the host 2 may send an abort command to the memory system 3 to erase information (e.g., an entry in the write management table 63) generated within the memory system 3 in response to the first first write command. This abort command is a command for the completed first first write command. In other words, this abort command is not a conventional abort command that interrupts an operation requested by a certain command, but a new type of abort command that erases information generated in response to the first first write command. This allows the writing in response to the first write command to be stopped, just as in the case of successful abort in Figure 22 described above. Note that if the host 2 does not send an abort command, the host 2 deletes the corresponding entry for the first write command in the lock data list 245 when the second second write command is completed. Furthermore, the memory system 3 deletes the entry for the first write command in the write management table 63 when the second write command is completed.

[0263] If the second first write command has already been sent to the memory system 3, the host 2 sends an abort command to stop the second first write command to the memory system 3. This can stop the writing in response to the first write command.

[0264] (Operation in response to a trim request that completely includes the LBA range specified in an issued but incomplete write command) The same operation can be achieved when the second write request described above is replaced with a trim request. That is, even if the LBA range specified in a subsequently generated trim request completely includes the LBA range specified in the issued but incomplete first write command, the first write command can be aborted in the same manner.

[0265] 24 and 25, the operation when the LBA range specified in a subsequently generated trim request completely includes the LBA range specified in the issued but incomplete write command will be described.

[0266] FIG. 24 shows an example of an operation in response to a trim request that specifies an LBA range that completely includes the LBA range specified by an issued but incomplete write command. The operation shown in FIG. 24 is performed, for example, after the write operation described above with reference to FIG. 11. The issued but incomplete write command is referred to as a first write command. User data to be written in response to the first write command is referred to as first user data 711. The trim request specifies one or more LBA ranges that completely include the LBA range specified by the first write command. Range information 72 is information that indicates one or more LBA ranges specified in the trim request. The first user data 711 and range information 72 are stored in the data buffer 241.

[0267] First, in the host 2, the IO reception unit 210 receives a trim request from the application 223 or the OS 221 ((1) in FIG. 24). The IO reception unit 210 sends the received trim request to the write / trim management unit 212 ((2) in FIG. 24).

[0268] If the write / trim manager 212 has not received the first completion for the first write command, it waits for the first completion for the first write command to be received. Note that the following describes an example in which the first completion for the first write command is a normal response.

[0269] In parallel with the operation of waiting for the first completion for the first write command, the write / trim manager 212 locks the range information 72 ((3) in FIG. 24).

[0270] After receiving the first completion of a normal response to the first write command, the write / trim management unit 212 requests the command issuing unit 211 to issue a trim command corresponding to the trim request ((4) in FIG. 24). In response to the request from the write / trim management unit 212, the command issuing unit 211 issues a trim command for deallocating the LBA range based on the range information 72. In other words, the command issuing unit 211 generates SQ entry information equivalent to the trim command for deallocating the LBA range based on the range information 72. The command issuing unit 211 sends the generated SQ entry information to the write / trim management unit 212 ((5) in FIG. 24).

[0271] The write / trim management unit 212 generates an entry for the lock data list 245 using the SQ entry information sent by the command issuer 211. The generated entry is referred to as a third entry. The third entry includes, for example, SQ entry information corresponding to the issued trim command and data area management information. This data area management information is information that can identify the storage area in the data buffer 241 where the range information 72 is stored. The write / trim management unit 212 adds the third entry to the lock data list 245 ((6) in FIG. 24).

[0272] Then, the command issuing unit 211 stores the issued trim command (SQ entry information) in the submission queue 242 ((7) in FIG. 24).

[0273] The command reception unit 121 of the memory system 3 acquires the trim command from the submission queue 242 ((8) in FIG. 24). Then, the command reception unit 121 sends the acquired trim command to the write / trim control unit 122 ((9) in FIG. 24).

[0274] The write / trim control unit 122 confirms that the trim command sent by the command reception unit 121 is an executable command. Specifically, the write / trim control unit 122 confirms, for example, that the data pointer is valid and that the LBA range specified in the range information 72 is valid. If the trim command is an executable command, the write / trim control unit 122 notifies the command reception unit 121 that reception of the trim command has been completed ((10) in FIG. 24).

[0275] In response to the notification from the write / trim control unit 122, the command reception unit 121 stores the first completion for the trim command (a completion indicating a successful completion) in the completion queue 243 ((11) in FIG. 24). This first completion includes the command ID of the trim command.

[0276] If the trim command acquired from the submission queue 242 is an unexecutable command, the command receiving unit 121 may store a completion indicating an abnormal end in the completion queue 243 as the first completion.

[0277] Next, the command issuing unit 211 of the host 2 acquires the first completion for the trim command from the completion queue 243 ((12) in FIG. 24). Then, the command issuing unit 211 sends the acquired first completion to the write / trim management unit 212 ((13) in FIG. 24).

[0278] If the first completion indicates a normal end, the write / trim management unit 212 updates the third entry corresponding to the trim command in the lock data list 245 ((14) in FIG. 24). More specifically, the write / trim management unit 212 adds, to the third entry, the assigned sequence number (i.e., information indicating the order in which the first completion was received) and information indicating that the first completion has been received. The write / trim management unit 212 notifies the IO reception unit 210 of the completion of the trim (normal end) ((15) in FIG. 24). Then, the IO reception unit 210 notifies the application 223 or the OS 221 of the completion of the trim ((16) in FIG. 24).

[0279] If the first completion indicates an abnormal termination, the write / trim management unit 212 unlocks the range information 72 in the data buffer 241 corresponding to the trim command ((17) in FIG. 24). Then, the write / trim management unit 212 deletes the third entry corresponding to the trim command from the locked data list 245 ((18) in FIG. 24). The write / trim management unit 212 notifies the IO reception unit 210 of the abnormal termination ((19) in FIG. 24). Then, the IO reception unit 210 notifies the application 223 or the OS 221 of the abnormal termination ((20) in FIG. 24).

[0280] If the first completion to the trim command is a normal response, the host 2 and memory system 3 further perform an operation to abort the first write command (abort operation). This abort operation is similar to the abort operation described above with reference to FIG.

[0281] As described above, the host 2 begins operation to cancel the first write command after receiving the first completion indicating the successful completion of the trim command. This is because, for example, if the LBA range specified by the trim command is write-protected due to security settings after the first completion of the first write command is successful but before the trim command is sent, the trim command will not be successful and the first write command must be completed successfully. Except for cases where the first completion for the trim command cannot be received due to a failure of the memory system 3, etc., in other words, when it is guaranteed that the first completion indicating the successful completion of the trim command will be received, the host 2 may begin operation to cancel the first write command before receiving the first completion indicating the successful completion of the trim command.

[0282] Furthermore, in the host 2 and memory system 3, an operation is performed to deallocate the specified LBA range in response to the trim command received in the memory system 3.

[0283] Fig. 25 shows an example of an operation in response to a trim command received in the memory system 3. The operation shown in Fig. 25 is performed after, for example, a write command preceding the trim command, which specifies an LBA range that overlaps with the LBA range specified in the trim command, is completed or aborted.

[0284] First, the write / trim control unit 122 of the memory system 3 uses the range information 72 corresponding to the trim command to deallocate the LBA range specified in the range information 72 ((1) in FIG. 25). The write / trim control unit 122 updates the logical-physical address conversion table 62 to indicate that the LBA range specified in the range information 72 is not mapped to any physical address, and deallocates the LBA range. Then, the write / trim control unit 122 notifies the command reception unit 121 of the completion of processing in accordance with the trim command ((2) in FIG. 25). The write / trim control unit 122 also adds the command ID of the trim command to the command log 51 ((3) in FIG. 25).

[0285] In response to the notification from the write / trim control unit 122, the command reception unit 121 sends a second completion indicating that the processing corresponding to the trim command has been completed to the host 2 ((4) in FIG. 25). More specifically, in response to the notification from the write / trim control unit 122, the command reception unit 121 stores the second completion for the trim command in the completion queue 243. The notification from the write / trim control unit 122 includes, for example, the command ID of the trim command for which processing has been completed.

[0286] If an error occurs in the processing according to the trim command, the command reception unit 121 sends a completion indicating the error to the host 2 as a second completion.

[0287] Next, the command issuing unit 211 of the host 2 acquires the second completion from the completion queue 243 ((5) in FIG. 25). Then, the command issuing unit 211 sends the acquired second completion to the write / trim management unit 212 ((6) in FIG. 25).

[0288] The write / trim management unit 212 receives the second completion from the command issuing unit 211 and unlocks the range information 72 corresponding to the trim command ((7) in FIG. 25). Then, the write / trim management unit 212 deletes the third entry corresponding to the trim command from the lock data list 245 ((8) in FIG. 25).

[0289] If the second completion indicates an error, the host 2 (specifically, the write / trim management unit 212) considers this to be a failure in the memory system 3. The write / trim management unit 212 stops processing the memory system 3 and performs abnormality processing as the information processing system 1.

[0290] As a result of the above trim and abort operations, if the LBA range specified in a subsequently generated trim request completely includes the LBA range specified in the issued but incomplete first write command, writing in response to the first write command in memory system 3 can be aborted.

[0291] Specifically, the host 2 transmits a trim command corresponding to the trim request to the memory system 3. When the host 2 receives a first completion indicating successful completion of the trim command from the memory system 3, the host 2 transmits an abort command to the memory system 3 to abort the first write command.

[0292] The memory system 3 receives an abort command from the host 2, and if writing in response to the first write command has not started, it aborts the first write command. The memory system 3 then returns a completion indicating successful abort of the first write command to the host 2. The host 2 deletes the entry corresponding to the first write command from the lock data list 245 based on the completion indicating successful abort.

[0293] As a result, in the memory system 3, writing to the NAND flash memory 5 in response to the first write command is not performed. In other words, writing to the LBA range that is deallocated by the trim request is not performed. Therefore, wear on the NAND flash memory 5 can be reduced.

[0294] As with the second example of the write operation described above, when the IO reception unit 210 of the host 2 receives a trim request to deallocate an LBA range, the command issuing unit 211 of the host 2 may be configured to issue two trim commands, and the memory system 3 may be configured to respond with two completions for each of the two trim commands. Even in this configuration, if the LBA range specified in a subsequently generated trim request completely includes the LBA range specified in the issued but incomplete first write command, the first write command may be aborted in the same manner.

[0295] Here, a case will be described in which there are multiple issued but incomplete write commands that specify an LBA range that is completely included in the LBA range specified in a subsequently generated write / trim request.

[0296] FIG. 26 shows an example of a write / trim request #2 that specifies an LBA range that completely includes the LBA ranges specified in each of the issued but incomplete write commands #1X and #1Y. "X" shown in FIG. 26 represents the LBA specified in the corresponding write command #1X. "Y" shown in FIG. 26 represents the LBA specified in the corresponding write command #1Y. "W" shown in FIG. 26 represents the LBA specified in the corresponding write / trim request #2. The LBA range specified in write / trim request #2 is the LBA range to be written or trimmed in accordance with this write / trim request (more specifically, the corresponding write command or trim command).

[0297] Specifically, write command #1X specifies the LBA range from LBA x+1 to LBA x+2. The LBA range specified by write command #1X is an LBA range in which nonvolatilization of user data according to write command #1X has not yet been completed.

[0298] Write command #1Y specifies an LBA range from LBA x+4 to LBA x+5. The LBA range specified by write command #1Y is an LBA range in which nonvolatilization of user data according to write command #1Y has not yet been completed.

[0299] Write / Trim request #2 specifies an LBA range from LBA x to LBA x+6.

[0300] In this way, the LBA range specified in write / trim request #2 completely includes the LBA ranges specified in each of the multiple write commands #1X and #1Y.

[0301] If the LBA range specified in a subsequently generated write / trim request completely includes the LBAs specified in multiple write commands that have been issued but are not yet completed, the abort operation described above is performed for each of those multiple write commands.

[0302] ((2) When the LBA range specified in a later generated write / trim request includes part of the LBA range specified in an issued but incomplete write command) If the LBA range specified in a later generated write / trim request includes part of the LBA range specified in the issued but incomplete write command, either (2-a) a method of correcting the issued but incomplete write command or (2-b) a method of canceling the issued but incomplete write command can be used. These two methods will be described below.

[0303] ((2-a) How to correct an issued but incomplete write command) Figure 27 shows an example of write / trim requests #2a and #2b that specify an LBA range that includes part of the LBA range specified in write command #1 that has been issued but not yet completed. "X" shown in Figure 27 represents the LBA specified in the corresponding write command #1. "W" shown in Figure 27 represents the LBA specified in the corresponding write / trim requests #2a and #2b. The LBA range specified in each of write / trim requests #2a and #2b is the LBA range to be written or trimmed in accordance with these write / trim requests (more specifically, the corresponding write command or trim command).

[0304] Specifically, write command #1 specifies an LBA range from LBA x+1 to LBA x+2. The LBA range specified by write command #1 is an LBA range in which nonvolatilization of user data according to write command #1 has not yet been completed.

[0305] Write / trim request #2a specifies an LBA range from LBA x to LBA x+1. The LBA range specified in write / trim request #2a includes a contiguous portion of the LBA range specified in write command #1, from the beginning to the end. Note that the contiguous portion from the beginning to the end may be only the first LBA.

[0306] Write / trim request #2b specifies an LBA range from LBA x+2 to LBA x+3. The LBA range specified in write / trim request #2b includes a contiguous portion of the LBA range specified in write command #1, extending from the end to the beginning. Note that the contiguous portion extending from the end to the beginning may be only the last LBA.

[0307] More specifically, the LBA range from LBA x to x+1 specified in write / trim request #2a includes LBA x+1 (i.e., the sector to be overwritten or trimmed) among LBAs x+1 and x+2 specified in write command #1, but does not include LBA x+2 (i.e., the sector not to be overwritten or trimmed). In other words, LBAs x+1 and x+2 specified in write command #1 include not only LBA x+1 (i.e., the sector to be overwritten or trimmed) among LBAs x and x+1 specified in write / trim request #2a, but also LBA x+2 (i.e., the sector not to be overwritten or trimmed).

[0308] Furthermore, the LBA range from LBA x+2 to x+3 specified in write / trim request #2b includes LBA x+2 (i.e., the sector to be overwritten or trimmed) among LBAs x+1 and x+2 specified in write command #1, but does not include LBA x+1 (i.e., the sector not to be overwritten or trimmed). In other words, LBAs x+1 and x+2 specified in write command #1 include not only LBA x+2 (i.e., the sector to be overwritten or trimmed) among LBAs x+2 and x+3 specified in write / trim request #2b, but also LBA x+1 (i.e., the sector not to be overwritten or trimmed).

[0309] In this way, a write / trim request specifying an LBA range that includes a portion of the LBA range specified by an issued but incomplete write command is, for example, (A) a write / trim request specifying an LBA range that includes a contiguous portion from the beginning to the end of the LBA range specified by the write command, or (B) a write / trim request specifying an LBA range that includes a contiguous portion from the end to the beginning of the LBA range specified by the write command.

[0310] Alternatively, a write / trim request specifying an LBA range that includes part of the LBA range specified in an issued but incomplete write command may be (C) a write / trim request specifying an intermediate LBA range that does not include either the beginning or the end of the LBA range specified in the write command.

[0311] FIG. 28 shows an example of a write / trim request #2 that specifies an intermediate LBA range that does not include the beginning or end of the LBA range specified by the issued but incomplete write command #1.

[0312] Specifically, write command #1 specifies an LBA range from LBA x to LBA x+4. The LBA range specified by write command #1 is an LBA range in which nonvolatilization of user data according to write command #1 has not yet been completed.

[0313] Write / Trim request #2 specifies an LBA range from LBA x+1 to LBA x+2. The LBA range specified in Write / Trim request #2 is the LBA range to be written or trimmed in response to this Write / Trim request (more specifically, the corresponding write command or trim command).

[0314] In this way, the LBA range specified in write / trim request #2 includes a portion of the LBA range specified in write command #1.

[0315] More specifically, LBAs x+1 and x+2 specified in write / trim request #2 include LBAs x+1 and x+2 (i.e., sectors to be overwritten or trimmed) within the LBA range from LBA x to x+4 specified in write command #1, but do not include the first LBA x and the contiguous LBA range from the last LBA x+4 to LBA x+3 (i.e., sectors that will not be overwritten or trimmed). In other words, the LBA range from LBA x to x+4 specified in write command #1 includes not only LBAs x+1 and x+2 (i.e., sectors to be overwritten or trimmed) specified in write / trim request #2, but also LBA x and the LBA range from LBA x+3 to x+4 (i.e., sectors that will not be overwritten or trimmed).

[0316] As shown in Figure 27, the LBA ranges specified in the subsequently generated write / trim requests #2a and #2b each include a portion of the LBA range specified in the issued but incomplete write command #1. As shown in Figure 28, the LBA range specified in the subsequently generated write / trim request #2 includes a portion of the LBA range specified in the issued but incomplete write command #1.

[0317] The operation will be described when the LBA range specified in the write request generated later includes part of the LBA range specified in the write command that has already been issued but is not yet completed.

[0318] Fig. 29 shows an example of an operation performed in response to a write request that specifies an LBA range that includes part of the LBA range specified in an issued but incomplete write command. The operation shown in Fig. 29 is performed, for example, after the write operation described above with reference to Fig. 11.

[0319] 21 , after the host 2 receives a first completion for an issued but incomplete write command (first write command), the host 2 and memory system 3 perform operations in accordance with a write request (hereinafter referred to as a third write request) that specifies an LBA range that includes part of the LBA range specified in the first write command. That is, after the host 2 receives a first completion for a successful response to the first write command, the host 2 sends a write command corresponding to the third write request (hereinafter referred to as a third write command) to the memory system 3 and manages the entry in the lock data list 245 that corresponds to the third write command. The memory system 3 updates the write management table 63 based on the third write command and returns the first completion for the third write command to the host 2. Then, if the first completion for the third write command is a successful response, the host 2 updates the entry in the lock data list 245 that corresponds to the third write command to indicate that the first completion has been received.

[0320] The user data to be written in response to the first write command is referred to as first user data 711. The user data requested to be written by the third write request is referred to as third user data 713. The first user data 711 and the third user data 713 are stored in the data buffer 241.

[0321] The command issuing unit 211 issues a modification command for modifying the first write command. That is, the command issuing unit 211 generates SQ entry information corresponding to the modification command for modifying the first write command. The issued modification command includes information that can identify the first write command to be modified (for example, a command ID) and information that indicates the LBA range in which writing is to be canceled. The LBA range in which writing is to be canceled indicates the overlapping portion between the LBA range specified in the first write command and the LBA range specified in the third write request. The command issuing unit 211 stores the issued modification command (SQ entry information) in the submission queue 242 ((1) in FIG. 29).

[0322] Next, the command reception unit 121 of the memory system 3 acquires the modification command from the submission queue 242 ((2) in FIG. 29). Then, the command reception unit 121 sends the acquired modification command to the write / trim control unit 122 ((3) in FIG. 29).

[0323] The write / trim control unit 122 updates the write management table 63 using the modification command sent by the command reception unit 121 ((4) in FIG. 29). Specifically, the write / trim control unit 122 identifies a corresponding entry in the write management table 63 using the command ID of the first write command specified in the modification command. If a write operation based on the identified entry has not started and the LBA range specified in the modification command is valid (i.e., within the LBA range specified in the first write command), the write / trim control unit 122 updates this entry so that writing to the LBA range specified in the modification command is canceled. More specifically, the write / trim control unit 122 generates modification command data 64 from information indicating the LBA range specified in the modification command. Then, the write / trim control unit 122 registers a pointer to the generated modification command data 64 in the pointer to modification command data field of this entry. As a result, when writing to the NAND flash memory 5 in accordance with the first write command is performed, the write / trim control unit 122 controls, based on the updated entry, so that writing is not performed to the LBA range specified by the modification command within the LBA range specified in the first write command.The write / trim control unit 122 then notifies the command receiving unit 121 that the modification of the first write command in accordance with the modification command has been successful (modification successful) ((5) in FIG. 29).

[0324] In addition, by making the modified command data 64 in the memory system 3 into a list structure, similar to the registration in the modified command data list in the host 2, operations such as (1) adding, (2) modifying, (3) inserting, and (4) deleting the modified command data can be performed.

[0325] If a write operation based on the identified entry has already started, or if the LBA range specified in the modification command is invalid, the write / trim control unit 122 notifies the command reception unit 121 that modification of the first write command in accordance with the modification command has failed (modification failure) ((5) in FIG. 29). In other words, the write / trim control unit 122 rejects modification of the first write command in accordance with the modification command. Also, if there is no entry in the write management table 63 that corresponds to the command ID of the first write command, the write / trim control unit 122 notifies the command reception unit 121 of modification failure ((5) in FIG. 29).

[0326] In response to the notification from the write / trim control unit 122, the command reception unit 121 stores a completion for the correction command in the completion queue 243 ((6) in FIG. 29). Specifically, when the write / trim control unit 122 notifies the command reception unit 121 that the correction was successful, the command reception unit 121 stores a completion indicating that the correction was successful (i.e., normal completion) in the completion queue 243. When the write / trim control unit 122 notifies the command reception unit 121 that the correction was unsuccessful, the command reception unit 121 stores a completion indicating that the correction was unsuccessful (i.e., abnormal completion) in the completion queue 243.

[0327] Next, the command issuing unit 211 of the host 2 acquires a completion for the modified command from the completion queue 243 ((7) in FIG. 29). Then, the command issuing unit 211 sends the acquired completion to the write / trim management unit 212 ((8) in FIG. 29).

[0328] If the completion indicates successful modification, the first write command has been modified, so the write / trim management unit 212 generates modified command data 246 indicating the LBA range specified in the modification command (i.e., the LBA range for which writing was canceled) ((9) in FIG. 29). Then, the write / trim management unit 212 registers a pointer to the generated modified command data 246 in the first entry (more specifically, the pointer field to the modified command data) in the lock data list 245 corresponding to the first write command ((10) in FIG. 29).

[0329] Furthermore, if the third write request is a write request that specifies an LBA range that includes a continuous portion from the beginning to the end of the LBA range specified in the above-mentioned (A) write command, the LBA range specified in the first write command is reduced so as to exclude the continuous portion from the beginning to the end in accordance with the modification. This operation will be explained below for (a) the case where the PRP is used as the data pointer and (b) the case where the SGL is used as the data pointer.

[0330] (a) When PRP is used as a data pointer In this case, the LBA range can be excluded simply by modifying the entry in the lock data list 245. That is, instead of generating modified command data 246 and registering the generated modified command data 246 in the modified command data list of the first entry, the write / trim management unit 212 updates the data pointer information in the SQ entry information of the first entry to indicate the storage location of the user data to be written in the reduced LBA range. Furthermore, the write / trim management unit 212 updates the first LBA of the LBA range in the SQ entry information of the first entry to indicate the reduced LBA range. Note that the write / trim management unit 212 may unlock user data 71 that no longer needs to be written.

[0331] Specifically, if the data pointer in the SQ entry information of the first entry in the lock data list 245 includes the first PRP entry 921 described with reference to Fig. 5(A), the write / trim management unit 212 rewrites the first PRP entry 921 so as to indicate the physical address of the storage area where the start of the user data 71 to be written to the new start LBA is stored. Also, if the data pointer in the SQ entry information of the first entry includes the second PRP entry 922 described with reference to Fig. 5(A), the write / trim management unit 212 rewrites the second PRP entry 922 so as to indicate the physical addresses of multiple storage areas where the user data 71 to be written to the new LBA range is stored.

[0332] In the host 2, the area where the user data 71 is stored may be managed using addresses in the logical address space with the data area management information in the lock data list 245. If the data area information is specified by a start LBA and an end LBA, the write / trim management unit 212 simply changes the start LBA to a new starting address. If the data area information is specified by a start LBA and data length, the write / trim management unit 212 changes both.

[0333] Regardless of whether the area where the user data 71 is stored is managed by physical addresses or logical addresses, the write / trim management unit 212 unlocks the storage area where the user data 71 that no longer needs to be written to the memory system 3 due to the change in the starting address of the LBA range is stored after confirming the successful completion of the modification command. This releases the storage area so that it can be used for another purpose.

[0334] (b) When SGL is used as a data pointer In this case, the data pointer in the SQ entry information of the first entry in the lock data list 245 indicates the address of the SGL segment. Each SGL segment is on the pointer list 244 and is also referenced by the memory system 3. When the first LBA is changed by a modification command, the contents of each SGL segment must also be modified accordingly. However, because each SGL segment is also referenced by the memory system 3, such modification requires a function to lock the storage area in which each SGL segment is stored and a recovery function in the event of an abnormal termination. In other words, modifying an SGL is more complex than modifying a storage area managed only by the host 2 or a storage area managed only by the memory system 3. Therefore, when an SGL is used, it is desirable for the host 2 to use modification command data 246 and for the memory system 3 to use modification command data 64.

[0335] If the third write request is a write / trim request specifying an LBA range including a contiguous portion extending from the end to the beginning of the LBA range specified in the write command (B) described above, the LBA range specified in the first write command is reduced in accordance with the modification so as to exclude the contiguous portion extending from the end to the beginning. In this case, the write / trim management unit 212 may update the number of sectors indicating the LBA range indicated by the SQ entry information in the first entry to indicate the reduced LBA range, instead of generating modified command data 246 and registering the generated modified command data 246 in the modified command data list of the first entry. In this case, the write / trim management unit 212 may unlock the user data 71 that no longer needs to be written.

[0336] If the third write request is either (B) a write / trim request specifying an LBA range that includes a continuous portion of the LBA range specified in the write command from the end to the beginning, or (C) a write / trim request specifying an LBA range that does not include the beginning or end of the LBA range specified in the write command, the beginning of the LBA range specified in the first write command is not changed. Therefore, even if the modified command data 246 is not registered in the modified command data list of the first entry, the write / trim management unit 212 does not need to change the data pointer or the beginning LBA that indicates the storage location of the user data 71 to be written in response to the first write command.

[0337] Furthermore, if the third write request is a write / trim request that specifies an intermediate LBA range that does not include the beginning or end of the LBA range specified in the (C) write command, the LBA range specified in the first write command will be modified to exclude the intermediate LBA range, resulting in two LBA ranges. These two LBA ranges can be identified by the LBA range indicated by the SQ entry information in the first entry and the LBA range indicated by the generated modified command data 246.

[0338] If the completion for the modification command indicates a modification failure, the first write command has not been modified, and the write operation according to the original first write command continues. In other words, the write / trim manager 212 does not generate modified command data 246 corresponding to the modification command, and does not update the first entry in the lock data list 245.

[0339] Fig. 30 shows an example of modified command data 246 generated by operation (9) in Fig. 29. The modified command data 246 includes the starting LBA "LBAx" of the canceled write, the number of sectors "n" whose write was canceled, and a pointer "NULL" to the next modified command data.

[0340] The first LBA of the canceled write indicates the first LBA of the LBA range specified in the modification command (i.e., the LBA range where the write was canceled). The number of sectors where the write was canceled indicates the length of the LBA range specified in the modification command. Therefore, the LBA range specified in the modification command can be obtained from the first LBA of the canceled write, "LBAx," and the number of sectors where the write was canceled, "n."

[0341] The pointer to the next modified command data indicates a pointer to another modified command data 246 that is generated for the first write command. In this case, since the modified command data 246 has not yet been generated, the pointer to the next modified command data is set to "NULL."

[0342] Note that if the LBA range for which writing has been canceled is simply widened by the modification in response to the next modification command for the first write command, the host 2 may update the already stored modification command data 246 to indicate the widened LBA range, instead of generating new modification command data 246. Also, if the modification in response to the next modification command for the first write command does not need to indicate the LBA range for which writing has been canceled and can be expressed as a reduction of the LBA range specified in the first write command, the corresponding modification command data 246 may be deleted, and the LBA range indicated by the SQ entry information in the first entry of the corresponding lock data list 245 may be updated to indicate the reduced LBA range.

[0343] Furthermore, if the writing of the entire LBA range specified in the first write command is canceled as a result of the modifications according to the multiple modification commands, an abort operation (i.e., the abort operation shown in Figure 22) is performed to stop the first write command, similar to the operation when the LBA range specified in the write / trim request generated after (1) above completely includes the LBA range specified in the issued but incomplete write command.

[0344] When an entry in the lock data list 245 corresponding to a write command is deleted, the modified command data 246 associated using a pointer to the modified command data in that entry is also deleted. If a pointer to the next modified command data is set in the associated modified command data 246, the other modified command data 246 associated by that pointer is also deleted. Similarly, all modified command data 246 associated in the list structure using pointers to the entry in the lock data list 245 being deleted are also deleted.

[0345] Figure 31 shows an example of the lock data list 245 in which the entries have been updated by the operation (10) in Figure 29. The lock data list 245 includes an entry 81 corresponding to the first write command and an entry 83 corresponding to the third write command.

[0346] 17, entry 81 is an entry indicating that the first completion for the first write command has already been received. In the pointer to modified command data field of entry 81, a pointer "ptr1" to modified command data 246 is set. This modified command data 246 is modified command data that is generated in response to receiving a completion indicating successful modification of the first write command from the memory system 3.

[0347] Entry 83 includes SQ entry information “sqentry_info3,” completion order “cseq3,” data area management information “region_info3,” and completion status “completed.” Entry 83 is an entry indicating that the first completion for the third write command has been received.

[0348] As a result of the above write and modify operations, if the LBA range specified in the third write request generated later includes part of the LBA range specified in the first write command that has been issued but not yet completed, part of the write in memory system 3 corresponding to the first write command can be canceled.

[0349] Specifically, the host 2 transmits a third write command corresponding to the third write request to the memory system 3. When the host 2 receives a first completion indicating successful completion for the third write command from the memory system 3, the host 2 transmits a correction command to the memory system 3 to correct the first write command.

[0350] The memory system 3 receives the modification command from the host 2, and if writing according to the first write command has not started and the LBA range specified in the modification command is valid, it modifies the first write command. The memory system 3 then returns a completion indicating successful modification of the first write command to the host 2. The host 2 updates the entry in the lock data list 245 corresponding to the first write command in response to the completion indicating successful modification. Specifically, the host 2 generates modified command data 246 in response to, for example, the completion indicating successful modification. The host 2 then registers the generated modified command data 246 in the modified command data list of the entry in the lock data list 245 corresponding to the first write command.

[0351] As a result, in the memory system 3, part of the write to the NAND flash memory 5 in response to the first write command is canceled. In other words, writing to the LBA range that will be overwritten by the third write request is not performed. Therefore, wear on the NAND flash memory 5 can be reduced.

[0352] Here, we will explain a case in which the second example of the write operation described above is used, that is, when the IO receiving unit 210 of the host 2 receives a request to write user data 71 to the NAND flash memory 5, the command issuing unit 211 of the host 2 sends two write commands, and the memory system 3 responds with two completions for each of the two write commands. In this case, if the host 2 has not received the first completion for the first first write command, or if the host 2 has received the first completion for the first first write command but has not yet sent a second first write command to the memory system 3, the host 2 sends a second first write command specifying a reduced LBA range to the memory system 3. This reduced LBA range is an LBA range obtained by excluding the LBA range for which writing should be canceled from the LBA range specified in the first first write command. This makes it possible to cancel part of the writing corresponding to the first write command, as in the case of successful correction in FIG. 29 described above. In this case, the write / trim control unit 122 of the memory system 3 modifies the start LBA, data pointer, and data length of the corresponding entry in the write management table 63. Alternatively, the write / trim control unit 122 may create modified command data 64 and write the pointer to the corresponding entry in the write management table 63.

[0353] If the LBA range specified in the first write command is divided into multiple LBA ranges by excluding the LBA range for which writing should be canceled, the host 2 sends a command indicating the excluded LBA ranges to the memory system 3. For example, this command may have a data structure similar to that of a trim command. The host 2 also creates modified command data 246 and writes a pointer to it in the entry of the lock data list 245 corresponding to the first write command.

[0354] If the second first write command has already been sent to the memory system 3, the host 2 sends a correction command for correcting the first write command to the memory system 3. This can cancel part of the writing corresponding to the first write command.

[0355] Note that a similar operation can be achieved even when the third write request described above is replaced with a trim request. That is, even when the LBA range specified in a subsequently generated trim request includes part of the LBA range specified in the issued but incomplete first write command, the first write command can be modified in a similar manner. In this case, in the operation described above with reference to Figures 21 and 29 to 31, the third write request is replaced with a trim request, and the third write command is replaced with a trim command. Note that the trim operation performed by the host 2 and memory system 3 in response to the trim request is as described above with reference to Figures 24 and 25.

[0356] Furthermore, similar to the second example of the write operation described above, when the IO reception unit 210 of the host 2 receives a trim request, the command issuing unit 211 of the host 2 may be configured to issue two trim commands, and the memory system 3 may be configured to respond with two completions for each of the two trim commands. Even in this configuration, if the LBA range specified in the trim request includes part of the LBA range specified in the first write command that has been issued but not yet completed, the first write command can be modified in a similar manner.

[0357] Here, a case will be described in which there are multiple issued but incomplete write commands that specify an LBA range that is partly or entirely included in the LBA range specified in a subsequently generated write / trim request.

[0358] FIG. 32 shows an example of a write / trim request #2a that specifies an LBA range that includes part or all of the LBA ranges specified in each of the issued but incomplete write commands #1X, #1Y, and #1Z. "X" shown in FIG. 32 represents the LBA specified in the corresponding write command #1X. "Y" shown in FIG. 32 represents the LBA specified in the corresponding write command #1Y. "Z" shown in FIG. 32 represents the LBA specified in the corresponding write command #1Z. "W" shown in FIG. 32 represents the LBA specified in the corresponding write / trim request #2a. The LBA range specified in write / trim request #2a is the LBA range to be written or trimmed in accordance with this write / trim request (more specifically, the corresponding write command or trim command).

[0359] Specifically, write command #1X specifies an LBA range from LBA x to LBA x+1. The LBA range specified by write command #1X is an LBA range in which nonvolatilization of user data according to write command #1X has not yet been completed.

[0360] Write command #1Y specifies an LBA range from LBA x+6 to LBA x+7. The LBA range specified by write command #1Y is an LBA range in which nonvolatilization of user data according to write command #1Y has not yet been completed.

[0361] Write command #1Z specifies LBA x+3. The LBA specified in write command #1Z is an LBA for which nonvolatilization of user data according to write command #1Z has not yet been completed.

[0362] Write / Trim request #2a specifies an LBA range from LBA x+1 to LBA x+6.

[0363] In this way, the LBA range specified in write / trim request #2a includes part of the LBA range specified in write command #1X, part of the LBA range specified in write command #1Y, and all of the LBAs specified in write command #1Z. In this case, for example, for write command #1Z, an operation is performed in which the LBA range specified in the write / trim request generated after the above-mentioned (1) completely includes the LBA range specified in the issued but incomplete write command. On the other hand, for write commands #1X and #1Y, an operation is performed using the method (2-a) of correcting the issued but incomplete write command in which the LBA range specified in the write / trim request generated after the above-mentioned (2) includes part of the LBA range specified in the issued but incomplete write command.

[0364] ((2-b) How to cancel an issued but incomplete write command) Next, a method for canceling an issued but incomplete write command will be described. In this method, when a write request is generated that specifies an LBA range that includes part of the LBA range specified in the issued but incomplete write command, the host 2 sends to the memory system 3 a write command for performing a write that combines the write corresponding to that write command with the write corresponding to the generated write request. The host 2 then cancels the issued but incomplete write command. A write command for performing a write that combines the write corresponding to the issued but incomplete write command with the write corresponding to a write request that specifies an LBA range that includes part of the LBA range specified in that write command is also referred to as a combined write command.

[0365] Fig. 33 shows an example of a combined write command #3 that is issued when a write request #2 is generated that specifies an LBA range that includes part of the LBA range specified in an issued but incomplete write command #1. "A" to "B" shown in Fig. 33 represent user data that should be written to the LBA specified in the corresponding write command #1. "C" to "D" shown in Fig. 33 represent user data that should be written to the LBA specified in the corresponding write request #2. In other words, each of the user data A to D represents a specific data string.

[0366] Specifically, write command #1 specifies the LBA range from LBA x+1 to LBA x+2. Write command #1 specifies user data A and B to be written to LBA x+1 and x+2, respectively. The LBA range specified by write command #1 is the LBA range in which the nonvolatilization of user data A and B in accordance with write command #1 has not yet been completed.

[0367] Write request #2 specifies an LBA range from LBA x to LBA x+1. Write request #2 specifies user data C and D to be written to LBA x and x+1, respectively.

[0368] The LBA range specified by write request #2 includes LBA x+1 (i.e., the sector to be overwritten), which is part of the LBA range specified by write command #1, and LBA x (i.e., the sector not to be overwritten), which is outside the LBA range specified by write command #1. In other words, the LBA range specified by write command #1 includes LBA x+1 (i.e., the sector to be overwritten), which is part of the LBA range specified by write request #2, and LBA x+2 (i.e., the sector not to be overwritten), which is outside the LBA range specified by write request #2.

[0369] Combined write command #3 is a write command for performing a write that combines the write corresponding to write command #1 and the write corresponding to write request #2. Combined write command #3 is generated based on user data C, D, and B that should ultimately be written in the LBA range from LBA x to LBA x+2 when the write corresponding to write command #1 is performed followed by the write corresponding to write request #2. Therefore, combined write command #3 specifies the LBA range from LBA x to LBA x+2. The LBA range from LBA x to LBA x+2 includes the LBA range specified in at least one of the LBA range specified in write command #1 and the LBA range specified in write request #2. Furthermore, combined write command #3 is associated with user data C, D, and B that should be written to LBA x, x+1, and x+2, respectively. In the range where write command #1 and write request #2 overlap, the user data of the later write request #2 is written.

[0370] Fig. 34 shows another example of a combined write command #3 that is issued when a write request #2 is generated that specifies an LBA range that includes part of the LBA range specified in an issued but incomplete write command #1. "A" to "E" shown in Fig. 34 represent user data that should be written to the LBA specified in the corresponding write command #1. "F" to "G" shown in Fig. 34 represent user data that should be written to the LBA specified in the corresponding write request #2. In other words, each of the user data A to G represents a specific data string.

[0371] Specifically, write command #1 specifies the LBA range from LBA x to LBA x+4. Write command #1 specifies user data A, B, C, D, and E to be written to LBAs x, x+1, x+2, x+3, and x+4, respectively. The LBA range specified by write command #1 is the LBA range in which the nonvolatilization of user data A, B, C, D, and E in accordance with write command #1 has not yet been completed.

[0372] Write request #2 specifies an LBA range from LBA x+1 to LBA x+2. Write request #2 specifies user data F and G to be written to LBA x+1 and x+2, respectively.

[0373] The LBA range specified in write request #2 includes LBAs x+1 and x+2 (i.e., sectors to be overwritten), which are part of the LBA range specified in write command #1. In other words, the LBA range specified in write command #1 includes LBAs x+1 and x+2 (i.e., sectors to be overwritten), which are part of the LBA range specified in write request #2, and LBAs x, x+3, and x+4 (i.e., sectors not to be overwritten), which are outside the LBA range specified in write request #2.

[0374] Combined write command #3 is a write command for performing a write that combines the write corresponding to write command #1 and the write corresponding to write request #2. Write command #3 is generated based on user data A, F, G, D, and E that should ultimately be written in the LBA range from LBA x to LBA x+4 when the write corresponding to write command #1 is performed followed by the write corresponding to write request #2. Therefore, combined write command #3 specifies the LBA range from LBA x to LBA x+4. The LBA range from LBA x to LBA x+4 includes the LBA range specified in at least one of the LBA range specified in write command #1 and the LBA range specified in write request #2. Furthermore, combined write command #3 is associated with user data A, F, G, D, and E that should be written to LBA x, x+1, x+2, x+3, and x+4, respectively. In the range where write command #1 and write request #2 overlap, the user data of the later write request #2 is written.

[0375] As shown in Figures 33 and 34, when a write request #2 is generated that specifies an LBA range that includes part of the LBA range specified in an issued but incomplete write command #1, a combined write command #3 is used to cancel write command #1.

[0376] Referring to Figures 35 and 36, we will explain the operation of issuing a combined write command and canceling an issued but incomplete write command when the LBA range specified in a later generated write request includes part of the LBA range specified in an issued but incomplete write command.

[0377] 35 shows an example of an operation in response to a write request that specifies a logical address range that includes a portion of the logical address range specified in an issued but incomplete write command. The operation shown in FIG. 35 is performed, for example, after the write operation described above with reference to FIG. 11. The issued but incomplete write command is referred to as a first write command. A write request that specifies an LBA range that includes a portion of the LBA range specified in the first write command is referred to as a third write request. User data to be written in response to the first write command is referred to as first user data 711. Furthermore, user data requested to be written by the third write request is referred to as third user data 713. The first user data 711 and third user data 713 are stored in the data buffer 241.

[0378] First, in the host 2, the IO reception unit 210 receives a third write request from the application 223 or the OS 221 ((1) in FIG. 35). The IO reception unit 210 sends the received third write request to the write / trim management unit 212 ((2) in FIG. 35).

[0379] If the write / trim management unit 212 has not received the first completion for the first write command, it waits for the first completion for the first write command. In the memory system 3, accepted write commands and trim commands can be executed in any order, regardless of the order in which they were received. Therefore, when multiple writes or trims are performed on one LBA, the host 2 must control the order in which the write requests or trim requests were generated from the application 223 or the OS 221 so that the content corresponding to the most recently generated write request or trim request is ultimately reflected in the NAND flash memory 5 of the memory system 3. Therefore, the command issue unit 211 and the write / trim management unit 212 wait for the first completion for the first write command and then perform an operation in response to the third write request. Note that the following example illustrates a case in which the first completion for the first write command is a normal response. If the first completion for the first write command is an abnormal response, the write operation described above with reference to FIGS. 11 to 18 is performed in response to the third write request.

[0380] After receiving the first completion of a normal response to the first write command, the write / trim manager 212 determines the user data 714 to be written in response to the combined write command (hereinafter referred to as combined user data 714). The combined user data 714 is the user data that should be finally written when writing in response to the first write command is performed and then writing in response to the third write request is performed.

[0381] When the PRP is used as a data pointer indicating the storage location of the combined user data 714, the write / trim management unit 212 copies a part of the first user data 711 and the third user data 713 used as the combined user data 714 to generate the combined user data 714. The write / trim management unit 212 stores the generated combined user data 714 in the data buffer 241.

[0382] In the PRP, the data storage location is expressed as a list (i.e., a list of PRP entries) that combines multiple physically discontinuous pages on the NVRAM 24. In the first page of the page group indicated by the list of PRP entries, the area where data is stored may start somewhere in the middle of the page. In other words, no data may be stored at the beginning of the first page. In the last page, the area where data is stored may end somewhere in the middle of the page. In other words, no data may be stored at the end of the last page. There must be no area where data is not stored in any of the pages between the first and last pages.

[0383] Now, consider the case where the page size of the NVRAM 24 is m times the sector size, which is the unit of LBA. Here, m is an integer greater than 1. In this case, the area in the NVRAM 24 where part of the first user data 711 and the third user data 713 used as the combined user data 714 are stored may start or end in the middle of a page. Therefore, it may be impossible to express the storage locations of the part of the first user data 711 and the third user data 713 used as the combined user data 714 in the list of PRP entries.

[0384] Therefore, when a PRP is used as a data pointer indicating the storage location of the combined user data 714, the write / trim management unit 212 copies a part of the first user data 711 and the third user data used as the combined user data 714, and stores them in the NVRAM 24 so that the storage location of the combined user data 714 becomes a group of pages that can be expressed by a list of PRP entries.

[0385] The write / trim management unit 212 generates a data pointer (here, a list of PRP entries) that indicates the storage location of the combined user data 714. Then, the write / trim management unit 212 locks the combined user data 714 ((3) in FIG. 35). FIG. 35 shows an example in which the combined user data 714 is stored in the data buffer 241 in the NVRAM 24 and locked.

[0386] When an SGL is used as a data pointer indicating the storage location of the combined user data 714, the write / trim management unit 212 does not need to copy the part of the first user data 711 and the third user data 713 used as the combined user data 714. The SGL can represent the storage locations of the part of the first user data 711 and the third user data 713 used as the combined user data 714. Therefore, the write / trim management unit 212 generates an SGL indicating the storage locations of the part of the first user data 711 and the third user data 713 used as the combined user data 714. Then, the write / trim management unit 212 locks the part of the first user data 711 and the third user data 713 used as the combined user data 714 ((4) in FIG. 35 ). The storage location of the part of the first user data 711 used as the combined user data 714 may be temporarily referenced by both the first write command and the combined write command. In this case, since the first user data 711 was already locked when the first write command was issued, the write / trim management unit 212 increments a reference counter for the portion of the first user data 711 used as the combined user data 714. The reference counter indicates the number of commands referencing the corresponding specific unit of data. When a new command referencing certain data is issued, the reference counter corresponding to that data is incremented. When processing according to a command referencing certain data is completed, the reference counter corresponding to that data is decremented. When the decremented reference counter becomes 0, the write / trim management unit 212 unlocks the corresponding data.

[0387] After locking the combined user data 714 when a PRP is used, or after locking a part of the first user data 711 and the third user data 713 used as the combined user data 714 when an SGL is used, the write / trim management unit 212 requests the command issuer 211 to issue a write command (combined write command) for writing the combined user data 714 ((5) in FIG. 35). The command issuer 211 issues the combined write command in response to the request from the write / trim management unit 212. That is, the command issuer 211 generates SQ entry information corresponding to the combined write command for writing the combined user data 714. The combined write command specifies an LBA range that includes the LBA range specified in the first write command and the LBA range specified in the third write request. The command issuer 211 sends the generated SQ entry information to the write / trim management unit 212 ((6) in FIG. 35).

[0388] The write / trim management unit 212 generates an entry for the lock data list 245 using the SQ entry information sent by the command issuer 211. The generated entry is referred to as the fourth entry. The fourth entry includes, for example, SQ entry information corresponding to the issued combined write command and data area management information. This data area management information is information that can identify the storage area in the data buffer 241 where the combined user data 714 is stored. The write / trim management unit 212 adds the fourth entry to the lock data list 245 ((7) in FIG. 35).

[0389] Then, the command issuing unit 211 stores the issued combined write command (SQ entry information) in the submission queue 242 ((8) in FIG. 35).

[0390] The subsequent operations in the memory system 3 in response to the combined write command ((9) to (13) in Figure 35) are the same as the operations in the memory system 3 described above with reference to Figure 11 ((8) to (12) in Figure 11).

[0391] Next, the command issuing unit 211 of the host 2 acquires the first completion for the combined write command from the completion queue 243 ((14) in FIG. 35). Then, the command issuing unit 211 sends the acquired first completion to the write / trim management unit 212 ((15) in FIG. 35).

[0392] If the first completion is a completion indicating normal completion, the write / trim management unit 212 updates the fourth entry corresponding to the combined write command in the lock data list 245 ((16) in FIG. 35). Specifically, the write / trim management unit 212 adds, to the fourth entry, the assigned sequence number (i.e., information indicating the order in which the first completion was received) and information indicating that the first completion has been received. The write / trim management unit 212 notifies the IO reception unit 210 of the completion of the write (normal completion) ((17) in FIG. 35). Then, the IO reception unit 210 notifies the application 223 or the OS 221 of the completion of the write ((18) in FIG. 35).

[0393] If the first completion indicates an abnormal termination, the write / trim management unit 212 unlocks the combined user data 714 ((19) in FIG. 35), or unlocks the part of the first user data 711 used as the combined user data 714 and the third user data 713 ((20) in FIG. 35). Then, the write / trim management unit 212 deletes the fourth entry from the locked data list 245 ((21) in FIG. 35). More specifically, the write / trim management unit 212 unlocks the combined user data 714 by using the data area management information in the fourth entry. Alternatively, the write / trim management unit 212 decrements the reference counter of the part of the first user data 711 used as the combined user data 714, and unlocks the third user data 713. Furthermore, if the write / trim management unit 212 has created a list of PRP entries or the second or subsequent segment of the SGL, it also releases the area of ​​the pointer list 244 in which these are stored. Then, the write / trim management unit 212 deletes the fourth entry from the lock data list 245. Furthermore, the write / trim management unit 212 notifies the IO reception unit 210 of the abnormal termination ((22) in FIG. 35). Then, the IO reception unit 210 notifies the application 223 or the OS 221 of the abnormal termination ((23) in FIG. 35).

[0394] If the first completion in response to the combined write command is a normal response, the information processing system 1 performs an operation (abort operation) to abort the first write command. This abort operation is the same as the abort operation described above with reference to FIG. 22. In the abort operation shown in FIG. 22, if the first write command is successfully aborted, the first user data 711 to be written in response to the first write command is unlocked ((9) in FIG. 22). In contrast, in the method using the combined write command, there is a case where part of the first user data 711 is referenced not only by the first write command but also by the combined write command. In that case, in response to the successful abort of the first write command, the write / trim management unit 212 unlocks the part of the first user data 711 that is not referenced by the combined write command, and decrements the reference counter of the part that is referenced by the combined write command. In addition, if the combined user data 714 is generated by copying a portion of the first user data 711, the write / trim management unit 212 unlocks the entire first user data 711 in response to the successful cancellation of the first write command.

[0395] 36 shows an example of a lock data list 245 updated in an abort operation when the first completion for the combined write command is a normal response. The lock data list 245 includes an entry 81 corresponding to the first write command and an entry 84 corresponding to the combined write command.

[0396] Entry 81 is an entry indicating that the first completion for the first write command has been received, similar to entry 81 shown in Fig. 17. Entry 81 is deleted in response to receiving a completion from memory system 3 indicating that the first write command has been successfully aborted.

[0397] Entry 84 includes SQ entry information “sqentry_info4,” completion order “cseq4,” data region management information “region_info4,” and completion status “completed.” Entry 84 is an entry indicating that the first completion for the combined write command has been received.

[0398] As a result of the above write and abort operations, if the LBA range specified in the third write request generated later includes part of the LBA range specified in the first write command that has been issued but not yet completed, writing in response to the first write command in the memory system 3 can be aborted.

[0399] Specifically, the host 2 sends a combined write command that combines the first write command and the third write request to the memory system 3. When the host 2 receives a first completion indicating successful completion for the combined write command from the memory system 3, the host 2 sends an abort command to the memory system 3 to stop the first write command.

[0400] The memory system 3 receives an abort command from the host 2, and if writing in response to the first write command has not started, it aborts the first write command. The memory system 3 then returns a completion indicating successful abort of the first write command to the host 2. The host 2 deletes the entry corresponding to the first write command from the lock data list 245 based on the completion indicating successful abort.

[0401] As a result, the memory system 3 stops writing to the NAND flash memory 5 in response to the first write command. In other words, writing to the LBA range that will be overwritten by the third write request is not performed. This reduces wear on the NAND flash memory 5.

[0402] If the memory system 3 has a security function and the LBA range that is not overwritten by the third write request becomes write-protected after the memory system 3 receives the first write command, the host 2 does not issue a combined write command. Alternatively, after the host 2 receives an error from the memory system 3, the write operation described above with reference to Figures 11 to 18 is performed in response to the third write request.

[0403] (Recovery action) Next, a recovery operation in the information processing system 1 will be described. The recovery operation is an operation for recovering, using data stored in the NVRAM 24, the writing of user data to the memory system 3 that could not be completed due to an abnormal termination or unintentional restart of either or both of the host 2 and the memory system 3. Here, an abnormal termination means that either or both of the host 2 and the memory system 3 terminate their operation before completing the writing of user data corresponding to all write commands received by the memory system 3. Furthermore, an unintentional restart means that either or both of the host 2 and the memory system 3 restart without completing the shutdown operation.

[0404] FIG. 37 shows an example of recovery operation in the information processing system 1. It is assumed here that either the host 2 or the memory system 3, or both, abnormally terminated or unintentionally restarted immediately before the current startup. Specifically, this occurs when the host 2 was operating normally but only the memory system 3 abnormally terminated or restarted; when the memory system 3 was operating normally but only the host 2 abnormally terminated or restarted; or when both the host 2 and the memory system 3 abnormally terminated or restarted. First, if the host 2 or the memory system 3 remains abnormally terminated, an operator manually restarts them, for example. Next, the command issuing unit 211 of the host 2 resets the memory system 3. If the host 2 continues to operate normally at this time, the command issuing unit 211 discards the submission queue 242 and the completion queue 243 and then recreates them. In other words, empty queues are created.

[0405] It is also assumed that there is a case where writing of user data to the memory system 3 could not be completed due to an abnormal termination or an unintended restart. In other words, it is assumed that the lock data list 245 contains an entry for a write command indicating that the first completion has been received.

[0406] First, the IO reception unit 210 of the host 2 suspends reception processing of a new I / O request from the application 223 or the OS 221. In other words, even if the IO reception unit 210 receives a new I / O request, it does not start processing the request. The recovery control unit 213 of the host 2 modifies the lock data list 245 associated with the memory system 3 so as to eliminate duplicated writing to one LBA ((1) in FIG. 37). Specifically, the recovery control unit 213 identifies one or more entries, starting from the top of the lock data list 245, that indicate the reception of the first completion. Using the identified one or more entries, if at least a portion of the LBA range specified in a previously issued write command overlaps with an LBA range specified in a subsequently issued write command or trim command, the recovery control unit 213 modifies or deletes the entry corresponding to the previously issued write command so as to prevent writing to the overlapping portion. This makes it possible to prevent an LBA from being overwritten or a write to an LBA that will later be trimmed when a write or trim based on the lock data list 245 is requested again from the memory system 3. This reduces wear on the NAND flash memory 5 of the memory system 3. A lock data list 245 that includes entries that have been modified to eliminate writes to duplicate LBAs is also referred to as a deduplicated lock data list 245.

[0407] After acquiring the deduplicated lock data list 245, the recovery control unit 213 sequentially identifies n entries, each indicating that the first completion has been received, from the top of the lock data list 245 ((2) in FIG. 37). n is an integer equal to or greater than 1.

[0408] The recovery control unit 213 selects one of the identified n entries from the lock data list 245. Because duplicates have been eliminated at this point, the recovery control unit 213 may process each entry in any order, and does not necessarily have to select each entry in order from the first. Hereinafter, the selected entry will also be referred to as the target entry. In the subsequent operations shown in Figure 37, the n entries are used one by one as the target entry, starting from the first.

[0409] The recovery control unit 213 uses the data area management information included in the target entry to lock the user data 71 or range information 72 in the corresponding data buffer 241 ((3) in FIG. 37). Then, the recovery control unit 213 uses the SQ entry information included in the target entry to request the command issuing unit 211 to issue a corresponding write command or a corresponding trim command ((4) in FIG. 37).

[0410] Note that when the host 2 is restarted, if there is an entry in the lock data list 245 indicating that the first completion has not been received, the recovery control unit 213 deletes the entry. This is because the application 223 or the like that made the request no longer exists, and the recovery control unit 213 cannot send a completion notification. An entry indicating that the first completion has not been received is, for example, an entry that does not include a completion order and a completion status. Since the first completion has not been received, the recovery control unit 213 determines that the write command or trim command corresponding to this entry has not been accepted by the memory system 3. Furthermore, since the first completion has not been received, the application 223 or the like that requested the write or trim corresponding to this entry has ended without being notified of the completion of the write or trim. Therefore, there is no need to resend the write command or trim command corresponding to the entry indicating that the first completion has not been received to the memory system 3. Therefore, the recovery control unit 213 deletes from the lock data list 245 the entry indicating that the first completion has not been received.

[0411] In response to a request from the recovery control unit 213 to issue either a write command or a trim command, the command issuing unit 211 stores the write command or trim command corresponding to the SQ entry information in the target entry in the submission queue 242 ((5) in Figure 37).

[0412] Then, the recovery control unit 213 deletes the completion order and completion status from the target entry ((6) in FIG. 37). This indicates that the target entry is in a state where the corresponding write command or trim command has been issued (sent) to the memory system 3, but the first completion has not yet been received.

[0413] The subsequent operations (7) to (11) in Figure 37, when the target entry corresponds to a write command, are the same as the operations (8) to (12) of the write operation described above with reference to Figure 11. Note that, when the target entry corresponds to a trim command, the operations (7) to (11) in Figure 37 are replaced with the operations (8) to (11) of the trim operation described above with reference to Figure 24. That is, the command reception unit 121 and the write / trim control unit 122 of the memory system 3 receive a write command or a trim command from the submission queue 242 and store the first completion in the completion queue 243.

[0414] Then, the command issuing unit 211 of the host 2 acquires the first completion for the write command or trim command from the completion queue 243 ((12) in FIG. 37). The command issuing unit 211 sends the acquired first completion to the recovery control unit 213 ((13) in FIG. 37).

[0415] The recovery control unit 213 receives the first completion from the command issuing unit 211 and updates the entry corresponding to the received first completion in the lock data list 245 ((14) in FIG. 37). Specifically, the recovery control unit 213 adds a sequence number indicating the order in which the completions were received and information indicating that the first completion has already been received to the entry corresponding to the received first completion.

[0416] 37, the host 2 changes the lock data list 245 so that duplicate writes to one LBA are eliminated and writes to be trimmed are eliminated. Thereafter, the host 2 can resend to the memory system 3, using the n entries each indicating that the first completion has been received, a write command requesting the writing of the corresponding user data 71, or a trim command requesting the deallocation of the LBA range based on the corresponding range information 72. Therefore, the transmission of a write command or trim command that could not be completed due to an abnormal termination or unintentional restart of either or both of the host 2 and the memory system 3, can be reproduced taking into account the order requested by the application 223 or the OS 221.

[0417] An operation according to the transmitted write command or trim command is performed in the memory system 3. When writing according to the transmitted write command, duplicate writing to one LBA is eliminated.

[0418] The recovery control unit 213 and command issuing unit 211 of the host 2 send to the memory system 3 a special flash command for completing a write command or a trim command for which a first completion indicating normal completion has been received, and start processing a new I / O request from the application 223 or the OS 221 after receiving a second completion for all of the write commands and trim commands sent from the host 2 to the memory system 3. Alternatively, the recovery control unit 213 and command issuing unit 211 may start processing a new I / O request from the application 223 or the OS 221 when they receive a first completion for all of the write commands and trim commands sent from the host 2 to the memory system 3. The new I / O request is a new data read request or data write request to the memory system 3. In other words, the command issuing unit 211 of the host 2 becomes able to issue a new read command or write command to the memory system 3 corresponding to the received new I / O request.

[0419] The above recovery operation makes it possible to complete the writing of user data and the deallocation of LBA ranges that could not be completed due to abnormal termination or unintentional restart of either or both of the host 2 and the memory system 3. In other words, the host 2 can recover incomplete writing and trimming for the memory system 3 by using the lock data list 245 that manages the processing status of the issued write commands and trim commands. Then, the command issuing unit 211 of the host 2 can start processing a new I / O request that has been accepted from the application 223 or the OS 221 by the IO accepting unit 210.

[0420] In any of the above-described operations, operations on data managing writing or trimming to the memory system 3 must be performed atomically to prevent data inconsistency even if processing is stopped at any time due to an abnormal power outage, a crash of the OS 221, or the like. In other words, a series of operations related to data managing writing or trimming to the memory system 3 must be performed so that they are not terminated midway. Therefore, for this operation, for example, a command guaranteed to be performed atomically or an algorithm that can restore a consistent state if the atomic operation is not completed is used. Operations that must be performed atomically include changing each entry in the lock data list 245, adding an entry to the lock data list 245, deleting an entry from the lock data list 245, generating modified command data 246, deleting modified command data 246, etc.

[0421] Furthermore, each entry in the lock data list 245 includes a completion order. However, as described above, if the write operation, abort operation, and correction operation described above are applied to all write requests and trim requests from the application 223 or OS 221, duplicate writes to one LBA will not be performed during the recovery operation, and trims will not be performed after writing to one LBA. Therefore, each entry in the lock data list 245 does not need to be provided with a completion order field. Furthermore, the memory system 3 does not need to guarantee the processing order of commands issued during the recovery operation. However, corresponding entries are added to the lock data list 245 in the order in which write requests and trim requests are received from the application 223 or OS 221, and as described above, if there is a previous command with a duplicate, the next command must be issued after the first completion for the previous command is received.

[0422] In addition, if a mode (speed priority mode) is provided in which the above-described write operation, abort operation, and correction operation are not applied in order to prioritize processing speed, the above-described write operation, abort operation, and correction operation are applied only to some write requests and trim requests from, for example, application 223 or OS 221. In this case, each entry in lock data list 245 needs to include a completion order.

[0423] Next, the processing executed in the host 2 and the memory system 3 will be described with reference to the flowcharts of FIGS.

[0424] (Write request control process on host 2) 38 is a flowchart showing an example of the procedure for write request control processing executed by the CPU 21 of the host 2. This write request control processing is processing for controlling writing to the NAND flash memory 5 of the memory system 3 depending on whether there is overlap in the LBA ranges specified between a new write request generated by the application 223 or the OS 221 and an issued but incomplete write command. This write request control processing is processing for realizing the above-mentioned (1) operation when the LBA range specified in a subsequently generated write / trim request completely includes the LBA range specified in the issued but incomplete write command, and (2-a) operation using a method for correcting the issued but incomplete write command when the LBA range specified in a subsequently generated write / trim request includes part of the LBA range specified in the issued but incomplete write command. The CPU 21 executes the write request control processing when a new write request is generated by the application 223 or the OS 221.

[0425] First, CPU 21 determines whether or not there is an entry in lock data list 245 indicating a write command (duplicate write command) that specifies an LBA range that at least partially overlaps with the LBA range specified in the current write request (step S101). Specifically, CPU 21 determines whether or not there is an overlap between the LBA range based on the SQ entry information included in each entry of lock data list 245 and the LBA range specified in the current write request.

[0426] If there is no entry for the duplicate write command in the lock data list 245 (no in step S101), the CPU 21 executes write request processing based on the current write request (step S102) and ends the write request control processing. The write request processing is processing by which the host 2 requests the memory system 3 to write user data. In the write request processing, the CPU 21 issues a write command to write the specified user data to the LBA range specified in the current write request. Furthermore, since there is no entry for the duplicate write command in the lock data list 245, the CPU 21 does not perform processing to cancel or modify the write command indicated by the lock data list 245. The specific steps of the write request processing will be described later with reference to the flowchart of FIG. 39.

[0427] If there are entries for duplicate write commands in the lock data list 245 (yes in step S101), the CPU 21 determines whether the first completions for all the duplicate write commands have been received (step S103). The CPU 21 determines this by checking whether the completion status in each entry indicates that the first completion has been received, or whether the entry has been deleted because the first completion indicated an abnormal termination. If the first completion for at least one duplicate write command has not yet been received (no in step S103), the processing by the CPU 21 returns to step S103. In other words, the CPU 21 waits until it has received the first completions for all the duplicate write commands.

[0428] If the first completions for all duplicate write commands have been received (yes in step S103), CPU 21 confirms that at least one completion is a normal response, that is, confirms that an entry for the duplicate write command remains in lock data list 245 (step S104). An entry corresponding to a duplicate write command for which the first completion was an abnormal response has been deleted from lock data list 245. Therefore, after receiving the first completions for all duplicate write commands, CPU 21 determines whether an entry for the duplicate write command remains in lock data list 245.

[0429] If there is no entry for the duplicate write command (no in step S104), that is, if an abnormality occurs in the processing of the duplicate write command in the memory system 3 and there is no entry for the duplicate write command in the lock data list 245, the CPU 21 performs write request processing based on the current write request (step S102) and ends the write request control processing. The CPU 21 does not perform processing to cancel or modify the write command indicated by the lock data list 245.

[0430] If an entry for a duplicate write command remains (step S104: yes), the CPU 21 executes write request processing based on the current write request (step S105). In the lock data list 245, the LBA range specified by the write command of an earlier entry may be modified or invalidated by a write command or trim command of a later entry. On the other hand, the LBA range specified by the write command of a later entry may not be modified or invalidated by a write command or trim command of the earlier entry. Therefore, in this embodiment, a sequence number is not required. Note that a sequence number is required if deduplication between the LBA range specified by the earlier write command and the LBA range specified by the later write command or trim command is not performed. Hereinafter, the write command issued in the write request processing of step S105 is referred to as the target write command.

[0431] The CPU 21 determines whether or not the first completion for the target write command has been received (step S106). If the first completion for the target write command has not been received (no in step S106), the processing by the CPU 21 returns to step S106. That is, the CPU 21 waits until the first completion for the target write command is received.

[0432] If the first completion for the target write command is received (yes in step S106), the CPU 21 determines whether the first completion for the target write command is a normal response (step S107). If the first completion for the target write command is an abnormal response (no in step S107), the CPU 21 ends the write request control process. In other words, since an abnormality occurred in the processing for the target write command in the memory system 3, the CPU 21 does not perform processing to cancel or correct the duplicate write command indicated by the lock data list 245.

[0433] If the first completion for the target write command is a normal response (yes in step S107), the CPU 21 determines whether the LBA range specified in the target write command (i.e., the current write request) includes all of the LBA ranges specified in one duplicate write command (step S108). If the LBA range specified in the target write command includes all of the LBA ranges specified in one duplicate write command (yes in step S108), the CPU 21 issues an abort command for the duplicate write command (step S109). The abort command includes information (e.g., a command ID) that can identify the duplicate write command to be aborted. Then, the CPU 21 stores the issued abort command (i.e., SQ entry information representing the abort command) in the submission queue 242 (step S110). This enables the CPU 21 to request the memory system 3 to abort writing of user data performed in response to the duplicate write command.

[0434] If the LBA range specified in the target write command includes only a portion of the LBA range specified in one duplicate write command (no in step S108), the CPU 21 issues a modification command for the duplicate write command (step S111). The modification command includes information capable of identifying the duplicate write command to be modified and information indicating the LBA range, within the LBA range specified in the duplicate write command, for which writing should be canceled. The CPU 21 then stores the issued modification command (i.e., SQ entry information representing the modification command) in the submission queue 242 (step S112). This enables the CPU 21 to request the memory system 3 to cancel a portion of the writing of user data performed in response to the duplicate write command.

[0435] Next, CPU 21 determines whether there is another duplicate write command using lock data list 245 (step S113). If there is another duplicate write command (yes in step S113), the processing by CPU 21 returns to step S108. As a result, either an abort command or a modify command is issued for the other duplicate write command.

[0436] If there is no other overlapping write command (no in step S113), the CPU 21 ends the write request control process.

[0437] By the above write request control process, when a new write request is generated by the application 223 or the OS 221, if there is an incomplete write command (duplicate write command) that specifies an LBA range that overlaps with the LBA range specified in the new write request, the CPU 21 can request the memory system 3 to cancel or modify the duplicate write command.

[0438] Specifically, the CPU 21 uses the lock data list 245 to determine whether there is a duplicate write command. If there is a duplicate write command, the CPU 21 uses the lock data list 245 to determine whether the LBA range specified in the new write request includes the entire LBA range specified in the duplicate write command, or only a portion of it. If the LBA range specified in the new write request includes the entire LBA range specified in the duplicate write command, the CPU 21 requests the memory system 3 to cancel the duplicate write command. If the LBA range specified in the new write request includes only a portion of the LBA range specified in the duplicate write command, the CPU 21 requests the memory system 3 to modify the duplicate write command.

[0439] As a result, if there is an overlapping write command whose LBA range overlaps with that of a new write request, the CPU 21 can request the memory system 3 to stop writing in accordance with the overlapping write command or to cancel part of the writing.

[0440] (Processing for writing user data to memory system 3 in host 2) 39 is a flowchart showing an example of the procedure of write request processing executed by the CPU 21 of the host 2. The write request processing is processing by which the host 2 requests the memory system 3 to write user data. The write request processing corresponds to steps S102 and S105 of the write request control processing described above with reference to FIG.

[0441] First, the CPU 21 acquires, from the write request, the location of a storage area in the data buffer 241 where the user data to be written to the NAND flash memory 5 is stored (step S201). If the user data to be written to the NAND flash memory 5 is stored in the RAM 22, the CPU 21 copies the user data to the data buffer 241. The CPU 21 then acquires the location of the storage area to which the user data is to be copied. Next, the CPU 21 locks and write-protects the user data stored in the data buffer 241 (step S202). More specifically, the CPU 21 uses the function of the OS 221 being executed to lock and write-protect the storage area (e.g., a page) where the user data is stored and which can be used by the driver 222. This prevents the storage area where the user data is stored from being unintentionally released or rewritten. That is, after the CPU 21 receives the first completion and notifies the application 223 or the OS 221 of the completion of the write request, it becomes possible to detect when the memory area in which the user data is stored is about to be overwritten.

[0442] The CPU 21 issues a write command (hereinafter referred to as a first write command) for writing the user data stored in the data buffer 241 to the NAND flash memory 5 (step S203). More specifically, the CPU 21 stores the SQ entry information of the first write command in the submission queue 242, and writes the value of the SQ Tail pointer to the SQ Tail doorbell register of the memory system 3.

[0443] Next, the CPU 21 adds an entry corresponding to the first write command to the lock data list 245 (step S204). The added entry includes, for example, SQ entry information corresponding to the first write command and data area management information. The SQ entry information corresponding to the first write command is information that represents the first write command. More specifically, the SQ entry information corresponding to the first write command is information that is stored in the submission queue 242 to cause the memory system 3 to execute processing according to the first write command. Furthermore, the data area management information corresponding to the first write command is information that can identify a storage area in the data buffer 241 in which user data corresponding to the first write command is stored. The SQ entry information also includes information for identifying a storage area in the data buffer 241, but this information is described using a physical address, so it is desirable that the data area management information be described using a logical address.

[0444] Note that, before the procedure of step S203 of storing the first write command in the submission queue 242, the CPU 21 may execute the procedure of step S204 of adding an entry corresponding to the first write command to the lock data list 245. Furthermore, the CPU 21 may execute the procedure of step S203 and the procedure of step S204 in parallel.

[0445] Through the above write request processing, the CPU 21 can request the memory system 3 to write user data stored in the data buffer 241. Furthermore, the CPU 21 can manage information related to the write requested to the memory system 3 (i.e., information related to the issued write command) using the lock data list 245.

[0446] (Processing for writing user data in memory system 3) 40 is a flowchart showing an example of the procedure of a write control process executed by the CPU 12 of the memory system 3. The write control process is a process for accepting a write command issued by the host 2 and controlling the writing of user data corresponding to the accepted write command. The CPU 12 executes the write control process in response to acquiring the write command issued by the host 2 from the submission queue 242. Here, the write command acquired from the submission queue 242 is referred to as a first target write command.

[0447] First, the CPU 12 updates the write management table 63 based on the first target write command (step S301). Specifically, the CPU 12 acquires, for example, a command ID, an LBA, a data length, and a data pointer from the first target write command. The CPU 12 adds an entry indicating the acquired command ID, an LBA, a data length, and a data pointer to the write management table 63.

[0448] Then, the CPU 12 notifies the host 2 of a first completion for the first target write command (step S302). More specifically, the CPU 12 stores the first completion in the completion queue 243 and notifies the host 2 of an interrupt. Note that the CPU 12 may store multiple completions in the completion queue 243 and then notify the host 2 of a single interrupt. The first completion for the first target write command includes the command ID of the first target write command.

[0449] Next, the CPU 12 determines whether writing of user data can be started (step S303). More specifically, the CPU 12 starts writing user data when, for example, the total amount of unwritten user data for one or more write commands that have returned a first completion, excluding the amount canceled in response to the modification command, reaches the write unit. The CPU 12 calculates the total amount of unwritten user data excluding the amount canceled in response to the modification command, using the write management table 63 and the modification command data 64. In other words, the CPU 12 calculates the amount of data by subtracting the amount of user data corresponding to the LBA range whose writing was canceled in response to the modification command from the total amount of unwritten user data stored in the data buffer 241 of the host 2.

[0450] In order to eliminate overlapping writes caused by the previous write command and the first target command, if an abort command or modification command for the previous write command is scheduled to be sent following the first target write command, a flag indicating that the command is scheduled to be sent may be added to the first target write command. If multiple abort commands or modification commands are sent, a flag indicating that another abort command or modification command is scheduled to be sent may be added to each of the abort commands or modification commands. This allows the CPU 12 to wait for the subsequent abort command or modification command without starting writing to the NAND flash memory 5, even if the total amount of unwritten user data reaches the write unit in response to receiving the first target write command. This prevents the abort command or modification command from failing. Furthermore, it is possible to prevent writing of unwritten user data from starting if the total amount of unwritten user data does not reach the write unit due to execution of the abort command or modification command.

[0451] If the total amount of unwritten user data excluding the canceled data does not reach the write unit (no in step S303), the CPU 12 ends the write control process.

[0452] If the total amount of unwritten user data excluding the canceled data reaches the write unit (yes in step S303), the CPU 12 transfers the user data of the write unit from the data buffer 241 of the host 2 to the NAND flash memory 5 of the memory system 3 (step S304). The CPU 12 writes the transferred user data to the NAND flash memory 5 (step S305). Next, the CPU 12 updates the logical-physical address conversion table 62 to indicate the correspondence between the physical address at which the user data is written and the LBA (step S306).

[0453] Next, the CPU 12 determines whether or not there is a write command for which the corresponding user data has become readable from the NAND flash memory 5 (step S307). If there is no write command for which the corresponding user data has become readable (no in step S307), the processing by the CPU 12 ends. In other words, the second completion indicating that the writing of the user data in response to the write command has been completed cannot yet be notified to the host 2, so the processing by the CPU 12 ends.

[0454] If there is one or more write commands for which the corresponding user data has been written in step S305 and become readable, i.e., if there is one or more completed write commands (yes in step S307), the CPU 12 notifies the host 2 of one or more second completions for these one or more write commands (step S308). Hereinafter, a write command for which the corresponding user data has been written and completed is referred to as a second target write command. The second completion for the second target write command includes the command ID of the second target write command. Then, the CPU 12 updates the write management table 63 (step S309). Specifically, the CPU 12 deletes the entry corresponding to the second target write command from the write management table 63. Note that, if there is modified command data 64 associated with the entry corresponding to the second target write command, the CPU 12 also deletes the modified command data 64. Then, the CPU 12 updates the command log 51 to add the command ID of the second target write command (step S310), and ends the write control process.

[0455] Through the above write control process, the CPU 12 can manage write commands received from the host 2 and control the writing of user data corresponding to the received write commands. Specifically, when the CPU 12 receives a write command from the host 2, it updates the write management table 63 based on the write command and returns a first completion to the host 2. Furthermore, when the user data for the write unit (user data excluding the amount canceled in accordance with the modification command) is stored in the data buffer 241, the CPU 12 writes the user data for the write unit to the NAND flash memory 5. Then, the CPU 12 returns a second completion to the host 2 for the write command corresponding to the user data for which writing has been completed.

[0456] Therefore, the CPU 12 can notify the host 2 of the processing status of the write command by returning the first completion and the second completion to the host 2. Furthermore, the CPU 12 can efficiently use the storage area of ​​the NAND flash memory 5 by writing using Delayed Write Completion.

[0457] The CPU 12 may write user data corresponding to the accepted write command with padding to the NAND flash memory 5 not only when the total amount of unwritten user data excluding the amount canceled in response to the modification command reaches the write unit (yes in step S303) but also when the time elapsed since accepting the write command exceeds a threshold. Specifically, when the time elapsed since accepting the write command exceeds the threshold, the CPU 12 transfers the user data corresponding to the accepted write command and excluding the amount canceled in response to the modification command from the data buffer 241 of the host 2 to the NAND flash memory 5. Then, the CPU 12 writes the transferred user data with padding to the NAND flash memory 5. That is, when the time elapsed since accepting the write command exceeds the threshold, the CPU 12 performs the procedure from step S304 onwards of the write control process in FIG. 40. In this case, the user data of the write unit in step S304 is replaced with data obtained by adding padding data to the user data corresponding to the accepted write command. This allows the CPU 12 to notify the host 2 of the second completion for the write command within the time expected by the host 2.

[0458] Furthermore, if the time since the erase operation was performed on a block of the NAND flash memory 5 exceeds a threshold, the CPU 12 may write user data with padding to the end of the block in the same manner as described above. This makes it possible to maintain the quality of the user data written in the block.

[0459] Furthermore, when a special flash command is received, the CPU 12 may write user data corresponding to all of the received write commands with padding to the NAND flash memory 5, and complete these write commands. That is, when a special flash command is received, the CPU 12 may perform the procedures from step S304 onwards of the write control process in Fig. 40. In this case, the user data for the write unit in step S304 is replaced with data obtained by adding padding data to the user data corresponding to the received write commands.

[0460] (Processing for canceling duplicate write commands in memory system 3) 41 is a flowchart showing an example of the procedure for abort control processing executed by the CPU 12 of the memory system 3. The abort control processing is processing based on an abort command received from the host 2. The CPU 12 executes the abort control processing in response to acquiring the abort command issued by the host 2 from the submission queue 242. Here, an example is shown in which the target of the abort by the abort command is a duplicate write command.

[0461] First, the CPU 12 acquires the command ID specified in the abort command (step S401). The acquired command ID is the command ID of the duplicate write command that should be aborted in response to the abort command. The CPU 12 determines whether or not there is an entry including the acquired command ID in the write management table 63 (step S402).

[0462] If the write management table 63 does not contain an entry containing the acquired command ID (no in step S402), the CPU 12 notifies the host 2 of a completion indicating abort failure (step S403) since there is no duplicate write command, and terminates the abort control process.

[0463] If the write management table 63 has an entry including the acquired command ID (yes in step S402), the CPU 12 determines whether or not write processing according to the duplicate write command has started (step S404). The CPU 12 determines that write processing according to the duplicate write command has started when, for example, the procedure of step S305 of the write control processing described above with reference to Fig. 40 has been performed or completed based on one or more write commands including the duplicate write command to be stopped. In other words, the CPU 12 determines whether writing to the NAND flash memory 5 has started or completed.

[0464] If the write process corresponding to the duplicate write command has started (yes in step S404), the CPU 12 cannot stop the write process corresponding to the duplicate write command, so it notifies the host 2 of a completion indicating an abort failure (step S403) and terminates the abort control process.

[0465] If the write process corresponding to the duplicate write command has not started (no in step S404), the CPU 12 deletes the entry corresponding to the duplicate write command (i.e., the entry including the acquired command ID) from the write management table 63 (step S405). If the transfer of user data corresponding to the duplicate write command from the data buffer 241 (step S304 in FIG. 40) has started, the CPU 12 cancels this. Even if this transfer has ended, the CPU 12 does not write the data to the NAND flash memory 5 (step S305 in FIG. 40). This allows the CPU 12 to cancel the writing of user data corresponding to the duplicate write command. Then, the CPU 12 notifies the host 2 of a completion indicating that the abort was successful (step S406). Furthermore, the CPU 12 notifies the host 2 of a completion indicating that the duplicate write command has been aborted (step S407), and ends the abort control process.

[0466] Note that the CPU 12 does not start the process of writing user data corresponding to the duplicate write command to the NAND flash memory 5 from the time it finds the entry in the write management table 63 containing the acquired command ID (step S402) until it deletes the entry (step S405). That is, if an abort command is received between steps S304 and S305, the CPU 12 suspends the write control process until the abort command is completed. Since the total amount of unwritten user data excluding the canceled data may still reach the write unit, the CPU 12 returns to step S303 and resumes the write control process after the abort command is completed. Note that if a flag indicating that the aforementioned abort command or modification command is to be sent following the write command is used, the abort process is completed before the determination in step S303. Therefore, in this case, after the total amount of unwritten user data excluding the canceled data reaches the write unit (yes in step S303), the total amount of user data does not change, and the CPU 12 does not need to recalculate the total amount of user data.

[0467] In addition, if a write process is performed after a time exceeding the threshold has elapsed, or if an abort command is received for a duplicate write command while processing using a flash command, and the process is stopped before step S305, the CPU 12 restarts the stopped process from the beginning.

[0468] By the above abort control process, when the CPU 12 receives an abort command from the host 2, if the write process corresponding to the duplicate write command has not started, the CPU 12 can stop writing user data corresponding to the duplicate write command.

[0469] (Processing for correcting duplicate write commands in memory system 3) 42 is a flowchart showing an example of the procedure of the modification control process executed by the CPU 12 of the memory system 3. The modification control process is a process based on a modification command received from the host 2. The CPU 12 executes the modification control process in response to acquiring the modification command issued by the host 2 from the submission queue 242.

[0470] First, the CPU 12 acquires the command ID specified in the modification command (step S501). The acquired command ID is the command ID of the write command (i.e., the duplicate write command) that should be modified in accordance with the modification command. The CPU 12 determines whether or not there is an entry including the acquired command ID in the write management table 63 (step S502). The entry including the acquired command ID is also referred to as the entry to be modified.

[0471] If there is no entry to be corrected in the write management table 63 (no in step S502), the CPU 12 sends a completion indicating correction failure to the host 2 since there is no duplicate write command (step S503), and ends the correction control process.

[0472] If the write management table 63 contains an entry to be corrected (step S502: yes), the CPU 12 determines whether or not write processing has started in response to the duplicate write command (step S504). The CPU 12 determines that write processing has started in response to the duplicate write command when, for example, the procedure of step S305 of the write control processing described above with reference to Fig. 40 has been performed or completed based on one or more write commands including the duplicate write command to be corrected. In other words, the CPU 12 determines whether writing to the NAND flash memory 5 has started or completed.

[0473] If the write process corresponding to the duplicate write command has started (yes in step S504), the CPU 12 cannot correct the write process corresponding to the duplicate write command, so it notifies the host 2 of a completion indicating that the correction has failed (step S503) and terminates the correction control process.

[0474] If the write process corresponding to the duplicate write command has not started (No in step S504), the CPU 12 acquires the LBA range from the entry to be modified (step S505). Specifically, the CPU 12 acquires the LBA range (first LBA range) based on the LBA and data length indicated in the entry to be modified. Then, the CPU 12 determines whether the LBA range (second LBA range) specified in the modification command is within the first LBA range (step S506).

[0475] If at least a part of the second LBA range is outside the first LBA range (no in step S506), the CPU 12 notifies the host 2 of a completion indicating that the correction has failed (step S503) since the specified second LBA range is not appropriate, and ends the correction control process.

[0476] If the second LBA range is within the first LBA range (step S506: yes), the CPU 12 updates the entry to be modified using the second LBA range (step S507). Specifically, the CPU 12 generates modification command data 64 indicating the second LBA range. The CPU 12 then registers a pointer to the generated modification command data 64 in the pointer-to-modification-command-data field of the entry to be modified. This allows the CPU 12 to manage the second LBA range within the first LBA range where writing should be canceled, using the entry to be modified and the modification command data 64. The CPU 12 then notifies the completion host 2 indicating successful modification (step S508), and terminates the modification control process.

[0477] Through the above modification control process, the CPU 12 can update the write management table 63 in accordance with the modification command received from the host 2 so as to cancel writing to the second LBA range within the first LBA range specified in the duplicate write command. In other words, the CPU 12 can modify the first LBA range specified in the duplicate write command in accordance with the modification command. Based on the updated write management table 63, the CPU 12 does not write user data to the second LBA range within the first LBA range specified in the duplicate write command.

[0478] (Processing based on the response to the write command from the memory system 3 in the host 2) 43 is a flowchart showing an example of the procedure of a write response reception process executed by the CPU 21 of the host 2. The write response reception process is a process based on a response (completion) to a write command received from the memory system 3. The CPU 21 executes the write response reception process in response to acquiring a completion to the write command from the completion queue 243.

[0479] First, CPU 21 identifies an entry in lock data list 245 that corresponds to the command ID in the acquired completion (step S601). CPU 21 uses the identified entry to determine whether the acquired completion is the first completion (step S602). Specifically, CPU 21 determines that the acquired completion is the first completion if, for example, no value is set as the completion status in the identified entry. Furthermore, CPU 21 determines that the acquired completion is the second completion if a value indicating that the first completion has been received is set as the completion status in the identified entry.

[0480] If the acquired completion is the first completion (yes in step S602), the CPU 21 determines whether the completion is a normal response (step S603).

[0481] If the acquired completion is a normal response (yes in step S603), the CPU 21 adds 1 to (i.e., increments) the variable Cseq used to assign a sequence number to a completion (step S604). Then, the CPU 21 updates the identified entry using the variable Cseq (step S605). Specifically, the CPU 21 adds (sets) the sequence number indicated by the variable Cseq as the completion order in the identified entry. As a result, the sequence number indicated by the variable Cseq is assigned to the acquired completion. The CPU 21 also adds a value indicating that the first completion has been received as the completion status in the identified entry. Then, the CPU 21 returns a response indicating that the write has been completed in response to the write request generated by the application 223 or the OS 221 (step S606), and ends the write response reception process.

[0482] Note that a method may be used in which a write command is sent twice to the memory system 3 in response to a write request generated by the application 223 or the OS 221, and a first completion for the first write command and a second completion for the second write command are received from the memory system 3. In this case, the CPU 21, for example, updates the entry identified in step S605, then stores the second write command in the submission queue 242 (step S607), rewrites the command ID of the identified entry with the command ID of the second write command, and ends the write response reception process.

[0483] If the acquired completion (i.e., the first completion) is an abnormal response (no in step S603), the CPU 21 unlocks the user data in the data buffer 241 associated with the command ID in the completion (step S608). After the data buffer 241 is unlocked, the application 223 or the OS 221 deletes the user data. The CPU 21 can identify the user data in the data buffer 241 to be unlocked, for example, by using the data management area information in the identified entry. When the user data is unlocked, the user data can be deleted. That is, the storage area in the data buffer 241 in which the user data is stored (i.e., the storage area in the NVRAM 24) is released. The CPU 21 deletes the identified entry from the locked data list 245 (step S609). Note that if the CPU 21 has created a list of PRP entries or the second or subsequent segment of the SGL for this entry, it also releases the area in the pointer list 244 in which they are stored. Then, the CPU 21 notifies the application 223 or the OS 221 that the process corresponding to the command of the identified entry has failed (step S610), and ends the write response reception process.

[0484] If the acquired completion is the second completion (no in step S602), the CPU 21 determines whether the completion is a normal response (step S611).

[0485] If the acquired completion is a normal response (yes in step S611), the CPU 21 unlocks the user data in the data buffer 241 associated with the command ID in the completion and also releases the write prohibition (step S612). Then, the CPU 21 deletes the identified entry from the locked data list 245 (step S613) and ends the write response reception process. Note that if the CPU 21 has created a list of PRP entries or the second or subsequent segment of the SGL for this entry, it also releases the area of ​​the pointer list 244 in which these are stored. Furthermore, if the CPU 21 has created modified command data 246 for this entry, it also releases the area in which the modified command data 246 is stored.

[0486] If the acquired completion (i.e., the second completion) is an abnormal response (no in step S611), the CPU 21 determines that the memory system 3 has failed, stops processing for the memory system 3 (step S614), notifies the OS 221 of the occurrence of the abnormality, and ends the write response reception process. In this case, abnormality processing is performed as the information processing system 1. Thereafter, the IO receiving unit 210 rejects all requests from the application 233 or the OS 211 that change user data, such as a write request or a trim request.

[0487] Through the write response reception process described above, the CPU 21 can perform different processes depending on whether the received completion is the first or second completion for the corresponding write command, and whether the received completion is a normal response or an abnormal response. That is, if the received completion is the first completion and a normal response, the CPU 21 adds the sequence number Cseq assigned to that completion and information indicating that the first completion has been received to the corresponding entry in the lock data list 245, and responds to the write request with a completion. If the received completion is the first completion and an abnormal response, the CPU 21 deletes the corresponding user data and the corresponding entry in the lock data list 245 from the NVRAM 24, and responds to the write request with a failure. If the received completion is the second completion and is a normal response, the CPU 21 deletes the corresponding user data (i.e., the user data for which writing has been completed) and the corresponding entry in the lock data list 245 from the NVRAM 24. If the received completion is the second completion and is an abnormal response, the CPU 21 determines that the memory system 3 has failed and stops processing the memory system 3.

[0488] (Processing based on the response to the abort command from the memory system 3 in the host 2) 44 is a flowchart showing an example of the procedure for abort response reception processing executed by the CPU 21 of the host 2. The abort response reception processing is processing based on a response (completion) to the abort command received from the memory system 3. The CPU 21 executes the abort response reception processing in response to acquiring a completion to the abort command from the completion queue 243. Here, an example is shown in which the abort command corresponding to the acquired completion is an abort command requesting the cancellation of a duplicate write command.

[0489] First, the CPU 21 determines whether the acquired completion is a normal response (step S701). That is, the CPU 21 determines whether the cancellation of the duplicate write command was successful based on the acquired completion.

[0490] If the acquired completion is a normal response (yes in step S701), the CPU 21 identifies an entry corresponding to the duplicated write command in the lock data list 245 (step S702). The CPU 21 uses the identified entry to unlock the user data in the data buffer 241 associated with the duplicated write command (step S703). The CPU 21 can identify the user data in the data buffer 241 to be unlocked, for example, by using the data area management information in the identified entry.

[0491] Then, CPU 21 deletes the identified entry from lock data list 245 (step S704) and ends the abort response reception process. If CPU 21 has created a list of PRP entries or the second or subsequent segment of the SGL for this entry, it also releases the area in pointer list 244 in which they are stored. If CPU 21 has created modified command data 246 for this entry, it also releases the area in which the modified command data 246 is stored.

[0492] If the acquired completion is an abnormal response (no in step S701), the CPU 21 ends the abort response reception process. That is, because the CPU 21 failed to cancel the duplicate write command, the CPU 21 ends the abort response reception process without releasing the lock on the user data associated with the duplicate write command and without deleting the entry corresponding to the duplicate write command from the lock data list 245.

[0493] By the above abort response reception process, if the CPU 21 has successfully aborted the duplicated write command, it can unlock the user data associated with the duplicated write command and delete the entry corresponding to the duplicated write command from the lock data list 245.

[0494] (Processing based on response to modification command from memory system 3 in host 2) 45 is a flowchart showing an example of the procedure of a modified response reception process executed by the CPU 21 of the host 2. The modified response reception process is a process based on a response (completion) to a modified command received from the memory system 3. The CPU 21 executes the modified response reception process in response to acquiring a completion to the modified command from the completion queue 243. Here, an example is shown in which the modified command corresponding to the acquired completion is a modified command requesting modification of a duplicate write command, and a PRP is used.

[0495] First, the CPU 21 determines whether the acquired completion is a normal response (step S801). That is, the CPU 21 determines whether the correction of the duplicate write command was successful based on the acquired completion.

[0496] If the acquired completion is a normal response (step S801: yes), CPU 21 identifies an entry corresponding to the duplicated write command in lock data list 245 (step S802). Then, CPU 21 determines whether the portion including the beginning of the LBA range (first LBA range) specified in the duplicated write command has been canceled based on the LBA range (second LBA range) specified in the modification command (step S803).

[0497] If the portion including the beginning of the first LBA range is canceled (step S803: yes), CPU 21 changes the LBA range and data pointer indicated by the SQ entry information in the identified entry (step S804), and terminates the correction response reception process. Specifically, CPU 21 changes the LBA range indicated by the SQ entry information (e.g., the starting LBA and data length) so as to indicate the LBA range obtained by excluding the second LBA range from the first LBA range. CPU 21 then changes the data pointer indicated by the SQ entry information so as to indicate the location where the user data to be written is stored in the LBA range obtained by excluding the second LBA range from the first LBA range. CPU 21 also unlocks and releases the user data area of ​​the portion that is no longer needed due to this exclusion.

[0498] The change of the data pointer in step S804 is possible when the PRP is used to indicate the storage area where the user data is stored, and the cancellation of the LBA range including the start LBA can be expressed simply by modifying the entry in the lock data list 245. On the other hand, when the SGL is used to indicate the storage area where the user data is stored, the cancellation of the LBA range including the start LBA cannot be expressed unless the data in the lock data list 245 read by the memory system 3 is also modified. In this case, the CPU 21 performs processing equivalent to that in step S807.

[0499] If the portion including the beginning of the first LBA range has not been canceled (no in step S803), CPU 21 determines whether the portion including the end of the first LBA range has been canceled based on the second LBA range (step S805).

[0500] If the portion including the end of the first LBA range is canceled (step S805: yes), the CPU 21 changes the LBA range indicated by the SQ entry information in the identified entry (step S806) and terminates the modification response reception process. Specifically, the CPU 21 changes the LBA range indicated by the SQ entry information to indicate an LBA range obtained by excluding the second LBA range from the first LBA range. Note that if the portion including the end of the first LBA range is canceled, the CPU 21 can manage, based on the changed LBA range, that the portion of the user data stored at the location indicated by the data pointer in the SQ entry information, from the beginning to the end of the changed user data, which is to be written. In other words, the beginning of the user data to be written is stored at the location indicated by the data pointer in the SQ entry information. Therefore, the CPU 21 does not need to change the data pointer indicated by the SQ entry information. The CPU 21 also unlocks and releases the storage area in which the portion of the user data that is no longer needed due to this exclusion is stored.

[0501] If the portion of the LBA range to be written that includes the end has not been canceled (no in step S805), that is, if an intermediate portion of the LBA range to be written that does not include the beginning or end has been canceled, CPU 21 generates modified command data 246 based on the second LBA range (step S807). Modified command data 246 includes, for example, the first LBA of the second LBA range and the length of the second LBA range (for example, the number of sectors). CPU 21 then registers the generated modified command data 246 in the modified command data list of the identified entry (step S808), unlocks the storage area in which the portion of user data that has become unnecessary due to this exclusion is stored, and ends the modified response receiving process.

[0502] If the completion is an abnormal response (no in step S801), the CPU 21 ends the modified response reception process. That is, since the modification of the duplicate write command has failed, the CPU 21 ends the modified response reception process without changing the entry corresponding to the duplicate write command.

[0503] By the above modification response receiving process, if the modification of the duplicate write command is successful, the CPU 21 can change the entry corresponding to the duplicate write command to indicate that writing to the second LBA range specified in the modification command has been canceled.

[0504] (Modification of write request control process in host 2) 46 is a flowchart showing a modified example of the procedure for write request control processing executed by the CPU 21 of the host 2. In the modified write request control processing, if there is an overlap in the LBA ranges specified between a new write request generated by the application 223 or the OS 221 and an issued but incomplete write command, the memory system 3 is requested to write to an LBA range combining the LBA range specified in the new write request and the LBA range specified in the issued but incomplete write command (duplicate write command). The memory system 3 is then requested to cancel the duplicate write command. In other words, this write request control processing is processing that realizes the above-mentioned (1) operation when the LBA range specified in a subsequently generated write / trim request completely includes the LBA range specified in the issued but incomplete write command, and (2-b) operation using a method for canceling the issued but incomplete write command when the LBA range specified in a subsequently generated write / trim request includes part of the LBA range specified in the issued but incomplete write command.

[0505] The LBA range specified in the write request includes at least a portion of the LBA range specified in the overlapping write command, and therefore the LBA range specified in the write request may include the entire LBA range specified in the overlapping write command.

[0506] When a new write request is generated by the application 223 or the OS 221, the CPU 21 executes a write request control process.

[0507] The procedures of steps S901, S902, and S903 in FIG. 46 are the same as the procedures of steps S101, S102, and S103 in the write request control process described above with reference to FIG.

[0508] If the lock data list 245 contains an entry indicating a write command (duplicate write command) that specifies an LBA range that at least partially overlaps with the LBA range specified in the current write request (yes in step S901), and if the first completions have been received for all of the duplicate write commands (yes in step S903), the CPU 21 determines whether or not any entries for the duplicate write commands remain in the lock data list 245 (step S904). Entries corresponding to duplicate write commands for which the first completion was an abnormal response have been deleted from the lock data list 245. Therefore, after receiving the first completions for all of the duplicate write commands, the CPU 21 determines whether or not any entries for the duplicate write commands remain in the lock data list 245.

[0509] If there are no duplicate write command entries remaining (No in step S904), that is, if the first completions for all duplicate write commands are abnormal responses, CPU 21 executes write request processing based on the current write request (step S902) and ends the write request control processing. The specific procedure for the write request processing is as described above with reference to the flowchart in Fig. 39.

[0510] If an entry for the duplicate write command remains (yes in step S904), the CPU 21 executes combined write request processing based on the write request and the duplicate write command (step S905). The combined write request processing is processing for requesting the memory system 3 to write a combined copy of the duplicate write command and the current write request. More specifically, in the combined write request processing, when user data is written to the NAND flash memory 5 of the memory system 3 in accordance with the duplicate write command and the current write request, the user data (combined user data) that should ultimately be written to the NAND flash memory 5 is determined. Then, one write command (combined write command) for writing the determined combined user data is issued to the memory system 3. Specific steps of the combined write request processing will be described later with reference to the flowchart of FIG. 47.

[0511] Next, CPU 21 determines whether or not the first completion for the combined write command has been received (step S906). If the first completion for the combined write command has not been received (no in step S906), the process by CPU 21 returns to step S906. That is, CPU 21 waits until the first completion for the combined write command is received.

[0512] When the first completion in response to the combined write command is received (Yes in step S906), the CPU 21 determines whether or not this completion is a normal response (step S907).

[0513] If the completion for the combined write command is a normal response (yes in step S907), the CPU 21 issues an abort command to cancel the duplicate write command (step S908). The CPU 21 stores the issued abort command in the submission queue 242 (step S909). Then, the CPU 21 determines whether or not there is another duplicate write command using the lock data list 245 (step S910). If there is another duplicate write command (yes in step S910), the processing by the CPU 21 returns to step S908. As a result, an abort command is issued for the other duplicate write command.

[0514] If there is no other overlapping write command (no in step S910), the CPU 21 ends the write request control process.

[0515] If the completion to the combined write command is an abnormal response (no in step S907), the CPU 21 ends the write request control process. That is, since writing according to the combined write command is not performed, the CPU 21 ends the write request control process without performing processing to cancel the overlapping write command.

[0516] With the write request control process of the above modified example, when a new write request is generated by application 223 or OS 221, if there is an incomplete write command (duplicate write command) that specifies an LBA range that overlaps with the LBA range specified in the new write request, CPU 21 can request memory system 3 to write a write that combines the new write request and the duplicate write command, and can request memory system 3 to cancel the duplicate write command.

[0517] Specifically, CPU 21 determines whether there is a duplicate write command using lock data list 245. If there is a duplicate write command, CPU 21 issues a combined write command based on the new write request and the duplicate write command. If the first completion for the combined write command is a normal response, CPU 21 issues an abort command to stop the duplicate write command.

[0518] This allows the CPU 21 to request the memory system 3 to stop writing in response to a new write request if there is a duplicate write command.

[0519] (Processing a combined write request on host 2) Fig. 47 is a flowchart showing an example of the procedure for combined write request processing executed by the CPU 21 of the host 2. The combined write request processing is processing for requesting the memory system 3 to perform a write that combines at least one duplicate write command that is incomplete and for which the first completion was a normal response and a new write request generated by the application 223 or the OS 221. The combined write request processing corresponds to step S905 of the write request control processing described above with reference to Fig. 46. In the following description with reference to Fig. 47, at least one duplicate write command that is incomplete and for which the first completion was a normal response will be simply referred to as a duplicate write command.

[0520] First, when user data is written to the NAND flash memory 5 of the memory system 3 in accordance with the duplicate write command and the current write request, the CPU 21 determines the user data (combined user data) that should ultimately be written to the NAND flash memory 5 (step S1001). The combined user data is determined according to the write request order of the duplicate write command and the current write request. In other words, the user data to be written to a certain LBA is the user data corresponding to the duplicate write command or write request that last requested writing to that LBA. Note that if the LBA range specified in the current write request completely includes the LBA range specified in the duplicate write command, the combined user data is the user data corresponding to the current write request.

[0521] The CPU 21 stores the combined user data in the data buffer 241 (step S1002). More specifically, the CPU 21 stores the user data to be written in response to the current write request in the data buffer 241. The user data to be written in response to the duplicate write command has already been stored in the data buffer 241.

[0522] A specific example will be described in which the PRP is used as information (i.e., a data pointer) indicating the storage location of the combined user data. The CPU 21 may copy user data to be included in the combined user data, among the user data to be written in response to a duplicate write command, to another storage area in the data buffer 241. For example, assume that the CPU 21 creates combined user data by sequentially combining user data stored in physical page A and physical page B. In this case, the CPU 21 generates the combined user data by copying user data stored in physical page B to another storage area (hereinafter referred to as the combined storage area) in the data buffer 241 whose physical address is continuous with that of physical page A. At this time, the combined user data is made to form a single continuous area in terms of logical addresses. Furthermore, the combined user data may be stored in the combined storage area from the middle of the first physical page. Similarly, the combined user data may be stored in the combined storage area up to the middle of the last physical page. However, the other physical pages included in the combined storage area must store the combined user data from start to finish. This makes it possible to specify the storage location of the combined user data using the PRP. In addition, if other user data is stored in another storage area in the data buffer 241 whose physical address is consecutive to physical page A, the CPU 21 generates combined user data by copying the user data stored in physical page A to another storage area in the data buffer 241 whose physical address is consecutive to physical page B.

[0523] When the SGL is used as information indicating the storage location of the combined user data, the CPU 21 does not need to copy the user data to be written in response to the duplicate write command. This is because the SGL can specify multiple storage areas starting from the middle of a physical page in the NVRAM 24 as storage locations for the user data. In this case, the CPU 21 creates an SGL that includes multiple SGL descriptors, each of which indicates multiple storage areas where the combined user data is stored.

[0524] The CPU 21 locks the stored combined user data (step S1003). Note that if user data to be written in response to the duplicate write command is used as part of the combined user data without being copied, that user data is already locked. If part of the combined user data is already locked, the CPU 21 increments the reference counter corresponding to the locked user data. The CPU 21 also newly locks the unlocked part of the combined user data. The reference counter is incremented when a new write command is issued to write the corresponding user data. The reference counter is decremented when a second completion is received for a write command to write the corresponding user data, or when the write command is aborted. Then, when the reference counter becomes 0 as a result of the decrement, the CPU 21 unlocks the corresponding user data.

[0525] Next, CPU 21 issues a write command (combined write command) that combines the overlapping write command and the current write request (step S1004). The combined write command specifies an LBA range that includes the LBA range specified in the overlapping write command and the LBA range specified in the current write request. The user data to be written in response to the combined write command is combined user data. If the LBA range specified in the current write request completely includes the LBA range specified in the overlapping write command, the combined write command is a write command that corresponds to the current write request.

[0526] The CPU 21 adds an entry corresponding to the combined write command to the lock data list 245 (step S1005), and then stores the combined write command in the submission queue 242 (step S1006), thereby completing the combined write request process.

[0527] By the above combined write request processing, the CPU 21 can request the memory system 3 to write combined user data based on the duplicate write command and the current write request. The combined user data is user data that should ultimately be written to the NAND flash memory 5 when user data is written to the NAND flash memory 5 of the memory system 3 in accordance with the duplicate write command and the current write request.

[0528] Next, the trim request control process will be described with reference to Figures 48 and 49. The trim request control process is a process for controlling writing to the NAND flash memory 5 of the memory system 3 depending on whether there is an overlap in the specified LBA range between a new trim request generated by the application 223 or the OS 221 and an issued but incomplete write command.

[0529] (Trim request control processing on host 2) 48 is a flowchart showing an example of the procedure of a trim request control process executed by the CPU 21 of the host 2. When a trim request is generated by the application 223 or the OS 221, the CPU 21 executes the trim request control process.

[0530] First, CPU 21 determines whether or not there is an entry in lock data list 245 indicating a write command (overlapping write command) that specifies an LBA range that at least partially overlaps with the LBA range specified in the trim request (step S1101). Specifically, CPU 21 determines whether or not there is an overlap between the LBA range based on the SQ entry information included in each entry of lock data list 245 and the LBA range specified in the trim request.

[0531] If there is no entry for the duplicate write command in the lock data list 245 (no in step S1101), the CPU 21 executes trim request processing based on the trim request (step S1102) and ends the trim request control processing. The trim request processing is processing by which the host 2 requests the memory system 3 to deallocate an LBA range. In the trim request processing, the CPU 21 issues a trim command to deallocate the LBA range specified in the trim request. Furthermore, since there is no entry for the duplicate write command in the lock data list 245, the CPU 21 does not perform processing to cancel or modify the write command indicated by the lock data list 245. The specific steps of the trim request processing will be described later with reference to the flowchart of FIG. 49.

[0532] If there is an entry for the duplicate write command in the lock data list 245 (yes in step S1101), the CPU 21 determines whether or not the first completions for all the duplicate write commands have been received (step S1103). If the first completion for at least one duplicate write command has not yet been received (no in step S1103), the processing by the CPU 21 returns to step S1103. In other words, the CPU 21 waits until it has received the first completions for all the duplicate write commands.

[0533] If the first completions for all duplicate write commands have been received (yes in step S1103), CPU 21 confirms that at least one completion is a normal response. That is, CPU 21 confirms that an entry for the duplicate write command remains in lock data list 245 (step S1104). If no entry for the duplicate write command remains (no in step S1104), there are no more duplicate write commands, so CPU 21 does not perform processing to cancel or modify the duplicate write command and proceeds to the trim request processing in step S1102.

[0534] If an entry for the duplicate write command remains (yes in step S1104), the CPU 21 executes trim request processing based on the trim request (step S1105). Hereinafter, the trim command issued in the trim request processing in step S1105 will be referred to as a target trim command.

[0535] The CPU 21 determines whether or not the first completion for the target trim command has been received (step S1106). If the first completion for the target trim command has not been received (no in step S1106), the process by the CPU 21 returns to step S1106. That is, the CPU 21 waits until the first completion for the target trim command is received.

[0536] If the first completion for the target trim command is received (yes in step S1106), the CPU 21 determines whether the first completion for the target trim command is a normal response (step S1107). If the first completion for the target trim command is an abnormal response (no in step S1107), the CPU 21 ends the trim request control process. In other words, because an abnormality occurred in the processing for the target trim command in the memory system 3, the CPU 21 does not perform processing to cancel or modify the duplicate write command indicated by the lock data list 245.

[0537] If the first completion for the target trim command is a normal response (yes in step S1107), the CPU 21 determines whether the LBA range specified in the target trim command (i.e., the current trim request) includes all of the LBA ranges specified in one overlapping write command (step S1108). If the LBA range specified in the target trim command includes all of the LBA ranges specified in one overlapping write command (yes in step S1108), the CPU 21 issues an abort command for the overlapping write command (step S1109). Then, the CPU 21 stores the issued abort command in the submission queue 242 (step S1110). This enables the CPU 21 to request the memory system 3 to abort writing of user data that should be performed in response to the overlapping write command.

[0538] If the LBA range specified by the target trim command includes only a portion of the LBA range specified by one overlapping write command (no in step S1108), the CPU 21 issues a modification command for the overlapping write command (step S1111). Then, the CPU 21 stores the issued modification command in the submission queue 242 (step S1112). This enables the CPU 21 to request the memory system 3 to cancel a portion of the writing of user data that should be performed in response to the overlapping write command.

[0539] Next, CPU 21 determines whether there is another duplicate write command using lock data list 245 (step S1113). If there is another duplicate write command (yes in step S1113), the processing by CPU 21 returns to step S1108. As a result, either an abort command or a modify command is issued for the other duplicate write command.

[0540] If there is no other overlapping write command (No in step S1113), the CPU 21 ends the trim request control process.

[0541] By the above trim request control process, when a trim request is generated by the application 223 or the OS 221, if there is an incomplete write command (duplicate write command) that specifies an LBA range that overlaps with the LBA range specified in the trim request, the CPU 21 can request the memory system 3 to cancel or modify the duplicate write command.

[0542] Specifically, the CPU 21 uses the lock data list 245 to determine whether there is a duplicate write command. If there is a duplicate write command, the CPU 21 uses the lock data list 245 to determine whether the LBA range specified in the trim request includes the entire LBA range specified in the duplicate write command, or only a portion of it. If the LBA range specified in the trim request includes the entire LBA range specified in the duplicate write command, the CPU 21 requests the memory system 3 to cancel the duplicate write command. If the LBA range specified in the trim request includes only a portion of the LBA range specified in the duplicate write command, the CPU 21 requests the memory system 3 to modify the duplicate write command.

[0543] As a result, if there is an overlapping write command for a trim request, the CPU 21 can request the memory system 3 to stop writing in response to the overlapping write command or to cancel part of the writing.

[0544] (Host 2 processing a trim request to memory system 3) 49 is a flowchart showing an example of the procedure for trim request processing executed by the CPU 21 of the host 2. The trim request processing is processing by which the host 2 requests the memory system 3 to release the allocation of an LBA range (i.e., trim). The trim request processing corresponds to steps S1102 and S1105 of the trim request control processing described above with reference to FIG.

[0545] First, CPU 21 stores range information indicating an LBA range to be deallocated in data buffer 241 (step S1201). The range information indicates one or more LBA ranges. CPU 21 locks the range information stored in data buffer 241 (step S1202). This prevents the storage area in which the range information is stored from being unintentionally released.

[0546] The CPU 21 issues a trim command (hereinafter referred to as a first trim command) for canceling the allocation of the LBA range based on the range information stored in the data buffer 241 (step S1203).

[0547] Next, the CPU 21 adds an entry corresponding to the first trim command to the lock data list 245 (step S1204). The added entry includes, for example, SQ entry information corresponding to the first trim command and data area management information. The SQ entry information corresponding to the first trim command is information that represents the first trim command. More specifically, the SQ entry information corresponding to the first trim command is information that is stored in the submission queue 242 to cause the memory system 3 to execute processing according to the first trim command. Furthermore, the data area management information corresponding to the first trim command is information that can identify a storage area in the data buffer 241 in which range information corresponding to the first trim command is stored.

[0548] Then, the CPU 21 stores the first trim command (that is, the SQ entry information representing the first trim command) in the submission queue 242 (step S1205).

[0549] After storing the first trim command in the submission queue 242 in step S1205, the CPU 21 may execute step S1204 to add an entry corresponding to the first trim command to the lock data list 245. Alternatively, the CPU 21 may execute step S1204 and step S1205 in parallel.

[0550] Through the above trim request processing, the CPU 21 can request the memory system 3 to perform a trim based on the range information stored in the data buffer 241. The CPU 21 can also manage information related to the trim requested of the memory system 3 (i.e., information related to the issued trim command) using the lock data list 245.

[0551] (Processing for trimming LBA range in memory system 3) 50 is a flowchart showing an example of the procedure for trim control processing executed by the CPU 12 of the memory system 3. The trim control processing is processing for accepting a trim command issued by the host 2 and releasing the allocation of a specified LBA range. The CPU 12 executes the trim control processing in response to acquiring the trim command issued by the host 2 from the submission queue 242. Here, the trim command acquired from the submission queue 242 is referred to as a target trim command.

[0552] First, the CPU 12 notifies the host 2 of the first completion for the target trim command (step S1301). The first completion for the target trim command includes the command ID of the target trim command.

[0553] Next, the CPU 12 determines whether or not trimming can be started (step S1302). More specifically, the CPU 12, for example, obtains an abort command or a modification command for the duplicate write command corresponding to the target trim command from the submission queue 242, processes the command, notifies the host 2 of a completion, and if writing to the NAND flash memory 5 in accordance with the duplicate write command has started, determines that trimming can be started when the writing is completed. Note that with respect to a write command received after returning the first completion for the target trim command, the CPU 12 does not start the write process to the NAND flash memory 5 until the target trim command is completed, even after returning the first completion for the write command to the host 2.

[0554] As with the write command described above, if an abort command or modification command for the write command (i.e., the duplicate write command) is scheduled to be sent following the target trim command, a flag indicating that it will be sent may be added to the trim command. This allows the CPU 12 to reliably identify and process the abort command or modification command for the duplicate write command. If multiple abort commands or modification commands are sent, flags indicating that further abort commands or modification commands are scheduled to be sent may be added to those abort commands or modification commands.

[0555] If trimming cannot be started (No in step S1302), the processing by the CPU 12 returns to step S1302.

[0556] If trimming can be started (step S1302: yes), the CPU 12 acquires range information specified in the target trim command from the data buffer 241 of the host 2 (step S1303). The range information indicates one or more LBA ranges. The CPU 12 releases the allocation of one or more LBA ranges indicated by the range information (step S1304). That is, the CPU 12 updates the logical-physical address conversion table 62 to indicate that one or more LBA ranges indicated by the range information are not mapped to any physical address in the NAND flash memory 5. The CPU 12 then notifies the host 2 of a second completion for the target trim command (step S1305), and ends the trim control process.

[0557] When the CPU 12 receives a special flash command, it writes user data corresponding to all of the received write commands with padding to the NAND flash memory 5, and completes these write commands. This satisfies the condition of step S1302, and the CPU 12 performs the processes of steps S1303 to S1305. After notifying the host 2 of the second completion for all of the trim commands, the CPU 12 notifies the host 2 of the completion of the special flash command.

[0558] By the above trim control process, the CPU 12 can deallocate the designated LBA range in response to a trim command received from the host 2.

[0559] (Processing based on response to trim command from memory system 3 in host 2) 51 is a flowchart showing an example of the procedure of a trim response reception process executed by the CPU 21 of the host 2. The trim response reception process is a process based on a response (completion) to a trim command received from the m...

Claims

1. An information processing device connectable to a memory system, a non-volatile memory; storing first data in the nonvolatile memory; storing, in the nonvolatile memory, first management data associated with the first data and including information corresponding to a first write command specifying a first logical address range; transmitting the first write command to the memory system for the first time; adding, to the first management data, information indicating that the first response to the first write command transmitted for the first time has been received in response to receiving from the memory system a first response to the first write command transmitted for the first time; and after receiving the first response, in response to receiving a second response to the first write command from the memory system, deleting the first data and the first management data from the nonvolatile memory. a processor; The processor: when a request is made to write second data to a third logical address range including a second logical address range that is at least a part of the first logical address range or to deallocate the third logical address range before receiving the second response to the first write command, sending a command to the memory system to cancel writing of the first data to at least the second logical address range in the writing of the first data to the first logical address range in response to the first write command; and further configured to update or delete the first management data if the write to the second logical address range is successfully stopped. Information processing device.

2. The processor is configured to delete the first data and the first management data from the nonvolatile memory in response to receiving the second response from the memory system as a second response to the first write command transmitted the first time after receiving the first response. The information processing device according to claim 1 .

3. The processor: sending the first write command to the memory system a second time after receiving the first response; and in response to receiving the second response from the memory system as a response to the second transmitted first write command, deleting the first data and the first management data from the nonvolatile memory. The information processing device according to claim 1 .

4. When the third logical address range includes the entire first logical address range, The processor: If it is requested to write the second data to the third logical address range before receiving the second response to the first write command transmitted for the first time, storing the second data in the nonvolatile memory; storing second management data in the nonvolatile memory, the second management data being associated with the second data and including information corresponding to a second write command specifying the third logical address range; further configured to transmit the second write command to the memory system a first time; The processor: when a third response to the first transmitted second write command is received from the memory system; adding information indicating that the third response to the second write command transmitted for the first time has been received to the second management data; sending a command to the memory system to stop writing the first data to the first logical address range in response to the first write command; If the writing to the first logical address range is successfully stopped, the first data and the first management data are deleted from the nonvolatile memory; and further configured to delete the second data and the second management data from the nonvolatile memory in response to receiving a fourth response to the second write command from the memory system after receiving the third response. The information processing device according to claim 1 .

5. the first logical address range includes the second logical address range and one or more fourth logical address ranges that are different from the second logical address range; If the third logical address range includes the second logical address range but does not include the fourth logical address range, The processor: If it is requested to write the second data to the third logical address range before receiving the second response to the first write command transmitted for the first time, storing the second data in the nonvolatile memory; storing second management data in the nonvolatile memory, the second management data being associated with the second data and including information corresponding to a second write command specifying the third logical address range; further configured to transmit the second write command to the memory system a first time; The processor: when a third response to the first transmitted second write command is received from the memory system; adding information indicating that the third response to the second write command transmitted for the first time has been received to the second management data; sending a command to the memory system to stop writing the first data to the second logical address range in response to the first write command; if the writing to the second logical address range is successfully stopped, updating the first management data so that the first write command specifies the one or more fourth logical address ranges and does not specify the second logical address range; and further configured to delete the second data and the second management data from the nonvolatile memory in response to receiving a fourth response to the second write command from the memory system after receiving the third response. The information processing device according to claim 1 .

6. The processor: If the write to the second logical address range is successfully aborted, the first management data is further configured to update the first write command so that the first write command specifies the one or more fourth logical address ranges and does not specify the second logical address range. The information processing device according to claim 5 .

7. the first logical address range includes the second logical address range and one or more fourth logical address ranges that are different from the second logical address range; when the first data includes one or more first data portions to be written to the one or more fourth logical address ranges, respectively, and a second data portion to be written to the second logical address range, The processor: If it is requested to write the second data to the third logical address range before receiving the second response to the first write command transmitted for the first time, storing the second data in the nonvolatile memory; storing second management data in the nonvolatile memory, the second management data being associated with the second data and the one or more first data sections, and including information corresponding to a second write command that specifies a logical address range including the one or more fourth logical address ranges and the third logical address range; further configured to transmit the second write command to the memory system a first time; The processor: when a third response to the first transmitted second write command is received from the memory system; adding information indicating that the third response to the second write command transmitted for the first time has been received to the second management data; sending a command to the memory system to stop writing the first data to the first logical address range in response to the first write command; If the writing to the first logical address range is successfully stopped, the first management data and at least the second data portion are deleted from the nonvolatile memory; and further configured to delete the second data, the one or more first data portions, and the second management data from the nonvolatile memory in response to receiving a fourth response to the second write command from the memory system after receiving the third response. The information processing device according to claim 1 .

8. The processor is configured to delete the second data and the second management data from the nonvolatile memory in response to receiving the fourth response from the memory system as a second response to the first transmitted second write command after receiving the third response. The information processing device according to claim 4 .

9. The processor: after receiving the third response, transmitting the second write command to the memory system for a second time; and in response to receiving the fourth response from the memory system as a response to the second write command transmitted for the second time, deleting the second data and the second management data from the nonvolatile memory. The information processing device according to claim 4 .

10. When the third logical address range includes the entire first logical address range, The processor: If a request is made to deallocate the third logical address range before the second response to the first write command transmitted for the first time is received, storing third data indicating the third logical address range in the nonvolatile memory; storing third management data including information corresponding to a first release command specifying the third logical address range in the nonvolatile memory; further configured to send the first release command to the memory system a first time; The processor: when a fifth response to the first release command transmitted for the first time is received from the memory system; adding information indicating that the fifth response to the first release command transmitted the first time has been received to the third management data; sending a command to the memory system to stop writing the first data to the first logical address range in response to the first write command; If the writing to the first logical address range is successfully stopped, the first data and the first management data are deleted from the nonvolatile memory; and further configured to delete the third data and the third management data from the nonvolatile memory in response to receiving a sixth response to the first release command from the memory system after receiving the fifth response. The information processing device according to claim 1 .

11. the first logical address range includes the second logical address range and one or more fourth logical address ranges that are different from the second logical address range; If the third logical address range includes the second logical address range but does not include the fourth logical address range, The processor: If a request is made to deallocate the third logical address range before receiving the second response to the first write command transmitted for the first time, storing third data indicating the third logical address range in the nonvolatile memory; storing third management data including information corresponding to a first release command specifying the third logical address range in the nonvolatile memory; further configured to send the first release command to the memory system a first time; The processor: when a fifth response to the first release command transmitted for the first time is received from the memory system; adding information indicating that the fifth response to the first release command transmitted the first time has been received to the third management data; sending a command to the memory system to stop writing the first data to the second logical address range in response to the first write command; if the writing to the second logical address range is successfully stopped, updating the first management data so that the first write command specifies the one or more fourth logical address ranges and does not specify the second logical address range; and further configured to delete the third data and the third management data from the nonvolatile memory in response to receiving a sixth response to the first release command from the memory system after receiving the fifth response. The information processing device according to claim 1 .

12. The processor: If the write to the second logical address range is successfully aborted, the first management data is further configured to update the first write command so that the first write command specifies the one or more fourth logical address ranges and does not specify the second logical address range. The information processing device according to claim 11.

13. The processor is configured to delete the third data and the third management data from the nonvolatile memory in response to receiving the sixth response from the memory system as a second response to the first release command transmitted the first time after receiving the fifth response. The information processing device according to any one of claims 10 to 12.

14. The processor: sending the first release command to the memory system a second time after receiving the fifth response; and in response to receiving the sixth response from the memory system as a response to the second transmitted first release command, deleting the third data and the third management data from the nonvolatile memory. The information processing device according to any one of claims 10 to 12.

15. An information processing device connectable to a memory system, a non-volatile memory; reading one or more first data portions stored in a first logical address range from the memory system; storing the one or more first data portions that have been read in the non-volatile memory; After one or more consecutive second data sections of the one or more first data sections stored in the nonvolatile memory are rewritten, storing first management data in the nonvolatile memory, the first management data including information corresponding to a first write command that is associated with the one or more second data sections and that specifies a second logical address range corresponding to the one or more second data sections; transmitting the first write command to the memory system for the first time; adding, to the first management data, information indicating that the first response to the first write command transmitted for the first time has been received in response to receiving from the memory system a first response to the first write command transmitted for the first time; and after receiving the first response, in response to receiving a second response to the first write command from the memory system, deleting the first management data from the nonvolatile memory. a processor; The processor: if a third data section of the one or more second data sections is rewritten before receiving the second response, sending a command to the memory system to stop writing of the one or more second data sections to the second logical address range in response to the first write command to a third logical address range corresponding to the third data section; and further configured to update or delete the first management data if the writing to the third logical address range is successfully stopped. Information processing device.

16. The processor is configured to delete the first management data from the nonvolatile memory in response to receiving the second response from the memory system as a second response to the first write command transmitted the first time after receiving the first response. The information processing device according to claim 15.

17. The processor: sending the first write command to the memory system a second time after receiving the first response; and in response to receiving the second response from the memory system as a response to the second transmitted first write command, deleting the first management data from the nonvolatile memory. The information processing device according to claim 15.

18. When the third data section includes the entirety of the one or more second data sections, The processor is configured to delete the first management data from the non-volatile memory if the write to the third logical address range is successfully stopped.

18. The information processing device according to claim 15.

19. the third data section includes either the leading data section or the trailing data section of the one or more second data sections, When the second logical address range includes the third logical address range and the fourth logical address range, The processor is further configured, if the write to the third logical address range is successfully aborted, to update the first management data so that the first write command does not specify the third logical address range, is associated with a data portion of the one or more second data portions that corresponds to the fourth logical address range, and specifies the fourth logical address range.

18. The information processing device according to claim 15.

20. the third data section does not include either the leading data section or the trailing data section of the one or more second data sections, When the second logical address range includes the third logical address range and one or more fourth logical address ranges, If the processor successfully stops writing to the third logical address range, and updating the first management data so that the first write command does not specify the third logical address range, is associated with data portions of the one or more second data portions that correspond to the one or more fourth logical address ranges, and specifies the one or more fourth logical address ranges.

18. The information processing device according to claim 15.

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