Storage system, data processing method, and device

Abstract

In order to improve the efficiency and reliability of data services without performing redundant data transmission between controller nodes, a storage system, a data processing method, and an apparatus are disclosed. The storage system includes a first controller and a second controller, and the two controllers communicate with a memory by sharing a same interface card. The shared interface card stores data from the first controller in a cache of the shared interface card, and asynchronously holds the data in the cache of the shared interface card in the memory. After the first controller fails, the data from the first controller stored by the shared interface device can be read from the cache (or memory) of the interface device by the interface device and provided to the second controller.

Description

[Technical Field]

[0001] This application relates to the field of computer technology, and in particular to storage systems, data processing methods and devices. [Background technology]

[0002] Dual-controller storage systems are widely used to provide users with reliable data services. A dual-controller storage system includes at least one dual-controller unit, and each dual-controller unit includes at least two controllers that share storage resources. FIG. 1 shows an example of a dual-controller storage system. As shown in FIG. 1, the dual-controller unit may include a first controller and a second controller, and the first controller and the second controller share at least one memory. The first controller may write data to the shared memory based on a write request sent by an application server. If the first controller fails, the second controller may query the shared memory for the data written by the first controller to ensure the availability of the data written by the first controller.

[0003] Because the memory access latency of a cache is typically much shorter than that of external memory, controllers typically use their own caches to asynchronously store data in shared memory. In the dual-controller system shown in FIG. 1, to ensure the availability of data in the cache of the first controller after the first controller fails, data updated by the first controller in its local cache must be synchronized in real time with the cache of the second controller. In this way, the second controller can find the data in the cache of the second controller and in the shared memory and return query results to the application server. The synchronization process requires redundant data transmission between controller nodes in the storage system, resulting in waste of transmission and storage resources in the storage system. Summary of the Invention [Means for solving the problem]

[0004] The present application provides a storage system, a data processing method, and an apparatus to improve the efficiency and reliability of data services without performing redundant data transmission between controller nodes.

[0005] According to a first aspect, the present application provides a storage system. The storage system includes a first controller and a second controller, the first controller and the second controller separately communicating with at least one memory through a shared interface device having a cache disposed therein. The first controller is configured to send a write command to the shared interface device. The shared interface device is configured to temporarily store first data to be written in the cache as instructed by the write command, and is further configured to asynchronously write the first data temporarily stored in the cache to the first memory in the at least one memory. The first memory may include one or more memories.

[0006] The first data may be all or part of the data to be written as instructed by the write instruction. When the first data is part of the data to be written as instructed by the write instruction, the method of storing other data (excluding the first data) to be written as instructed by the write instruction by the shared interface device is not limited in the present application. Optionally, the shared interface device may synchronously write the other data to be written as instructed by the write instruction to the first memory or a memory (other than the first memory) in the at least one memory.

[0007] Optionally, the second controller is configured to send a write command to the shared interface device to instruct it to write the third data. The shared interface device is further configured to temporarily store the third data in a cache, and to asynchronously write the third data temporarily stored in the cache to one or more memories in the at least one memory. For example, the shared interface device may asynchronously write the third data to the first memory.

[0008] The third data may be all or part of the data to be written as instructed by the write instruction. When the third data is part of the data to be written as instructed by the write instruction, the method of storing other data (excluding the third data) to be written as instructed by the write instruction by the shared interface device is not limited in the present application. Optionally, the shared interface device may synchronously write the other data to be written as instructed by the write instruction to the first memory or a memory (other than the first memory) in the at least one memory.

[0009] The first controller and the second controller may together use a cache of the shared interface device to asynchronously write data to a first memory connected to the shared interface device, which helps to improve utilization of the cache resources of the shared interface device and utilization of the memory resources connected to the shared interface device.

[0010] Optionally, the second controller is configured to send a read instruction to the shared interface device after the first controller fails, the read instruction instructing it to query the second data, where the second data may be all or a portion of the first data. The shared interface device is further configured to retrieve all or a portion of the second data from the cache and provide all or a portion of the second data to the second controller in accordance with the read instruction. When the shared interface device retrieves a portion of the second data from the cache and other data in the second data is retained or backed up, the shared interface device may query and retrieve other data in the second data from a memory (e.g., the first memory) connected to the shared interface device.

[0011] The second data may be all or part of the data to be read as instructed by the read instruction. When the second data is part of the data to be read as instructed by the read instruction, the method by which the shared interface device obtains other data (excluding the second data) to be read as instructed by the read instruction is not limited in the present application. Optionally, the shared interface device may obtain other data from one or more memories in the at least one memory.

[0012] Meanwhile, because the access latency of the cache of the shared interface device is shorter than the access latency of the memory connected to the shared interface device, the shared interface device uses the cache to temporarily store the first data for the first controller and asynchronously writes the first data to the first memory connected to the shared interface device. This helps reduce the storage latency of the first data and improve the efficiency of the data service provided by the storage system. Meanwhile, the second controller does not need to perform mirror backup for the data written to the cache by the first controller. After a failure of the first controller occurs, the shared interface device can provide the data written for the first controller in the cache to the second controller. This helps ensure the availability of the data in the cache without adding redundant data transmission between nodes and improves the reliability of the data service provided by the storage system.

[0013] Optionally, the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller, and a query range from which the shared interface device obtains all or a portion of the second data in the cache includes the first partition and the second partition.

[0014] The fact that the first partition is different from the second partition means that the storage space corresponding to the first partition in the cache does not overlap with the storage space corresponding to the second partition in the cache. This helps reduce contention that occurs when the shared interface device writes data to the cache for different controllers, improving the reliability of the data service provided by the storage system. After the shared interface device receives a read command, it may be difficult for the shared interface device to determine the location of the second data in the cache. To improve the availability of the data in the cache, the query range in which the shared interface device queries for the second data may include the first partition and the second partition. This helps the second controller retrieve the data written for the first controller and the second controller in the cache.

[0015] Optionally, the write instruction instructs writing data to the first memory.

[0016] Optionally, the shared interface device is specifically configured to temporarily store first data in the first partition, temporarily store third data in the second partition, and successively transmit the first data temporarily stored in the first partition and the third data temporarily stored in the second partition to the first memory. Optionally, the write instruction sent by the first controller may instruct the first data to be written to the first memory, and the write instruction sent by the second controller may instruct the third data to be written to the first memory.

[0017] The data in the first partition and the data in the second partition that are to be written to the same memory are sent to the first memory consecutively. This helps the first memory to execute the writing task of the first data and the second data consecutively. If the storage locations of the first data and the second data in the first memory are adjacent or even consecutive, the change in the writing location of the first memory is reduced, and the storage efficiency of the first memory is improved.

[0018] Optionally, the at least one memory further includes a second memory, wherein a memory access latency of the second memory is shorter than a memory access latency of the first memory. The shared interface device is further configured to synchronize and back up the first data to the second memory after receiving a write instruction. Optionally, the shared interface device may retrieve all or a portion of the second data from the second memory according to a read instruction when the cache is abnormal, and provide all or a portion of the second data to the second controller.

[0019] The data written to the cache is synchronously backed up to a second memory connected to the shared interface device. In this way, even if the cache is abnormal, for example, if the data in the cache is not retained or is lost, the shared interface device can still find the data in the second memory. This helps to improve the availability of the data in the cache and the reliability of the data service provided by the storage system.

[0020] Optionally, the storage system further includes a third memory connected to the first controller. The first controller is further configured to back up the first data in the third memory and, when the cache is abnormal, transfer the data backed up in the third memory to a fourth memory in the at least one memory via the shared interface device. Optionally, when the cache is abnormal, the shared interface device is further configured to retrieve all or a portion of the second data from the fourth memory according to a read command and provide all or a portion of the second data to the second controller. The fourth memory may be the first memory, the second memory, or another memory connected to the shared interface device.

[0021] In this way, even if the cache is abnormal, for example, the cached data is lost, the shared interface device can still find the cached data in at least one memory, which helps to improve the availability of the cached data and the reliability of the data service provided by the storage system.

[0022] Optionally, the data includes service data and / or metadata of the service data, the service data being data to be written as requested by a data write request received by the first controller.

[0023] Optionally, the shared interface device is an interface card or a disk enclosure, the interface card being disposed (e.g., inserted) in the first controller or the second controller, and the disk enclosure being configured to incorporate at least one memory.

[0024] Optionally, the shared interface device communicates with the first controller using a Peripheral Component Interconnect Express PCIe protocol or a Serial Attached Small Computer System Interface SAS protocol.

[0025] Optionally, the shared interface device communicates with the second controller using a Peripheral Component Interconnect Express PCIe protocol or a SAS protocol.

[0026] Optionally, each memory in the at least one memory has only a single port for communicating with the shared interface device, and port reconfiguration does not need to be performed on the memory, which helps to reduce costs.

[0027] According to a second aspect, the present application provides a data processing method, which may be applied to a storage system. The storage system includes a first controller and a second controller, and the first controller and the second controller separately communicate with at least one memory through a shared interface device in which a cache is arranged. The method may include the first controller sending a write command to the shared interface device. The shared interface device temporarily stores first data to be written in the cache as instructed by the write command, and then asynchronously writes the first data temporarily stored in the cache to the first memory in the at least one memory.

[0028] Optionally, the second controller may send a write command to the shared interface device to instruct it to write the third data. The shared interface device may temporarily store the third data in a cache and asynchronously write the third data temporarily stored in the cache to one or more memories in the at least one memory. For example, the shared interface device may asynchronously write the third data to the first memory.

[0029] Optionally, the second controller sends a read instruction to the shared interface device after the first controller fails, the read instruction instructing to query second data, the second data being all or a part of the first data, and the shared interface device retrieves all or a part of the second data from a cache according to the read instruction, and provides all or a part of the second data to the second controller.

[0030] Optionally, the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller, and a query range from which the shared interface device obtains all or a portion of the second data in the cache includes the first partition and the second partition.

[0031] Optionally, temporarily storing the first data in the cache by the shared interface device includes temporarily storing the first data in the first partition by the shared interface device. Temporarily storing the third data in the cache by the shared interface device includes temporarily storing the third data in the second partition by the shared interface device. Asynchronously writing the first data and the third data temporarily stored in the cache to the first memory by the shared interface device may include sequentially transmitting the first data temporarily stored in the first partition and the third data temporarily stored in the second partition to the first memory by the shared interface device. Optionally, the write instruction sent by the first controller may instruct writing the first data to the first memory, and the write instruction sent by the second controller may instruct writing the third data to the first memory.

[0032] Optionally, the at least one memory further includes a second memory, wherein a memory access latency of the second memory is shorter than a memory access latency of the first memory. The method further includes, by the shared interface device, synchronizing and backing up the first data to the second memory after receiving the write instruction. When the cache is abnormal, the shared interface device retrieves all or a portion of the second data from the second memory according to the read instruction and provides all or a portion of the second data to the second controller.

[0033] Optionally, the storage system further includes a third memory connected to the first controller, and the method further includes the first controller backing up the first data in the third memory. When the cache is abnormal, the first controller transfers the data backed up in the third memory to a fourth memory in the at least one memory via the shared interface device. When the cache is abnormal after the shared interface device receives a read instruction, the shared interface device retrieves all or a portion of the second data from the fourth memory in accordance with the read instruction and provides all or a portion of the second data to the second controller.

[0034] Optionally, the data includes service data and / or metadata of the service data, the service data being data to be written as requested by a data write request received by the first controller.

[0035] Optionally, the shared interface device is an interface card or a disk enclosure, the interface card being inserted into the first controller or the second controller, and the disk enclosure being configured to incorporate at least one memory.

[0036] Optionally, the shared interface device communicates with the first controller and / or the second controller using a Peripheral Component Interconnect Express PCIe protocol.

[0037] Optionally, each memory in the at least one memory has only a single port for communicating with the shared interface device.

[0038] The first controller, the second controller, and the shared interface device in the storage system provided in the first aspect may be configured to execute the method provided in the second aspect. Therefore, for the technical effects provided by the method provided in the second aspect, please refer to the technical effects provided by the corresponding storage system described above. Details will not be described again here.

[0039] According to a third aspect, the present application provides a data processing method, which may be applied to a shared interface device in a storage system. The storage system includes a first controller and a second controller, and the first controller and the second controller separately communicate with at least one memory through a shared interface device in which a cache is arranged. The method includes the shared interface device receiving a write command sent by the first controller to instruct the shared interface device to write first data. The shared interface device temporarily stores the first data in the cache and then asynchronously writes the first data temporarily stored in the cache to the first memory in the at least one memory.

[0040] Optionally, the method further includes receiving, by the shared interface device, a write command sent by the second controller to write third data, the write command instructing the shared interface device to temporarily store the third data in a cache, and then asynchronously write the third data temporarily stored in the cache to one or more memories (e.g., the first memory) in the at least one memory.

[0041] Optionally, the shared interface device receives a read instruction sent by the second controller after the first controller fails, the read instruction instructing to query second data, the second data being all or a part of the first data, and the shared interface device retrieves all or a part of the second data from a cache according to the read instruction, and provides all or a part of the second data to the second controller.

[0042] Optionally, the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller, and a query range from which the shared interface device obtains all or a portion of the second data in the cache includes the first partition and the second partition.

[0043] Optionally, temporarily storing the first data in the cache by the shared interface device includes temporarily storing the first data in the first partition by the shared interface device. Temporarily storing the third data in the cache by the shared interface device includes temporarily storing the third data in the second partition by the shared interface device. Asynchronously writing the first data and the third data temporarily stored in the cache to the first memory by the shared interface device may include sequentially transmitting the first data temporarily stored in the first partition and the third data temporarily stored in the second partition to the first memory by the shared interface device. Optionally, the write instruction sent by the first controller may instruct writing the first data to the first memory, and the write instruction sent by the second controller may instruct writing the third data to the first memory.

[0044] Optionally, the at least one memory further includes a second memory, wherein a memory access latency of the second memory is shorter than a memory access latency of the first memory. The method further includes, by the shared interface device, synchronizing and backing up the first data to the second memory after receiving the write instruction. When the cache is abnormal, the shared interface device retrieves all or a portion of the second data from the second memory according to the read instruction and provides all or a portion of the second data to the second controller.

[0045] Optionally, the storage system further includes a third memory connected to the first controller. The method further includes, when the cache is abnormal after the shared interface device receives the read command, the shared interface device obtains all or a portion of the second data from the connected fourth memory in accordance with the read command and provides all or a portion of the second data to the second controller. All or a portion of the second data in the fourth memory is transferred by the first controller from the third memory to the fourth memory via the shared interface device after the cache becomes abnormal, and the data in the third memory includes the first data backed up by the first controller.

[0046] Optionally, the data includes service data and / or metadata of the service data, the service data being data to be written as requested by a data write request received by the first controller.

[0047] Optionally, the shared interface device is an interface card or a disk enclosure, the interface card being inserted into the first controller or the second controller, and the disk enclosure being configured to incorporate at least one memory.

[0048] Optionally, the shared interface device communicates with the first controller and / or the second controller using a Peripheral Component Interconnect Express PCIe protocol.

[0049] Optionally, each memory in the at least one memory has only a single port for communicating with the shared interface device.

[0050] The shared interface device provided in the first aspect may be configured to execute the method provided in the third aspect. Therefore, for the technical effects provided by the method provided in the third aspect, please refer to the technical effects provided by the corresponding storage system described above. Details will not be described again here.

[0051] According to a fourth aspect, the present application provides a shared interface device, wherein a cache may be disposed in the shared interface device. The shared interface device may include a receiving module, a storage module, and a query module. The receiving module is configured to receive a write command transmitted by a first controller, the write command instructing the first controller to write first data. The first controller and the second controller separately communicate with at least one memory via the shared interface device. The storage module is configured to temporarily store the first data in a cache of the storage module, and is further configured to asynchronously write the first data temporarily stored in the cache to the first memory in the at least one memory.

[0052] Optionally, the receiving module is further configured to receive a write command sent by the second controller, instructing to write the third data. The storage module is configured to temporarily store the first data in a cache of the storage module, and is further configured to asynchronously write the third data temporarily stored in the cache to one or more memories in the at least one memory. For example, the storage module may asynchronously write the third data to the first memory.

[0053] Optionally, the receiving module is further configured to receive a read instruction sent by the second controller after the first controller fails, the read instruction instructing to query second data, the second data being all or a portion of the first data. The query module is configured to retrieve all or a portion of the second data from the cache according to the read instruction, and provide all or a portion of the second data to the second controller.

[0054] Optionally, the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller, and a query range from which the query module obtains all or a portion of the second data in the cache includes the first partition and the second partition.

[0055] Optionally, the storage module is specifically configured to temporarily store the first data in the first partition, temporarily store the third data in the second partition, and successively transmit the first data temporarily stored in the first partition and the third data temporarily stored in the second partition to the first memory. Optionally, the write instruction sent by the first controller may instruct the first data to be written to the first memory, and the write instruction sent by the second controller may instruct the third data to be written to the first memory.

[0056] Optionally, the at least one memory further includes a second memory, and a memory access latency of the second memory is shorter than a memory access latency of the first memory. The storage module is further configured to: synchronize and back up the first data to the second memory after receiving a write instruction, and, when the cache is abnormal, retrieve all or a portion of the second data from the second memory according to a read instruction, and provide all or a portion of the second data to the second controller.

[0057] Optionally, the storage system further includes a third memory connected to the first controller. The query module is further configured to, after the receiving module receives the read command, when the cache is abnormal, obtain all or a portion of the second data from the connected fourth memory in accordance with the read command and provide all or a portion of the second data to the second controller. All or a portion of the second data in the fourth memory is transferred by the first controller from the third memory to the fourth memory via the shared interface device after the cache becomes abnormal, and the data in the third memory includes the first data backed up by the first controller.

[0058] Optionally, the data includes service data and / or metadata of the service data, the service data being data to be written as requested by a data write request received by the first controller.

[0059] Optionally, the shared interface device is an interface card or a disk enclosure, the interface card being inserted into the first controller or the second controller, and the disk enclosure being configured to incorporate at least one memory.

[0060] Optionally, the shared interface device communicates with the first controller and / or the second controller using a Peripheral Component Interconnect Express PCIe protocol.

[0061] Optionally, each memory in the at least one memory has only a single port for communicating with the shared interface device.

[0062] The shared interface device provided in the fourth aspect may have the function of the shared interface device in the storage system provided in the first aspect. Therefore, for the technical effects provided by the shared interface device provided in the fourth aspect, please refer to the technical effects provided by the corresponding shared interface device described above. Details will not be described again here.

[0063] According to a fifth aspect, the present application provides a computing device, wherein a first controller and a second controller are in separate communication with at least one memory via the computing device, the computing device including a memory and a processor, the memory including a cache, and the processor executing computer instructions stored in the memory to enable the computing device to perform the method described in any possible implementation of the third aspect.

[0064] Optionally, the computing device is an interface card or a disk enclosure, the interface card being inserted into the first controller or the second controller, and the disk enclosure being configured to incorporate at least one memory.

[0065] Optionally, the computing device communicates with the first controller and / or the second controller using a Peripheral Component Interconnect Express PCIe protocol.

[0066] According to a sixth aspect, the present application provides a computer-readable storage medium comprising instructions which, when executed on a computing device, enable the computing device to perform a method as set forth in any possible implementation of the third aspect.

[0067] An eleventh aspect of the present application provides a computer program product, the computer program product including program code that, when executed by a computing device, can perform the method described in any possible implementation of the third aspect of the present application.

[0068] The apparatus provided in the present application may be configured to execute the method steps executed by the shared interface device in the aforementioned storage system. Therefore, for the technical effects that can be obtained by the apparatus of the present application, please refer to the technical effects that can be obtained by the aforementioned storage system. Details will not be described again here.

[0069] The first controller and the second controller in the claims and summary of the present application may be, for example, any two different controllers of the storage nodes in the description of the embodiments of the present application. For example, the first controller may be controller a and the second controller may be controller b, or the first controller may be controller b and the second controller may be controller a.

[0070] The shared interface device in the claims and summary of the present application may be, for example, any shared interface device connected to at least two controllers of a storage node in the description of the embodiments of the present application. For example, the shared interface device may be shared interface device a or shared interface device b. For example, the shared interface device may be shared interface device a, and the shared interface device may specifically be interface card a or disk enclosure a.

[0071] The at least one memory in the claims and summary of the present application may be, for example, at least one memory connected to the shared interface device a or the shared interface device b in the description of the embodiments of the present application. For example, the shared interface device is the interface card a. The at least one memory may include memory a1, memory a2, and memory a3.

[0072] The first memory in the claims and summary of the present application may be, for example, any one or more memories connected to the shared interface device a or the shared interface device b in the description of the embodiments of the present application. For example, the shared interface device is the interface card a. The first memory may include memory a2.

[0073] For example, the first controller and the second controller are the controller a and the controller b, respectively, mentioned in the description of the embodiments of the present application. The write command sent by the first controller in the claims and summary of the present application may be, for example, the write command 1 or the write command 1-1 mentioned in the description of the embodiments of the present application, and the write command sent by the second controller may be, for example, the write command 2 or the write command 2-2 mentioned in the description of the embodiments of the present application.

[0074] It is still used as an example that the first controller and the second controller are the controller a and the controller b, respectively, mentioned in the description of the embodiments of the present application. The first data and the third data in the claims and the summary of the invention of the present application may be, for example, the target data 1 and the target data 2, respectively, mentioned in the description of the embodiments of the present application.

[0075] The read instruction in the claims and summary of the present application may be, for example, read instruction 1, read instruction 1-1, read instruction 2, or read instruction 2-1 mentioned in the description of the embodiments of the present application. The second data in the claims and summary of the present application may be, for example, target data 3 or target data 4 mentioned in the description of the embodiments of the present application. Optionally, target data 3 or target data 4 may be all or a part of target data 1, or target data 3 or target data 4 may be all or a part of target data 2.

[0076] For example, in the description of the embodiments of the present application, the first controller is controller a. The third memory in the claims and summary of the present application may include, for example, memory c1 connected to controller a in the description of the embodiments of the present application.

[0077] For example, in the description of the embodiments of the present application, the first controller is controller b. The third memory in the claims and summary of the present application may include, for example, memory c2 connected to controller b in the description of the embodiments of the present application.

[0078] For example, in the description of the embodiments of the present application, the first controller is controller a. The second memory in the claims and summary of the present application may include, for example, memory a1 in the description of the embodiments of the present application.

[0079] For example, the shared interface device in the claims and summary of the present application is interface card a in the description of the embodiments of the present application, and the first partition and the second partition may be, for example, partition 1 and partition 2, respectively, in the cache of interface card a. [Brief explanation of the drawings]

[0080] [Figure 1] 1 shows an example of the structure of an existing storage system. [Figure 2] 1 illustrates an example of a possible system architecture to which an embodiment of the present application is applicable. [Figure 3-1] 1 shows an example of a possible structure of storage nodes in a storage system in the present application. [Figure 3-2] 1 shows an example of a possible structure of storage nodes in a storage system in the present application. [Figure 3-3] 1 shows an example of a possible structure of storage nodes in a storage system in the present application. [Figure 4] 1 illustrates an example of a possible data processing method performed by a storage node in the present application. [Figure 5] 1 shows an example of the process by which interface card a stores cached data in memory. [Figure 6] 10 illustrates an example of another possible data processing method performed by a storage node in the present application. [Figure 7] 10 illustrates an example of another possible data processing method performed by a storage node in the present application. [Figure 8] 10 illustrates an example of another possible data processing method performed by a storage node in the present application. [Figure 9] 1 shows an example of a possible structure of a shared interface device in the present application. DETAILED DESCRIPTION OF THE INVENTION

[0081] SUMMARY OF THE INVENTION The present application provides a storage system, a data processing method, and an apparatus. The following first describes an example of a system architecture to which the present application can be applied, with reference to FIG.

[0082] FIG. 2 illustrates an example of a system architecture to which an embodiment of the present application can be applied. The system architecture corresponding to FIG. 2 includes a storage system and at least one application server. The application server and the storage system may be connected via a communication network. See FIG. 2. The storage system may include one storage node, in which a storage control unit and one or more memories are disposed. The memory may be a hard disk drive (HDD), a solid-state drive (SSD), a storage class memory (SCM), or another type of storage disk. Alternatively, the memory may be a storage server or another type of computing device configured to provide storage services.

[0083] FIG. 2 merely illustrates an example and is not a limitation on a system architecture to which an embodiment of the present application is applicable. The system architecture corresponding to FIG. 2 may include more or fewer application servers or storage nodes. The embodiment of the present application may be applied to a central storage system or a distributed storage system. Optionally, the system architecture to which the embodiment of the present application is applicable may include one or more storage nodes, for example, the storage nodes shown in FIG. 2. The storage nodes shown in FIG. 2 may be understood as a storage array or a storage server. This embodiment of the present application is not limited to each storage node in the distributed storage system being the storage node shown in FIG. 2.

[0084] In order to improve the reliability of the storage system, the storage control unit of the storage node shown in Figure 2 may include at least two controllers. An example in which two controllers are arranged in the storage control unit is used. The storage node shown in Figure 2 may be specifically shown in Figure 3-1.

[0085] See Figure 3-1. The storage node may include a controller a and a controller b. The controller a and the controller b may be understood as controllers in a storage array or controllers in a storage server. The storage node may further include a shared interface device a and a shared interface device b. The shared interface device a and the shared interface device b are separately configured to connect to at least one memory. For ease of distinction, the memory connected to the shared interface device a is referred to as memory a, and the memory connected to the shared interface device b is referred to as memory b. The memory a and the memory b may be understood as memories in the at least one memory shown in Figure 2. The controller a and the controller b may communicate with at least one memory a under the shared interface device a through the shared interface device a, and the controller a and the controller b may communicate with at least one memory b under the shared interface device b through the shared interface device b.

[0086] See Figure 3-1. Caches may be located in shared interface device a and shared interface device b. Controller a and controller b may both be connected to shared interface device a to jointly access the cache in shared interface device a and the connected memory a. Controller a and controller b may further both be connected to shared interface device b to jointly access the cache in shared interface device b and the connected memory b.

[0087] Optionally, power protection for the cache in shared interface device a may be implemented via controller a and / or controller b, and power protection for the cache in shared interface device b may be implemented via controller a and / or controller b. For example, when both controller a and controller b are normal, power protection for the cache in shared interface device a may be implemented via controller a, and power protection for the cache in shared interface device b may be implemented via controller b. After a failure occurs in controller a, power protection for the cache in shared interface device a and power protection for the cache in shared interface device b may be implemented via controller b.

[0088] FIG. 3-1 is an example, not a limitation, of the structure of a storage node. Optionally, a storage node corresponding to FIG. 3-1 may include more controllers, more or fewer shared interface devices, or more or fewer memories a or b. For example, a storage node corresponding to FIG. 3-1 may not include shared interface device b or memory b subordinate to shared interface device b.

[0089] The shared interface device a or the shared interface device b shown in FIG. 3-1 is configured to perform at least one of the following operations on data between the controller and the memory: caching, processing, and forwarding. "Forwarding" may refer to transparent transmission or protocol format conversion. FIGS. 3-2 and 3-3 each show examples of possible structures of storage nodes corresponding to FIG. 3-1. The following describes two different types of shared interface devices with reference to the storage nodes shown in FIGS. 3-2 and 3-3.

[0090] 1. The shared interface device is an interface card.

[0091] In the storage node corresponding to FIG. 3-2, the shared interface device a may be an interface card a connected to the controller a, and the shared interface device b may be an interface card b connected to the controller b. Optionally, the shared interface device a may be connected to the controller a in a plug-in manner. For example, the interface card a may be connected to a peripheral component interconnect (PCI) riser device of the controller a. Similarly, the shared interface device b may be connected to the controller b in a plug-in manner. For example, the interface card b may be connected to a PCIe riser device of the controller b.

[0092] See Figure 3-2. Controller a and controller b may each include a processor, a cache, and a riser device, and interface card a and interface card b may each include a processor, a cache, and multiple ports.

[0093] The processor may include one or more general-purpose processors, such as a central processing unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0094] In FIG. 3-2, an example is used in which the riser device in controller a or controller b is a PCIe riser device. The riser device may be another type of riser device, for example, an extended industry standard architecture (EISA) riser device. The riser device may also be called a bus, and may include an address bus, a data bus, a control bus, etc.

[0095] A cache may include volatile memory, such as random access memory (RAM). Alternatively, a cache may include non-volatile memory, such as read-only memory (ROM), flash memory, a hard disk drive (HDD), or a solid-state drive (SSD). Alternatively, a cache may include a combination of the aforementioned types.

[0096] The PCIe riser device may include multiple ports. In Figure 3-2, each numbered square represents a port. See Figure 3-2. The multiple ports in the PCIe riser device may include port 11, port 12, port 13, and port 14. The multiple ports of interface card a and interface card b may include port 21, port 22, and port 23, respectively.

[0097] See the solid connecting lines in Figure 3-2. The processor of controller a can access interface card a sequentially via ports 11 and 12 in controller a and port 21 of interface card a to establish a communication connection between controller a and interface card a. See the dashed connecting lines in Figure 3-2. The processor of controller b can access interface card a sequentially via ports 11 and 14 in controller b, ports 14 and 13 in controller a, and port 22 of interface card a to establish a communication connection between controller b and interface card a.

[0098] Similarly, optionally, the processor of controller b may access interface card b sequentially via ports 11 and 12 in controller b and port 21 of interface card b to implement a communication connection between controller b and interface card b. The processor of controller a may access interface card b sequentially via ports 11 and 14 in controller a, ports 14 and 13 in controller b, and port 22 of interface card b to implement a connection between controller a and interface card b.

[0099] As described above, interface card a and interface card b may be connected above to controller a and controller b, respectively. In addition, interface card a may be further connected below to one or more memories a via ports, and interface card b may be further connected below to one or more memories b via ports. See FIG. 3-2. Interface card a may be connected to port 31 of disk enclosure a via port 23 to access memory a1, memory a2, and memory a3 installed in disk enclosure a. Interface card b may be connected to disk enclosure b via port 23 to access memory b1, memory b2, and memory b3 in disk enclosure b. Each of memory a1, memory a2, and memory a3 may be understood as one memory a, and each of memory b1, memory b2, and memory b3 may be understood as one memory b.

[0100] Optionally, interface card a and / or interface card b may be a serial attached SCSI (SAS) card or a redundant array of independent disks (RAID) card, where SCSI is an abbreviation for small computer system interface. In the storage node corresponding to FIG. 3-2 , optionally, the connection between interface card a and controller a may be based on a peripheral component interconnect express (PCIe) protocol, and the connection between interface card a and memory a may be based on a SAS protocol, a Fibre Channel (FC) protocol, a Gigabit Ethernet (GE) protocol, or the like. Similarly, the connection between interface card b and controller b may be based on a PCIe protocol, and the connection between interface card b and memory b may be based on a SAS protocol, a FC protocol, a GE protocol, or the like.

[0101] Because the cache is located in interface card a and controller a and controller b are both connected to interface card a, controller a and controller b can share not only memory a under interface card a but also the cache in interface card a. Similarly, because the cache is located in interface card b and controller a and controller b are connected to interface card b, controller a and controller b can share not only memory b under interface card b but also the cache in interface card b.

[0102] Further, refer to FIG. 3-2. Through only one port of one interface card (e.g., interface card a or interface card b), controller a and controller b can share the memory under the interface card. This helps to conserve the port resources of the interface card. In this way, the interface card can be connected to more memory, and the storage resources shared by controller a and controller b are expanded. In addition, the memory connected to the interface card may have only one port used to connect to the interface card to communicate with controller a and controller b separately, and port reconfiguration does not need to be performed for the memory. This helps to reduce costs. For example, the disk enclosure and the memory under the disk enclosure in FIG. 3-2 may be understood as one memory. The disk enclosure may have only one port connected to the interface card to communicate with controller a and controller b separately, and port reconfiguration does not need to be performed for the disk enclosure.

[0103] In Figure 3-2, the interface card communicating with the storage disks via a disk enclosure is used as an example and not a limitation. Optionally, the interface card may be directly connected to a single-port hard disk. Optionally, the interface card may communicate with another type of computing device configured to provide storage services, such as a storage server.

[0104] FIG. 3-2 is an example, not a limitation, of the structure of a storage node. Optionally, a storage node corresponding to FIG. 3-2 may include more controllers, more or fewer interface cards, and more or less memory. For example, a storage node may not include interface card b or memory subordinate to interface card b.

[0105] 2. The shared interface device is a disk enclosure.

[0106] In the storage node corresponding to FIG. 3-3, the shared interface device a may be a disk enclosure a, and the shared interface device b may be a disk enclosure b. Optionally, one or more memories a connected to the disk enclosure may be incorporated in the disk enclosure a, and one or more memories b connected to the disk enclosure may be incorporated in the disk enclosure b. Optionally, the one or more memories a may include at least one type of storage disk, such as an HDD and an SSD. Similarly, optionally, the one or more memories b may include at least one type of storage disk, such as an HDD and an SSD.

[0107] See Figure 3-3. Controller a and controller b may each include a processor and a cache, and disk enclosure a and disk enclosure b may each include a processor, a cache, multiple ports, and a hard disk mounting mechanism (e.g., the groove shown in Figure 3-3). For the processor and the cache, see the relevant content of Figure 3-2. Details will not be described again here. See Figure 3-3. The multiple ports of disk enclosure a and disk enclosure b may include port 21 and port 22, respectively. A memory (e.g., memory a1, memory a2, or memory a3) may be arranged behind the mounting mechanism of disk enclosure a and may communicate separately with the processor of disk enclosure a. A memory (e.g., memory b1, memory b2, or memory b3) may be arranged behind the mounting mechanism of disk enclosure b and may communicate separately with the processor of disk enclosure b.

[0108] Optionally, controller a may access disk enclosure a sequentially via ports 21 and 22 of interface card a and port 31 of disk enclosure a to establish a communication connection between controller a and disk enclosure a. Controller b may access disk enclosure a sequentially via ports 21 and 23 of interface card b and port 32 of disk enclosure a to establish a communication connection between controller b and disk enclosure a.

[0109] Similarly, optionally, controller b may access disk enclosure b sequentially via ports 21 and 22 of interface card b and port 31 of disk enclosure b to establish a communication connection between controller b and disk enclosure b. Controller a may access disk enclosure b sequentially via ports 21 and 23 of interface card a and port 32 of disk enclosure b to establish a communication connection between controller a and disk enclosure b.

[0110] As described above, disk enclosure a and disk enclosure b may be connected above to controller a and controller b, respectively. In addition, disk enclosure a may be further connected below to one or more memories a via ports, and disk enclosure b may be further connected below to one or more memories b via ports. See Figure 3-3. Disk enclosure a may access memory a1, memory a2, and memory a3 incorporated in disk enclosure a, and disk enclosure b may access memory b1, memory b2, and memory b3 incorporated in disk enclosure b. Each of memory a1, memory a2, and memory a3 may be understood as one memory a, and each of memory b1, memory b2, and memory b3 may be understood as one memory b.

[0111] Because a cache is located in disk enclosure a and controller a and controller b are both connected to disk enclosure a, controller a and controller b may not only share memory a under disk enclosure a but also share the cache in disk enclosure a. Similarly, because a cache is located in disk enclosure b and controller a and controller b are connected to disk enclosure b, controller a and controller b may not only share memory b under disk enclosure b but also share the cache in disk enclosure b.

[0112] Disk enclosure a and disk enclosure b may both be connected to controller a, and the connection between disk enclosure a and controller a and the connection between disk enclosure b and controller a may be based on the SAS protocol, the Fibre Channel (FC) protocol, the Gigabit Ethernet (GE) protocol, etc. Similarly, disk enclosure b and disk enclosure a are both connected to controller b, and the connection between disk enclosure b and controller b may be based on the SAS protocol, the Fibre Channel (FC) protocol, the Gigabit Ethernet (GE) protocol, etc.

[0113] FIG. 3-3 is an example, not a limitation, of the structure of a storage node. Optionally, a storage node corresponding to FIG. 3-3 may include more controllers, more or fewer interface cards, more or fewer disk enclosures, or more or less memory. For example, a storage node corresponding to FIG. 3-3 may not include disk enclosure b or the memory in disk enclosure b. For example, interface card a or interface card b may be connected to more memory.

[0114] In the storage nodes shown in FIG. 3-1, 3-2, or 3-3, one connection line between ports may represent one or more connection links. The connection line between port 12 and port 21 in FIG. 3-2 is used as an example. The connection link represented by the connection line may include a PCIe bus used to transmit data signals and a control bus used to transmit control signals. For example, transmission of control signals, handshake information, and status information between controller A and interface card A may be performed via the control bus. The control signal may include a start signal that enables interface card A to start operation. The start signal may include, for example, a predetermined position signal (used to determine whether interface card A is inserted into the correct slot), a power-on enable signal, a clock signal, and a reset signal of interface card A. The handshake information may be used by controller A and interface card A to perform port negotiation to determine the transmission bandwidth and transmission rate of the transmission channel between controller A and interface card A.

[0115] Optionally, in the storage nodes shown in Figure 3-1, Figure 3-2, or Figure 3-3, there may be a connection link between controller a and controller b. For example, the connection link is used to transmit heartbeat information to monitor each other's status in real time.

[0116] The above describes the connection links required by controller a and controller b to call a shared interface device (e.g., shared interface device a and shared interface device b) using Figures 3-1, 3-2, and 3-3. The following describes the control logic for calling the shared interface device by the controllers using an example with reference to the mode of calling the shared interface device by controller a and controller b.

[0117] In this embodiment of the present application, the mode of invoking the shared interface device by the controller in the storage node is not limited. Optionally, the invocation mode may be an active / standby mode or an active-active mode.

[0118] (1) Active / standby mode In the active / standby mode, the controllers in the storage nodes have different positions relative to the shared interface device and are classified as active controllers and standby controllers of the shared interface device.

[0119] It is assumed that controller a and controller b are the active controller and standby controller of shared interface device a, respectively. Under normal operating conditions, controller a can call shared interface device a to perform data storage services and data query services, and controller b cannot call shared interface device a to perform data storage services or data query services. When controller a fails, controller b can take over shared interface device a and call shared interface device a to perform data storage services and / or data query services to ensure the availability of data in the cache of shared interface device a and the availability of data in memory a.

[0120] The storage node shown in Figure 3-2 is used as an example to explain a specific possible active / standby switchover process. Under normal operating conditions, port 21 of interface card a is in an active state, and port 22 is in an inactive state. In this way, interface card a can be called by controller a but cannot be called by controller b. When controller a fails, controller a can notify controller b using a heartbeat signal or a power-off interrupt signal between controllers a and b, and controller b can compete to become the active controller for interface card a. Controller b can notify interface card a of an active / standby switchover event to allow port 21 of interface card a to enter an inactive state and stop being called by controller a, and port 22 of interface card a to enter an active state and start being called by controller b.

[0121] (2) Active-active mode In the active-active mode, the controllers in the storage nodes have the same position with respect to the shared interface device. Optionally, controller a and controller b may alternately call shared interface device a or shared interface device b at different times. When controller a is abnormal and unable to operate, controller b may call shared interface device a and / or shared interface device b to perform data query services to ensure the availability of data in the caches of shared interface device a and / or shared interface device b and the availability of data in the connected memories.

[0122] When the conditions for invoking a shared interface device are met, a controller in a storage node may take over the corresponding shared interface device to provide data storage services and data query services using the cache of the corresponding shared interface device and the memory connected to the shared interface device. The following describes a process by which the controller in a storage node invokes a shared interface device to provide data storage services and data query services.

[0123] The following describes the process in which controller a provides data storage services through interface card a.

[0124] FIG. 4 shows an example of a method procedure in which controller a stores data via interface card a. The structure other than the application server in FIG. 4 may be, for example, the storage node shown in FIG. 3-2. To simplify the accompanying drawings, FIG. 4 does not specifically show controller b, interface card b, and memory under interface card b, and does not show a PCIe riser device in controller a. A possible embodiment of the data processing method provided in the present application may include the following steps S401 to S404.

[0125] S401: The application server sends a write request 1 to the controller a.

[0126] The application server may send a data write request 1 (abbreviated as write request 1) to the controller a, and the write request 1 is used to request to store service data 1. The storage system in this embodiment of the present application may provide data storage services through a software system, such as a file system, a block storage system, or an object storage system. Correspondingly, the service data to be written as requested by the write request 1 may be data in the form of a file, a data block, an object, or the like.

[0127] Step S401 is an optional step. The fact that the write request 1 is sent by the application server is not limited in this embodiment of the present application. Optionally, the write request 1 may be sent by a client of a terminal or by a software system used by the storage system. Optionally, the service data 1 may be user data or system data generated by the software system. The location of the software system is not limited in this embodiment of the present application. For example, the software system may be located in controller a, controller b, or another controller, the software system may be located in the application server, or the software system may be located in an independent server.

[0128] S402: Controller a sends write command 1 to interface card a.

[0129] Controller a may send write command 1 to interface card a based on write request 1, where write command 1 instructs interface card a to store data 1.

[0130] The data 1 includes, but is not limited to, service data 1. Optionally, the controller a may generate metadata 1 that describes the service data 1. Correspondingly, the data 1 may include service data 1 and metadata 1. For example, when the service data 1 is held in the memory a2, the metadata 1 may describe the storage location of the service data 1 in the memory a2. The storage location may be a logical address or a physical address.

[0131] S403: Interface card a uses cache and memory a2 to store data 1 to be written as instructed by write command 1.

[0132] After receiving the write command, interface card a may store data 1 using its cache and memory a2. Because controller a and controller b share the cache of interface card a, to reduce contention caused by controller a and controller b writing data to the cache of interface card a, optionally, the cache of interface card a may be divided into a write partition of controller a (referred to as partition 1) and a write partition of controller b (referred to as partition 2). Partition 1 and partition 2 are two different storage spaces in the cache of interface card a. Being different from partition 1 may mean that the storage space corresponding to partition 1 and the storage space corresponding to partition 2 do not overlap. For example, in step S403, interface card a may store data 1 using partition 1 and memory a2 in the cache of interface card a.

[0133] After receiving the write command 1, the interface card a may asynchronously write the target data 1 in the data 1 to the memory a2 using a cache. Optionally, the write command 1 may indicate a storage address of the data to be written, and the storage address may point to at least one memory under the interface card a. In this embodiment of the present application, an example is used in which the write command 1 indicates that the storage address of the target data 1 points to the memory a2. The storage address may be a logical address or a physical address in the memory a2. For example, the storage address may be in a logical block addressing (LBA) mode.

[0134] The interface card a asynchronously writing the target data 1 to the memory a2 using the cache may mean that the interface card a first temporarily stores the target data 1 in the cache (e.g., partition 1) and then writes the target data 1 to the memory a2. In addition, after writing the target data 1 to the cache and before writing the target data 1 to the memory a2, the interface card a sends a success notification to the controller a, which is used to notify the controller a that the write command 1 is completed and the target data 1 is stored. Optionally, the controller a may consider the target data 1 to be retained in the memory a2 based on the success notification.

[0135] Optionally, target data 1 may be all of the data in data 1. Alternatively, optional target data 1 may be a portion of the data in data 1, and interface card a may store other data in data 1 (excluding target data 1) using a different storage method. For example, interface card a may synchronously write the other data to memory a2.

[0136] The interface card a synchronously writes the other data to the memory a2, which means that the interface card a sends a success notification to the controller a only after writing the other data to the memory a2 to notify the controller a that the other data has been stored.

[0137] In this embodiment of the present application, an example is used in which the interface card a holds the target data 1 and other data in a memory a2. Optionally, the interface card a may store data to be written in multiple memories a as instructed by the write command 1, for example, the target data 1 may be held in the memory a2 and other data may be held in a memory a3.

[0138] In this embodiment of the present application, the write instruction 1 may include one or more instructions. For example, the write instruction 1 may include a write instruction 1-1 that instructs writing target data 1 and a write instruction 1-2 that instructs writing other data.

[0139] Optionally, interface card a may determine target data 1 based on a data type. For example, target data 1 may be metadata 1, and the other data may be service data 1. Alternatively, optionally, interface card a may determine target data 1 based on a data length. For example, assuming that the data length of write command 1-1 is less than a length threshold and the data length of write command 1-2 is less than a length threshold, interface card a may use a cache to asynchronously hold the data to be written as instructed by write command 1-1 and synchronously hold the data to be written as instructed by write command 1-2. Because the data length of metadata is usually small, if the length of service data 1 is also small, target data 1 may include both metadata 1 and service data 1.

[0140] Optionally, write command 1 may indicate a storage method, and interface card a may store data in the storage method indicated by write command 1. For example, write command 1-1 indicates asynchronous storage, and write command 1-2 indicates synchronous storage. By using the cache of interface card a, interface card a may asynchronously store data to be written as instructed by write command 1-1 in memory a2, and synchronously store data to be written as instructed by write command 1-2 in memory a2.

[0141] In this embodiment of the present application, the interface card a asynchronously writes the target data 1 to the memory a2 using the cache, and is not limited to only storing the target data 1 in the cache after the interface card a extracts the target data 1 from the write command 1-1. Optionally, the interface card a may store the write command 1-1 in the cache and send the write command 1-1 in the cache to the memory a2 after sending a success notification to the controller a. The memory a2 may analyze the target data 1 from the write command 1-1 and store the target data 1.

[0142] Similarly, the interface card a synchronously writes the other data to the memory a2, and the interface card a extracts the other data from the write command 1-2 and then transmits only the other data to the memory a2, but is not limited to this. Optionally, the interface card a may transmit the write command 1-2 to the memory a2, and the memory a2 may analyze the other data from the write command 1-2 and store the other data.

[0143] Because the communication protocol (e.g., PCIe protocol) between interface card a and controller a is typically different from the communication protocol (e.g., SAS protocol) between interface card a and memory a2 or disk enclosure a, before sending the write command sent by controller a to memory a2, interface card a may convert the format of the write command, for example, convert the format of write command 1 from PCIe protocol format to SAS protocol format.

[0144] Steps S4031 to S4033 shown in Figure 4 show an example of a possible procedure in which interface card a uses a cache to asynchronously write target data 1 to memory a2. See Figure 4. Possible detailed steps of step S403 may include the following steps:

[0145] S4031: Interface card a temporarily stores target data 1 in partition 1.

[0146] After receiving write command 1, interface card a may write target data 1 to be written to partition 1 as instructed by write command 1. Referring to the above description, optionally, the cache of interface card a may include partition 1 and partition 2. In S4031, interface card a writing target data 1 to partition 1 in the cache of interface card a is used as an example and not a limitation.

[0147] Optionally, the write command 1 may further indicate a cache address of the target data 1 in the partition 1. The cache address may be a logical address or a physical address. The interface card a may store the target data 1 in the partition 1 based on the cache address indicated by the write command 1.

[0148] S4032: Interface card a sends a success notification 1 to controller a.

[0149] After the target data 1 is successfully written to the cache, the interface card a may send a success notification to the controller a to notify the controller a that the write command 1 has been completed and the target data 1 has been successfully stored.

[0150] S4033: Interface card a writes target data 1 in partition 1 to memory a2.

[0151] The interface card a may asynchronously write the first data temporarily stored in the cache to a memory connected to the interface card a. For example, after notifying the controller a that the target data 1 has been successfully stored, the interface card a may write the target data 1 in the cache to the memory a2 to retain the target data 1. Optionally, see FIG. 4. The interface card a may store the target data 1 in the memory a2 via the disk enclosure a.

[0152] Optionally, after notifying the controller a that the target data 1 has been successfully stored, the interface card a may write the target data 1 to the memory a2 when a retention condition is met. The retention condition may be related to at least one of the following factors: the size of the available storage space of the cache, the total length of the data in the cache to be written to the memory a2, and whether the memory a2 is idle.

[0153] To improve the storage efficiency of memory a2, optionally, interface card a may collectively transmit target data 1 in partition 1 and other data in the cache to memory a2. The other data may include data to be written as instructed by another received write command other than write command 1 of S402. The location of the other data in the cache is not limited in this embodiment of the present application. For example, the other data may include data in partition 1 and / or data in partition 2.

[0154] See Figure 5. It is assumed that partition 2 of the cache of interface card a further stores target data 2 to be written as instructed by write instruction 2 sent by controller b. In addition, partition 1 further stores target data m to be written as instructed by write instruction m and target data n to be written as instructed by write instruction n sent by controller a, and partition 2 further stores target data p to be written as instructed by write instruction p sent by controller b, where m, n, and p are positive integers greater than 2, and m, n, and p are not equal to each other. Optionally, interface card a may collectively send target data 1 and target data m in partition 1 and target data 2 in partition 2 to memory a2.

[0155] In one example, it is assumed that the storage address (LBA1) of target data 1, the storage address (LBA2) of target data 2, and the storage address (LBAm) of target data m all point to memory a2. When the total length of target data 1, target data 2, and target data m reaches a threshold, interface card a may collectively send target data 1, target data 2, and target data m to memory a2. Optionally, the storage address of the target data in the cache may be the storage address indicated by the corresponding write instruction described above.

[0156] To further improve the storage efficiency of memory a2, interface card a may optionally send data adjacent to storage addresses to memory a2 in a collective manner. Please refer to FIG. 5 further. It is assumed that the storage address (LBAn) of target data n and the storage address (LBAp) of target data p also point to memory a2, but the storage space indicated by LBA1 is adjacent to the storage spaces indicated by LBA2 and LBAm, and the storage space indicated by LBA1 is not adjacent to the storage spaces indicated by LBAn or LBAp. Therefore, interface card a does not need to send target data 1 and target data n or target data p in a collective manner to memory a2.

[0157] The interface card a collectively transmitting target data 1, target data 2, and target data m to memory a2 may mean that the interface card a distributes target data 1, target data 2, and target data m to memory a2 using one instruction. Optionally, the interface card a may distribute target data n and target data p to memory a2 using another instruction. Alternatively, the interface card a collectively transmitting target data 1, target data 2, and target data m to memory a2 may mean that the interface card a distributes target data 1, target data 2, and target data m to memory a2 using multiple consecutive instructions. The multiple instructions do not include instructions used to store other data (e.g., target data n, target data p, or data synchronously stored in memory a2).

[0158] It can be seen that the interface card a collectively transmits the target data 1, the target data 2, and the target data m to the memory a2, which can be understood as the interface card a continuously transmitting the target data 1, the target data 2, and the target data m to the memory a2. This helps the memory a2 continuously process the storage tasks of the target data 1, the target data 2, and the target data m. When the storage addresses of the target data 1, the target data 2, and the target data m are adjacent or even consecutive, the large jump of the write address of the memory a2 can be reduced, and the addressing period can be reduced. In this way, the storage efficiency of the memory a2 is improved.

[0159] Optionally, the interface card a or the controller a may determine whether a retention condition is met. Optionally, the write instruction 1 may further instruct the target data 1, the target data 2, and the target data m to be collectively transmitted to the memory a2.

[0160] S404: The controller a sends a write success response 1 to the application server.

[0161] After successfully storing data 1 through interface card a, controller a may send write success response 1 to the application server, which may notify that write request 1 is completed and service data 1 has been stored. Optionally, after interface card a notifies controller a that data 1 has been stored, controller a may determine that service data 1 has been successfully stored.

[0162] As mentioned in step S403 above, optionally, interface card a may asynchronously write data 1 to memory a2 using its cache, and after writing data 1 to the cache but before writing data 1 to memory a2, notify controller a that data 1 has been stored. Correspondingly, controller a may send write success response 1 to the application server after data 1 has been written to the cache of interface card a but before data 1 is retained in memory a2. This helps to reduce the data storage latency perceived by the application server.

[0163] As mentioned in the above step S403, optionally, the interface card a may asynchronously write the target data 1 (e.g., metadata 1) to the memory a2 via the cache, and after writing the target data 1 to the cache and before writing the target data 1 to the memory a2, notify the controller a that the target data 1 has been stored. In addition, the interface card a may synchronously write other data (e.g., service data 1) in the data 1 (excluding the target data 1) to the memory a2, and after writing the other data to the memory a2, more specifically, after successfully storing the other data in the memory a2, notify the controller a that the other data has been stored. Correspondingly, the controller a may send a write success response 1 to the application server after the target data 1 is written to the cache of the interface card a and after the other data is retained in the memory a2. Compared to synchronously retaining all data in the data 1 in the memory a2, this helps to reduce the data storage latency perceived by the application server.

[0164] In order to avoid the case where the data in the cache is unavailable after a cache error occurs in interface card a, optionally, after step S402, the method in this embodiment of the present application may further include S405.

[0165] S405: The interface card a synchronizes and backs up the target data 1 to the memory a1.

[0166] After receiving write command 1, interface card a may synchronously write target data 1 to memory a1. In other words, after writing target data 1 to both the cache and memory a1, but before writing target data 1 to memory a2, interface card a executes step S4032. The data written to the cache is backed up in memory a1 connected to interface card a. In this way, even if the cache is abnormal, for example, not retained, or the data in the cache is lost, interface card a can still find the cached data in memory a1. This helps improve the availability of data in the cache and improve the reliability of the data service provided by the storage system.

[0167] Optionally, the memory access latency of the memory a1 may be shorter than the memory access latency of the memory a2. For example, the memory a1 may be an SSD, and the memory a2 may be an HDD. FIG. 4 only uses an example in which the memory a1 and the memory a2 are connected to the interface card a via a disk enclosure. Optionally, the memory a1 and / or the memory a2 may be directly connected to the interface card a.

[0168] In order to avoid the case where the data in the cache is unavailable after a cache error occurs in interface card a, optionally, after step S401, the method in this embodiment of the present application may further include S406 and S407.

[0169] S406: The controller a stores the target data 1 in the memory c1.

[0170] S407: When the cache is abnormal, the controller a transfers the target data 1 to the memory a2 via the interface card a.

[0171] Optionally, the storage system further includes a memory c1 connected to the controller a. After receiving the write request, the controller a is further configured to write the target data 1 to the memory c1. Optionally, the controller a determines that the target data 1 has been successfully stored only after the target data 1 has been written to both the cache of the interface card a and the memory c1.

[0172] After the cache becomes abnormal, the controller a may transfer the data in the memory c1 (including the target data 1) to a memory under the interface card a, such as the memory a2 or another memory, via the interface card a. In this way, even if the cache becomes abnormal, for example, if the data in the cache is not retained or is lost, the interface card a can still find the cached data in at least one memory. This helps to improve the availability of the data in the cache and the reliability of the data service provided by the storage system.

[0173] The following describes the process by which controller b provides data storage services through interface card a.

[0174] FIG. 6 shows an example of a method procedure in which controller b stores data via interface card a. The structure other than the application server in FIG. 6 may be, for example, the storage node shown in FIG. 3-2. To simplify the accompanying drawings, FIG. 6 does not specifically show interface card b and the memory under interface card b, and does not show PCIe riser devices in controller a and controller b. Another possible embodiment of the data processing method provided in the present application may include the following steps S601 to S604.

[0175] S601: The application server sends a write request 2 to the controller b.

[0176] Step S601 can be understood with reference to the above step S401. For example, write request 2 can be understood with reference to the related description of write request 1.

[0177] In this embodiment of the present application, it is not limited that the write request 1 and the write request 2 are from the same device. For example, the write request 1 and the write request 2 may be from different application servers, or one may be from an application server and the other may be from a software system.

[0178] In this embodiment of the present application, it is not limited that the service data 1 corresponding to the write request 1 and the service data 2 corresponding to the write request 2 are the same type of data. For example, the service data 1 may be user data, and the service data 2 may be system data.

[0179] S602: The controller b sends a write command 2 to the interface card a.

[0180] Controller b may send write command 2 to interface card a based on write request 2, and write command 2 instructs interface card a to store data 2. Step S602 may be understood with reference to step S402. For example, write command 2 may be understood with reference to the related description of write command 1, and data 2 may be understood with reference to data 1 described above.

[0181] Referring to the connection method shown in Figure 3-2, unlike S402, since interface card a is inserted into controller a, the line through which controller b sends write command 2 to interface card a is different from the line through which controller a sends write command 1 to interface card a.

[0182] S603: Interface card a uses cache and memory a3 to store data2 to be written as instructed by write command2.

[0183] After receiving the write command 2, the interface card a may use the cache and the memory a3 to store the data 2. In this embodiment of the present application, the fact that the memory a3 is different from the memory a2 is used as an example and not a limitation. Optionally, the interface card a may use the cache and the memory a2 to store the data 2.

[0184] Step S603 can be understood with reference to step S403. For example, after receiving write command 2, interface card b may asynchronously write target data 2 in data 2 to memory a3 using a cache. Optionally, target data 2 may be all of the data in data 2. Alternatively, optional, target data 2 may be a portion of the data in data 2, and interface card b may store other data in data 2 (excluding target data 2) using another storage method. For example, interface card b may synchronously write other data to memory a3. Write command 2 may include one or more commands. For example, write command 2 may include write command 2-1 instructing to write target data 2 and write command 2-2 instructing to write other data.

[0185] Similar to step S403, referring to FIG. 6, possible detailed steps of step S603 may include the following steps:

[0186] S6031: Interface card a temporarily stores target data 2 in partition 2.

[0187] S6032: The interface card a sends a success notification 2 to the controller b.

[0188] S6033: Interface card a writes target data 2 in partition 2 to memory a3.

[0189] Partition 2 may be understood with reference to partition 2 mentioned in step S403, and S6031 to S6033 may be understood with reference to S4031 to S4033, respectively.

[0190] S604: The controller b sends a write success response 2 to the application server.

[0191] After successfully storing data 2 through interface card a, controller b may send a write success response to the application server to complete the data storage service. Optionally, after interface card a notifies controller b that data 2 has been stored, controller b may determine that data 2 has been successfully stored.

[0192] As mentioned in step S603 above, optionally, interface card a may asynchronously write data 2 to memory a3 using its cache, and after writing data 2 to the cache but before writing data 2 to memory a3, notify controller b that data 2 has been stored. Correspondingly, controller b may send write success response 2 to the application server after data 2 has been written to the cache of interface card a but before data 2 is retained in memory a3. This helps to reduce the data storage latency perceived by the application server.

[0193] As mentioned in the above step S603, optionally, interface card a may asynchronously write target data 2 (e.g., metadata 2) to memory a3 using a cache, and after writing target data 2 to the cache and before writing target data 2 to memory a3, notify controller b that target data 2 has been stored. In addition, interface card a may synchronously write other data (e.g., service data 2) in data 2 (excluding target data 2) to memory a3, and after writing the other data to memory a3, more specifically, after successfully storing the other data in memory a3, notify controller b that the other data has been stored. Correspondingly, controller b may send write success response 2 to the application server after target data 2 is written to the cache of interface card a and after the other data is retained in memory a3. Compared to synchronously retaining all data in data 2 in memory a3, this helps reduce the data storage latency perceived by the application server.

[0194] In order to avoid the case where the data in the cache is unavailable after a cache error occurs in interface card a, optionally, after step S602, the method in this embodiment of the present application may further include S605.

[0195] S605: The interface card a synchronously writes the target data 2 into the memory a1.

[0196] For step S605, please refer to step S405. Details will not be described again here. For example, optionally, the memory access latency of memory a1 may be shorter than the memory access latency of memory a2. For example, memory a1 may be an SSD, and memory a2 may be an HDD. In FIG. 6, only an example is used in which memory a1 and memory a2 are connected to interface card a via a disk enclosure. Optionally, memory a1 and / or memory a2 may be directly connected to interface card a.

[0197] In order to avoid the case where the data in the cache is unavailable after a cache error occurs in interface card a, optionally, after step S601, the method in this embodiment of the present application may further include S606 and S607.

[0198] S606: The controller b stores the target data 2 in the memory c.

[0199] S607: When the cache is abnormal, the controller b transfers the target data 2 to the memory a3 via the interface card a.

[0200] Optionally, the storage system further includes a memory c2 connected to the controller b. After receiving the write request, the controller b is further configured to write the target data 2 to the memory c2. After the cache becomes abnormal, the controller b may transfer the data in the memory c2 (including the target data 2) to a memory under the interface card a, such as the memory a3 or another memory, via the interface card a. In this way, even if the cache becomes abnormal, for example, if the data in the cache is not retained or is lost, the interface card a can still find the cached data in at least one memory. This helps to improve the availability of the data in the cache and improve the reliability of the data service provided by the storage system.

[0201] Controller b may provide data storage services through interface card b. See FIG. 3-2. Since interface card b is inserted into controller b, the process by which controller b provides data storage services through interface card b is referred to in the embodiment corresponding to FIG. 4. Specifically, for the steps performed by controller b, refer to the steps performed by controller a in the embodiment corresponding to FIG. 4, and for the steps performed by interface card b, refer to the steps performed by interface card a in the embodiment corresponding to FIG. 4.

[0202] Controller a may provide data storage services through interface card b. See FIG. 3-2. Since interface card b is inserted into controller b, the process of controller a providing data storage services through interface card b is referred to in the embodiment corresponding to FIG. 6. Specifically, for the steps performed by controller a, refer to the steps performed by controller b in the embodiment corresponding to FIG. 6, and for the steps performed by interface card b, refer to the steps performed by interface card a in the embodiment corresponding to FIG. 6.

[0203] The following describes the process in which controller a provides data query service through interface card a.

[0204] FIG. 7 shows an example of a method procedure in which controller a inquires about data through interface card a. The structure other than the application server in FIG. 7 may be, for example, the storage node shown in FIG. 3-2. To simplify the accompanying drawings, FIG. 7 does not specifically show controller b, interface card b, and memory under interface card b, and does not show a PCIe riser device in controller a. Another possible embodiment of the data processing method provided in the present application may include the following steps S701 to S704.

[0205] S701: The application server sends a read request 1 to the controller a.

[0206] The application server may send a data read request 1 (short, read request 1) to the controller a, and the read request 1 is used to request to read the service data 3. The service data 3 may be the service data 1 described in S401 or the service data 2 described in S601. In this embodiment of the present application, the fact that the read request 1 is sent by the application server is used as an example and not a limitation. For another possible source of the read request 1, please refer to the related content of S401.

[0207] S702: Controller a sends read command 1 to interface card a.

[0208] After receiving the read request 1, the controller a may send a read command 1 to the interface card a, which instructs the interface card a to query the data 3. The data 3 may be the service data 2, or may include the service data 2 and data other than the service data 2.

[0209] S703: Interface card a queries the cache and connected memory for data 3 to be read as instructed by read command 1, and provides data 3 to controller a.

[0210] After receiving read command 1, interface card a may query data 3. The query range may include the cache of interface card a and memories connected to interface card a (e.g., memory a1, memory a2, and memory a3).

[0211] The query method of interface card a within the query range is not limited in this embodiment of the present application. Optionally, interface card a may traverse the cache, memory a1, memory a2, and memory a3 to query data 3. Then, interface card a may return one or more query results to controller a. Optionally, interface card a may sequentially access the cache and connected memory in a specific order, and if data 3 is found, interface card a stops searching for data 3. For example, interface card a may first search for data 3 in the cache. If data 3 is found, interface card a returns data 3 to controller a; if data 3 is not found, interface card a continues to search for data 3 in memory a1. If interface card a finds data 3 in memory a1, interface card a returns data 3 to controller a; if interface card a does not find data 3 in memory a1, interface card a continues to search for target data 3 in memory a2. By analogy, controller a may return the first found data 3 to controller a and stop searching for data 3. If controller a fails to find data 3 within all search ranges, controller a may notify controller a that the query failed.

[0212] In this embodiment of the present application, data 3 may include target data 3, and target data 3 may be all or a part of first target data. The first target data may be target data 1 mentioned in S403 or target data 2 mentioned in S603. Since interface card a uses a cache to temporarily store the first target data, if interface card a receives read command 1 before the first target data is stored, interface card a may obtain all or a part of target data 3 from the cache according to read command 1.

[0213] See the content of S403. The cache of interface card a may be divided into partition 1 and partition 2 shown in FIG. 7. Partition 1 may be used to store data for controller a, and partition 2 may be used to store data for controller b. The query range in which interface card a queries target data 3 in the cache may include partition 1 and partition 2. If target data 3 is all or part of target data 1, interface card a may obtain all or part of target data 3 from partition 1, or if target data 3 is all or part of target data 2, interface card a may obtain all or part of target data 3 from partition 2. In FIG. 7, a solid line with an arrow between a processor and partition 2 may indicate that the processor finds target data 3 in partition 2, and a dashed line with an arrow between a processor and partition 1 or disk enclosure a may indicate that the range in which the processor searches for target data 3 includes partition 1 and disk enclosure a.

[0214] If interface card a receives read command 1 after the first target data is retained, interface card a may retrieve all or part of target data 3 from a connected memory (e.g., memory a1, memory a2, or memory a3) in accordance with read command 1.

[0215] See step S405 or S605. It is assumed that interface card a synchronizes and backs up the first target data to memory a1. In this way, if the target data 3 in the cache is not retained or is not retained completely and the cache is abnormal, interface card a can retrieve all or part of the target data 3 from memory a1. This helps to improve the availability of the data in the cache.

[0216] See steps S406 and S407, or see steps S606 and S607. Assume that controller a backs up target data 1 to memory c1, or controller b backs up target data 2 to memory c2, and after the cache becomes abnormal, controller a transfers the backup data to memory a2, or controller b transfers the backup data to memory a3. In this way, when target data 3 in the cache is not retained or is not retained completely and the cache is abnormal, interface card a can retrieve all or part of target data 3 from memory a2 or memory a3. This helps to improve the availability of data in the cache.

[0217] Optionally, the read command 1 may indicate a search range for the data 3, for example, to instruct the interface card a to query the cache of the interface card a and the memory under the disk enclosure a for the data 3. In this embodiment of the present application, the method by which the interface card a queries for other data (except the target data 3) in the data 3 is not limited. Optionally, the interface card a may also query the cache and the connected memory for other data, or may query only the connected memory for other data. After finding the other data, the interface card a may return the other data to the controller a. If the other data is not found, the controller a may notify the controller a that the query failed.

[0218] In this embodiment of the present application, the read instruction 1 may include one or more instructions. For example, the read instruction 1 may include a read instruction 1-1 that instructs to query the target data 3 and a read instruction 1-2 that instructs to query data other than the target data 3. The read instruction 1-1 may instruct to query the cache of the interface card a and the memory under the interface card a for the target data 3, and the read instruction 1-2 instructs to query the memory under the interface card a for other data.

[0219] For example, the target data 3 is metadata 3 that describes service data 3. It is assumed that the metadata 3 describes the storage location of the service data 3 in memory a3. After retrieving the metadata 3 from the cache, the interface card a may retrieve the service data 3 from memory a3 based on the metadata 3.

[0220] S704: The controller a sends the query result 1 to the application server.

[0221] When the controller a receives the data 3 returned by the interface card a, the controller a may obtain the service data 3 from the data 3 and send the query result 1 carrying the service data 3 to the application server.

[0222] If controller a does not receive data 3 returned by interface card a within a certain period of time, or interface card a feedbacks a query failure, controller a may send a query result 1 to the application server that does not carry service data 3, and the query result indicates that service data 3 cannot be found.

[0223] See Figure 7. Assume that target data 3 is stored in partition 2. It can be seen that target data 3 is data stored by interface card a for controller b. In this way, even if controller b fails, interface card a can query controller a for the data of controller b in partition 2, and controller a will send the data to the application server. This helps to ensure the availability of the data of controller b in the cache of interface card a, and therefore helps to improve the reliability of the storage system.

[0224] The following describes the process in which controller b provides data query service through interface card a.

[0225] FIG. 8 shows an example of a method procedure in which controller b queries data through interface card a. The structure other than the application server in FIG. 8 may be, for example, the storage node shown in FIG. 3-2. To simplify the accompanying drawings, FIG. 8 does not specifically show interface card b and the memory under interface card b, and does not show PCIe riser devices in controller a and controller b. Another possible embodiment of the data processing method provided in the present application may include the following steps S801 to S804.

[0226] S801: The application server sends a read request 2 to the controller b.

[0227] Step S801 can be understood with reference to the above step S701. For example, read request 2 can be understood with reference to the related description of read request 1.

[0228] In this embodiment of the present application, the read request 1 and the read request 2 are not limited to being from the same device. For example, the read request 1 and the read request 2 may be from different application servers, or one may be from an application server and the other may be from a software system.

[0229] S802: Controller b sends read command 2 to interface card a.

[0230] After receiving read request 2, controller b may send read command 2 to interface card a, which instructs it to query data 4.

[0231] Step S802 can be understood with reference to step S702. Referring to the connection method shown in FIG. 3-2, unlike S702, because interface card a is inserted into controller a, the line through which controller b sends read command 2 to interface card a is different from the line through which controller a sends read command 1 to interface card a.

[0232] S803: Interface card a queries the cache and connected memory for data 4 to be read as instructed by read command 2, and provides data 4 to controller b.

[0233] After receiving read command 2, interface card a may query the cache and memory connected to interface card a (e.g., memory a1, memory a2, and memory a3) for data 4 to be read as instructed by read command 2.

[0234] Step S803 can be understood with reference to step S703.

[0235] For example, data 4 may include target data 4, and target data 4 may be all or a part of first target data. The first target data may be target data 1 mentioned in S403 or target data 2 mentioned in S603. Since interface card a uses a cache to temporarily store the first target data, if interface card a receives read command 2 before the first target data is retained, interface card a may obtain all or a part of target data 4 from the cache according to read command 2.

[0236] For example, the read command 2 may include one or more commands. For example, the read command 2 may include a read command 2-1 that instructs to query the target data 4 and a read command 2-2 that instructs to query data other than the target data 4. The read command 2-1 may instruct to query the cache of the interface card a and the memory under the interface card a for the target data 4, and the read command 2-2 instructs to query the memory under the interface card a for other data.

[0237] For example, if interface card a receives read command 2 after the first target data is retained, interface card a may retrieve all or part of target data 4 from a connected memory (e.g., memory a1, memory a2, or memory a3) in accordance with read command 2.

[0238] For example, see step S405 or S605. It is assumed that interface card a synchronizes and backs up the first target data to memory a1. In this way, if the target data 4 in the cache is not retained or is not retained completely and the cache is abnormal, interface card a can retrieve all or part of the target data 4 from memory a1. This helps to improve the availability of the data in the cache.

[0239] For example, see steps S406 and S407, or steps S606 and S607. Assume that controller a backs up target data 1 to memory c1, or controller b backs up target data 2 to memory c2, and after the cache becomes abnormal, controller a transfers the backup data to memory a2, or controller b transfers the backup data to memory a3. In this way, when target data 4 in the cache is not retained or is not retained completely and the cache is abnormal, interface card a can retrieve all or part of target data 4 from memory a2 or memory a3. This helps to improve the availability of data in the cache.

[0240] S804: The controller b sends the query result 2 to the application server.

[0241] When the controller b receives the data 4 returned by the interface card a, the controller b may obtain the service data 4 from the data 4 and send the query result carrying the service data 4 to the application server.

[0242] If controller b does not receive data 4 returned by interface card a within a certain period of time, or interface card a feedbacks a query failure, controller b may send a query result to the application server that does not carry service data 4, and the query result indicates that service data 4 cannot be found.

[0243] See Figure 8. Assume that target data 4 is stored in partition 1. It can be understood that target data 4 is data stored by interface card a for controller a. In this way, even if controller a fails, interface card a can query controller b for controller a's data in partition 1, and controller b will send the data to the application server. This helps to ensure the availability of controller a's data in interface card a's cache, and therefore helps to improve the reliability of the storage system.

[0244] Controller b may provide a data query service through interface card b. See FIG. 3-2. Since interface card b is inserted into controller b, the process of controller b providing a data query service through interface card b is shown in the embodiment corresponding to FIG. 7. Specifically, for the steps performed by controller b, see the steps performed by controller a in the embodiment corresponding to FIG. 7, and for the steps performed by interface card b, see the steps performed by interface card a in the embodiment corresponding to FIG. 7.

[0245] The controller a may provide a data query service through the interface card b. See FIG. 3-2. Since the interface card b is inserted into the controller b, the process of the controller a providing a data storage service through the interface card b may refer to the embodiment corresponding to FIG. 8. Specifically, for the steps performed by the controller a, refer to the steps performed by the controller b in the embodiment corresponding to FIG. 8, and for the steps performed by the interface card b, refer to the steps performed by the interface card a in the embodiment corresponding to FIG. 8.

[0246] For the data storage services and data query services provided by each controller in the storage node corresponding to Figure 3-3, please refer to the corresponding services provided by the corresponding controller in the storage node corresponding to Figure 3-2 described above. For example, by replacing the interface card a in the embodiment corresponding to Figure 4 with the disk enclosure a, the process in which the controller a shown in Figure 3-3 provides the data storage service through the disk enclosure a can be determined.

[0247] The foregoing describes in detail the storage system and the data processing method related to the storage system provided in the embodiments of the present application. In order to better implement the aforementioned solutions in the embodiments of the present application, the following correspondingly further provides related devices configured to cooperate in implementing the aforementioned solutions.

[0248] FIG. 9 is a schematic diagram of the structure of a shared interface device according to an embodiment of the present application. The shared interface device may be the shared interface device a or the shared interface device b in the method embodiment of FIG. 3-1, or the interface card a or the interface card b in the method embodiment of FIG. 3-2 or FIG. 3-3, and may perform the method and steps performed by the corresponding shared interface device in the method of the corresponding embodiment. The first controller and the second controller separately communicate with at least one memory through the shared interface device. As shown in FIG. 9, the shared interface device 900 includes a receiving module 901, a storage module 902, and an inquiry module 903.

[0249] The receiving module 901 is configured to receive a write command sent by the first controller. For specific implementation, please refer to the relevant description of step S402 in Figure 4 or the relevant description of step S602 in Figure 6. Details will not be described again here.

[0250] The storage module 902 is configured to temporarily store the first data to be written as instructed by the write command in a cache of the storage module 902, and is further configured to asynchronously write the first data temporarily stored in the cache to a first memory in at least one memory. For specific implementations, please refer to the relevant description of step S403. For example, for details, please refer to the relevant description of step S4031 or steps S4031 to S4033, or refer to the relevant description of step S603. For example, for details, please refer to the relevant description of step S6031 or steps S6031 to S6033. The details will not be described again here.

[0251] The receiving module 901 is further configured to receive a read command sent by the second controller after the first controller fails, the read command instructing to query second data, and the second data is all or part of the first data. For specific implementations, please refer to the relevant description of step S702 in Figure 7 or the relevant description of step S802 in Figure 8. Details will not be described again here.

[0252] The query module 903 is configured to obtain all or part of the second data from the cache according to the read command, and provide all or part of the second data to the second controller. For specific implementations, please refer to the relevant description of step S703 in Figure 7 or the relevant description of step S803 in Figure 8. Details will not be described again here.

[0253] Optionally, the cache includes a first partition and a second partition. The first partition is used to temporarily store data for the first controller but is not used to temporarily store data for the second controller. The second partition is used to temporarily store data for the second controller but is not used to temporarily store data for the first controller. A query range from which the query module 903 obtains all or a portion of the second data in the cache includes the first partition and the second partition.

[0254] Optionally, the write instruction instructs writing first data to the first memory, and the storage module 902 is specifically configured to temporarily store the first data in the first partition. The storage module 902 is further configured to sequentially transmit the first data temporarily stored in the first partition and the second data temporarily stored in the second partition to the first memory, wherein the first data includes data written to the first memory as instructed by the first controller, and the second data includes data written to the first memory as instructed by the second controller.

[0255] Optionally, the at least one memory further includes a second memory, and a memory access latency of the second memory is shorter than a memory access latency of the first memory. The storage module 902 is further configured to: synchronize and back up the first data to the second memory after receiving a write instruction, and, when the cache is abnormal, retrieve all or a portion of the second data from the second memory according to a read instruction, and provide all or a portion of the second data to the second controller.

[0256] Optionally, the storage system further includes a third memory connected to the first controller. After the receiving module 901 receives the read command, the query module 903 is further configured to, when the cache is abnormal, obtain all or a portion of the second data from the connected fourth memory in accordance with the read command and provide all or a portion of the second data to the second controller. After the cache becomes abnormal, all or a portion of the second data in the fourth memory is transferred by the first controller from the third memory to the fourth memory via the shared interface device, and the data in the third memory includes the first data backed up by the first controller.

[0257] Optionally, the data includes service data and / or metadata of the service data, the service data being data to be written as requested by a data write request received by the first controller.

[0258] Optionally, the shared interface device is an interface card or a disk enclosure, the interface card being inserted into the first controller or the second controller, and the disk enclosure being configured to incorporate at least one memory.

[0259] Optionally, the shared interface device communicates with the first controller and / or the second controller using a Peripheral Component Interconnect Express PCIe protocol.

[0260] An embodiment of the present application further provides a computing device. The first controller and the second controller separately communicate with at least one memory via the computing device. The computing device includes a memory and a processor. The memory includes a cache. The processor executes computer instructions stored in the memory to enable the computing device to perform the method performed by the shared interface device a or the shared interface device b described above. Optionally, the computing device may be, for example, the interface card a or the interface card b shown in FIG. 3-2, or may be, for example, the disk enclosure a or the disk enclosure b shown in FIG. 3-3.

[0261] The present application further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, can perform some or all of the steps recorded in any one of the above-described method embodiments.

[0262] An embodiment of the present invention further provides a computer program comprising instructions, which, when executed by a computer, may cause the computer to perform some or all of the steps of any of the methods for provisioning region resources.

[0263] In the above-mentioned embodiments, the description of each embodiment has its own focus, and for the parts not described in detail in one embodiment, please refer to the related descriptions of other embodiments.

[0264] Those skilled in the art will understand that the aforementioned computer-readable storage medium includes any non-transitory machine-readable medium that can store program code, such as a USB flash drive, a removable hard disk drive, a magnetic disk, an optical disk, a RAM, an SSD, or a non-volatile memory.

[0265] It should be noted that for ease of explanation, the above-described method embodiments are expressed as a combination of a series of operations. However, those skilled in the art should understand that the present application is not limited to the described order of operations, as some steps may be performed in other orders or simultaneously according to the present application. It should be further appreciated by those skilled in the art that all the embodiments described herein belong to exemplary embodiments, and related operations and modules are not necessarily required by the present application. "A and / or B" in the embodiments of the present application can be understood as two solutions, namely, "A and B" and "A or B."

[0266] In the specification, claims, and accompanying drawings of this application, terms such as "first," "second," "third," and "fourth" are intended to distinguish between similar objects, but do not necessarily indicate a particular order or sequence. Terms so used are interchangeable where appropriate, and it should be understood that this is merely a distinguishing method for describing objects having the same attributes in the embodiments of this application.

[0267] In some embodiments provided in the present application, it should be understood that the disclosed devices may be implemented in other ways. For example, the described device embodiments are merely examples. For example, the division into units is merely a logical division of functions, and other divisions may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the shown or described mutual couplings or direct couplings or communication connections may be implemented via some interfaces. Indirect couplings or communication connections between devices or units may be implemented electronically or in other forms.

[0268] The units described as separate parts may or may not be physically separate, and the parts presented as units may or may not be physical units, and may be located in one location or distributed across multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0269] In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0270] Finally, please note that the above embodiments are only intended to illustrate the technical solutions of the present application, rather than limiting the present invention. [Explanation of symbols]

[0271] 11 ports 12 ports 13 ports 14 ports 21 ports 22 ports 23 ports 31 ports 32 ports 900 Shared Interface Devices 901 Receiver Module 902 Memory Module 903 Query Module

Claims

1. A storage system comprising a first controller and a second controller, a shared interface device plugged into the first controller, the first controller and the second controller separately communicating with at least one memory through the shared interface device in which a cache is disposed; the first controller is configured to send a write command to the shared interface device to instruct it to write first data; the shared interface device is configured to temporarily store the first data in the cache, and is further configured to asynchronously write the first data temporarily stored in the cache to a first memory in the at least one memory; the second controller is configured to send a read command to the shared interface device after the first controller fails, the read command instructing the shared interface device to query second data, the second data being all or a portion of the first data; the shared interface device is further configured to retrieve all or a portion of the second data from the cache in accordance with the read instruction and provide the all or the portion of the second data to the second controller.

2. the second controller is further configured to send a write command to the shared interface device to instruct the shared interface device to write third data; the shared interface device is further configured to temporarily store the third data in the cache, and to asynchronously write the third data temporarily stored in the cache to the first memory. The storage system of claim 1.

3. 3. The storage system of claim 2, wherein the cache comprises a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller, and a query range through which the shared interface device obtains all or a portion of the second data in the cache includes the first partition and the second partition.

4. The shared interface device specifically includes: temporarily storing the first data in the first partition and temporarily storing the third data in the second partition; The first data temporarily stored in the first partition and the third data temporarily stored in the second partition are successively transmitted to the first memory. The storage system of claim 3 , configured to:

5. the at least one memory further comprises a second memory, wherein a memory access latency of the second memory is shorter than a memory access latency of the first memory, and the shared interface device: After receiving the write command, synchronously backing up the first data to the second memory; When the cache is abnormal, obtain the whole or the part of the second data from the second memory according to the read command, and provide the whole or the part of the second data to the second controller.

5. The storage system of claim 1, further configured to:

6. The storage system further includes a third memory connected to the first controller, the first controller backing up the first data in the third memory; When the cache is abnormal, the data backed up in the third memory is transferred to a fourth memory in the at least one memory via the shared interface device. further configured as follows: the shared interface device When the cache is abnormal, obtain the whole or the part of the second data from the fourth memory according to the read command, and provide the whole or the part of the second data to the second controller.

5. The storage system of claim 1, further configured to:

7. 5. The storage system of claim 1, wherein the data includes service data and / or metadata of the service data, the service data being data to be written as requested by a data write request received by the first controller.

8. 5. The storage system of claim 1, wherein the shared interface device is an interface card or a disk enclosure, the interface card being inserted into the first controller or the second controller, and the disk enclosure being configured to incorporate the at least one memory.

9. 5. The storage system of claim 1, wherein the shared interface device communicates with the first controller and / or the second controller using a Peripheral Component Interconnect Express (PCIe) protocol.

10. 5. The storage system of claim 1, wherein each of the at least one memory has only a single port for communicating with the shared interface device.

11. A data processing method, wherein a storage system comprises a first controller and a second controller, a shared interface device is plugged into the first controller, and the first controller and the second controller separately communicate with at least one memory through the shared interface device in which a cache is located, the method comprising: sending, by the first controller, a write command to the shared interface device to instruct it to write first data; temporarily storing, by the shared interface device, the first data in the cache, and asynchronously writing, by the shared interface device, the first data temporarily stored in the cache to a first memory in the at least one memory; sending a read command by the second controller to the shared interface device after the first controller fails, the read command instructing the shared interface device to query second data, the second data being all or a portion of the first data; obtaining, by the shared interface device, all or a portion of the second data from the cache in accordance with the read instruction, and providing the all or the portion of the second data to the second controller; data processing methods, including

12. The method comprises: sending, by the second controller, a write command to the shared interface device to instruct it to write third data; temporarily storing the third data in the cache by the shared interface device, and asynchronously writing the third data temporarily stored in the cache to the first memory; 12. The method of claim 11, further comprising:

13. 13. The method of claim 12, wherein the cache comprises a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller, and a query range from which the shared interface device obtains the whole or part of the second data in the cache includes the first partition and the second partition.

14. The step of temporarily storing the first data and the third data in the cache by the shared interface device includes: temporarily storing the first data in the first partition and temporarily storing the third data in the second partition by the shared interface device. Including, The step of asynchronously writing the first data and the third data temporarily stored in the cache to the first memory by the shared interface device includes: transmitting, by the shared interface device, the first data temporarily stored in the first partition and the third data temporarily stored in the second partition to the first memory in succession; 14. The method of claim 13, comprising:

15. The at least one memory further comprises a second memory, wherein a memory access latency of the second memory is shorter than a memory access latency of the first memory, and the method further comprises: synchronously backing up the first data to the second memory by the shared interface device after receiving the write command; by the shared interface device, when the cache is abnormal, obtaining all or a portion of the second data from the second memory according to the read command, and providing all or a portion of the second data to the second controller; 15. The method of any one of claims 11 to 14, further comprising:

16. The storage system of claim 1, wherein the first controller is connected to the second controller via a Peripheral Component Interconnect Express (PCIe) device.

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