Flushing cache lines to persistent memory

Abstract

To provide a method for optimizing flush operations in devices by prioritizing persistent cache line flushing during a power failure, an integrated circuit system, a program, and a recording medium.SOLUTION: In a device of an integrated circuit system, processing for tagging a cache line that stores a memory write request includes the steps of: receiving, via a communication link, a cache line comprising a destination address; determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent; and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] The present disclosure relates generally to flashing integrated circuits, and more particularly to handling persistent memory during flashing of one or more circuit dies.

[0002] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, as described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

[0003] A Peripheral Component Interconnect Express (PCIe) link is used to connect devices (e.g., field programmable gate arrays (FPGAs)) to a central processing unit. The devices may receive instructions from the central processing unit and may operate according to the instructions to perform one or more tasks. The devices may be connected to one or more memories, but the one or more memories may be private to the device (e.g., not readily accessible to the central processing unit) due to limitations of the PCIe link. As such, the central processing unit and the device or memory controller of the one or more memories may need to perform direct media access (DMA) operations to communicate with each other and with the one or more memories (e.g., to perform memory reads or writes to the one or more memories). Such DMA is expensive in power and time.

[0004] To overcome memory-related limitations of Peripheral Component Interconnect Express (PCIe) links, communication links (e.g., coherent links) can be used to increase the amount of memory or storage readily available to a computer processing unit (CPU) and managed by an operating system. In fact, when a coherent link is used to connect a device to a central processing unit, the device and the central processing unit can join each other's memory pools without performing direct media access (DMA) operations. That is, the memory associated with or managed by the central processing unit and the memory associated with or managed by the device can be standard memory via a coherent link and are logically similar. Such an application is called memory expansion.

[0005] One type of memory that may be coupled to a central processing unit is persistent memory. Persistent memory stores data that persists even when there is a power loss. That is, data stored in persistent memory is preserved during or after a power loss event. Another type of memory that may be coupled to a central processing unit is volatile memory. Volatile memory stores data that is lost when the volatile memory loses power. Similar types of memory may be coupled to devices. Coherent links allow both persistent and volatile memory coupled to either the central processing unit and the device to function as standard memory for the operating system. A flush instruction may move cache lines directed to persistent memory and cache lines directed to volatile memory from the central processing unit to their destination memories (e.g., persistent memory coupled to the device and volatile memory coupled to the device). However, tags or distinctions between cache lines of persistent memory or cache lines of volatile memory may not exist in the memory hierarchy. [Brief explanation of the drawings]

[0006] The various aspects of the present disclosure may be better understood from the following detailed description and by reference to the drawings, in which:

[0007] [Figure 1] 1 is a block diagram of an integrated circuit system including a central processing unit, a device, and a coherent link, where the device is coupled to persistent memory and volatile memory, according to an embodiment of the present disclosure.

[0008] [Figure 2] FIG. 2 is a block diagram of components that may result in power loss flow according to an embodiment of the present disclosure.

[0009] [Figure 3] FIG. 1 is a block diagram of components with data path flow for a cache line for a single channel memory controller according to an embodiment of the present disclosure.

[0010] [Figure 4] 10 is a flowchart illustrating a process for tagging a cache line that stores a memory write request directed to persistent memory according to an embodiment of the present disclosure.

[0011] [Figure 5] 10 is a flowchart illustrating a process for determining whether to commit or gracefully drop a cache line that stores a memory write request, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] One or more specific embodiments are described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described herein. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's particular objectives, including adherence to system-related and business-related constraints, which may vary from implementation to implementation. Moreover, it should be understood that such a development effort may be complex and time-consuming, but is nevertheless a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0013] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, it should be understood that references to "one embodiment" or "embodiments" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0014] An integrated circuit system may include a central processing unit and devices connected to the central processing unit via a coherent link. The devices may support or be coupled to persistent and volatile memory. Because the central processing unit and devices are coherently connected, the memory coupled to the devices can participate in the central processing unit's memory pool. As such, the memory coupled to the central processing unit and the memory coupled to the devices may be logically similar and function as standard memory. Many times, the integrated circuit system may receive a power failure signal. It is beneficial for the integrated circuit system to maintain certain memories during and after a power failure event. In practice, only certain types of memory can maintain data after losing power.

[0015]

[0003] Central processing units and devices may be coupled to various types of memory, including volatile memory and persistent memory. Volatile memory stores data that is lost when the volatile memory loses power. Thus, after a power loss event, data stored in volatile memory is not recoverable because the volatile memory requires some power to maintain its state.

[0016] Persistent memory stores data that persists even when there is a power loss, i.e., data stored in persistent memory is preserved during or after a power loss event. Because data stored in a cache line is not persistent during a power loss event until it is present in persistent memory, it is beneficial to flush cache lines that are directed to persistent memory to ensure that they reach persistent memory.

[0017] The present embodiments generally relate to systems and methods for flushing cache lines to persistent memory. The systems and methods provided herein include tagging cache lines to provide a distinction between cache lines directed to persistent memory and cache lines directed to volatile memory. For example, cache lines may be tagged as directed to persistent memory and / or volatile memory in the memory hierarchy of an integrated circuit system. Cache lines directed to storage may also be tagged. The systems and methods disclosed herein may be particularly useful during a power loss event in an integrated circuit system. For example, in response to an integrated circuit system receiving an indication that a power loss event is occurring, cache lines directed to volatile memory may be gracefully completed (e.g., acknowledged and dropped), while cache lines directed to persistent memory may be committed to persistent memory. Advantages of the systems and methods disclosed herein include, among other things, optimization of memory controller processing latency, read processing latency, volatile write processing latency, and persistent write processing latency. In fact, using current technology, memory controller processing latency, read processing latency, volatile write processing latency, and persistent write processing latency can be optimized, as only tagged or only untagged cache lines can be processed and fully flushed in an integrated circuit system, which can be particularly useful during a power loss event.

[0018] FIG. 1 is a block diagram of an integrated circuit system 10 according to an embodiment of the present disclosure. The integrated circuit system 10 includes a central processing unit 12, a device 14, a communication link (e.g., in the illustrated embodiment, a coherent link 16) attaching the device 14 to the central processing unit 12, and a battery backup 40. The central processing unit 12 may be any suitable central processing unit, such as an INTEL® XEON® processor. The device 14 may be any suitable device, such as a field programmable gate array (FPGA) device or an application specific integrated circuit (ASIC) device. The central processing unit 12 and the device 14 are coupled to each other via a coherent link 16 (e.g., a coherent attached actuator or a coherent attached device). For example, the coherent link 16 may be any suitable coherent link, such as an INTEL® Ultra Path Interconnect (INTEL UPI) or a Computer Express Link (CXL). The integrated circuit system 10 also includes a memory 18 and a storage 20 coupled to the central processing unit 12 , and a memory 22 and a storage 24 coupled to the device 14 .

[0019] Specifically, in the illustrated embodiment, central processing unit 12 is coupled to volatile memory 26 (e.g., one or more of double data rate 4 (DDR4), double data rate 5 (DDR5), low power double data rate 4 (LPDDR4)), persistent memory 28 (e.g., Intel Optane persistent memory, Intel Optane solid state device (SSD), Intel Optane dual in-line memory module (DIMM)), and storage 20. Volatile memory 26, persistent memory 28, and storage 20 are managed by the operating system of integrated circuit system 10. Device 14 is coupled to volatile memory 30, persistent memory 32, and storage 24, which are also managed by the operating system of integrated circuit system 10. Coherent link 16 enables device 14 to function as a memory controller for volatile memory 30 and persistent memory 32 for central processing unit 12. The coherent link 16 also allows the volatile memory 30 and persistent memory 32 to function as standard operating system memory and can be accessed by the central processing unit 12 without using direct media access (DMA). The storage 24 coupled to the device 14 is also standard operating system storage and can therefore be accessed by the central processing unit 12 without using direct media access (DMA). The volatile memory 26, persistent memory 28, and storage 20 may be logically similar to the volatile memory 30, persistent memory 32, and storage 24, each functioning as standard operating system memory or storage, respectively. Therefore, direct media access (DMA) operations between the central processing unit 12 and the device 14 may not be required for the central processing unit 12 to write to or read from the persistent memory 32, volatile memory 30, or storage 24.

[0020] Data may move around integrated circuit system 10 in amounts called cache lines (e.g., 64 bytes). Cache lines may carry requests, such as read or write requests to read from or write to memory or storage. Cache lines from central processing unit 12 may be provided to device 14 over coherent link 16. Coherent link 16 may be configured to perform operations including decoding cache lines and directing them to particular memory channels. Device 14 includes a volatile memory data path 34, a persistent memory data path 36, and a storage data path 38. These data paths function to process cache lines directed to the respective data paths. That is, cache lines for volatile memory 30 may be sent to volatile memory data path 34, cache lines for persistent memory 32 may be sent to persistent memory data path 36, and cache lines for storage 24 may be placed on storage data path 38. In some embodiments, the only data path within device 14 is persistent memory data path 36. Additionally, in some embodiments, device 14, memory 22, and storage 24 may be located on a Peripheral Component Interconnect Express (PCIe) card or on the motherboard of integrated circuit system 10.

[0021] Integrated circuit system 10 is configured to identify cache lines directed to persistent memory and tag them with metadata to distinguish them in the memory hierarchy from cache lines directed to volatile memory. For example, logic circuitry of central processing unit 12 may be configured to identify persistent memory directed to a cache line and tag it with metadata indicating that the cache line is directed to persistent memory 28, and logic circuitry or soft logic of or on device 14 may be configured to identify persistent memory directed to a cache line and tag it with metadata indicating that the cache line is directed to persistent memory 32. In some cases, integrated circuit system 10 may determine a type of memory or storage associated with a destination address of the cache line. The type of memory or storage may be persistent (e.g., persistent memory, storage) or non-persistent (e.g., volatile memory), and tagging the cache line may include tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.

[0022] It should be noted that while the systems and techniques described herein make specific reference to coherent links (e.g., coherent link 16), embodiments are not limited to coherent links. Indeed, the systems and techniques described herein may relate to integrated circuit devices that relate to non-coherent links (e.g., standard Peripheral Component Interconnect Express (PCIe) instead of coherent link 16). Thus, in some embodiments, the integrated circuit device may alternatively include a non-coherent link coupling device 14 to central processing unit 12.

[0023] As integrated circuit system 10 operates, central processing unit 12 may perform operations related to persistent memory, volatile memory, and / or storage. Accordingly, cache lines may be moved from central processing unit 12 to a desired persistent memory destination, a desired volatile memory destination, and / or a desired storage destination. Central processing unit 12 may flush cache lines to memory or storage destinations. For example, central processing unit 12 may flush cache lines to a power-fail-protected area to protect data when a power-fail signal is received by central processing unit 12. Flushing may involve moving cache lines related to a request, such as a write request, to the particular destination of the write request. For example, a cache line originating from central processing unit 12 and storing the write request in persistent memory 28 may be flushed to persistent memory 28, which is the cache line's final destination. Cache lines may be flushed from central processing unit 12 to volatile memory 26, persistent memory 28, or storage 20. Cache lines may also be flushed from central processing unit 12 to volatile memory 30, persistent memory 32, or storage 24. It takes a finite amount of time for volatile memory 30, cache lines to be flushed to persistent memory 32 or storage 24. Cache lines destined for volatile memory 30, persistent memory 32, or storage 24 are pending (e.g., not committed to their destination) until they reach volatile memory 30, persistent memory 32, or storage 24. For example, a cache line directed to persistent memory 32 is pending if the cache line is still on coherent link 16, in the memory hierarchy of central processing unit 12, or in device 14. In fact, the cache line is not committed to memory until it reaches its particular memory or storage destination. It is important to note that pending cache lines may be subject to being dropped if integrated circuit system 10 does not have enough power to commit the cache line to its memory destination.

[0024] A flush operation may involve the transmission of cache lines destined for memory. For example, cache lines originating from central processing unit 12 may be destined for persistent memory 32 coupled to device 14. As such, the cache lines are transmitted from central processing unit 12 over coherent link 16 to device 14 and ultimately to persistent memory 32. In some cases, in response to receiving a power failure signal, integrated circuit system 10 may commit to memory only those cache lines tagged as destined for persistent memory 28 or persistent memory 32 to expedite completion of the flush operation. In these cases, selectively committing to memory only cache lines destined for persistent memory 28 or persistent memory 32, as indicated by the tagging, while refraining from committing cache lines destined for volatile memory 26 or volatile memory 30, may expedite completion of the flush operation. In practice, such tag-based selective committing can be used to expedite the flush operation and reduce the amount of power required to maintain integrated circuit system 10 after integrated circuit system 10 detects a power failure. Therefore, the total time to flush all cache lines may be reduced to the total time to flush the queue containing cache lines directed to persistent memory 28 and cache lines directed to persistent memory 32.

[0025] At some point, a power failure may occur on integrated circuit system 10. That is, the power supply of integrated circuit system 10 may fail to provide integrated circuit system 10 with enough power to continue processing via, for example, alternating current (A / C) power. In the event of a power failure, integrated circuit system 10 may be susceptible to losing information stored in pending cachelines, which are cachelines that have not yet been committed to memory or storage, and / or information stored in volatile memory 26 and volatile memory 30. As described above, persistent memory 28, persistent memory 32, storage 20, and storage 24 may be configured to avoid losing cacheline data committed to persistent memory or storage upon a power loss, since persistent memory and storage are preserved. Thus, if cachelines directed to persistent memory are not flushed and committed to persistent memory, integrated circuit system 10 may lose information in cachelines directed to persistent memory. Furthermore, flushing cachelines may take a finite amount of time to complete. Therefore, it is desirable to have a secondary power supply or power sources that can provide power to integrated circuit system 10 in the event that integrated circuit system 10 detects a power failure so that its cache lines, particularly those destined for persistent memory, are allotted sufficient time to be fully flushed to persistent memory.

[0026] With this in mind, to mitigate the effects of power failures, integrated circuit system 10 includes a battery backup 40. Battery backup 40 is configured to provide power to integrated circuit system 10 or certain components of integrated circuit system 10 in response to detecting a power failure of the power supply of integrated circuit system 10. Battery backup 40 may provide power to components of integrated circuit system 10 for a finite amount of time (e.g., 100 microseconds, 10 milliseconds). Such power may be used, for example, to flush cache lines (e.g., memory write requests) from central processing unit 12 to volatile memory 30, persistent memory 32, or storage 24. In this embodiment, battery backup 40 is configured to provide sufficient power to commit pending persistent memory cache lines to persistent memory. In some embodiments, battery backup 40 may be configured to provide sufficient power to commit pending persistent memory cache lines to persistent memory and to commit pending cache lines to storage. For example, the duration of the sustained power may be determined based on the amount of cache lines that need to be flushed to persistent memory or storage. The battery backup 40 may be optimized to flush cache lines of persistent memory without considering flushing cache lines of volatile memory, and in fact, cache lines of volatile memory may not need to be flushed to system memory because volatile memory loses its state after failing to receive power.

[0027] When a power loss event occurs, cachelines that are still pending (e.g., not in persistent memory 28 or 32, storage 20 or 24, or volatile memory 26 or 30) may not reach their destination. For example, even though a cacheline may be intended to be committed to persistent memory 28 or 32, the cacheline is not persistent until the cacheline is committed to persistent memory 28 or 32. Thus, if a cacheline is destined for persistent memory but is still pending (e.g., not in persistent memory) and a power failure occurs, the cacheline is not preserved but rather lost or dropped. When power is restored to integrated circuit system 10 after dropping a cacheline destined for persistent memory 28 or 32, central processing unit 12 may not be able to read the cacheline from persistent memory 28 or 32 because the cacheline was dropped before entering persistent memory 28 or 32. Similarly, a cache line relating to persistent memory 28 or persistent memory 32, storage 20 or storage 24, or volatile memory 26 or volatile memory 30 is not considered to be flushed until the cache line reaches persistent memory 28 or persistent memory 32, storage 20 or storage 24, or volatile memory 26 or volatile memory 30.

[0028] Power from battery backup 40 may be used by integrated circuit system 10 to flush cache lines to their respective memory or storage in the event of a power failure. In response to receiving an indication of a power failure, integrated circuit system 10 may be configured to prioritize flushing of certain cache lines. For example, integrated circuit system 10 may be configured to process only cache lines that are directed to persistent memory 28 or persistent memory 32. As described above, metadata tagging may indicate that a cache line is directed to persistent memory 28 or persistent memory 32. Because cache lines directed to persistent memory 28 or persistent memory 32 are distinguished from cache lines directed to other memories via metadata tagging, integrated circuit system 10 may identify and process cache lines that are directed to persistent memory and gracefully complete (e.g., respond with a response (default response), dropped) them, and drop cache lines that are not directed to persistent memory (e.g., persistent memory 28 or persistent memory 32) as indicated by the metadata tagging. Gracefully completing may include responding to cachelines with a default response (e.g., one or more zeros). Thus, battery backup 40 may have reduced power sustainment requirements because fewer cachelines need to be committed to memory. For example, battery backup 40 may only need to have enough power to commit cachelines to persistent memory after a power failure of integrated circuit system 10's power source (e.g., alternating current (A / C) power). This may be useful for committing cachelines directed to persistent memory 28 or persistent memory 32 to memory and gracefully completing (e.g., responding with a response and dropping) cachelines directed to volatile memory 26 or volatile memory 30, since cachelines directed to volatile memory 26 or volatile memory 30 will be lost if integrated circuit system 10 shuts down.This is because if volatile memory 26 and volatile memory 30 lose power, the data stored in volatile memory 26 and volatile memory 30 will be lost. Volatile memory 26 and volatile memory 30 require power to maintain any information stored in their respective volatile memories 26 and 30. In some cases, it may also be useful to commit cache lines destined for storage 20 or storage 24 to storage and refrain from committing other cache lines. Indeed, in some embodiments, cache lines destined for persistent memory 28, persistent memory 32, storage 20, and / or storage 24 may be selectively guaranteed to be committed to persistent memory and storage, as indicated based on cache line metadata tagging, distinguishing the processing of these cache lines from cache lines in volatile memory. In such embodiments, the committing of these distinguished cache lines may be guaranteed by ensuring that battery backup 40 has sufficient power to commit the distinguished cache lines to persistent memory or storage after a power failure.

[0029] For example, at a particular time, 100 cache lines may be pending arrival at memory managed by device 14. 90 of the 100 cache lines may be destined for volatile memory 30, and 10 cache lines may be destined for persistent memory 32. If a power failure is detected by integrated circuit system 10, integrated circuit system 10 may process and commit the 10 cache lines destined for persistent memory 32 and simply complete (e.g., acknowledge and drop) the 90 cache lines destined for volatile memory 26. Thus, using this embodiment, battery backup 40 may be sufficient to provide power to integrated circuit system 10 for 1 / 10 of the time it takes to process and commit all 100 cache lines. The reduced time to flush cache lines destined for persistent memory, caused in part by refraining from committing cache lines of volatile memory to volatile memory, allows for a reduced battery size. Thus, battery backup 40 may be reduced, resulting in reduced battery cost and size. Indeed, in the present example, battery backup 40 only needs to provide enough power for 10 cache lines directed to persistent memory 32, as opposed to the power required to flush 100 cache lines. Thus, battery backup 40 may store a reduced amount of energy, since the time required to keep integrated circuit system 10 alive after a power failure is reduced.

[0030] In some embodiments, battery backup 40 is designed based on the depth of the persistent memory cache line queue. For example, battery backup 40 may be designed to power integrated circuit system 10 for a period calculated based on the time it takes to process and commit cache lines from the persistent memory cache line queue. In fact, battery backup 40 may be tuned to support cache lines destined for persistent memory without considering cache lines destined for volatile memory. Thus, in some embodiments, sizing battery backup 40 affects the persistent memory cache line queue but not the volatile memory cache line queue. In some embodiments, battery backup 40 may be designed based on the depth of the persistent memory cache line queue and the storage cache line queue.

[0031] In some embodiments, the integrated circuit system 10 may selectively provide backup power on certain cache line paths to reduce the amount of backup power and costs associated with the battery backup 40. Specifically, the device 14 may include multiple power supplies. Each of the multiple power supplies may power a specific memory controller. The battery backup 40 may selectively power only the memory controller of the persistent memory 32 in the event of a power failure. Thus, the power supply powering the volatile memory 30 fails without using backup power. As another example, the battery backup 40 may only selectively power the persistent memory data path 36, while the storage data path 38 and the volatile memory data path 34 do not receive backup power from the power supply in response to a power failure. In different embodiments, other combinations of battery backup power may exist. For example, the battery backup 40 may be configured to power the persistent memory data path 36 and the storage data path 38, while the volatile memory data path 34 remains unpowered.

[0032] 2 is a block diagram 60 of the flow that occurs in response to the detection of a power failure with respect to integrated circuit system 10, according to an exemplary embodiment of the present disclosure. In the embodiment shown, central processing unit 12 of integrated circuit system 10 includes a platform controller unit (PCU 62), core processors (cores 64), a memory controller (MC) 66, and a storage controller (SC) 68. Memory controller 66 represents two memory controllers, one for volatile memory 26 and one for persistent memory 28. Storage controller 68 manages storage 20.

[0033] In the illustrated embodiment, device 14 includes coherent link logic 70 (e.g., soft INTEL Ultra Path Interconnect (INTEL UPI) logic), which includes a decoder 72 (e.g., a coherent link decoder) for decoding coherent link requests and a write pending queue (“wpq”) 74. Write pending queue 74 represents multiple write pending queues, one for volatile memory 30, one for persistent memory 32, and one for storage 24. Device 14 also includes a storage controller 76 for managing storage 24 and a memory controller 78. Memory controller 78 represents two memory controllers, one for volatile memory 30 and one for persistent memory 32. Memory controller 78 may include a non-transitory, tangible, computer-readable medium containing instructions executable by a processor of memory controller 78. The instructions may include instructions for managing memory coupled to memory controller 78 and requests configured to access memory coupled to memory controller 78. The storage controller 76 and memory controller 78 may be configured to store pending transactions (e.g., read requests, write requests).

[0034] In the illustrated embodiment, power supply 80 (e.g., an AC power supply) provides power to integrated circuit system 10. In some embodiments, when power supply 80 provides power to integrated circuit system 10, integrated circuit system 10 may process both read and write requests for cache lines directed to storage or memory, regardless of whether a tag is detected. At some point, a power failure may be detected by integrated circuit system 10. In response to detecting a power failure, a signal indicating a power failure may be asserted (e.g., by power supply 80) to notify platform logic 82 (e.g., platform logic) of the detected power failure. The signal may also cause platform logic 82 to initiate power loss processing. A timer 84 (e.g., a platform control hub ADR timer) may be instructed to start for how long integrated circuit system 10 may be powered after the power failure, and a signal may be sent to both central processing unit 12 and device 14 to notify the power failure. In response to receiving this signal (e.g., a data packet indicating a power failure), central processing unit 12 may prepare to issue a flush of its memory hierarchy. Specifically, central processing unit 12 may selectively flush and commit cachelines to persistent memory 28 and / or storage 20 based on the tagging of the cachelines' metadata, while refraining from committing cachelines directed to volatile memory 26 to volatile memory 26. Cachelines directed to volatile memory 26 may be completed gracefully (e.g., acknowledged with a response and dropped). Similarly, device 14 may selectively change from committing cachelines directed to persistent memory 32, volatile memory 30, and storage 24 to simply flushing and committing cachelines directed to persistent memory 32 or storage 24, while refraining from committing cachelines directed to volatile memory 30 to volatile memory 30, based on the tagging of the cachelines' metadata. Cachelines directed to volatile memory 30 may be processed gracefully (e.g., acknowledged with a response and dropped).The battery backup 40 may provide power to the integrated circuit system 10 for a period of time specified by the timer. The timing of the battery backup 40 and the timer 84 may be identified or determined based on a worst-case scenario for flushing cache lines to persistent memory 28, persistent memory 32, storage 20, and / or storage 24. For example, the worst-case scenario may include, or may be based at least in part on, the time it may take for one or more cache lines destined for persistent memory 28 to reside on the central processing unit 12 and be flushed to persistent memory 28. The battery backup may be sized based on a queue length corresponding to the amount of cache lines committed to persistent memory 28, and not based on a queue length corresponding to the amount of cache lines committed to volatile memory 30.

[0035] As previously mentioned, pending cachelines may reside in various locations along integrated circuit system 10. By way of example, cachelines directed to any of persistent memory 28, volatile memory 26, and storage 20 may be located in the memory hierarchy of central processing unit 12, and cachelines directed to any of persistent memory 32, volatile memory 30, and storage 24 may be located in the memory hierarchy of central processing unit 12, coherent link 16, or device 14. In either case, during processing being performed in response to detecting a power failure, integrated circuit system 10 may transition itself from processing and committing pending cachelines directed to each memory and storage to identifying and committing each cacheline directed to persistent memory or storage to persistent memory or storage and simply completing (e.g., responding and dropping) cachelines directed to volatile memory.

[0036] 3 is a block diagram of a data path flow for a cache line entering device 14 from coherent link 16 and destined for memory for a single channel memory controller (e.g., a memory write request from central processing unit 12) in accordance with an embodiment of the present disclosure. In some embodiments, the data path flow shown in FIG. 3 may be used when integrated circuit system 10 detects a power failure. In the embodiment shown, device 14 includes a first die 100 and a second die 102. In first die 100, a cache line entering device 14 via coherent link 16 from central processing unit 12 is recorded in an appropriate queue. The cache line is also configured to pass a link cyclic redundancy check (LCRC) 104. In the illustrated embodiment, a cacheline may be stored in a response queue (Resp FIFO 106), a request queue (Req FIFO 108), a write batch queue (WB FIFO 110), a non-coherent bypass queue (NCB FIFO 112), a non-coherent standard queue (NCS FIFO 114), or a snooze queue (SNP FIFO 116) based on the attributes of the cacheline. For example, a cacheline associated with a memory write request may proceed to the write batch queue (WB FIFO 110). After the cacheline is stored in the appropriate queue, the cacheline proceeds to an advanced interface bus (AIB 118) connecting the first die 100 to the second die 102. The cacheline then proceeds to the second die 102 of the device 14, which, in the illustrated embodiment, includes coherent link logic (CL logic 120) (e.g., coherent link soft logic).

[0037] Within coherent link soft logic 120, decoder 122 identifies cache lines that are destined for persistent memory and tags them with metadata. Alternatively, in some embodiments, cache lines that are destined for volatile memory may be tagged with metadata. The cache lines, and their tags, if applicable, then proceed downstream to the appropriate queues, including a coherent read pending queue (RPQ-C 124), a non-coherent read pending queue (RPQ-NC 126), and a write pending queue (WPQ 128). At second die 102 of device 14, it is determined whether the cache line is destined for persistent memory 129. If device 14 determines that the cache line is destined for persistent memory 129, then device 14 tags the cache line with metadata indicating that the cache line is destined for persistent memory 129. Alternatively, if device 14 determines that the cacheline is destined for volatile memory 130, then device 14 may tag the cacheline with metadata indicating that the cacheline is destined for volatile memory 130. The cacheline then proceeds downstream to memory controller 132, which may accept the cacheline into its respective queue 134. Cachelines that are not tagged as being destined for persistent memory 129 are straightforwardly completed (e.g., acknowledged with a response and dropped) because these cachelines may be destined for volatile memory 130. In some embodiments, cachelines that are not tagged as being destined for persistent memory 129 are dropped in coherent link soft logic 120 or memory controller 132. In some embodiments, hard logic, or a combination of coherent link soft logic and hard logic, may perform processing similar to coherent link soft logic 120.

[0038] In some embodiments, control and status registers (CSRs) within coherent link logic 120 can be configured with supported downstream memories, memory ranges, and memory types. Example configuration and status register definitions for each memory controller are provided in Table 1 below. [Table 1]

[0039] Table 1 shows various types of memory based on the configuration of memory controlled by the memory controller. The TYPE field may indicate PERSISTENT if the memory controller manages only persistent memory, or VOLATILE if the memory controller manages only volatile memory. The BOTH_VP and BOTH_VP types indicate support / management for both persistent and volatile memory. In the illustrated embodiment, memory controller 132 manages persistent memory 129 and volatile memory 130, so the type indicated by the memory controller is either BOTH_PV or BOTH_VP. For the purposes of this discussion, we will assume that the TYPE is BOTH_VP, indicating that memory addresses from START_RANGE to PARTITION are memory addresses in volatile memory 130 and that memory addresses from PARTITION to END_RANGE are memory addresses in persistent memory 129.

[0040] Table 2 below provides an example of how cache lines directed to a memory controller are tagged according to an embodiment. [Table 2]

[0041] In Table 2, different types of cache lines are tagged based on the position of the memory address within the cache line and / or the type of memory managed by memory controller 132. Coherent link logic 120 (e.g., decoder 122) tags a cache line as being directed to persistent memory if the request address is between START_RANGE and END_RANGE and the only type of memory supported by the memory controller is persistent memory. Coherent link logic 120 does not tag a cache line as being directed to persistent memory if the request address is between START_RANGE and END_RANGE and the only type of memory supported by the memory controller is volatile memory. Because the memory controller manages both persistent memory and volatile memory, and TYPE is BOTH_VP, indicating that memory addresses between START_RANGE and PARTITION are memory addresses of volatile memory and memory addresses between PARTITION and END_RANGE are memory addresses of persistent memory, the position of the memory address within the cache line is determined to determine whether the cache line is tagged. For example, if the request address is between START_RANGE and PARTITION and the type of memory managed by the memory controller is BOTH_VP, the coherent link logic 120 does not tag the cache line because the requested memory address is volatile memory. If the request address is between PARTITION and END_RANGE and the type of memory managed by the memory controller is BOTH_VP, the coherent link logic 120 tags the cache line because the requested memory address is persistent memory.

[0042] 3, there may be a data path flow for a cache line entering device 14 from coherent link 16 with respect to storage destination (e.g., a storage write request from central processing unit 12). In practice, a storage controller (not shown in FIG. 3) may manage storage 136, and decoder 122 may determine whether a storage request for a cache line is tagged and whether it is committed to storage 136.

[0043] 3, cache lines directed to volatile memory 130 or directed to storage 136 may additionally and / or alternatively be tagged with metadata. For example, memory cache lines directed to volatile memory 130 may be tagged with metadata, and untagged memory cache lines (e.g., cache lines directed to persistent memory) may be identified and committed to persistent memory.

[0044] 4 is a process 160 for tagging a cache line that is directed to persistent memory and that stores a memory write request. In some embodiments, process 160 may be performed by device 14, central processing unit 12, or decoder 72.

[0045] Process 160 includes receiving a memory write request (block 162). The memory write request may originate from central processing unit 12 and may be directed to persistent memory managed by device 14. Alternatively, the memory write request may originate from central processing unit 12 and may be directed to persistent memory managed by central processing unit 12.

[0046] It is determined whether the memory write request is destined for persistent memory (block 164). For example, the range address of the memory write request may be decoded via a decoder (e.g., decoder 122 or a decoder of central processing unit 12) to determine the destination of the memory write request.

[0047] If the memory write request is destined for persistent memory, the process 160 proceeds to tagging the memory write request as being destined for persistent memory (block 166). The memory write request may be tagged using metadata. For example, in response to decoding a range address of the memory write request and determining, via the decoder, that the range address is for persistent memory, the decoder may tag the memory write request as being destined for persistent memory.

[0048] Returning to block 164, if the memory write request is not destined for persistent memory, process 160 does not proceed to tagging the memory write request as being directed to persistent memory (block 168). Note that in some embodiments, write requests that are not tagged as being destined for persistent memory may be further tagged, i.e., tagged as being directed to an appropriate destination (e.g., volatile memory or storage). In these embodiments, tagging these write requests not destined for persistent memory may indicate a different destination. Similar processing illustrated in process 160 may be performed by a storage controller. Additionally, cache lines storing other requests (e.g., read requests) destined for memory may be utilized in embodiments of process 160.

[0049] Other embodiments of process 160 include tagging or distinguishing between cache lines directed to storage and / or cache lines directed to volatile memory. For example, cache lines directed to storage may be decoded via a decoder to determine a range address of the storage destination. Based on the determination of the range address of the cache line directed to storage, the cache line may or may not be tagged. Similarly, cache lines directed to volatile memory may be decoded via a decoder to determine the range address of the cache line's memory destination. Based on the determination that the range address of the cache line is directed to volatile memory, the cache line may be tagged, thus providing a distinction between cache lines of persistent memory and cache lines of volatile memory.

[0050] 5 illustrates a process 180 for determining whether to commit or gracefully drop (e.g., drop in response) a cache line storing a memory write request in accordance with an embodiment of the present disclosure. In some embodiments, process 180 may be performed by device 14 or central processing unit 12. For example, process 180 may be performed by a memory controller of central processing unit 12 or a memory controller of device 14.

[0051] At block 182, the memory controller receives a memory write request. The memory write request may include data to be written to a memory managed by the memory controller.

[0052] The memory controller proceeds to determine whether the memory write request is tagged (block 184). For example, the memory write request may be tagged with metadata that can be used to determine the destination of the memory write request, i.e., whether it is a memory write request to persistent memory or a memory write request to volatile memory. The metadata may indicate that the memory write request is directed to persistent memory.

[0053] In response to the memory write request being tagged, the memory controller may commit the memory write request to memory (block 186). For example, in response to the memory write request being tagged as being directed to persistent memory, the memory write request may be committed to persistent memory.

[0054] Returning to block 184, if the memory controller determines that the memory write request is not tagged, the memory controller may gracefully complete (e.g., respond with a response and drop) the memory write request (block 188). Such operation of process 180 may be particularly beneficial when memory write requests tagged as being directed to persistent memory and untagged memory write requests are directed to volatile memory. In particular, in this case, memory write requests directed to volatile memory may be gracefully completed (e.g., responded with a response and dropped) during a power failure because data in volatile memory is lost after a power failure occurs.

[0055] When a storage controller receives a storage write request, a similar process shown in process 180 may be performed by the storage controller. Also, cache lines storing other requests (e.g., read requests) may be utilized in embodiments of process 180. During a power failure event, a memory controller or storage controller may selectively process read requests by responding with zeros and gracefully terminating read requests. Also, during a power failure event, a memory controller or storage controller may selectively process write requests by committing tagged write requests destined for memory or storage and gracefully completing (e.g., responding with a response and dropping) untagged write requests.

[0056] The present systems and techniques relate to embodiments for optimizing flush operations in a device by prioritizing persistent cache lines for flushing during a power failure. In particular, the present systems and techniques reduce the time required for the integrated circuit system 10 to remain operational after the integrated circuit system 10 detects a power failure by selectively refraining from completing the flush of certain cache lines (e.g., not committing the cache lines to certain memory or storage). Such reduced time also reduces the amount of power required to complete pending flush operations. As such, battery backup size may be based on the amount of cache lines directed to persistent memory, as opposed to based on the amount of cache lines directed to persistent memory and the amount of cache lines directed to volatile memory.

[0057] Illustrative Embodiments

[0058] Exemplary embodiment 1. receiving a cache line having a destination address at a device of the integrated circuit system via a coherent link; determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent; tagging the cache line with metadata in a manner indicating a type of memory or storage associated with the destination address; A method for providing

[0059] Exemplary embodiment 2. In response to determining that a type of memory or storage associated with the destination address is persistent, tagging the cache line with metadata indicating that the cache line is directed to persistent memory; In response to determining that a type of memory or storage associated with the destination address is non-persistent, refraining from tagging the cache line with metadata indicating that the cache line is directed to persistent memory; processing the cache line based on the presence or absence of metadata indicating that the cache line is directed to persistent memory; The method of exemplary embodiment 1, comprising:

[0060] Exemplary embodiment 3. receiving a power fail signal at the integrated circuit system; In response to receiving a power fail signal and a cache line having a memory write request, selectively committing the cache line to persistent memory if the tagging step indicates that the type of memory or storage associated with the destination address is persistent; otherwise, selectively refraining from committing the cache line to volatile memory if the tagging step indicates that the type of memory associated with the destination address is non-persistent. The method of exemplary embodiment 1, comprising:

[0061] Exemplary embodiment 4. In response to receiving a power fail signal and a cache line with a memory read request, dropping the memory read request and returning a response indicating the drop. The method of exemplary embodiment 1, comprising:

[0062] Exemplary embodiment 5. In response to receiving a power fail signal and a cache line having a storage write request, Committing the cache line to storage The method of exemplary embodiment 1, comprising:

[0063] Exemplary embodiment 6. Processing the cache line via a memory or storage controller regardless of what the tag of the cache line indicates. The method of exemplary embodiment 1, comprising:

[0064] Exemplary embodiment 7. The method of exemplary embodiment 1, performed by coherent link soft logic within the device.

[0065] Exemplary embodiment 8. 1. An integrated circuit system comprising: a central processing unit; A device, a memory controller configured to manage memory coupled to the device; and a decoder configured to decode the cache line to determine a destination for the cache line; a device having a communications link coupling the device to a central processing unit; a volatile memory coupled to the device; Persistent memory attached to the device Equipped with Integrated circuit systems include: Receives the cache line, Identifying whether a cache line is directed to persistent memory or volatile memory; Metadata is used to tag cache lines to distinguish cache lines directed to persistent memory from cache lines directed to volatile memory. An integrated circuit system configured to:

[0066] Exemplary embodiment 9. The memory controller is Receives a power failure signal, In response to receiving a power fail signal and a cache line having a memory write request, selectively committing the cache line to persistent memory if the cache line is destined for persistent memory; Otherwise, if the cache line is directed to volatile memory, selectively refrain from committing the cache line to volatile memory. The integrated circuit system of exemplary embodiment 8 is configured as follows.

[0067] Exemplary embodiment 10. 10. The integrated circuit system of example embodiment 9, comprising a battery backup configured to provide power to the integrated circuit system when a power fail signal is asserted to the integrated circuit system, the battery backup configured to support committing persistent cache lines after the power fail signal.

[0068] Exemplary embodiment 11. The integrated circuit system of exemplary embodiment 15, wherein the battery backup is sized based on a queue length corresponding to the amount of cache lines committed to persistent memory and not based on a queue length corresponding to the amount of cache lines committed to volatile memory.

[0069] Exemplary embodiment 12. The memory controller is Receives a power failure signal, In response to receiving a power fail signal and a cache line having a memory read request, Respond to the cache line in the response The integrated circuit system of exemplary embodiment 8 is configured such that the response has a default response.

[0070] Exemplary embodiment 13. storage coupled to the device; the device has a storage controller configured to manage the storage; Integrated circuit systems include: receiving the second cache line; Identifying whether the second cache line is directed to persistent memory, volatile memory, or storage; Tag cache lines with metadata to distinguish them from cache lines that are directed to volatile or persistent memory The integrated circuit system of exemplary embodiment 8 is configured as follows.

[0071] Exemplary embodiment 14. The integrated circuit system of exemplary embodiment 8, wherein the device comprises a field programmable gate array (FPGA) device or an application specific integrated circuit (ASIC) device.

[0072] Exemplary embodiment 15. The logic on the device is receiving a second cache line from the central processing unit; determining whether the second cache line is directed to persistent memory; In response to determining that the second cache line is directed to persistent memory, tagging the second cache line with the metadata to ensure committing the second cache line to persistent memory; In response to determining that the second cache line is directed to persistent memory, Simply drop the second cache line The integrated circuit system of exemplary embodiment 8 is configured as follows.

[0073] Exemplary embodiment 16. 10. The integrated circuit system of exemplary embodiment 8, wherein the central processing unit is coupled to the second persistent memory and the second volatile memory, and the central processing unit is configured to tag second cache lines directed to the second persistent memory or the second volatile memory to distinguish the second cache lines directed to the second persistent memory from the second cache lines directed to the second volatile memory.

[0074] Exemplary embodiment 17. A non-transitory tangible computer-readable medium comprising instructions that, when executed by a processor of a memory controller, cause the memory controller to: receiving a cache line in a queue configured to store pending operations; determining whether a cache line is directed to persistent memory or non-persistent memory based on whether the cache line is tagged with metadata; Procedures for identifying power failures; In response to identifying a power failure, committing the cache line to memory in response to the cache line being directed to persistent memory; and a step of refraining from committing a cache line to memory in response to the cache line being directed to non-persistent memory; A non-transitory tangible computer-readable medium for causing a process having the steps:

[0075] Exemplary embodiment 18. The process continues until a power failure is present. 18. The non-transitory tangible computer-readable medium of example embodiment 17, having a procedure for committing a cache line to memory regardless of whether the cache line is directed to persistent memory or non-persistent memory.

[0076] Exemplary embodiment 19. 18. The non-transitory tangible computer-readable medium of Example Embodiment 17, wherein the queue has a write pending queue.

[0077] Exemplary embodiment 20. The cache line has a memory read request and the process is If a cache line is directed to non-persistent memory, the default procedure for responding to the cache line is 18. The non-transitory tangible computer-readable medium of exemplary embodiment 17, having:

[0078] While the embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. The present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure, as defined by the following appended claims.

[0079] The technology presented and claimed herein refers to and applies to tangible objects and examples of practical nature that clearly advance the art, and is therefore not abstract, intangible, or purely theoretical. Furthermore, to the extent that any claim appended at the end of this specification includes one or more elements designated as "means" for "performing" a "function" or as steps for "performing" a "function," it is intended that such elements be construed under U.S. § 112(f). However, for any claim including elements designated in any other manner, it is not intended that such elements be construed under U.S. § 112(f).

Claims

1. 1. A method for flushing cache lines for persistent memory, comprising: receiving, via a coherent link at a decoder of a device of the integrated circuit system, a cache line associated with a destination address of the memory write request; determining, in the decoder of the device, a type of memory associated with the destination address of the memory write request, the type of memory comprising persistent memory or non-persistent memory; tagging the cache line with metadata at the decoder of the device based on the determination, the metadata indicating the type of memory associated with the destination address of the memory write request; receiving, at a memory controller of the device and from the decoder of the device, the memory write request to write the cache line of data to the destination address, the memory write request tagged with the metadata; receiving a power fail signal at the memory controller; in response to receiving the power fail signal and the memory write request at the memory controller, selectively committing, at the memory controller, the cache line to the persistent memory if the tagging indicates that the type of memory associated with the destination address is the persistent memory; otherwise, if the tagging step indicates that the type of memory associated with the destination address is the non-persistent memory, selectively refraining at the memory controller from committing the cache line to the non-persistent memory; A method for providing the above.

2. in response to receiving a power fail signal and the cache line having a memory read request; dropping the memory read request and returning a response indicating the dropping. The method of claim 1 , comprising:

3. A method for flushing cache lines associated with persistent memory, comprising: receiving a cache line having a destination address at a device of the integrated circuit system via a coherent link; determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent; tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address; in response to receiving a power fail signal and the cache line having a memory read request; dropping the memory read request and returning a response indicating the drop; A method for providing the above.

4. The method of claim 1 , wherein the method is performed by coherent link soft logic within the device.

5. 1. An integrated circuit system comprising: a central processing unit; A device, a memory controller configured to manage memory coupled to the device; and a decoder configured to decode a cache line to determine a destination for said cache line; a device having a communications link coupling the device to the central processing unit; a volatile memory coupled to the device; a persistent memory coupled to the device; and Equipped with The decoder receiving, via a coherent link, the cache line associated with a destination address of a memory write request; determining a type of memory associated with the destination address of the memory write request, the type of memory comprising the persistent memory or the volatile memory; tagging the cache line with metadata based on the determination, the metadata indicating the type of memory associated with the destination address of the memory write request; It is configured as follows: The memory controller Receives a power failure signal, receiving a memory write request from the decoder to write the cache line of data to the destination address, the memory write request tagged with the metadata; in response to receiving the power fail signal and the memory write request; selectively committing the cache line to the persistent memory if the tagging indicates that the type of memory associated with the destination address is the persistent memory; Otherwise, if the tagging indicates that the type of memory associated with the destination address is the volatile memory, selectively refrain from selectively committing the cache line to the volatile memory. An integrated circuit system configured to:

6. 6. The integrated circuit system of claim 5, further comprising a battery backup configured to provide power to the integrated circuit system when the power fail signal is asserted to the integrated circuit system, the battery backup configured to support committing persistent cache lines after the power fail signal.

7. 7. The integrated circuit system of claim 6, wherein the battery backup is sized based on a queue length corresponding to an amount of cache lines committed to the persistent memory and not based on a queue length corresponding to an amount of cache lines committed to the volatile memory.

8. The memory controller Receives a power failure signal, in response to receiving the power fail signal and the cache line having a memory read request; Response to the cache line 8. An integrated circuit system according to claim 5, configured to:

9. An integrated circuit system comprising: a central processing unit; A device, a memory controller configured to manage memory coupled to the device; and a decoder configured to decode a cache line to determine a destination for said cache line; a device having a communications link coupling the device to the central processing unit; a volatile memory coupled to the device; a persistent memory coupled to the device; and Equipped with The integrated circuit system comprises: Receives the cache line, Identifying whether the cache line is directed to the persistent memory or the volatile memory; Using metadata to tag the cache lines to distinguish cache lines directed to the persistent memory from cache lines directed to the volatile memory. It is configured as follows: The memory controller Receives a power failure signal, in response to receiving the power fail signal and the cache line having a memory read request; Response to the cache line wherein the response comprises a default response.

10. a storage coupled to the device; the device has a storage controller configured to manage the storage; The integrated circuit system comprises: receiving a second cache line; Identifying whether the second cache line is directed to the persistent memory, the volatile memory, or the storage; tagging the cache lines with metadata to distinguish them from cache lines directed to the volatile memory or the persistent memory; 10. The integrated circuit system according to claim 5, configured to:

11. 11. The integrated circuit system of claim 5, wherein the device comprises a field programmable gate array (FPGA) device or an application specific integrated circuit (ASIC) device.

12. The logic on the device comprises: receiving a second cache line from the central processing unit; determining whether a second cache line is directed to the persistent memory; in response to determining that the second cache line is directed to the persistent memory, tagging the second cache line with metadata to ensure commitment of the second cache line to the persistent memory; In response to determining that the second cache line is not directed to persistent memory, Drop the second cache line 12. The integrated circuit system according to claim 5, configured to:

13. 13. The integrated circuit system of claim 5, wherein the central processing unit is coupled to a second persistent memory and a second volatile memory, and wherein the central processing unit is configured to tag second cache lines directed to the second persistent memory or the second volatile memory to distinguish second cache lines directed to the second persistent memory from second cache lines directed to the second volatile memory.

14. The memory controller receiving a cache line associated with a destination address of the memory write request in a queue configured to store pending operations; determining whether the cache line is directed to persistent memory or non-persistent memory associated with the destination address of the memory write request based on a tag added in a decoder of a device in an integrated circuit system in metadata of the memory write request; receiving a power failure signal; in response to receiving the power fail signal and the memory write request; selectively committing the cache line to memory if the tag indicates that the type of memory associated with the destination address is the persistent memory; and otherwise, selectively refraining from committing the cache line to memory if the tag indicates that the type of memory associated with the destination address is the non-persistent memory. A computer program for executing

15. The computer program product of claim 14 , wherein the queue comprises a write pending queue.

16. The cache line includes a memory read request, and the memory controller responding to the cache line with a default response; dropping the cache line; 16. A computer program product according to claim 14 or 15, which causes the computer to execute the following:

17. A memory controller, receiving a cache line in a queue configured to store pending operations; determining whether the cache line is directed to persistent memory or non-persistent memory based on whether the cache line is tagged with metadata; Procedures for identifying power failures; in response to identifying the power supply failure; committing the cache line to memory in response to the cache line being directed to persistent memory; and refraining from committing the cache line to memory in response to the cache line being directed to non-persistent memory; Execute The cache line includes a memory read request, and the memory controller responding to the cache line with a default response; dropping the cache line; A computer program for executing

18. A computer-readable recording medium storing a computer program according to any one of claims 14 to 17.

19. means for receiving, at a decoder device of the integrated circuit system via a coherent link, a cache line associated with a destination address of the memory write request; means in the decoder of the device for determining a type of memory associated with the destination address of the memory write request, the type of memory comprising persistent memory or non-persistent memory; means, in the decoder of the device, for tagging the cache line with metadata based on the determination, the metadata indicating the type of memory associated with the destination address of the memory write request; means for receiving, at a memory controller of the device and from the decoder of the device, the memory write request for writing data of the cache line to the destination address, the memory write request being tagged with the metadata; means for receiving a power fail signal in the memory controller; In response to receiving the power fail signal and the memory write request, at the memory controller: means, in the memory controller, for selectively committing the cache line to the persistent memory if the tagging means indicates that the type of memory associated with the destination address is the persistent memory; otherwise, means in the memory controller for selectively refraining from committing the cache line to the non-persistent memory if the tagging step indicates that the type of memory associated with the destination address is the non-persistent memory; A system comprising:

20. a processing circuit; a communication link; a memory coupled to the processing circuit via the communication link, the memory comprising a volatile memory device and a persistent memory device; a memory controller configured to manage memory used by the processing circuitry; and Equipped with the memory controller having a decoder configured to decode a cache line to determine a destination for the cache line; The decoder receiving, via the coherent link, a cache line associated with the destination address of the memory write request; determining a type of memory associated with the destination address of the memory write request, the type of memory comprising the persistent memory device or the volatile memory device; tagging the cache line with metadata based on the determination, the metadata indicating the type of memory associated with the destination address of the memory write request; It is configured as follows: The memory controller Receives a power failure signal, receiving the memory write request from the decoder to write the cache line of data to the destination address, the memory write request tagged with the metadata; in response to receiving the power fail signal and the memory write request; selectively committing the cache line to the persistent memory device if the tagging indicates that the type of memory associated with the destination address is the persistent memory device; Otherwise, if the tagging indicates that the type of memory associated with the destination address is the volatile memory device, selectively refrain from selectively committing the cache line to the volatile memory device. The system is configured as follows:

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