Integrated contact silicide with tunable work function

Abstract

A method for reducing the interface resistance of a semiconductor device utilizes a dual work function metal silicide. In some embodiments, the method may include selectively depositing a metal silicide layer on an Epi surface and adjusting the metal to silicon ratio of the metal silicide layer during deposition to vary the work function of the metal silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function of the P-type Epi surface may be adjusted to a value of about 5.0 eV, and the work function of the N-type Epi surface may be adjusted to a value of about 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to the deposition of a contact etch stop layer and an activation anneal.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION

[0001] Embodiments of the present principles relate generally to semiconductor manufacturing. [Background technology]

[0002] The speed of semiconductor devices, such as metal-on-semiconductor transistors, depends on the resistance of the source / drain contacts. The lower the resistance, the faster the transistor. Traditionally, to reduce contact resistance, titanium silicide-based materials have been applied to the source / drain epitaxial surfaces of the metal contact interface. The material composition is different for N-type transistors as opposed to P-type transistors. However, the inventors have observed that titanium silicide-based materials are not optimal for any one type of transistor and are limited in that they cannot be tailored based on the transistor type. Furthermore, the inventors have observed that the high resistance associated with titanium silicide-based materials, while tolerable in large-scale devices, is detrimental in small-scale devices.

[0003]

[0003] Accordingly, the present inventors have provided a method for fabricating an enhanced interface between the Epi surface and the metal contact, thereby improving conductivity and resulting in superior performance, lower operating voltage, and higher speed. Summary of the Invention

[0004]

[0004] A method and apparatus for forming a highly conductive interface between an Epi surface and a metal contact is provided herein.

[0005]

[0005] In some embodiments, a method for reducing the interface resistance between an Epi surface and a metal material may include selectively depositing a metal silicide layer on the Epi surface and adjusting the metal-to-silicon ratio of the metal silicide layer during deposition to vary the work function of the metal silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than about 0.5 eV at the P-type Epi surface or the N-type Epi surface.

[0006] In some embodiments, the method further comprises: the metal silicide layer being a molybdenum silicide-based material or a ruthenium silicide-based material; the work function of the P-type Epi surface being adjusted to a value of about 5.0 eV; the work function of the N-type Epi surface being adjusted to a value of about 3.8 eV; depositing the metal silicide layer using atomic layer deposition; further adjusting the metal to silicon ratio by depositing metal or silicon on the metal silicide layer using atomic layer deposition, ion implantation, or plasma vapor deposition; the P-type Epi surface being a silicon germanium material with or without a silicon cap layer; and the N-type Epi surface being a molybdenum cap layer. The method may include depositing a silicon phosphide material with or without a contact etch stop layer, selectively depositing a metal silicide layer on the Epi surface before depositing the contact etch stop layer, adjusting the metal to silicon ratio of the metal silicide layer during deposition before depositing the contact etch stop layer, performing an activation anneal after adjusting the metal to silicon ratio, performing an activation anneal before selectively depositing the metal silicide layer, and / or depositing a conformal nitride based etch stop layer on the substrate, depositing a dielectric layer on the substrate, opening contacts in the substrate, and depositing a bulk fill material on the contacts.

[0007]

[0007] In some embodiments, a method for reducing the interface resistance between an Epi surface and a metal material may include selectively depositing a molybdenum silicide layer on the Epi surface using atomic layer deposition, and adjusting the metal-to-silicon ratio of the molybdenum silicide layer during deposition to vary the work function of the molybdenum silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than about 0.5 eV at the P-type Epi surface or the N-type Epi surface.

[0008]

[0008] In some embodiments, the method may further include tuning the work function of the P-type Epi surface to a value of about 5.0 eV and tuning the work function of the N-type Epi surface to a value of about 3.8 eV; further tuning the metal-to-silicon ratio by depositing molybdenum or silicon onto the molybdenum silicide layer using atomic layer deposition, ion implantation, or plasma-enhanced vapor deposition; the P-type Epi surface being a silicon germanium material with or without a silicon cap layer and the N-type Epi surface being a silicon phosphide material with or without a molybdenum cap layer; selectively depositing a molybdenum silicide layer on the Epi surface before depositing the contact etch stop layer; tuning the metal-to-silicon ratio of the molybdenum silicide layer before depositing the contact etch stop layer; and / or performing an activation anneal after tuning the metal-to-silicon ratio or before selectively depositing the molybdenum silicide layer.

[0009]

[0009] In some embodiments, a non-transitory computer-readable medium is provided having stored thereon instructions that, when executed, cause a method to be performed for reducing interfacial resistance between an Epi surface and a metal material on a substrate, the method may include selectively depositing a metal silicide layer on the Epi surface, and adjusting the metal-to-silicon ratio of the metal silicide layer during deposition to vary the work function of the metal silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than about 0.5 eV at the P-type Epi surface or the N-type Epi surface.

[0010]

[0010] In some embodiments, the method may further include depositing a metal silicide layer using atomic layer deposition, adjusting the metal to silicon ratio by depositing metal or silicon on the metal silicide layer using atomic layer deposition, ion implantation, or plasma-enhanced vapor deposition, the work function of the P-type Epi surface being adjusted to a value of approximately 5.0 eV and the work function of the N-type Epi surface being adjusted to a value of approximately 3.8 eV, and / or selectively depositing a metal silicide layer on the Epi surface before depositing the contact etch stop layer, and performing an activation anneal after adjusting the metal to silicon ratio.

[0011]

[0011] Other further embodiments are disclosed below.

[0012]

[0012] The embodiments of the present principles summarized above and described in more detail below can be understood by reference to the exemplary embodiments of the present principles shown in the accompanying drawings, which illustrate, however, only exemplary embodiments of the present principles and should not be considered limiting in scope, as the present principles may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0013] [Figure 1] A method for reducing interfacial resistance on an Epi surface, according to some embodiments of the present principles. [Figure 2] FIG. 10 is a cross-sectional view of an Epi plane according to some embodiments of the present principles. [Figure 3] FIG. 1C shows a cross-sectional view of an Epi surface with a metal suicide layer, in accordance with some embodiments of the present principles. [Figure 4] FIG. 1C shows a cross-sectional view of an Epi surface with metal silicide diffused into a silicon cap layer, according to some embodiments of the present principles. [Figure 5] 1A-1C are cross-sectional views of Epi surfaces with work function tuned metal suicide layers, in accordance with some embodiments of the present principles. [Figure 6] 1 is a graph of the work function of a tunable metal silicide layer, in accordance with some embodiments of the present principles; [Figure 7] A method for reducing the interface resistance between the Epi surface and metal contacts using the tunable work function of the metal silicide layer and the increased contact area of ​​the metal silicide layer according to some embodiments of the present principles. [Figure 8A-C] A is a cross-sectional view of a source / drain Epi surface formed on a substrate in accordance with some embodiments of the present principles; B is a cross-sectional view of a source / drain Epi surface with a wrap-around metal silicide layer in accordance with some embodiments of the present principles; and C is a cross-sectional view of a source / drain Epi surface with an etch stop layer in accordance with some embodiments of the present principles. [Figure 8D-F] D is a cross-sectional view of a source / drain Epi surface with a dielectric layer according to some embodiments of the present principles; E is a cross-sectional view of a source / drain Epi surface after etching of the dielectric layer according to some embodiments of the present principles; and F is a cross-sectional view of a source / drain Epi surface after deposition of a bulk fill layer according to some embodiments of the present principles. [Figure 9] 1A-1C are cross-sectional views illustrating different metal suicide interface regions, in accordance with some embodiments of the present principles. [Figure 10] 1 is a top view of an integrated tool, according to some embodiments of the present principles; DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0028] To facilitate understanding, the same reference numerals have been used, wherever possible, to designate identical elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0015]

[0029] The method of the present principles enables the formation of highly conductive contacts that facilitate higher speeds and lower operating voltages for semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors. The method creates optimal work functions for specific silicides for N-type or P-type MOS contacts by adding metal or silicon sources before, during, or after the MOS deposition process to vary the metal-to-silicon composition in the metal silicide. N-type and P-type contacts require different work function metals to achieve low Schottky barrier heights (SBH). A single metal silicide with a fixed work function cannot achieve low SBH for both N-type and P-type contacts. A tunable work function metal silicide, such as that found in the present method, allows for the work function to be adjusted to obtain the lowest contact resistance for N-type and P-type contacts separately.

[0016]

[0030] The present method has the advantage of using a single metal without separate metal processes to achieve dual silicides, and the silicon content can be easily adjusted by adding additional cycles of silicon (Si) precursors, epitaxial (Epi) Si layers, Si implants, or plasma vapor deposition (PVD) Si layers. The present method also has the advantage of using the same metal silicide with different metal-to-silicon ratios for the N-type and P-type contacts in an alternative process, while allowing the metal content to be adjusted by adding additional atomic layer deposition (ALD) cycles of metal precursors, PVD metal layers, metal implants, or CVD metal deposition. The metals used in the present method also have the advantages of low deposition temperatures (e.g., below about 150°C), high thermal stability, and selective deposition. The low deposition temperatures also have the advantage of maintaining the thermal balance of structures already formed on the substrate before performing the present method.

[0017]

[0031] Conventional approaches rely on a single work function silicide for both the N-type and P-type contacts, or achieve different silicides for the N-type and P-type contacts by depositing different metals on either the N-type or P-type Epi surface. Our method allows for lower N-type or P-type contact resistance using a single metal by varying the silicon content in the metal silicide to achieve different work functions. Briefly, a pre-cleaning process is used to remove oxide from the silicon, silicon phosphide (SiP), or silicon germanium (SiGe) source / drain Epi surface within the contact trenches, followed by metal deposition from a metal precursor on the Epi surface within the contact trenches. Next, silicon is deposited from a silicon precursor on the same surface to form the metal silicide. This deposition process is repeated until the desired silicide thickness is achieved. The metal-to-silicon ratio can be adjusted by changing the deposition duty cycle until the desired work function of the silicide is achieved. The metal-to-silicon ratio can be adjusted by adding additional metal or silicon cycles, implants, or PVD metal or silicon at the beginning or end of silicide formation. An optional annealing process can be used to further reduce the resistivity of the silicide.

[0018]

[0032] The high thermal stability of the metal silicides used in this method allows for the deposition of thermally stable, conformal, and selective silicide materials prior to the formation of the contact etch stop layer (CESL). The silicide material can withstand high-temperature rapid melt growth (RMG) anneals and other thermal processes. The silicides form surrounding the source / drain epitaxial layers, providing a substantially larger surface area than the silicides in the contact trenches on the top facets of the source / drain epitaxial layers. Furthermore, silicides with appropriate capping reduce dopant outdiffusion, maintaining a high dopant concentration at the interface and lowering contact resistance. The high thermal stability and excellent selectivity of the silicides used in this method allow for the deposition of the silicide prior to the nitride etch stop layer and metal gate anneal. Existing titanium-based silicides cannot withstand RMG anneals and cannot be used in the initial silicide deposition process.

[0019]

[0033] In conventional approaches, silicide is deposited after the contact is opened, limiting the contact area to the region of the contact opening. In the method of the present invention, the silicide covers the entire Epi surface of the source / drain contact, providing a conductive path for the contact down to the Epi facet, substantially increasing the contact area and reducing contact resistivity. Briefly, the method involves selectively depositing a metal silicide on the source / drain Epi surface, using, for example, but not limited to, ALD deposition. After selective metal silicide deposition, an activation anneal is performed. The Epi and metal silicide depositions can be performed on the same platform or in an integrated tool without breaking vacuum. The metal silicide remains stable up to 1100°C or higher. Alternatively, an activation anneal can be performed on the source / drain Epi surface prior to selective metal silicide deposition.

[0020]

[0034] For brevity, the epitaxially grown structure or "Epi surface" or surface abbreviated as "Epi" described herein may include the surface of a source / drain Epi structure, such as a MOS transistor and / or other semiconductor structure. However, the method of the present principles may also be used to reduce the interface resistance between an Epi surface and a metal layer of other structures, etc. FIG. 1 illustrates a method 100 for reducing the interface resistance of an Epi surface on a substrate, according to some embodiments. For illustrative purposes, reference is made to FIGS. 2-5 during the description of method 100. In diagram 200A of FIG. 2, a P-type Epi surface 206A includes an epitaxially grown source / drain material, such as a SiGe layer 202A about 30 nm to about 40 nm thick, and may also include a silicon cap layer 204A about 1 nm to about 10 nm thick. In FIG. 2, diagram 200B, the N-type Epi surface 206B may include an epitaxially grown source / drain material, such as a SiP layer 202B about 30 nm to about 40 nm thick, and a molybdenum (Mo) cap layer 204B about 1 nm to about 10 nm thick. In block 102 of method 100, a metal silicide layer is deposited on the Epi surface. The deposition process is at a low temperature of less than about 150° C. In some embodiments, the deposition process has a deposition temperature of about 120° C. The metal silicide layer may be molybdenum silicide or ruthenium silicide, for example. The deposition process may be an ALD process, and the metal silicide layer may be deposited to a thickness of about 5 nm to about 10 nm. In some embodiments, the metal silicide layer is about 6 nm to about 8 nm thick. The deposition process includes depositing a metal from a metal precursor on the Epi surface and depositing silicon from a silicon precursor on the Epi surface to form the metal silicide layer. The deposition process can be repeated until the desired metal silicide thickness is achieved.

[0021]

[0035] In block 104, the metal-to-silicon ratio of the metal silicide layer is adjusted during deposition to vary the work function based on whether the Epi surface is P-type or N-type. The amount of silicon and the amount of metal deposition can be varied to achieve a desired work function based on the metal-to-silicon ratio. In some embodiments, the metal-to-silicon ratio can be adjusted by an ALD process using different amounts of molybdenum hexafluoride (MoF) and disilane (HSi) or trisilane (HSi(SiH)) precursors in the deposition process. The metal-to-silicon ratio can also be adjusted by changing the duty cycle of silicon and metal deposition until the desired work function of the metal silicide layer is achieved. To adjust the metal-to-silicon ratio, additional metal or silicon cycles, implants, or PVD metal or silicon can be added at the beginning or end of silicide formation (see optional block 106 below). An optional annealing step can be used to further reduce the resistivity of the metal silicide.

[0022]

[0036] In FIG. 3, diagram 300A, a metal silicide layer is formed, for example, from P-type Mo deposited on P-type Epi surface 206A. x Si y In FIG. 3, view 300B, the metal silicide layer may be, for example, N-type Mo deposited on N-type Epi surface 206B. x Si y It may be layer 308B. P-type Mo x Si y Layer 308A and N-type Mo x Si y Layer 308B advantageously utilizes the same metal and silicon composition but a different metal to silicon ratio to vary the work function of the deposited metal silicide depending on whether the Epi surface is P-type or N-type (x>y for N-type, y>x for P-type). In diagram 400A of FIG. 4, P-type Mo x Si y Layer 308A diffuses into silicon cap layer 204A, resulting in Mo a Si bIn FIG. 400B, an N-type Mo silicide layer is formed. x Si y Layer 308B diffuses into the molybdenum cap layer 204B during deposition, forming Mo a Si b The ratio of "a" to "b" is different between the N-type epitaxial layer 206B and the P-type epitaxial layer 206A, with a>b for N-type and b>a for P-type.

[0023]

[0037] A higher metal concentration than silicon concentration is used for the N-type Epi surface, and a higher silicon concentration than metal concentration is used for the P-type Epi surface. The work function can be tuned to provide a Schottky barrier height of less than 0.5 eV for a P-type Epi surface (work function greater than about 4.6 eV) or an N-type Epi surface (work function less than about 4.2 eV). In some embodiments, the work function can be tuned to provide a Schottky barrier height of about 0.3 eV or less for a P-type Epi surface (work function about 5.0 eV) or an N-type Epi surface (work function about 3.8 eV). A lower Schottky barrier height means more current can flow and lower contact resistance. Mo x Si y After deposition of the layer, the metal to contact ratio may reach the desired ratio and the work function (metal to silicon ratio) Mo a Si b The adjustment can be completed. x Si y If the desired metal-to-contact ratio is not achieved through layer deposition, the process may continue to optional block 106 .

[0024]

[0038] In optional block 106, the metal to silicon ratio of the deposited metal silicide layer can be further adjusted by depositing metal or silicon on the metal silicide layer deposited on the Epi surface, as shown in FIG. 5. The metal or silicon can be deposited using ALD, ion implantation, or PVD-based processes, etc. In FIG. 500A, silicon or metal can be deposited on a metal silicide (e.g., P-type Mo) to further adjust the work function as needed.x Si y In FIG. 500B, silicon or metal is deposited on a metal silicide (N-type Mo) as needed to achieve a lower Schottky barrier height and subsequently a lower interfacial resistance. x Si y In some embodiments, a metal silicide is deposited (510B) on the Epi surface to further tune the work function. In some embodiments, the further tuning process can be performed before the selective deposition of a metal silicide on the Epi surface (block 102).

[0025]

[0039] 6 illustrates the Schottky barrier value on the Y-axis versus the metal work function value on the X-axis, with various work function points possible by varying the metal to silicon ratio of the metal silicide (e.g., molybdenum silicide, ruthenium silicide, etc.). c is the Schottky barrier φ based on the following equation 1: B is related to. TIFF0007747871000001.tif15170 Reducing the Schottky barrier height reduces the contact resistance (interface resistance between the Epi surface and the metal material). In some embodiments, the reduction in interfacial resistance can be 30% or more compared to prior art techniques such as titanium silicide.

[0026]

[0040] The first work function line 602 shows possible work function values ​​for the metal silicide compositions of the present invention deposited on a P-type Epi surface. The second work function line 604 shows possible work function values ​​for the metal silicide compositions of the present invention deposited on an N-type Epi surface. The points within the dashed box 606 indicate work function values ​​for conventionally used fixed work function metal silicides, such as titanium silicide, on either P-type or N-type Epi surfaces (the work function is the same for both contact types). Because titanium silicide cannot be tuned, optimal Schottky barrier heights are not achieved, resulting in high interfacial resistance. Because the metal silicides of the present invention have tunable work functions, the same metal silicide can be used on both P-type and N-type Epi surfaces and adjusted accordingly. For N-type Epi surfaces, the first indicator point 608 shows possible work function values ​​of approximately 3.8 eV with Schottky barrier heights of approximately 0.3 eV or less. For a P-type Epi surface, the second indicator 610 shows a possible work function value of about 5.0 eV with a Schottky barrier height of about 0.3 eV or less.

[0027]

[0041] The inventors have found that the metal silicides of the present method are thermally stable up to temperatures of approximately 1100°C (for spike anneals) or higher. This thermal stability allows the metal silicide to be deposited in several locations within a MOS process without worrying about when to perform high-temperature annealing processes such as activation anneals. The thermal properties of metal silicides advantageously allow flexibility in their use to further reduce interface resistance through increased contact surface area with the metal silicide layer. Figure 7 illustrates a method 700 for reducing the interface resistance between an Epi surface and a metal contact through work function tuning and increased contact surface area with the metal silicide layer. References to Figures 8A through 8F are used to explain the process of method 700. In some embodiments, the substrate may have a P-type source / drain Epi surface and an N-type source / drain Epi surface. The upper flow portion of method 700 shows processes specific to the P-type source / drain Epi surface (702A-712A) and processes specific to the N-type source / drain Epi surface (702B-712B). The upper flow portion does not indicate that the P-type and N-type processes are performed simultaneously. The P-type source / drain Epi surface process may be performed before or after the N-type source / drain Epi surface process. After the P-type and N-type specific processes are completed, the remaining processes (714-722) may be performed simultaneously on both the P-type source / drain Epi surface and the N-type source / drain Epi surface. For substrates with only P-type source / drain Epi surfaces, the N-type source / drain Epi surface processes (702B-712B) are not performed. For substrates with only N-type source / drain Epi surfaces, the P-type source / drain Epi surface processes (702A-712A) are not performed.

[0028]

[0042] The following process is applied to a substrate having a P-type structure. In block 702A, one or more P-type source / drain Epi layers are formed. In diagram 800A of FIG. 8A, trench 830 has source / drain Epi layers 806 formed from, for example, but not limited to, SiGe for the P-type Epi layer. Source / drain Epi layers 806 are grown from layer 802 on the substrate and isolated within shallow trench isolation (STI) 804. In this example, source / drain Epi layers 806 have an upper facet 808 and a lower facet 810 (which is an undercut surface). In optional block 704A, an activation anneal can be performed before or after metal silicide layer formation, as indicated by optional block 714. In some embodiments, the activation anneal can include a spike anneal, which can be performed at a temperature of about 1100° C. In block 706A, a pre-clean process is performed to remove any contamination and oxides from the silicon or SiGe source / drain Epi surface in the trench 830. In block 708A (see also block 102 of method 100 in FIG. 1 ), a metal silicide layer 812 is selectively deposited on the top facet 808 and bottom facet 810 of the source / drain Epi surface 806, as shown in diagram 800B of FIG. 8B. The selective deposition involves selectively depositing metal from a metal precursor on the source / drain Epi surface in the trench 830 and selectively depositing silicon from a silicon precursor on the same surface to form the metal silicide layer 812 that covers or encases the source / drain Epi surface 806. The selective deposition process is repeated until the desired metal silicide thickness is achieved.

[0029]

[0043] In block 710A (see also block 104 of method 100 in FIG. 1 ), the metal-to-silicon ratio of the metal silicide layer is adjusted during deposition to vary the work function based on the source / drain Epi surface 806 being a P-type Epi surface. The amount of silicon and the amount of metal can be varied to achieve a desired work function based on the metal-to-silicon ratio. The metal-to-silicon ratio can also be adjusted by changing the duty cycle of silicon and metal deposition until the desired work function of the metal silicide layer is reached. Additional metal or silicon cycles, implants, or PVD metal or silicon can be added at the beginning or end of silicide formation to adjust the metal-to-silicon ratio (see optional block 712A). An optional annealing process can be used to further reduce the resistivity of the metal silicide. In optional block 712A, the metal-to-silicon ratio of the deposited metal silicide layer can be further adjusted by depositing metal or silicon on the metal silicide layer deposited on the source / drain Epi surface 806. The metal or silicon can be deposited using ALD, ion implantation, or PVD-based processes, etc. In some embodiments, a further conditioning process can be performed before the selective deposition of metal silicide on the source / drain Epi surface (block 708A).

[0030]

[0044] The following process is applied to a substrate having an N-type structure. In block 702B, one or more N-type source / drain Epi layers are formed. In diagram 800A of FIG. 8A, trench 830 has source / drain Epi layers 806 formed from, for example, but not limited to, SiP for an N-type Epi layer. Source / drain Epi layers 806 are grown from layer 802 on the substrate and isolated within shallow trench isolation (STI) 804. In this example, source / drain Epi layers 806 have an upper facet 808 and a lower facet 810 (which is an undercut surface). In optional block 704B, an activation anneal can be performed before or after metal silicide layer formation, as indicated by optional block 714. In some embodiments, the activation anneal can include a spike anneal, which can be performed at a temperature of about 1100° C. In block 706B, a pre-clean process is performed to remove any contamination and oxides from the silicon or SiP source / drain Epi surface in the trench 830. In block 708B (see also block 102 of method 100 in FIG. 1 ), a metal silicide layer 812 is selectively deposited on the top facet 808 and bottom facet 810 of the source / drain Epi surface 806, as shown in diagram 800B of FIG. 8B. The selective deposition involves selectively depositing metal from a metal precursor on the source / drain Epi surface in the trench 830 and selectively depositing silicon from a silicon precursor on the same surface to form the metal silicide layer 812 covering or enveloping the source / drain Epi surface 806. The selective deposition process is repeated until the desired metal silicide thickness is achieved.

[0031]

[0045] In block 710B (see also block 104 of method 100 in FIG. 1 ), the metal-to-silicon ratio of the metal silicide layer is adjusted during deposition to vary the work function based on the source / drain Epi surface 806 being an N-type Epi surface. The amount of silicon deposition and the amount of metal deposition can be varied to achieve a desired work function based on the metal-to-silicon ratio. The metal-to-silicon ratio can also be adjusted by changing the duty cycle of silicon and metal deposition until the desired work function of the metal silicide layer is achieved. Additional metal or silicon cycles, implants, or PVD metal or silicon can be added at the beginning or end of silicide formation to adjust the metal-to-silicon ratio (see optional block 712B). An optional annealing process can be used to further reduce the resistivity of the metal silicide. In optional block 712B, the metal-to-silicon ratio of the deposited metal silicide layer can be further adjusted by depositing metal or silicon on the metal silicide layer deposited on the source / drain Epi surface 806. The metal or silicon can be deposited using ALD, ion implantation, or PVD-based processes, etc. In some embodiments, a further conditioning process can be performed before the selective deposition of metal silicide on the source / drain Epi surface (block 708B).

[0032]

[0046] The following process applies to substrates having N-type structures, P-type structures, or both. In optional block 714, an activation anneal can be performed after deposition of the metal silicide layer 812, as described above, or before deposition of the metal silicide layer 812 (see optional block 704). If the activation anneal is performed after metal silicide formation and conditioning, the source / drain Epi surface and metal silicide deposition and work function tuning can be performed on the same platform or integrated tool, and can be performed without breaking vacuum (see, for example, integrated tool 1000 in FIG. 10 below), resulting in lower cost and higher yield. The metal silicide's envelopment of the source / drain Epi surface provides a substantially larger surface area than silicide in contact trenches above the source / drain Epi surface, as found in conventional methods. Furthermore, with proper capping, the metal silicide can reduce dopant diffusion and maintain a high dopant concentration at the interface, resulting in lower contact resistance. The silicide of this method has high thermal stability and good selectivity, allowing the metal silicide to be deposited before the nitride etch stop layer and metal gate anneal. In block 716, an etch stop layer 814 for the source / drain Epi surface 806 is deposited on the substrate, as shown in diagram 800C of FIG. 8C. The etch stop layer 814 may be a nitride layer, such as a silicon nitride layer, conformally deposited on the source / drain Epi surface of the trench 830. In block 718, a dielectric layer 816 is deposited on the substrate to fill the trench 830, as shown in diagram 800D of FIG. 8D. In some embodiments, the dielectric layer 816 may be a silicon dioxide layer or the like. In block 720, the top facet 808 of the source / drain Epi surface 806 is opened, as shown in diagram 800E of FIG. 8E. This opening is achieved by etching away a portion of the dielectric layer 816 and etch stop layer 814 to expose the metal suicide layer 812 on the top facet 808 of the source / drain Epi surface 806. In block 722, a bulk fill material is deposited in the trench 830 on the substrate, as shown in diagram 800F of Figure 8F. In some embodiments, the bulk fill material may be a cobalt-based material, or the like.

[0033]

[0047] A comparison of source / drain Epi structures is shown in diagram 900 of FIG. 9. A conventionally constructed source / drain Epi structure 902 has only a top surface portion in contact with a silicide layer 906, which in turn contacts the bulk fill 818. A source / drain Epi structure 904 constructed using the method of the present invention results in a source / drain Epi structure 904 in which the metal silicide layer encases the source / drain Epi surface. The amount of additional surface area in contact with the silicide in the structure of our method is approximately 70% or more greater than that found in the conventional structure. The inventors have discovered that even though the contact area of ​​the bulk fill 818 in contact with the silicide is the same in both the conventional source / drain Epi structure 902 and the source / drain Epi structure 904 of our method, the source / drain Epi structure 904 of our method provides significantly greater current flow (and consequently significantly lower interfacial resistance) by approximately 40% or more.

[0034]

[0048] The methods described herein can be performed in individual process chambers, which can be provided in a stand-alone configuration or as part of a cluster tool, such as the integrated tool 1000 described below with respect to FIG. 10 (i.e., a cluster tool). An advantage of using the integrated tool 1000 is that there are no vacuum breaks, and therefore no need to degas and pre-clean substrates before processing. In some embodiments, the methods described above can be advantageously performed in an integrated tool to limit or eliminate vacuum breaks between processes, which can improve process throughput as well as limit or prevent substrate contamination. The integrated tool 1000 includes a vacuum-tight processing platform 1001, a factory interface 1004, and a system controller 1002. The processing platform 1001 includes multiple processing chambers, such as 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F, operably coupled to vacuum substrate transfer chambers (transfer chambers 1003A and 1003B). The factory interface 1004 is operably coupled to the transfer chamber 1003A by one or more load lock chambers (two load lock chambers, such as 1006A and 1006B shown in FIG. 10).

[0035]

[0049] In some embodiments, the factory interface 1004 includes at least one docking station 1007 and at least one factory interface robot 1038 to facilitate transfer of semiconductor substrates. The docking station 1007 is configured to receive one or more front-opening unified pods (FOUPs). In the embodiment of FIG. 10, four FOUPs are shown, such as 1005A, 1005B, 1005C, and 1005D. The factory interface robot 1038 is configured to transfer substrates from the factory interface 1004 to the processing platform 1001 through load lock chambers, such as 1006A and 1006B. Each of the load lock chambers 1006A and 1006B has a first port coupled to the factory interface 1004 and a second port coupled to the transfer chamber 1003A. The load lock chambers 1006A and 1006B are coupled to a pressure control system (not shown) that pumps the load lock chambers 1006A and 1006B to facilitate passage of substrates between the vacuum environment of the transfer chamber 1003A and the substantially ambient (e.g., atmospheric) environment of the factory interface 1004. The transfer chambers 1003A, 1003B have vacuum robots 1042A, 1042B disposed therein. The vacuum robot 1042A can transfer substrates 1021 between the load lock chambers 1006A, 1006B, the processing chambers 1014A and 1014F, and the cool down station 1040 or the pre-clean station 1042. The vacuum robot 1042B can transfer the substrate 1021 between the cool down station 1040 or the pre-clean station 1042 and the processing chambers 1014B, 1014C, 1014D, and 1014E.

[0036]

[0050] In some embodiments, processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F are coupled to transfer chambers 1003A and 1003B. Processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F comprise at least an atomic layer deposition (ALD) process chamber, a chemical vapor deposition (CVD) process chamber, an ion implantation chamber, and a physical vapor deposition (PVD) process chamber. Additional chambers, such as an annealing chamber, an additional CVD chamber, an additional ALD chamber, or an additional PVD chamber, may also be provided. The ALD chamber, CVD chamber, ion implantation chamber, and PVD chamber may include any chamber suitable for performing all or part of the methods described herein, as described above. In some embodiments, one or more optional service chambers (shown as 1016A and 1016B) may be coupled to transfer chamber 1003A. Service chambers 1016A and 1016B may be configured to perform other substrate processes such as degassing, orientation, substrate metrology, cool down, etc.

[0037]

[0051] The system controller 1002 controls the operation of the integrated tool 1000 using direct control of the process chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F, or alternatively, by controlling the process chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F and computers (or controllers) associated with the integrated tool 1000. In operation, the system controller 1002 enables data collection and feedback from each chamber and system to optimize the performance of the integrated tool 1000. The system controller 1002 generally includes a central processing unit (CPU) 1030, memory 1034, and support circuits 1032. The CPU 1030 may be any form of general-purpose computer processor usable in an industrial environment. The support circuits 1032 are conventionally coupled to the CPU 1030 and may include cache, clock circuits, input / output subsystems, power supplies, etc. Software routines, such as methods as described above, may be stored in memory 1034 and, when executed by CPU 1030, transform CPU 1030 into a special purpose computer (system controller 1002). Software routines may also be stored and / or executed by a second controller (not shown) located remotely from integrated tool 1000.

[0038]

[0052] Embodiments according to the present principles may be implemented in hardware, firmware, software, or any combination thereof. Also, embodiments may be implemented as instructions stored using one or more computer-readable media and readable and executable by one or more processors. A computer-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform or a "virtual machine" running on one or more computing platforms). For example, a computer-readable medium may include any suitable form of volatile or non-volatile memory. In some embodiments, a computer-readable medium may include a non-transitory computer-readable medium.

[0039]

[0053] While the forgoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope thereof.

Claims

1. 1. A method for reducing interfacial resistance between an Epi surface and a metal material, comprising: Selectively depositing a metal silicide layer on the Epi surface by selectively depositing metal from a metal precursor and silicon from a silicon precursor to form a metal silicide layer on the Epi surface; adjusting the metal-to-silicon ratio of the metal silicide layer during deposition of the metal silicide layer to vary the work function of the metal silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than about 0.5 eV at the P-type Epi surface or the N-type Epi surface; A method comprising:

2. 10. The method of claim 1, wherein the metal suicide layer is a molybdenum suicide-based material or a ruthenium suicide-based material.

3. 10. The method of claim 1, wherein the work function of the P-type Epi surface is adjusted to a value of about 5.0 eV.

4. 10. The method of claim 1, wherein the work function of the N-type Epi surface is adjusted to a value of about 3.8 eV.

5. depositing said metal silicide layer using atomic layer deposition. The method of claim 1 further comprising:

6. further adjusting the metal to silicon ratio by depositing metal or silicon onto the metal silicide layer using atomic layer deposition, ion implantation, or plasma enhanced vapor deposition. The method of claim 1 further comprising:

7. 10. The method of claim 1, wherein the P-type Epi surface is a silicon germanium material with or without a silicon cap layer, and the N-type Epi surface is a silicon phosphide material with or without a molybdenum cap layer.

8. selectively depositing the metal silicide layer on the Epi surface before depositing a contact etch stop layer; adjusting the metal-to-silicon ratio of the metal silicide layer during deposition before depositing the contact etch stop layer; The method of claim 1 further comprising:

9. performing an activation anneal after adjusting the metal to silicon ratio; The method of claim 8 further comprising:

10. performing an activation anneal before selectively depositing the metal silicide layer. The method of claim 8 further comprising:

11. depositing a conformal nitride based etch stop layer on the substrate; depositing a dielectric layer on the substrate; opening contacts in the substrate; depositing a bulk fill material on said contact; The method of claim 8 further comprising:

12. 1. A method for reducing interfacial resistance between an Epi surface and a metal material, comprising: Selectively depositing a molybdenum silicide layer on the Epi surface using atomic layer deposition by selectively depositing molybdenum from a molybdenum precursor and silicon from a silicon precursor to form a molybdenum silicide layer on the Epi surface; adjusting the metal-to-silicon ratio of the molybdenum silicide layer during deposition of the molybdenum silicide layer to vary the work function of the molybdenum silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than about 0.5 eV at the P-type Epi surface or the N-type Epi surface; A method comprising:

13. 13. The method of claim 12, wherein the work function of the P-type Epi surface is tuned to a value of about 5.0 eV and the work function of the N-type Epi surface is tuned to a value of about 3.8 eV.

14. further adjusting the metal to silicon ratio by depositing molybdenum or silicon into the molybdenum silicide layer using atomic layer deposition, ion implantation, or plasma enhanced vapor deposition. The method of claim 12 further comprising:

15. 13. The method of claim 12, wherein the P-type Epi surface is a silicon germanium material with or without a silicon cap layer, and the N-type Epi surface is a silicon phosphide material with or without a molybdenum cap layer.

16. selectively depositing the molybdenum silicide layer on the Epi surface prior to depositing a contact etch stop layer; adjusting the metal to silicon ratio of the molybdenum silicide layer before depositing the contact etch stop layer; The method of claim 12 further comprising:

17. performing an activation anneal after adjusting the metal-to-silicon ratio or before selectively depositing the molybdenum silicide layer; 17. The method of claim 16, further comprising:

18. 1. A non-transitory computer readable medium having stored thereon instructions that, when executed, cause a method for reducing interfacial resistance between an Epi surface and a metal material on a substrate, the method comprising: Selectively depositing a metal silicide layer on the Epi surface by selectively depositing metal from a metal precursor and silicon from a silicon precursor to form a metal silicide layer on the Epi surface; adjusting the metal-to-silicon ratio of the metal silicide layer during deposition of the metal silicide layer to vary the work function of the metal silicide layer based on whether the Epi surface is a P-type Epi surface or an N-type Epi surface to achieve a Schottky barrier height of less than about 0.5 eV at the P-type Epi surface or the N-type Epi surface; 1. A non-transitory computer-readable medium comprising:

19. The method further comprises: depositing the metal silicide layer using atomic layer deposition; adjusting the metal to silicon ratio by depositing metal or silicon into the metal silicide layer using atomic layer deposition, ion implantation, or plasma-enhanced vapor deposition; Including, The work function of the P-type Epi surface is adjusted to a value of about 5.0 eV, and the work function of the N-type Epi surface is adjusted to a value of about 3.8 eV.

20. The non-transitory computer-readable medium of claim 18.

20. The method further comprises: selectively depositing the metal silicide layer on the Epi surface before depositing a contact etch stop layer; performing an activation anneal after adjusting the metal to silicon ratio; 20. The non-transitory computer-readable medium of claim 18, comprising:

21. The method of claim 1, wherein selectively depositing the metal silicide layer is performed at a deposition temperature of about 150° C. or less.

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