Semiconductor device and manufacturing method thereof

Abstract

To ensure the reliability of a semiconductor device and to improve the performance of the semiconductor device.SOLUTION: A semiconductor device including regions 1A and 2A has an n-type semiconductor substrate SUB having a surface TS and back surfaces BS1 and BS2, an IGBT formed on the semiconductor substrate SUB in the region 1A, and a diode formed on the semiconductor substrate SUB in the region 2A. Here, the thickness T1 of the semiconductor substrate SUB in the region 1A is thinner than the thickness T2 of the semiconductor substrate SUB in the region 2A.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including an IGBT and a manufacturing method thereof. [Background technology]

[0002] Trench-gate IGBTs (Insulated Gate Bipolar Transistors) are widely used as IGBTs with low on-resistance. Semiconductor modules equipped with a semiconductor chip on which an IGBT is formed and a semiconductor chip on which a freewheeling diode is formed are used in power conversion devices for controlling motors, etc. The freewheeling diodes are connected in antiparallel to the IGBT, and the cycle repeats: when one is on, the other is off.

[0003] For example, Patent Document 1 discloses a reverse-conducting IGBT (RC-IGBT) configured by connecting a freewheeling diode in antiparallel to an IGBT. The IGBT and the freewheeling diode are formed on the same semiconductor substrate and built into a single semiconductor chip. Use of such an RC-IGBT can reduce the size of the power conversion device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-011000 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors have studied semiconductor devices (semiconductor chips) equipped with RC-IGBTs. They found that while thinning the semiconductor substrate reduces on-resistance, it also increases the likelihood of ringing during turn-off. For example, if the semiconductor substrate is sufficiently thick, holes are reinjected from the p-type collector region formed on the backside of the semiconductor substrate. This allows carriers to remain even after turn-off is complete, alleviating the electric field on the backside and preventing ringing. If the semiconductor substrate is too thin, punch-through occurs at the end of turn-off. Since the thickness of the depletion layer fluctuates, when the thickness of the depletion layer becomes approximately the same as the thickness of the semiconductor substrate, carriers are depleted on the backside, generating a high electric field and resulting in ringing.

[0006] On the other hand, in a diode, an n-type cathode region is formed on the back side of the semiconductor substrate, and since there is no supply of holes from the back side, the depletion layer spreads from both the front side and the back side. If the semiconductor substrate is too thin, the depletion layer from the front side and the depletion layer from the back side will connect, causing punch-through and ringing. If the IGBT and diode are formed on the same semiconductor substrate and the thickness of the semiconductor substrate in each region is the same, the risk of ringing occurring is greater in the diode.

[0007] Therefore, when considering the reliability of RC-IGBTs, it is necessary to set the thickness of the semiconductor substrate to match the characteristics of the diode in order to suppress ringing. That is, the thickness of the semiconductor substrate needs to be thick enough to prevent ringing from occurring in the diode. However, in IGBTs, the semiconductor substrate is thicker than necessary, which increases the on-resistance. In other words, prioritizing the reliability of the semiconductor device will result in a decrease in the performance of the semiconductor device.

[0008] Therefore, it is desirable to develop a technology that can suppress the occurrence of ringing in both the IGBT and the diode, and reduce the on-resistance of the IGBT, i.e., a technology that can ensure the reliability of the semiconductor device and improve the performance of the semiconductor device.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A brief summary of a representative embodiment of the present invention will be given below.

[0011] In one embodiment, the semiconductor device includes a first region and a second region. The semiconductor device also includes a first conductivity type semiconductor substrate having a front surface and a back surface, an IGBT formed in the semiconductor substrate in the first region, and a diode formed in the semiconductor substrate in the second region. Here, the thickness of the semiconductor substrate in the first region is thinner than the thickness of the semiconductor substrate in the second region.

[0012] In one embodiment, a method for manufacturing a semiconductor device including a first region and a second region includes the steps of: (a) preparing a semiconductor substrate of a first conductivity type having a front surface and a back surface; (b) forming an IGBT in the semiconductor substrate in the first region and forming a diode in the semiconductor substrate in the second region; and (c) making the thickness of the semiconductor substrate in the first region thinner than the thickness of the semiconductor substrate in the second region. [Effects of the Invention]

[0013] According to one embodiment, the reliability of the semiconductor device can be ensured and the performance of the semiconductor device can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2]1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 6] FIG. 1 is a schematic diagram showing an etching process using an etching solution containing TMAH. [Figure 7] 1 is a plan view showing a semiconductor substrate in a wafer state in the first embodiment. [Figure 8] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 15] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 16] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device in accordance with a second embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 18] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 20] 13A to 13C are plan views showing a manufacturing process of the opening in the fifth embodiment. [Figure 21] FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0017] Furthermore, in this application, when a numerical range such as "1 to 10 μm" is expressed, it means "1 μm or more and 10 μm or less." The same applies to other numerical values ​​and other units.

[0018] (Embodiment 1) <Structure of semiconductor device> The semiconductor device 100 according to the first embodiment will be described below with reference to FIGS. 1 to 5. FIGS. 1 to 3 are plan views showing a semiconductor chip that is the semiconductor device 100. FIG. 1 mainly shows the wiring layer. FIG. 2 mainly shows the structure in the vicinity of the front surface TS of the semiconductor substrate SUB. FIG. 3 shows the structure of the back surface BS of the semiconductor substrate SUB. FIG. 4 is a perspective view based on a cross section taken along line AA shown in FIGS. 1 to 3. FIG. 5 is an enlarged cross-sectional view of region 1A and region 2A shown in FIG. 4.

[0019] The semiconductor device 100 includes a region 1A where a semiconductor element such as an IGBT is formed, a region 2A where a semiconductor element such as a diode is formed, and a peripheral region 3A that surrounds the region 1A and the region 2A in a plan view. The semiconductor device 100 constitutes an RC-IGBT and can be used in a power conversion device for controlling a motor, etc.

[0020] The semiconductor substrate SUB has a front surface TS and a back surface BS. A main feature of the present application is that the thickness of the semiconductor substrate SUB in region 1A is thinner than the thickness of the semiconductor substrate SUB in region 2A. Depending on each embodiment or each manufacturing process, the front surface TS and back surface BS in region 1A may be referred to as front surface TS1 and back surface BS1, and the front surface TS and back surface BS in region 2A may be referred to as front surface TS2 and back surface BS2.

[0021] As shown in FIG. 1, most of the semiconductor device 100 is covered with an emitter electrode EE. A gate wiring GW is formed around the emitter electrode EE. A portion of each of the emitter electrode EE and the gate wiring GW is covered with a protective film (not shown). The areas exposed from the protective film serve as an emitter pad and a gate pad. External connection terminals such as wire bonding or clips (copper plates) are connected to the emitter pad and the gate pad, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring board.

[0022] As shown in FIGS. 4 and 5, the semiconductor device 100 includes a semiconductor substrate SUB having a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The drift region NV may be a laminated structure of an n-type silicon substrate and a semiconductor layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a laminated structure will also be described as the semiconductor substrate SUB. The impurity concentration of the drift region NV is 1×10 13 ~2×10 14 cm -3 is.

[0023] On the front surface TS side of the semiconductor substrate SUB, a plurality of trenches TR are formed in the semiconductor substrate SUB in the regions 1A and 2A. The bottoms of the trenches TR are located lower than the base region PB, which will be described later. A gate insulating film GI is formed inside the trenches TR. A gate electrode GE1 is formed on the gate insulating film GI so as to fill the insides of the trenches TR in the region 1A. A gate electrode GE2 is formed on the gate insulating film GI so as to fill the insides of the trenches TR in the region 2A. The gate insulating film GI is made of, for example, a silicon oxide film and has a thickness of, for example, 50 to 100 nm. The gate electrodes GE1 and GE2 are made of, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0024] On the front surface TS side of the semiconductor substrate SUB, a p-type base region (semiconductor region) PB is formed in the semiconductor substrate SUB in regions 1A and 2A. An n-type emitter region (semiconductor region) NE is formed in the base region PB in region 1A. A p-type anode region (semiconductor region) PA is formed in the base region PB in region 2A. As shown in FIG. 4, a p-type high-concentration diffusion region (semiconductor region) PR is formed in a part of the base region PB in region 1A. In region 1A, an emitter potential is supplied to the base region PB via the high-concentration diffusion region PR.

[0025] The impurity concentration of the base region PB is 1×10 16 ~1×10 18 cm -3 The impurity concentration of the emitter region NE is higher than that of the drift region NV, and is 1×10 18 ~1×10 21 cm -3 The impurity concentration of the anode region PA is higher than that of the base region PB, and is 1×10 18 ~1×10 21 cm -3 The impurity concentration of the high-concentration diffusion region PR is higher than that of the base region PB, and is 1×10 18 ~1×10 21 cm -3 is.

[0026] 4, on the front surface TS side of the semiconductor substrate SUB, a p-type well region (semiconductor region) PW is formed in the semiconductor substrate SUB in the peripheral region 3A, and a field insulating film FI is formed on the semiconductor substrate SUB in the peripheral region 3A. The well region PW is formed to a position deeper than the bottom of the trench TR. The impurity concentration of the well region PW is lower than the impurity concentration of the base region PB, and is 1×10 15 ~1×10 17 cm -3 The field insulating film FI is made of, for example, a silicon oxide film and has a thickness of, for example, 600 to 1000 nm.

[0027] An interlayer insulating film IL is formed on a surface TS of the semiconductor substrate SUB in regions 1A to 3A. A contact hole is formed in the interlayer insulating film IL. An emitter electrode EE is formed on the interlayer insulating film IL so as to fill the inside of the contact hole. The emitter electrode EE is electrically connected to the emitter region NE, the anode region PA, the base region PB, and the heavily doped diffusion region PR, and supplies an emitter potential to these regions.

[0028] Although not shown here, a gate wiring GW is also formed on the interlayer insulating film IL in the same process as the emitter electrode EE. The emitter electrode EE and gate wiring GW are made of, for example, a titanium nitride film and an aluminum film formed on the titanium nitride film. The aluminum film is the main conductor film of the emitter electrode EE and gate wiring GW, and is sufficiently thicker than the titanium nitride film.

[0029] 2, in the first embodiment, the plurality of gate electrodes GE1, GE2 each extend in the Y direction and are adjacent to each other in the X direction. That is, the plurality of trenches TR each extend in the Y direction and are adjacent to each other in the X direction. In the peripheral region 3A, the plurality of gate electrodes GE1 are connected to gate lead-out portions GE1a, which are electrically connected to the gate wiring GW via contact holes formed in the interlayer insulating film IL. Therefore, a gate potential is supplied to the gate electrode GE1 from the gate wiring GW.

[0030] In the peripheral region 3A, the gate electrodes GE2 are connected to gate lead-out portions GE2a, which are electrically connected to the emitter electrode EE via contact holes formed in the interlayer insulating film IL, so that the emitter potential is supplied to the gate electrodes GE2 from the emitter electrode EE.

[0031] The gate lead portions GE1a and GE2a are configured in a pattern larger than the gate electrodes GE1 and GE2, and are made of a polycrystalline silicon film buried inside the trenches TR via the gate insulating film GI.

[0032] On the back surface BS side of the semiconductor substrate SUB, an n-type buffer region (semiconductor region) NB is formed on the back surface BS of the semiconductor substrate SUB in regions 1A to 3A. The buffer region NB is provided to prevent a depletion layer extending from the pn junction on the front surface TS side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off. The impurity concentration of the buffer region NB is higher than the impurity concentration of the drift region NV, and is 5×10 16 ~5×10 17 cm -3 is.

[0033] On the back surface BS side of the semiconductor substrate SUB, a p-type collector region (semiconductor region) PC is formed on the back surface BS of the semiconductor substrate SUB in region 1A, and an n-type cathode region (semiconductor region) NC is formed on the back surface BS of the semiconductor substrate SUB in region 2A and peripheral region 3A. The collector region PC and the cathode region NC are located below the buffer region NB. The impurity concentration of the collector region PC is 1×10 17 ~1×10 21 cm -3 The impurity concentration of the cathode region NC is higher than that of the drift region NV, and is 1×10 18 ~1×10 21 cm -3 is.

[0034] A collector electrode CE is formed on the back surface BS of the semiconductor substrate SUB in region 1A. The collector electrode CE is electrically connected to the collector region PC and the cathode region NC and supplies a collector potential to these regions. The collector electrode CE is made of a laminated film including, for example, a nickel silicide film and metal films such as a titanium film, a nickel film, and a gold film sequentially formed on the nickel silicide film.

[0035] <Main features of the first embodiment> 3 to 5, in the first embodiment, an opening OP1 is formed in the back surface BS of the semiconductor substrate SUB in the region 1A. Therefore, a step is generated in the back surface BS of the semiconductor substrate SUB such that the back surface BS1 of the semiconductor substrate SUB in the region 1A is located higher than the back surface BS2 of the semiconductor substrate SUB in the region 2A. That is, the thickness T1 of the semiconductor substrate SUB in the region 1A is thinner than the thickness T2 of the semiconductor substrate SUB in the region 2A.

[0036] 5, the thickness T1 of the semiconductor substrate SUB in region 1A is the thickness from the front surface TS of the semiconductor substrate SUB to the back surface BS1 of the semiconductor substrate SUB. The thickness T2 of the semiconductor substrate SUB in region 2A is the thickness from the front surface TS of the semiconductor substrate SUB to the back surface BS2 of the semiconductor substrate SUB. The thicknesses T1 and T2 are set to, for example, 50 to 160 μm, with thickness T1 being thinner than thickness T2 by 1 to 10 μm. More preferably, thickness T2 is 85 μm, and thickness T1 is thinner than thickness T2 by 5 μm.

[0037] Therefore, the distance from the base region PB of region 1A to the collector region PC of region 1A is shorter than the distance from the base region PB of region 2A to the cathode region NC of region 2A. In other words, the thickness of the drift region NV of region 1A is thinner than the thickness of the drift region NV of region 2A.

[0038] As described above, if the thickness of the semiconductor substrate SUB in the region 1A where the IGBT is formed is the same as the thickness of the semiconductor substrate SUB in the region 2A where the diode is formed, there is a problem that the risk of ringing occurring is greater in the diode. Therefore, considering the reliability of the RC-IGBT, it is necessary to increase the thickness of the semiconductor substrate SUB in the region 2A to suppress ringing in the region 2A. However, this also increases the thickness of the semiconductor substrate SUB in the region 1A. This causes a problem of an increase in the on-resistance of the IGBT.

[0039] In the first embodiment, the thickness of the semiconductor substrate SUB is changed, so that ringing can be suppressed in the region 2A and the on-resistance can be reduced in the region 1A. That is, the reliability of the semiconductor device can be ensured and the performance of the semiconductor device can be improved.

[0040] In the first embodiment, the thickness of the semiconductor substrate SUB in the peripheral region 3A is the same as that in the region 2A, that is, thickness T2. That is, thickness T1 of the semiconductor substrate SUB in the region 1A is thinner than thickness T2 of the semiconductor substrate SUB in the peripheral region 3A. Therefore, like in the region 2A, the occurrence of ringing can be suppressed in the peripheral region 3A, making it easier to ensure a high breakdown voltage. Furthermore, since an n-type cathode region NC is also formed on the back surface BS2 of the semiconductor substrate SUB in the peripheral region 3A, the injection of excess holes is reduced, making it easier to ensure a high breakdown voltage and breakdown resistance.

[0041] <Method for forming opening OP1> A method for forming the opening OP1, that is, a technique underlying a method for changing the thickness of the semiconductor substrate SUB, will be described below with reference to Fig. 6. In the first embodiment, the opening OP1 is formed by performing an etching process using an etching solution containing tetramethylammonium hydroxide (TMAH).

[0042] Figure 6 shows the state of a semiconductor substrate made of silicon after etching using an etching solution containing TMAH. The crystal plane of the surface of the semiconductor substrate is the (100) plane.

[0043] A mask layer, such as a resist pattern or silicon oxide film, is selectively formed on a semiconductor substrate, and an etching process using an etching solution containing TMAH is performed using the mask layer as a mask. This forms a groove in the semiconductor substrate. After a certain period of time, all of the crystal planes on the side of the groove become (111) planes, and the side of the groove becomes flat. In addition, the angle θ between the surface of the semiconductor substrate and the side of the groove is 54.7 degrees.

[0044] The semiconductor substrate SUB of the first embodiment has the same configuration as that shown in Fig. 6. That is, the crystal plane of the front surface TS of the semiconductor substrate SUB is the (100) plane, and the crystal plane of the side surface of the opening OP1 is the (111) plane. The angle θ formed between the front surface TS of the semiconductor substrate SUB and the side surface of the opening OP1 is 54.7 degrees.

[0045] This etching process does not use immersion technology using an ArF laser, but instead employs an inexpensive processing method, thereby suppressing increases in manufacturing costs. Note that the above etching process can also be performed using an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) instead of TMAH. However, TMAH is commonly used as a developer, for example, when forming a resist pattern. Therefore, in the manufacturing process of semiconductor devices, TMAH has the advantage of being universally easy to use in terms of solution management after the etching process. Therefore, it is preferable to use an etching solution containing TMAH for the above etching process.

[0046] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device 100 according to the first embodiment will be described below with reference to Figures 7 to 14. Note that the following mainly describes the region 1A and the region 2A shown in Figure 5.

[0047] To briefly outline each manufacturing step, first, a semiconductor substrate SUB having an n-type drift region NV is prepared. Next, an IGBT is formed in region 1A, and a diode is formed in region 2A. After that, the thickness of the semiconductor substrate SUB in region 1A is made thinner than the thickness of the semiconductor substrate SUB in region 2A.

[0048] 7, an orientation flat OF is provided on a semiconductor substrate SUB in a wafer state. In the first embodiment, the orientation flat OF is <110> It is processed along the direction.

[0049] As shown in FIG. 8, trenches TR are formed in regions 1A and 2A of the semiconductor substrate SUB on the front surface TS side of the semiconductor substrate SUB. First, an insulating film made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB, and the insulating film is patterned by photolithography and dry etching to form a hard mask. Next, an anisotropic etching process is performed on the semiconductor substrate SUB using the hard mask as a mask, thereby forming trenches TR in the semiconductor substrate SUB. Thereafter, the hard mask is removed by wet etching or the like.

[0050] At this point, the thickness of the semiconductor substrate SUB is thicker than in the state shown in FIG. 5, and the back surface of the semiconductor substrate SUB is shown as back surface BS0. The thickness from the front surface TS to the back surface BS0 is approximately 700 to 800 μm. The thickness of the semiconductor substrate SUB is reduced by a polishing process described later, and the back surface BS0 becomes the back surface BS.

[0051] Although not shown here, before forming the trench TR, a field insulating film FI shown in FIG. 4 is formed on the surface TS of the semiconductor substrate SUB in the peripheral region 3A by, for example, thermal oxidation.

[0052] As shown in FIG. 9, a gate insulating film GI is formed inside the trench TR and on the surface TS of the semiconductor substrate SUB by thermal oxidation. Next, a polycrystalline silicon film doped with n-type impurities is formed on the gate insulating film GI by, for example, CVD so as to fill the inside of the trench TR. Next, the polycrystalline silicon film formed outside the trench TR is removed by dry etching. The polycrystalline silicon film formed inside the trench TR in region 1A remains as gate electrode GE1, and the polycrystalline silicon film formed inside the trench TR in region 2A remains as gate electrode GE2. Although not shown here, the gate extension portions GE1a and GE2a shown in FIG. 2 are also formed in the process of forming the gate electrodes GE1 and GE2.

[0053] 10, on the front surface TS side of the semiconductor substrate SUB, a p-type base region PB is formed in the semiconductor substrate SUB in regions 1A and 2A by photolithography and ion implantation. The base region PB is formed to be shallower than the bottom of the trench TR. Although not shown here, before or after forming the base region PB, a p-type well region PW shown in FIG. 4 is formed by photolithography and ion implantation.

[0054] Next, on the front surface TS side of the semiconductor substrate SUB, an n-type emitter region NE is formed in the base region PB of region 1A by photolithography and ion implantation, and a p-type anode region PA is formed in the base region PB of region 2A. Although not shown here, before or after forming the emitter region NE and the anode region PA, a p-type high-concentration diffusion region PR shown in FIG. 4 is formed by photolithography and ion implantation. Thereafter, a heat treatment is performed, for example, at 950°C for 30 seconds to activate the impurities contained in each impurity region.

[0055] 11, in regions 1A and 2A, an interlayer insulating film IL is formed on a surface TS of a semiconductor substrate SUB by, for example, a CVD method. Next, contact holes reaching the emitter region NE and the anode region PA are formed in the interlayer insulating film IL by photolithography and dry etching. Although not shown here, the contact holes are also formed on the heavily doped diffusion region PR and the gate lead portions GE1a and GE2a.

[0056] As shown in FIG. 12, an emitter electrode EE is formed on the interlayer insulating film IL so as to fill the contact hole. First, a titanium nitride film and an aluminum film are sequentially formed on the interlayer insulating film IL by, for example, sputtering. Next, the titanium nitride film and the aluminum film are patterned to form the emitter electrode EE. Note that a gate wiring GW is also formed on the interlayer insulating film IL by the same process as the process of forming the emitter electrode EE.

[0057] By this step, the gate electrode GE1 is electrically connected to the gate wiring GW, and the emitter region NE, the anode region PA, the base region PB, the heavily doped diffusion region PR and the gate electrode GE2 are electrically connected to the emitter electrode EE.

[0058] Next, in the regions 1A and 2A, the back surface BS0 of the semiconductor substrate SUB is polished to reduce the thickness of the semiconductor substrate SUB. In FIG. 12, the back surface of the semiconductor substrate SUB after the polishing step is illustrated as back surface BS. This polishing step allows the thickness of the semiconductor substrate SUB to be adjusted to a thickness T2 that is optimal for the diode characteristics. The thickness T2 is, for example, 50 to 160 μm, and more preferably 85 μm.

[0059] 13, an opening OP1 is formed in the back surface BS of the semiconductor substrate SUB, thereby making the thickness BS1 of the semiconductor substrate SUB in region 1A thinner than the thickness BS2 of the semiconductor substrate SUB in region 2A. First, an opening is formed in the back surface BS of the semiconductor substrate SUB in region 1A, and a mask pattern MP1 is formed to selectively cover the back surface BS of the semiconductor substrate SUB in region 2A. The mask pattern MP1 is made of, for example, a resist pattern or an insulating film such as a silicon oxide film patterned using a resist pattern.

[0060] Next, an etching process is performed using an etching solution containing TMAH, using the mask pattern MP1 as a mask, to form an opening OP1 in the back surface BS of the semiconductor substrate SUB in region 1A. As a result, a step is generated in the back surface BS of the semiconductor substrate SUB such that the back surface BS1 of the semiconductor substrate SUB in region 1A is positioned higher than the back surface BS2 of the semiconductor substrate SUB in region 2A. Next, the mask pattern MP1 is removed by ashing or wet etching. Note that, as shown in FIG. 3, in the first embodiment, the shape of the opening OP1 is rectangular with the long sides along the Y direction and the short sides along the X direction.

[0061] The mask pattern MP1 is formed so as to cover the back surface BS of the semiconductor substrate SUB in the peripheral region 3 A. Therefore, after the etching process using the etching solution containing TMAH, the thickness of the semiconductor substrate SUB in the region 1 A is thinner than the thickness of the semiconductor substrate SUB in the peripheral region 3 A.

[0062] As shown in Figure 14, a buffer region NB, a collector region PC, and a cathode region NC are sequentially formed on the back surface BS of the semiconductor substrate SUB. First, on the back surface BS side of the semiconductor substrate SUB, an n-type buffer region NB is formed in the semiconductor substrate SUB in regions 1A and 2A by ion implantation. Next, on the back surface BS side of the semiconductor substrate SUB, a p-type collector region PC is formed in the semiconductor substrate SUB in region 1A by photolithography and ion implantation, and an n-type cathode region NC is formed in the semiconductor substrate SUB in region 2A. The buffer region NB and n-type cathode region NC are also formed in the semiconductor substrate SUB in the peripheral region 3A.

[0063] Next, the collector electrode CE is formed, resulting in the structure shown in Fig. 5. In regions 1A and 2A, the collector electrode CE is formed on the back surfaces BS1 and BS2 of the semiconductor substrate SUB by, for example, sputtering. This process electrically connects the collector region PC and the cathode region NC to the collector electrode CE.

[0064] Thereafter, the semiconductor substrate SUB in a wafer state is subjected to a dicing process or the like to separate the semiconductor substrate SUB, and a plurality of semiconductor devices 100, which are semiconductor chips, are obtained.

[0065] (Embodiment 2) 15 and 16, a semiconductor device 100 according to the second embodiment will be described below. The following mainly describes the differences from the first embodiment, and a description of the points that overlap with the first embodiment will be omitted.

[0066] 15, in the second embodiment, as in the first embodiment, the thickness T3 of the semiconductor substrate SUB in the region 1A is smaller than the thickness T2 of the semiconductor substrate SUB in the region 2A. However, in the second embodiment, an opening OP2 is formed in the surface TS of the semiconductor substrate SUB in the region 1A. As a result, a step is generated in the surface TS of the semiconductor substrate SUB such that the surface TS1 of the semiconductor substrate SUB in the region 1A is located lower than the surface TS2 of the semiconductor substrate SUB in the region 2A.

[0067] Therefore, since the thickness T3 of the region 1A is thinner than the thickness T1 of the first embodiment, the distance from the base region PB of the region 1A to the collector region PC of the region 1A is shorter than that of the first embodiment. In other words, the thickness of the drift region NV of the region 1A is thinner than that of the first embodiment. This makes it possible to further reduce the on-resistance of the IGBT while maintaining the diode performance at the same level as that of the first embodiment.

[0068] On the other hand, the thickness T3 of the region 1A can also be designed to be the same as the thickness T1 of the first embodiment. In that case, the thickness T2 of the region 2A will be thicker than the thickness T2 of the first embodiment. As a result, the distance from the base region PB of the region 2A to the cathode region NC of the region 2A will be longer than in the first embodiment. In other words, the thickness of the drift region NV of the region 2A will be thicker than in the first embodiment. Therefore, it is possible to further reduce the risk of ringing occurring in the diode while maintaining the same level of IGBT performance as in the first embodiment.

[0069] The thickness T1 of the semiconductor substrate SUB in region 1A is the thickness from the front surface TS1 of the semiconductor substrate SUB to the back surface BS1 of the semiconductor substrate SUB. The thickness T3 of the semiconductor substrate SUB in region 2A is the thickness from the front surface TS2 of the semiconductor substrate SUB to the back surface BS2 of the semiconductor substrate SUB. The thickness T1 is thinner than the thickness T3 by 100 to 300 nm.

[0070] The front surface TS of the semiconductor substrate SUB is where trench TR formation and ion implantation depth adjustment are performed, and therefore requires higher photolithography accuracy than the back surface BS of the semiconductor substrate SUB. Therefore, if the front surface TS1 of the semiconductor substrate SUB in the region 1A is recessed too much, variations in photolithography resolution may occur. Therefore, it is preferable that the depth of the opening OP2 is shallower than the depth of the opening OP1.

[0071] 16 shows a manufacturing process for forming the opening OP2 according to the second embodiment. The manufacturing process of FIG. 16 is performed before the process of forming the trench TR of FIG.

[0072] First, a mask pattern MP2 is formed to open the surface TS of the semiconductor substrate SUB in region 1A and selectively cover the surface TS of the semiconductor substrate SUB in region 2A. The mask pattern MP2 is, for example, a resist pattern or an insulating film such as a silicon oxide film patterned using a resist pattern. Next, using the mask pattern MP2 as a mask, an etching process is performed using an etching solution containing TMAH, thereby forming an opening OP2 in the surface TS of the semiconductor substrate SUB in region 1A. Thereafter, the mask pattern MP2 is removed by ashing, wet etching, or the like.

[0073] The subsequent manufacturing steps are the same as those shown in FIG.

[0074] Although the example shown here is one in which the opening OP1 is provided in the back surface BS of the semiconductor substrate SUB and the opening OP2 is provided in the front surface TS of the semiconductor substrate SUB, it is also possible to provide only the opening OP2 without providing the opening OP1. Even in this case, compared to the conventional technology, it is possible to suppress ringing in the region 2A and reduce the on-resistance in the region 1A.

[0075] (Embodiment 3) The semiconductor device 100 according to the third embodiment will be described below with reference to Fig. 17. The following mainly describes the differences from the first embodiment, and the description of the points that overlap with the first embodiment will be omitted.

[0076] In the first embodiment, an n-type cathode region NC was formed over the entire back surface BS2 of the semiconductor substrate SUB in the region 2A. As shown in FIG. 17, in the third embodiment, not only the cathode region NC but also a p-type hole injection region (semiconductor region) PH is formed in the semiconductor substrate SUB in the region 2A on the back surface BS2 side of the semiconductor substrate SUB. The hole injection region PH is formed so as to replace a part of the cathode region NC and is in contact with the cathode region NC. The impurity concentration of the hole injection region PH is 1×10 17 ~1×10 21 cm -3 is.

[0077] In such a diode, the ON operation mainly occurs between the cathode region NC and the anode region PA. Since the carrier density immediately above the hole injection region PH is lower than the carrier density immediately above the cathode region NC, the ON operation does not generally occur immediately above the hole injection region PH.

[0078] When a reverse bias is applied to the diode (recovery operation), holes are discharged to the anode region PA, and electrons are discharged to the cathode region NC. By making part of the cathode region NC the hole injection region PH, the carrier density during on-state operation differs in parts, and therefore the depletion layer expands differently directly above the cathode region NC and directly above the hole injection region PH.

[0079] Some of the electrons emitted during recovery operation do not pass through the hole injection region PH but flow toward the cathode region NC. At this time, IR-Drop occurs due to the electron current and the resistance component of the buffer region NB. Because the hole injection region PH is in contact with the cathode region NC, the PN junction is transiently turned on when IR-Drop exceeds 0.7 V (built-in voltage). As a result, holes are injected from the hole injection region PH, and a plasma region is formed near the cathode region NC. Because the plasma region stops the expansion of the depletion layer, the electric field is relaxed on the back surface BS2 of the semiconductor substrate SUB, making it easier to suppress ringing. In other words, the hole injection region PH further improves the reliability of the semiconductor device.

[0080] Such a hole injection region PH can be formed after the formation of the buffer region NB in ​​FIG. 14. That is, on the back surface BS2 side of the semiconductor substrate SUB, the p-type hole injection region PH is formed in the region 2A of the semiconductor substrate SUB by photolithography and ion implantation. The hole injection region PH, the cathode region NC, and the collector region PC may be formed in any order.

[0081] Furthermore, the technology disclosed in the third embodiment can be used in appropriate combination with the technology disclosed in the second embodiment.

[0082] (Fourth embodiment) A semiconductor device 100 according to the fourth embodiment will be described below with reference to Figures 18 and 19. The following mainly describes differences from the first embodiment, and explanations of points that overlap with the first embodiment will be omitted. Figure 18 mainly shows the structure near the front surface TS of the semiconductor substrate SUB. Figure 19 shows the structure of the back surface BS of the semiconductor substrate SUB.

[0083] In the first embodiment, the semiconductor substrate SUB in a wafer state shown in FIG. <110> In the fourth embodiment, the semiconductor substrate SUB in a wafer state has an orientation flat OF processed along the direction of the substrate. <100> An orientation flat OF is provided, which is machined along the direction.

[0084] When forming an opening OP1 in such a semiconductor substrate SUB by etching using an etching solution containing TMAH, the crystal plane of the side surface of the opening OP1 will not be the (111) plane if processing is to be performed into the shape shown in Fig. 3. Therefore, in the fourth embodiment, it is necessary to rotate the mask pattern MP1 for forming the opening OP1 by 45 degrees.

[0085] As shown in Figure 19, the shape of the opening OP1 in embodiment 4 is rectangular, with the long side running along a direction tilted 45 degrees from the Y direction (third direction) and the short side running along a direction tilted 90 degrees from the third direction (fourth direction).

[0086] Accordingly, the layout of the trenches TR and gate electrodes GE1, GE2 formed in the regions 1A and 2A must also be changed so as to be inclined at 45 degrees. In the first embodiment, the trenches TR are formed in a stripe shape extending in the Y direction, but in the fourth embodiment, a plurality of rectangular trenches TR are arranged in the third direction. That is, each of the plurality of trenches TR has a rectangular shape having a first portion extending in the Y direction and a second portion extending in the X direction. The plurality of trenches TR are connected to each other along the third direction. Note that, as in the first embodiment, the gate electrodes GE1, GE2 are embedded inside the rectangular trenches TR.

[0087] In this way, the semiconductor substrate SUB <100> Even when an orientation flat OF processed along the direction is provided, the IGBT in region 1A and the diode in region 2A can be formed to match the shape of the opening OP1, and ringing can be suppressed in region 2A while the on-resistance can be reduced in region 1A.

[0088] Furthermore, the technology disclosed in the fourth embodiment can be used in appropriate combination with the technology disclosed in the second and third embodiments.

[0089] (Embodiment 5) 20 and 21, a semiconductor device 100 according to the fifth embodiment will be described below. The following mainly describes the differences from the fourth embodiment, and a description of the points that overlap with the fourth embodiment will be omitted.

[0090] In the fifth embodiment, similarly to the fourth embodiment, the semiconductor substrate SUB in a wafer state has: <100> An orientation flat OF is provided, which is processed along the direction. Therefore, the mask pattern MP1 for forming the opening OP1 needs to be rotated by 45 degrees. However, in the fifth embodiment, the layout of the trench TR and the gate electrodes GE1 and GE2 formed in the region 1A and the region 2A is the same as that shown in FIG.

[0091] In the fifth embodiment, the opening shape of the mask pattern MP1 is devised. As shown in Fig. 20, a plurality of quadrangles each having a side along the third direction and a side along the fourth direction are prepared as the layout of the processing mask for the mask pattern MP1. These are then combined so that they extend in the Y direction as a whole. The mask pattern MP1 is formed using such a processing mask.

[0092] That is, the opening shape of the mask pattern MP1 is a shape in which a plurality of quadrangles, each having a side along the third direction and a side along the fourth direction, are joined together so as to extend generally in the Y direction. By etching the back surface BS of the semiconductor substrate SUB using this mask pattern MP1 as a mask, an opening OP1 extending generally in the Y direction is formed, as shown in FIG.

[0093] The opening shape of the mask pattern MP1 has right-angled portions like the connecting portions of the above-mentioned squares, and when etching is performed using an etching solution containing TMAH, such portions tend to become rounded.

[0094] In this way, the semiconductor substrate SUB <100> Even if an orientation flat OF processed along the direction is provided, a layout similar to that shown in FIG. 2 can be achieved.

[0095] Furthermore, the technology disclosed in the fifth embodiment can also be used in appropriate combination with the technology disclosed in the second and third embodiments.

[0096] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0097] 100 Semiconductor device 1A area (IGBT area) 2A region (diode region) 3A outer area BS, BS1, BS2 Backside of semiconductor substrate CE collector electrode EE emitter electrode FI field insulating film GE1, GE2 gate electrodes GE1a, GE2a Gate pull-out section GI gate insulating film GW Gate wiring IL Interlayer insulating film OF Orientation Flat OP1, OP2 opening MP1, MP2 mask patterns NB buffer area NC cathode region NE emitter region NV drift region PA anode region PB Base Area PC Collector Area PH hole injection region PR high concentration diffusion region PW well region SUB Semiconductor substrate T1~T3 Semiconductor substrate thickness TR Trench TS, TS1, TS2 Surface of semiconductor substrate

Claims

1. A semiconductor device including a first region and a second region, a semiconductor substrate of a first conductivity type having a front surface and a back surface; an IGBT formed on the semiconductor substrate in the first region; a diode formed in the semiconductor substrate in the second region; Equipped with A semiconductor device, wherein the thickness of the semiconductor substrate in the first region is thinner than the thickness of the semiconductor substrate in the second region by a range of 1 μm or more and 10 μm or less.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein a step is generated on the back surface of the semiconductor substrate such that the back surface of the semiconductor substrate in the first region is located higher than the back surface of the semiconductor substrate in the second region.

3. A semiconductor device including a first region and a second region, a semiconductor substrate of a first conductivity type having a front surface and a back surface; an IGBT formed on the semiconductor substrate in the first region; a diode formed in the semiconductor substrate in the second region; Equipped with a thickness of the semiconductor substrate in the first region is thinner than a thickness of the semiconductor substrate in the second region; a step is generated on the rear surface of the semiconductor substrate such that the rear surface of the semiconductor substrate in the first region is located higher than the rear surface of the semiconductor substrate in the second region; A semiconductor device, wherein a step is generated on the surface of the semiconductor substrate such that the surface of the semiconductor substrate in the first region is located lower than the surface of the semiconductor substrate in the second region.

4. 4. The semiconductor device according to claim 1, a base region of a second conductivity type, which is formed in the semiconductor substrate in the first region on the front surface side of the semiconductor substrate and has a conductivity type opposite to the first conductivity type; an emitter region of the first conductivity type formed in the base region of the first region; a trench formed in the semiconductor substrate in the first region on the front surface side of the semiconductor substrate so that the bottom of the trench is located lower than a base region; a gate insulating film formed inside the trench; a gate electrode formed on the gate insulating film so as to fill the trench; a collector region of the second conductivity type formed in the semiconductor substrate in the first region on the back surface side of the semiconductor substrate; an anode region of the second conductivity type formed in the semiconductor substrate in the second region on the front surface side of the semiconductor substrate; a cathode region of the first conductivity type formed in the semiconductor substrate in the second region on the back surface side of the semiconductor substrate; an interlayer insulating film formed on the surface of the semiconductor substrate in the first region and the second region; an emitter electrode and a gate wiring formed on the interlayer insulating film; a collector electrode formed on the back surface of the semiconductor substrate in the first region and the second region; Further provided with the gate electrode is electrically connected to the gate wiring; the base region, the emitter region, and the anode region are electrically connected to the emitter electrode; The collector region and the cathode region are electrically connected to the collector electrode.

5. 5. The semiconductor device according to claim 4, the semiconductor device further comprising: a hole injection region of the second conductivity type formed in the semiconductor substrate in the second region on the back surface side of the semiconductor substrate so as to be in contact with the cathode region.

6. 5. The semiconductor device according to claim 4, further including an outer peripheral region surrounding the first region and the second region in a plan view; the cathode region is also formed in the semiconductor substrate in the peripheral region on the back surface side of the semiconductor substrate, A semiconductor device, wherein the thickness of the semiconductor substrate in the first region is thinner than the thickness of the semiconductor substrate in the peripheral region.

7. 5. The semiconductor device according to claim 4, the base region is also formed in the semiconductor substrate in the second region; the anode region is formed in the base region of the second region; A semiconductor device, wherein a distance from the base region of the first region to the collector region of the first region is shorter than a distance from the base region of the second region to the cathode region of the second region.

8. 1. A method for manufacturing a semiconductor device including a first region and a second region, comprising: (a) providing a semiconductor substrate of a first conductivity type having a front surface and a back surface; (b) forming an IGBT in the semiconductor substrate in the first region and a diode in the semiconductor substrate in the second region; (c) reducing the thickness of the semiconductor substrate in the first region by 1 μm or more and 10 μm or less than the thickness of the semiconductor substrate in the second region; A method for manufacturing a semiconductor device comprising:

9. 9. The method for manufacturing a semiconductor device according to claim 8, The step (b) comprises: (b1) forming a trench in the first region of the semiconductor substrate on the front surface side of the semiconductor substrate; (b2) forming a gate insulating film inside the trench; (b3) forming a gate electrode on the gate insulating film so as to fill the trench; (b4) forming a base region of a second conductivity type, which is opposite to the first conductivity type, in the semiconductor substrate of the first region on the surface side of the semiconductor substrate so as to be shallower than the bottom of the trench; (b5) forming an emitter region of the first conductivity type in the base region of the first region; (b6) forming an anode region of the second conductivity type in the semiconductor substrate in the second region on the front surface side of the semiconductor substrate; (b7) forming an interlayer insulating film on the surface of the semiconductor substrate in the first region and the second region; (b8) forming an emitter electrode on the interlayer insulating film so as to be electrically connected to the base region, the emitter region, and the anode region, and forming a gate wiring on the interlayer insulating film so as to be electrically connected to the gate electrode; (b9) forming a collector region of the second conductivity type in the semiconductor substrate in the first region on the back surface side of the semiconductor substrate; (b10) forming a cathode region of the first conductivity type in the semiconductor substrate in the second region on the back surface side of the semiconductor substrate; (b11) forming a collector electrode on the back surface of the semiconductor substrate in the first region and the second region so as to be electrically connected to the collector region and the cathode region; The method for manufacturing a semiconductor device includes the steps of:

10. A method for manufacturing a semiconductor device including a first region and a second region, comprising: (a) providing a semiconductor substrate of a first conductivity type having a front surface and a back surface; (b) forming an IGBT in the semiconductor substrate in the first region and a diode in the semiconductor substrate in the second region; (c) making the thickness of the semiconductor substrate in the first region thinner than the thickness of the semiconductor substrate in the second region; Equipped with The step (b) comprises: (b1) forming a trench in the first region of the semiconductor substrate on the front surface side of the semiconductor substrate; (b2) forming a gate insulating film inside the trench; (b3) forming a gate electrode on the gate insulating film so as to fill the trench; (b4) forming a base region of a second conductivity type, which is opposite to the first conductivity type, in the semiconductor substrate of the first region on the surface side of the semiconductor substrate so as to be shallower than the bottom of the trench; (b5) forming an emitter region of the first conductivity type in the base region of the first region; (b6) forming an anode region of the second conductivity type in the semiconductor substrate in the second region on the front surface side of the semiconductor substrate; (b7) forming an interlayer insulating film on the surface of the semiconductor substrate in the first region and the second region; (b8) forming an emitter electrode on the interlayer insulating film so as to be electrically connected to the base region, the emitter region, and the anode region, and forming a gate wiring on the interlayer insulating film so as to be electrically connected to the gate electrode; (b9) forming a collector region of the second conductivity type in the semiconductor substrate in the first region on the back surface side of the semiconductor substrate; (b10) forming a cathode region of the first conductivity type in the semiconductor substrate in the second region on the back surface side of the semiconductor substrate; (b11) forming a collector electrode on the back surface of the semiconductor substrate in the first region and the second region so as to be electrically connected to the collector region and the cathode region; and The step (c) is performed after the steps (b1) to (b8) and before the steps (b9) to (b11), (c1) forming a first mask pattern that opens the back surface of the semiconductor substrate in the first region and selectively covers the back surface of the semiconductor substrate in the second region; (c2) after the step (c1), performing an etching process using an etching solution containing tetramethylammonium hydroxide as a mask to form a first opening on the back surface of the semiconductor substrate in the first region; (c3) after the step (c2), removing the first mask pattern; The method for manufacturing a semiconductor device comprising the steps of:

11. 11. The method for manufacturing a semiconductor device according to claim 10, The step (c) is performed after the step (b8) and before the step (c1), (c0) reducing the thickness of the semiconductor substrate by polishing the back surface of the semiconductor substrate in the first region and the second region; The method for manufacturing a semiconductor device further comprises:

12. 11. The method for manufacturing a semiconductor device according to claim 10, The step (c) is performed after the step (a) and before the steps (b1) to (b11), (c4) forming a second mask pattern that opens the surface of the semiconductor substrate in the first region and selectively covers the surface of the semiconductor substrate in the second region; (c5) after the step (c4), performing an etching process using the second mask pattern as a mask and an etching solution containing tetramethylammonium hydroxide to form a second opening in the surface of the semiconductor substrate in the first region; (c6) after the step (c5), removing the second mask pattern; The method for manufacturing a semiconductor device further comprises:

13. 11. The method for manufacturing a semiconductor device according to claim 10, The semiconductor substrate prepared in the step (a) has an orientation flat processed along a <110> direction; a plurality of the trenches are formed in the semiconductor substrate in the first region; The plurality of trenches each extend in a first direction in a plan view and are adjacent to each other in a second direction perpendicular to the first direction in a plan view; A method for manufacturing a semiconductor device, wherein the first opening has a rectangular shape with long sides along the first direction and short sides along the second direction.

14. 11. The method for manufacturing a semiconductor device according to claim 10, The semiconductor substrate prepared in the step (a) has an orientation flat processed along a <100> direction; a plurality of the trenches are formed in the semiconductor substrate in the first region; Each of the plurality of trenches has a rectangular shape having a first portion extending in a first direction in a plan view and a second portion extending in a second direction perpendicular to the first direction in a plan view; the plurality of trenches are connected to one another along a third direction tilted 45 degrees from the first direction, A method for manufacturing a semiconductor device, wherein the shape of the first opening is rectangular with a long side along the third direction and a short side along a fourth direction tilted 90 degrees from the third direction.

15. 11. The method for manufacturing a semiconductor device according to claim 10, The semiconductor substrate prepared in the step (a) has an orientation flat processed along a <100> direction; a plurality of the trenches are formed in the semiconductor substrate in the first region; The plurality of trenches each extend in a first direction in a plan view and are adjacent to each other in a second direction perpendicular to the first direction in a plan view; a method for manufacturing a semiconductor device, wherein the opening shape of the first mask pattern is a shape formed by connecting multiple rectangles each having a side along a third direction tilted 45 degrees from the first direction and a side along a fourth direction tilted 90 degrees from the third direction, so that the rectangles extend overall in the first direction.

16. 11. The method for manufacturing a semiconductor device according to claim 9, The step (b) is performed after the step (b8) and before the step (b11), (b12) forming a hole injection region of the second conductivity type in the semiconductor substrate in the second region on the back surface side of the semiconductor substrate so as to be in contact with the cathode region; The method for manufacturing a semiconductor device further comprises:

17. 11. The method for manufacturing a semiconductor device according to claim 9, the semiconductor substrate includes a peripheral region that surrounds the first region and the second region in a plan view, In the step (b10), the cathode region is also formed in the semiconductor substrate in the peripheral region on the back surface side of the semiconductor substrate, In the step (c), the thickness of the semiconductor substrate in the first region is thinner than the thickness of the semiconductor substrate in the peripheral region.

18. 11. The method for manufacturing a semiconductor device according to claim 9, In the step (b4), the base region is also formed in the semiconductor substrate in the second region; In the step (b6), the anode region is formed in the base region of the second region; A method for manufacturing a semiconductor device, wherein a distance from the base region of the first region to the collector region of the first region is shorter than a distance from the base region of the second region to the cathode region of the second region.

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