High-performance high-speed Mux-D scan flip-flop

Abstract

To provide high performance high speed MUX-D scan flip flop.SOLUTION: There is provided a high speed Mux-D scan flip-flop (FF) that bypasses a scan multiplexer to a masterkeeper side path and eliminates a delay overhead of a traditional Mux-D scan circuit topology. The design is compatible with a simple scan metrology of Mux-D scan while maintaining a small area and a small number of inputs / outputs compared to the traditional Mux-D scan circuit topology. Since the scan Mux is not in a forward critical path of FF, the circuit topology has the same high performance as a level sensitive scan flip-flop and can be easily converted to a bare pass gate version. The new high speed Mux-D scan flip flop combines the advantages of the traditional LSSD and the Mux-D scan flip flop without their respective drawbacks.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an apparatus for sampling data. [Background technology]

[0002] High-performance design for modern microprocessors, discrete graphics, digital signal processors (DSPs), and hardware accelerators in laptops and servers is becoming increasingly important due to the emergence of new applications such as artificial intelligence (AI), machine learning, autonomous driving, and security / cryptocurrency. At the same time, there is a desire to reduce silicon costs, improve time-to-market (TTM), and slow the scaling cadence of process technology nodes. These requirements must be met while meeting stringent frequency and performance targets, power, and / or leakage budgets. One important standard cell and fundamental building block of digital integrated circuits is the flip-flop, which is required to store state in any sequential logic. Each latch or flip-flop is expected to contain testability circuit hooks (also called scan logic) that are used only for testing (e.g., design-for-test (DFT)). These scan logics can, for example, consume approximately 70% of the latch's standard cell size or be a fraction of the critical delay-limited frequency. As such, scan logic represents significant overhead. Summary of the Invention

[0003] Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure, which should not be construed as limiting the disclosure to the particular embodiments but are merely for purposes of illustration and understanding. [Brief explanation of the drawings]

[0004] [Figure 1] Figure 1 shows a level sensitive scanning design. [Figure 2] FIG. 2 shows an input data multiplexer (Mux-D) scan flip-flop (FF). [Figure 3A] FIG. 3A illustrates scannable clock logic that controls high-speed Mux-D scan FFs, according to some embodiments. [Figure 3B] FIG. 3B shows a schematic diagram of FIG. 3A, according to some embodiments. [Figure 4] FIG. 4 shows a schematic diagram of a high-speed Mux-D scan FF controlled by scannable clock logic according to some embodiments. [Figure 5] FIG. 5 shows a schematic diagram of a bare pass gate (BP) high-speed mux-D scan FF controlled by scannable clock logic, according to some embodiments. [Figure 6] FIG. 6 illustrates a vectorized high-speed Mux-D scan FF according to some embodiments. [Figure 7] FIG. 7 illustrates a smart device, computer system, or SoC having high-speed Mux-D scan flip-flops according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005] Various embodiments disclose a novel high-speed Mux-D scan flip-flop (FF) that bypasses the conventional input data scan multiplexer to the master-keeper side path, eliminating the delay overhead of conventional Mux-D scan circuit topologies. The high-speed Mux-D scan FF is compatible with the simple scan metrology of Mux-D scan while maintaining a small area and a small number of inputs / outputs compared to conventional Mux-D scan circuit topologies. Because the scan mux is not in the FF's forward critical path, the circuit topology has similar high performance to a level-sensitive scan design (LSSD) scan FF and can be easily converted to a bare-pass gate version. The high-speed Mux-D scan flip-flop of various embodiments combines the advantages of conventional LSSD and Mux-D scan flip-flops without their respective disadvantages.

[0006] There are many technical advantages of various embodiments. For example, bypassing the scan mux to the master-keeper side path eliminates the delay overhead of a Mux-D scan topology. The design of a high-speed Mux-D scan FF is compatible with the simple scan metrology of a Mux-D scan FF. The FFs of various embodiments offer a small area and a small number of inputs / outputs as a conventional Mux-D scan FF. The FFs of various embodiments have high performance similar to LSSD scan flip-flops. The FFs of various embodiments can be converted to bare pass-gate versions for higher performance. The FFs of various embodiments can be organized into vectored FF topologies. Other technical advantages will be apparent from the various figures and embodiments.

[0007] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments of the present disclosure.

[0008] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or may have arrows at one or more ends to indicate the direction of the primary flow of information. Such designations are not intended to be limiting. Rather, lines are used in connection with one or more exemplary embodiments to facilitate understanding of a circuit or logic unit. Any signal represented as dictated by design necessity or choice may, in fact, include one or more signals that can travel in either direction and be implemented with any suitable type of signaling.

[0009] In the specification and claims, the term "connected" means a direct connection, e.g., an electrical, mechanical, or magnetic connection, between the things that are connected, without any intermediate device.

[0010] Here, the term "analog signal" refers to any continuous signal whose time-varying characteristics (variables) are representations of other time-varying quantities, i.e., similar to another time-varying signal.

[0011] Here, the term "digital signal" refers to a physical signal that is a representation of a sequence of discrete values ​​(a quantified discrete-time signal), e.g., any bit stream, or an analog signal that has been digitized (sampled and converted from analog to digital).

[0012] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection, or an indirect connection through one or more passive or active intermediary devices, between the objects that are connected.

[0013] As used herein, the term "adjacent" generally refers to the location of something next to (e.g., directly adjacent to or in close proximity to one or more of) or adjacent to (e.g., abutting) another thing.

[0014] The term "circuit" or "module" refers to one or more passive and / or active components arranged to cooperate with each other to provide a desired function.

[0015] The term "signal" refers to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an" and "the" include plural references. The meaning of "in" includes "inside" and "on."

[0016] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another, resulting in a reduced layout area. The term "scaling" also generally refers to downsizing layouts and devices within the same technology node. The term "scaling" also refers to adjusting (e.g., slowing down or speeding up) signal frequency relative to other parameters, such as power supply levels.

[0017] The terms "substantially," "close," "approximately," "near," and "about," etc., generally mean within + / - 10% of a target value.

[0018] The use of ordinal adjectives such as "first," "second," and "third" to describe common objects, unless otherwise specified, merely indicates that different instances of similar objects are being referred to and does not imply that the objects so described must be in a given sequence, temporally, spatially, in ranking, or otherwise.

[0019] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0020] In the specification and claims, when the terms "left," "right," "front," "rear," "top," "bottom," "upper," "lower," etc. appear, they are used for descriptive purposes and not necessarily to describe permanent relative positions.

[0021] It is pointed out that elements of a figure having the same reference number (or name) as elements of another figure may operate or function in a manner similar to that described, but is not limited to such.

[0022] For purposes of the embodiments, the transistors in the various circuit and logic blocks described herein are metal-oxide-semiconductor (MOS) transistors or their derivatives, where MOS transistors include drain, source, gate, and bulk terminals. Transistors and / or derivatives of MOS transistors also include other devices that implement transistor functions, such as tri-gate and FinFET transistors, gate-all-around cylindrical transistors, tunnel FETs (TFETs), square wire, rectangular ribbon transistors, ferroelectric FETs (FeFETs), or carbon nanotube or spintronic devices. The symmetrical source and drain terminals of a MOSFET are, i.e., identical terminals, and are used interchangeably herein. On the other hand, TFET devices have asymmetrical source and drain terminals. Those skilled in the art will understand that other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., can be used without departing from the scope of the present disclosure.

[0023] Figure 1 shows a level-sensitive scan design 100. LSSD 100 consists of scan gadget 101, which is coupled to the side of the slave-keeper flip-flop and does not intersect with the forward-critical delay path of the flip-flop. The flip-flops consist of inverters inv1, inv2, inv3, inv4, inv5, and inv6; tri-state inverters invTS1 and invTS2; transmission gates TG1 and TG2; nodes data (d), d1, d1b, d1bd, d1bdb, nc1, nc2, and clock (clk). Scan gadget 101 consists of inverters inv7, inv8, inv9, inv10, and inv11; tri-state inverters invTS3, invTS4, and invTS5; nodes sca (scan input clock a), scb (scan input clock b), n11, n10, n1, and sout, coupled as shown. Since LSSD 100 has no extra gates in the forward path, LSSD 100 can also be easily converted to a bare-path gate version for higher performance. However, scan gadget 101 requires a larger area, complex scan metrology, two scan clocks, and more input / output pins.

[0024] FIG. 2 shows an input-data multiplexer (Mux-D) scan flip-flop (FF) 200. Mux-D scan design inserts a multiplexer (Mux) 201 at the input of the flip-flop, which selects either the data d or scan si input using a select signal ssb. Here, the suffix "b" indicates a logic inversion or signal inversion, and the suffix "d" indicates a delay without logic inversion. For example, ssb is the inverse of ss, and d1bd is the delayed and non-inverted version of d1b. Signal names and node names are used interchangeably herein. For example, the name "ss" can refer to the signal ss or the node ss, depending on the context.

[0025] The FF consists of inverters inv1, inv2, inv3, inv4, inv5, and inv6; tristate inverters invTS1 and invTS2; transmission gates TG1 and TG2; nodes d1, d1bd, d1bdb, and nc1; clock clk; and output q, coupled as shown. The Mux-D 201 consists of inverter inv7, buffer buf1, inverters invTS3 and invTS4, and nodes ss, in, si, ssb, and d, coupled as shown. The Mux-D 201 is in the forward critical delay path of the flip-flop, resulting in slower performance (than without it) and cannot be converted to a bare pass-gate version. However, the low overhead of the Mux-D scan 201 in terms of area and the simple scan with a single scan clock and few input / output pins make this design more attractive and easier to implement.

[0026] FIG. 3A shows scannable clock logic 300 for controlling high-speed Mux-D scan FFs according to some embodiments. Logic 300 includes an inverter MC1 that receives a clock clk as an input, OR logic 301, and AND logic 302. OR logic 301 includes a NOR gate MS1 and an inverter MS2 coupled as shown. Inputs to OR logic 301 are the clock clk and scan enable ssb. The output of OR logic 301 is nc3s. AND logic 302 includes a NAND gate MC2 and an inverter MC3. Inputs to AND logic 302 are the output nc1 of inverter MC1 and scan enable ssb. The output of AND logic 302 is nc3.

[0027] 3B shows the schematic 320 of FIG. 3A according to some embodiments. Inverter MC1 includes p-type transistor MP1 and n-type transistor MN1. NOR gate MS1 includes p-type transistor MP2 and n-type transistors MN2 and MN3.

[0028] 4 shows a schematic diagram of a high-speed Mux-D scan FF 400 controlled by scannable clock logic according to some embodiments. The high-speed Mux-D scan FF 400 includes inverters M1, M2, M4, M7, and M8; transmission pass gates M3 and M6; tristable inverters M2s, M5, M5, and M9; nodes d, db, dbdd, dbddb, dbddd, dbddb, si, sib; and output q. Transmission gates M3 and M6 and the tristable inverters are controlled by signals generated by scan-enabled clock logic 300 / 320.

[0029] In various embodiments, the data "d" and scan "si" inputs of the Mux Scan (Figure 2) are split into two separate master paths. The scan input si is bypassed to the master-keeper side path (including tristable inverters M2 and M5) and removed from the forward critical flip-flop delay path. The four scan select (ssb) gate master clocks are derived from the clock input using ssb gate NAND (MC2) and NOR (MS1) gates. The p-type transistor MP2 of the clock NOR gate (MS1) is shared with the clock inverter (MC1) p-type device MP1 to reduce input clock pin capacitance (pin-cap) and reduce clock power overhead.

[0030] Of the four derived clocks, two, nc2 and nc3, are the data side of the master latch and are connected to the transmission gate (M3) and master keeper (M5) of the forward path. The other two, nc2s and nc3s, are the scan side of the master latch and are connected to the scan tristate (M2s) and an additional master keeper (M5s). These clocks are gated by the scan select ssb so that only one of the master clock pair switches during normal or scan operation modes, minimizing power overhead.

[0031] The data master clocks (nc2 and nc3) are switched only during normal operation mode, and the scan master clocks (nc2 and nc3) are switched only during scan operation. One clock pair switching enables one master path. For example, one clock pair switching enables the data-side path during normal mode or the bypass scan path during scan operation mode, maintaining flip-flop functionality. The scan topology of various embodiments is fully compatible with traditional simple Mux-D scan metrology. Because the scan Mux is bypassed to the keeper-side path, the design of various embodiments eliminates the scan Mux delay overhead in traditional Mux-D scan flip-flops. The critical data path of the high-speed Mux-D flip-flop is similar to that of the LSSD scan flip-flop, thus resulting in similar high performance. Additionally, the number of scan clocks and scan inputs / outputs is the same as that of traditional Mux-D scan flip-flops.

[0032] In some embodiments, a device is provided that includes a master latch having a first data path and a second data path. The first data path includes a scan path (e.g., an electrical path originating from input si) that inputs to a memory circuit of the master latch. The second data path is a non-scan path (e.g., a data input path originating from data input d) that inputs through a transmission gate M3 coupled to the memory circuit. In various embodiments, when the device is a flip-flop instead of a latch, the device includes a slave latch (e.g., circuitry to the right of inverter M4) coupled to the master latch (e.g., circuitry to the left of inverter M4).

[0033] In various embodiments, the device includes a first inverter M1 for receiving input data d and a second inverter M2 coupled in series with the first inverter M1 via a node db. The second inverter is coupled to a transmission gate M3 via a node dbd. The transmission gate M3 is controlled by nc3 and nc2 generated by the scan select enable clock circuit 300 / 320.

[0034] In various embodiments, the memory circuit includes a first tristable inverter M5 having an input dbdd coupled to a transmission gate M3, and a second tristable inverter M5 having an input Sib coupled to the scan path and the output of the first tristable inverter M5s. The output dbdd of the second tristable inverter M5s is coupled to the transmission gate M3. The first tristable inverter M5s is controlled by nc3s and nc2s generated by circuit 300 / 320. The second tristable inverter M5s is controlled by nc2 and nc3 generated by circuit 300 / 320.

[0035] In various embodiments, transmission gate M3 is a first transmission gate, and the slave latch is coupled to the master latch through inverter M4, and the slave latch includes a second transmission gate M6 coupled to the output dbdb of inverter M4. Here, the memory circuit is a first memory circuit, and the slave latch includes a second memory circuit (including inverter M8 and tristable inverter M9) coupled to the second transmission gate M6. The second transmission gate M6 and tristable inverter M9 are controllable by clocks clk and nc1 (generated by circuit 300 / 320).

[0036] In various embodiments, the scan path includes a tristable inverter M2s having an input coupled to the scan input si and an output coupled to the input of a second tristable inverter, the tristable inverter M2s being controllable by nc2s and nc3s generated by circuit 300 / 320.

[0037] In various embodiments, the FF includes circuitry 300 / 320 for generating a scan select based on a gated clock derived from the input clock clk. The scan select based on the gated clock controls first transmission gate M3, controls first and second tristable inverters (M5s and M5) of the memory circuit, and controls the tristable inverters of the scan path. As described herein, circuitry 300 / 320 also controls tristable inverter M9 and second transmission gate M6.

[0038] In some embodiments, circuit 300 / 320 includes an inverter MC1 having an input coupled to input clock clk and an output nc1. Circuit 300 / 320 also includes AND logic 302 coupled to the output of inverter MC1. The AND logic receives a scan select signal as an input. Circuit 300 / 320 also includes OR logic 301 coupled to input clk of inverter MC1 and to output nc1 of inverter MC1, the OR logic receiving a scan select signal ssb as an input.

[0039] FIG. 5 shows a schematic diagram of a bare pass gate (BP) high-speed mux-D scan FF 500 controlled by scannable clock logic according to some embodiments. FF 500 is similar to FF 400, but for eliminating input data inverters M1 and M2. By eliminating inverters M1 and M2, pass gate M3 becomes a bare pass gate (BP). The high-speed mux-D FF of various embodiments (400 or 500) can be used in critical timing paths where it is desired to meet strict timing requirements. However, the embodiments are not limited to such, and the high-speed Mux-D FF can be used in place of a conventional FF. [Table 1]

[0040] Table 1 shows a summary of clk2Q (clock output delay), setup, and black hole time (BHT) delays for both rising and falling data edges. The high-speed Mux-D improved the BHT by 1.2 au (arbitrary units) for rising edges and 1.9 au for falling edges compared to the conventional Mux-D scan flip-flop, achieving an overall worst-case BHT improvement of 1.0 au. The bare pass gate (BP) high-speed Mux-D improved the BHT by 1.5 au for rising edges and 2.1 au for falling edges compared to the conventional Mux-D scan flip-flop, achieving an overall worst-case BHT improvement of 1.4 au for the same process technology node, temperature, and supply voltage. [Table 2]

[0041] Table 2 summarizes the power overhead associated with high-speed Mux-D topologies. This example shows that the high-speed Mux-D and BP high-speed Mux-D incur 21% and 13% cell-level power overheads compared to conventional Mux-D scan flip-flops at 20% data activity. This overhead can be reduced at the block level by sparingly inserting high-speed Mux-D topologies only in critical paths and using conventional Mux-Ds in other non-critical paths. Multi-bit vectorized flip-flops amortize the power overhead associated with separate data and scan clock generation in the high-speed Mux-D across multiple flip-flops, reducing the cell-level power overhead of the high-speed Mux-D. For example, the dual-bit version of the BP high-speed Mux-D incurs only 1% power overhead at 20% data activity compared to conventional Mux-D flip-flops.

[0042] In various embodiments, the inverters can be replaced with logic gates such as NAND gates or NOR gates configured as inverters and can also be used to force a logic output using an enable signal (e.g., power saving mode). Although some embodiments are illustrated with scan-controllable multiplexers, the FFs can be implemented without scan-controllable multiplexers.

[0043] 6 illustrates a vectored high-speed Mux-D scan FF 600 according to some embodiments. In various embodiments, scan control clocks nc2s, nc3s, nc2, and nc3, and input clocks clk and nc1, are provided to "n" FFs (e.g., 4001-400n or 5001-500n). In this case, multiple data inputs d0-dn are vectored to generate outputs q0-qn with shared scannable clock logic 300 / 320.

[0044] FIG. 7 illustrates a smart device, computer system, or SoC (System-on-Chip) having high-speed Mux-D scan flip-flops according to some embodiments of the present disclosure. In some embodiments, device 2500 represents any suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IoT) device, a server, a wearable device, a set-top box, a wireless-enabled electronic reader, etc. It will be understood that certain components are shown generically and that not all components of such a device are shown in apparatus 2500. Any component herein can have high-performance high-speed Mux-D scan flip-flops. For example, any critical timing path can use high-performance high-speed Mux-D scan flip-flops.

[0045] In one embodiment, device 2500 includes a system on a chip (SoC) 2501. An exemplary boundary of SOC 2501 is shown using dotted lines in FIG. 22 and several exemplary components are shown as being contained within SOC 2501; however, SOC 2501 may include any suitable component of device 2500.

[0046] In some embodiments, device 2500 includes a processor 2504. Processor 2504 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, processing core, or other processing means. The processing operations performed by processor 2504 include execution of an operating platform or operating system on which applications and / or device functions execute. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting computing device 2500 to other devices, and / or similar operations. The processing operations may also include operations related to audio I / O and / or display I / O.

[0047] In some embodiments, the processor 2504 includes multiple processing cores (also referred to as cores) 2508a, 2508b, 2508c. Although only three cores 2508a, 2508b, 2508c are illustrated, the processor 2504 may include any other suitable number of processing cores, such as tens or hundreds of processing cores. The processor cores 2508a, 2508b, 2508c may be implemented on a single integrated circuit (IC) chip. Furthermore, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers, or other components.

[0048] In some embodiments, the processor 2504 includes a cache 2506. In one embodiment, sections of the cache 2506 may be dedicated to individual cores 2508 (e.g., a first section of the cache 2506 dedicated to core 2508a, a second section of the cache 2506 dedicated to core 2508b, etc.). In one embodiment, one or more sections of the cache 2506 may be shared between two or more of the cores 2508. The cache 2506 may be divided into different levels, e.g., a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0049] In some embodiments, processor core 2504 may include a fetch unit for retrieving instructions (including instructions with conditional branches) for execution by core 2504. The instructions may be retrieved from any storage device, such as memory 2530. Processor core 2504 may also include a decode unit for decoding the retrieved instructions. For example, the decode unit may decode the retrieved instructions into multiple micro-operations. Processor core 2504 may also include a schedule unit for performing various operations related to storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instruction is ready to be dispatched, e.g., until all source values ​​of the decoded instruction are available. In one embodiment, the schedule unit may schedule and / or issue (or dispatch) the decoded instructions to the execution units for execution.

[0050] The execution units may execute dispatched instructions after the instructions are decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit). In one embodiment, the execution units may include two or more execution units (e.g., an imaging computation unit, a graphics computation unit, a general-purpose computation unit, etc.). The execution units may also perform various arithmetic operations such as addition, subtraction, multiplication, and / or division and may include one or more arithmetic logic units. In one embodiment, a coprocessor (not shown) may perform various arithmetic operations in conjunction with the execution units.

[0051] Additionally, the execution units may execute out-of-order instructions. Thus, processor core 2504, in one embodiment, may be a faulty processor core. Processor core 2504 may include a retirement unit. The retirement unit may retire executed instructions after the instructions have been committed. In one embodiment, retiring an executed instruction may result in the processor state being committed from execution of the instruction, physical registers used by the instruction being deallocated, and so on. Processor core 2504 may also include a bus unit that enables communication between components of processor core 2504 and other components via one or more buses. Processor core 2504 may also include one or more registers that store data accessed by various components of core 2504, such as values ​​related to assigned application priorities and / or subsystem state (mode) associations.

[0052] In some embodiments, device 2500 includes connectivity circuitry 2531. For example, connectivity circuitry 2531 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks) that, for example, enable device 2500 to communicate with external devices. Device 2500 can be isolated from external devices, such as other computing devices, wireless access points, or base stations.

[0053] In one embodiment, the connectivity circuit 2531 may include multiple different types of connectivity. To generalize, the connectivity circuit 2531 may include cellular connectivity circuitry, wireless connectivity circuitry, etc. The cellular connectivity circuitry of the connectivity circuit 2531 generally refers to cellular network connectivity provided by a wireless carrier, such as a GSM (Global System for Mobile Communications) or variants or derivatives, a CDMA (Code Division Multiple Access) or variants or derivatives, a TDM (Time Division Multiplexing) or variants or derivatives, a 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) system or variants or derivatives, a 3GPP Long Term Evolution (LTE) system or variants or derivatives, a 3GPP LTE-Advanced (LTE-A) system or variants or derivatives, a 5th Generation (5G) wireless system or variants or derivatives, a 5G mobile network system or variants or derivatives, a 5G New Radio (NR) system or variants or derivatives, or other cellular service standard. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 2531 refers to non-cellular wireless connections and may include personal area networks (e.g., Bluetooth, near field, etc.), local area networks (e.g., Wi-Fi), and / or wide area networks (e.g., WiMax), and / or other wireless communications. In one embodiment, the connectivity circuitry 2531 may include a network interface, such as a wired or wireless interface, such that a system embodiment may be incorporated into a wireless device, e.g., a mobile phone or personal digital assistant.

[0054] In some embodiments, device 2500 includes a control hub 2532 that represents hardware devices and / or software components related to interaction with one or more I / O devices. For example, processor 2504 may communicate with one or more of a display 2522, one or more peripheral devices 2524, a storage device 2528, one or more other external devices 2529, etc. via control hub 2532. Control hub 2532 may be a chipset, a platform control hub (PCH), and / or the like.

[0055] For example, control hub 2532 represents one or more connection points for additional devices to connect to device 2500, such as through which a user may interact with the system. For example, devices that may be attached to device 2500 (e.g., device 2529) include a microphone device, a speaker or stereo system, an audio device, a video system or other display device, a keyboard or keypad device, or other I / O devices for specific applications, such as a card reader or other device.

[0056] As described above, the control hub 2532 can interact with acoustic devices, the display 2522, and the like. For example, input via a microphone or other acoustic device can provide input or commands for one or more applications or functions of the device 2500. Furthermore, acoustic output can be provided instead of or in addition to a display output. In another example, if the display 2522 includes a touchscreen, the display 2522 also functions as an input device that can be at least partially managed by the control hub 2532. Additional buttons or switches may also be present on the computing device 2500 to provide I / O functionality managed by the control hub 2532. In one embodiment, the control hub 2532 manages devices such as an accelerometer, a camera, a light sensor, or other environmental sensors, or other hardware that can be included in the device 2500. The input can be part of direct user interaction or can provide environmental input to the system to affect system operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash for a camera, or other features).

[0057] In some embodiments, the control hub 2532 may couple to various devices using any suitable communication protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

[0058] In some embodiments, display 2522 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with device 2500. Display 2522 may include a display interface, a display screen, and / or a hardware device used to provide a display to a user. In some embodiments, display 2522 includes a touchscreen (or touchpad) device that provides both output and input to a user. In one embodiment, display 2522 may communicate directly with processor 2504. Display 2522 may be one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In one embodiment, display 2522 may be a head-mounted display, such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0059] In some embodiments, although not shown, in addition to (or instead of) the processor 2504, the device 2500 may include a graphics processing unit (GPU) with one or more graphics processing cores that may control one or more aspects of content display on the display 2522.

[0060] The control hub 2532 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections to the peripheral devices 2524.

[0061] It will be understood that device 2500 may be a peripheral device to other computing devices and may have peripheral devices connected to it. Device 2500 may have a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 2500. In addition, the docking connector allows device 2500 to be connected to certain peripherals that allow computing device 2500 to control content output to, for example, audiovisual or other systems.

[0062] In addition to dedicated docking connectors or other proprietary connection hardware, device 2500 can make peripheral connections through common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), DisplayPort including Firewire, or other types.

[0063] In some embodiments, the connectivity circuitry 2531 may be coupled to a control hub 2532, for example, instead of or in addition to being directly coupled to the processor 2504. In some embodiments, the display 2522 may be coupled to the control hub 2532, for example, instead of or in addition to being directly coupled to the processor 2504.

[0064] In some embodiments, device 2500 includes memory 2530 coupled to processor 2504 via memory interface 2534. Memory 2530 includes memory devices for storing information within device 2500. Memory may include non-volatile memory devices (whose state does not change when power to the memory device is interrupted) and / or volatile memory devices (whose state is indeterminate when power to the memory device is interrupted). Memory device 2530 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with performance suitable for functioning as process memory. In one embodiment, memory 2530 may operate as system memory for device 2500 to store data and instructions used by one or more processors 2504 when executing applications or processes. Memory 2530 may store application data, user data, music, photos, documents, or other data, as well as system data related to the execution of applications and functions of device 2500.

[0065] Elements of various embodiments and examples may also be provided as a machine-readable medium (e.g., memory 2530) for storing computer-executable instructions (e.g., instructions for performing any other process discussed herein). The machine-readable medium (e.g., memory 2530) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that may be transmitted by data signal from a remote computer (e.g., server) to a requesting computer (e.g., client) over a communications link (e.g., modem or network connection).

[0066] In some embodiments, device 2500 includes temperature measurement circuitry 2540 for measuring the temperature of, for example, various components of device 2500. In one embodiment, temperature measurement circuitry 2540 may be embedded in, coupled to, or attached to various components whose temperatures are measured and monitored. For example, temperature measurement circuitry 2540 may measure the temperature of one or more of cores 2508a, 2508b, 2508c, voltage regulator 2514, memory 2530, SOC 2501's motherboard, and / or any suitable component of device 2500.

[0067] In some embodiments, device 2500 includes power measurement circuitry 2542, for example, to measure power consumed by one or more components of device 2500. In one embodiment, in addition to or instead of measuring power, power measurement circuitry 2542 may measure voltage and / or current. In one embodiment, power measurement circuitry 2542 may be embedded in, coupled to, or attached to various components whose power, voltage, and / or current consumption is measured and monitored. For example, power measurement circuitry 2542 may measure power, current, and / or voltage supplied by one or more voltage regulators 2514, power supplied to SOC 2501, power supplied to device 2500, power consumed by processor 2504 (or any other component) of device 2500, etc.

[0068] In some embodiments, device 2500 includes one or more voltage regulator circuits, generally referred to as voltage regulators (VRs) 2514VR, which have high-bandwidth and low-power differential-to-single-ended Type III compensators. VR 2514 generates signals at appropriate voltage levels that can be supplied to operate any appropriate components of device 2500. By way of example only, VR 2514 is shown providing signals to processor 2504 of device 2500. In some embodiments, VR 2514 receives one or more voltage identification (VID) signals and generates voltage signals at appropriate levels based on the VID signals. Various types of VRs may be utilized for VR 2514. For example, VR 2514 may include a “buck” VR, a “boost” VR, a combination buck VR and boost VR, a low-dropout (LDO) regulator, a switching DC-DC regulator, etc. Buck VRs are commonly used in power delivery applications that require an input voltage to be converted to an output voltage at a ratio less than unity. Boost VRs are commonly used in power delivery applications that require an input voltage to be converted to an output voltage at a ratio greater than one. In some embodiments, each processor core has its own VR controlled by the PCU 2510a / b and / or the PMIC 2512. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital LDOs, analog LDOs, or a combination of digital and analog LDOs. The VR is an adaptive VR that can provide an adaptive voltage output, as described in connection with various embodiments.

[0069] In some embodiments, device 2500 includes one or more clock generator circuits, generally referred to as clock generators 2516. Clock generator 2516 generates clock signals at appropriate frequency levels that may be provided to any appropriate components of device 2500. By way of example only, clock generator 2516 is shown providing clock signals to processor 2504 of device 2500. In some embodiments, clock generator 2516 receives one or more frequency identification (FID) signals and generates clock signals at appropriate frequencies based on the FID signals. Clock generator 2516 is an adaptive clock source that may provide adaptive frequency outputs, as described in connection with various embodiments.

[0070] In some embodiments, device 2500 includes a battery 2518 that powers various components of device 2500. By way of example only, battery 2518 is shown powering processor 2504. Although not shown in the figures, device 2500 may include charging circuitry for, for example, recharging the battery based on alternating current (AC) power received from an AC adapter.

[0071] In some embodiments, device 2500 includes a power control unit (PCU) 2510 (also referred to as a power management unit (PMU), power controller, etc.). In one embodiment, some sections of PCU 2510 may be implemented by one or more processing cores 2508, and these sections of PCU 2510 are symbolically shown using dotted boxes and labeled PCU 2510a. In one embodiment, some other sections of PCU 2510 may be implemented outside of processing cores 2508, and these sections of PCU 2510 are symbolically shown using dotted boxes and labeled as PCU 2510b. PCU 2510 may perform various power management operations for device 2500. PCU 2510 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) and may perform various power management operations for device 2500.

[0072] In some embodiments, device 2500 includes a power management integrated circuit (PMIC) 2512, for example, to perform various power management operations for device 2500. In some embodiments, PMIC 2512 is a reconfigurable power management IC (RPMIC) and / or an Intel® Mobile Voltage Positioning (IMVP) chip. In one embodiment, the PMIC is in an IC chip separate from processor 2504. The PMIC 2512 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to perform various power management operations for device 2500.

[0073] In one embodiment, device 2500 includes one or both of PCU 2510 or PMIC 2512. In one embodiment, either one of PCU 2510 or PMIC 2512 may not be present in device 2500, and therefore these components are illustrated using dashed lines.

[0074] Various power management operations of device 2500 may be performed by PCU 2510, by PMIC 2512, or by a combination of PCU 2510 and PMIC 2512. For example, PCU 2510 and / or PMIC 2512 may select a power state (e.g., a P-state) for various components of device 2500. For example, PCU 2510 and / or PMIC 2512 may select a power state (e.g., in accordance with the Advanced Configuration and Power Interface (ACPI) specification) for various components of device 2500. By way of example only, PCU 2510 and / or PMIC 2512 may transition various components of device 2500 into a sleep state, an active state, an appropriate C-state (e.g., a C0 state or other appropriate C-state in accordance with the ACPI specification). In one embodiment, the PCU 2510 and / or the PMIC 2512 can control the voltage output by the VR 2514 (e.g., SCVR) and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or an FID signal, respectively. In one embodiment, the PCU 2510 and / or the PMIC 2512 may control features related to battery power usage, charging of the battery 2518, and power saving operation.

[0075] The clock generator 2516 may include a phase-locked loop (PLL), a frequency-locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 2504 has its own clock source. Thus, each core can operate at a frequency independent of the operating frequencies of the other cores. In some embodiments, the PCU 2510 and / or PMIC 2512 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core may be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 2510 and / or PMIC 2512 determines the operating state of each core of the processor and, when the PCU 2510 and / or PMIC 2512 determines that a core is operating below its target performance level, appropriately mechanically adjusts the frequency and / or power supply voltage of that core without the core clock source (e.g., that core's PLL) losing lock. For example, if a core draws less current from the power supply rails than the total current allocated for that core or processor 2504, the PCU 2510 and / or PMIC 2512 may temporarily increase the power draw for that core or processor 2504 (e.g., by increasing the clock frequency and / or power supply voltage level) so that the core or processor 2504 can operate at a higher performance level. Thus, the voltage and / or frequency can be temporarily increased for the processor 2504 without compromising product reliability.

[0076] In one embodiment, the PCU 2510 and / or the PMIC 2512 may perform power management operations based, at least in part, on receiving measurements from, for example, the power measurement circuit 2542, the temperature measurement circuit 2540, the charge level of the battery 2518, and / or any other suitable information that may be used for power management. To that end, the PMIC 2512 is communicatively coupled to one or more sensors to sense / detect various values / fluctuations in one or more factors that affect the power / thermal behavior of the system / platform. Examples of the one or more factors include current, voltage sag, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be located in physical proximity to (and / or in thermal contact / coupled with) one or more components or logic / IP blocks of the computer system. Additionally, in at least one embodiment, the sensors may be directly connected to the PCU2510 and / or PMIC2512 to enable the PCU2510 and / or PMIC2512 to manage processor core energy based, at least in part, on the values ​​detected by one or more sensors.

[0077] Also shown is an example software stack for device 2500 (although not all elements of the software stack are shown). By way of example only, processor 2504 may execute application program 2550, operating system 2552, one or more power management (PM)-specific application programs (e.g., commonly referred to as PM applications 2558), and / or similar programs. PM applications 2558 may also be executed by PCU 2510 and / or PMIC 2512. OS 2552 may also include one or more PM applications 2556a, 2556b, 2556c. OS 2552 may also include various drivers 2554a, 2554b, 2554c, etc., some of which may be specific for power management purposes. In some embodiments, device 2500 may further include basic input / output system (BIOS) 2520. BIOS 2520 may communicate with OS 2552 (e.g., via one or more drivers 2554) and with processor 2504.

[0078] For example, one or more of PM applications 2558, 2556, drivers 2554, BIOS 2520, etc. may be used to implement power management specific tasks, such as, for example, controlling the voltage and / or frequency of various components of device 2500, controlling the wake-up state, sleep state, and / or other appropriate power state of various components of device 2500, controlling battery power usage, charging battery 2518, functions related to power saving operations, etc.

[0079] References herein to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but not necessarily in all embodiments. Various aspects of "an embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. When the specification describes a component, feature, structure, or characteristic as "may include," "might include," or "potentially include," that particular component, feature, structure, or characteristic need not be included. When the specification or claims refer to "an" element, it does not exclude the presence of only one of that element. When the specification or claims refer to "additional" elements, it does not exclude the presence of one or more of the additional elements.

[0080] Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0081] While the present disclosure has been described in relation to specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. It is intended that the embodiments of the present disclosure encompass all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0082] Furthermore, for ease of explanation and discussion, and to avoid obscuring the disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings. Furthermore, devices may be shown in block diagram form to avoid obscuring the disclosure and in recognition of the fact that details regarding the implementation of such block diagram devices will vary greatly depending on the platform on which the disclosure is implemented (i.e., such details should be well within the purview of one skilled in the art). Where specific details (e.g., circuits) are described to illustrate exemplary embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without these specific details or with variations thereof. Accordingly, the description herein is therefore to be regarded as illustrative and not limiting.

[0083] The following examples are provided to illustrate various embodiments, and these examples may depend on one another in any suitable way.

[0084] Example 1: a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input via a transmission gate coupled to the memory circuit; a slave latch coupled to the master latch.

[0085] Example 2: The device of Example 1, a first inverter for receiving input data; a second inverter coupled in series with the first inverter, the second inverter coupled to the transmission gate;

[0086] Example 3: The device of Example 1, The memory circuit is a first tristable inverter having an input coupled to the transmission gate; a second tristable inverter having an input coupled to the scan path and the output of the first tristable inverter, the output of the tristable inverter coupled to the transmission gate.

[0087] Example 4: The apparatus of Example 3, the transmission gate is a first transmission gate; The slave latch is coupled to the master latch through an inverter, The slave latch has a second transmission gate coupled to the output of the inverter.

[0088] Example 5: The apparatus of Example 4, the memory circuit is a first memory circuit; The slave latch has a second memory circuit coupled to a second transmission gate.

[0089] Example 6: The apparatus of Example 4, The scan path comprises a tristable inverter having an input coupled to the scan input and an output coupled to the input of a second tristable inverter.

[0090] Example 7: The apparatus of Example 6, a circuit for generating a scan select based on a gated clock derived from an input clock; Scan select based on gate clock is Controls the first transmission gate, controlling the first tri-stable inverter and the second tri-stable inverter of the memory circuit; Controlling the Tri-state Inverter of the Scan Path This is for the purpose.

[0091] Example 8: 7. The apparatus of Example 6, wherein the circuit comprises: an inverter having an input and an output coupled to the input clock; an AND logic coupled to the output of the inverter, the AND logic being for receiving a scan select signal as an input; and OR logic coupled to the input of the inverter, the OR logic being for receiving a scan select signal as an input.

[0092] Example 9: The device of Example 1, The data input is received directly by the transmission gate without any intervening buffers or inverters.

[0093] Example 10: a circuit for generating a scan select based on a gated clock derived from an input clock; a vectoring flip-flop circuit for receiving a scan select based on a gated clock from the circuit; The flip-flops in the vectored flip-flop circuit are: a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input via a transmission gate coupled to the memory circuit; a slave latch coupled to the master latch.

[0094] Example 11: 11. The apparatus of Example 10, The flip-flops in the vectored flip-flop circuit are: a first inverter for receiving input data; a second inverter coupled in series with the first inverter, the second inverter coupled to the transmission gate.

[0095] Example 12: 11. The apparatus of Example 10, The memory circuit is a first tristable inverter having an input coupled to the transmission gate; a second tristable inverter having an input coupled to the scan path and the first output, the output of the second tristable inverter coupled to the transmission gate.

[0096] Example 13: 13. The apparatus of Example 12, the transmission gate is a first transmission gate; The slave latch is coupled to the master latch through an inverter, The slave latch has a second transmission gate coupled to the output of the inverter.

[0097] Example 14: 14. The apparatus of Example 13, the memory circuit is a first memory circuit; The slave latch has a second memory circuit coupled to a second transmission gate.

[0098] Example 15: 14. The apparatus of Example 13, The scan path comprises a tristable inverter having an input coupled to the scan input and an output coupled to the input of a second tristable inverter.

[0099] Example 16: 16. The apparatus of Example 15, Scan select based on gate clock is Controls the first transmission gate, controlling the first tri-stable inverter and the second tri-stable inverter of the memory circuit; Controlling the Tri-state Inverter of the Scan Path This is for the purpose.

[0100] Example 17: 16. The apparatus of claim 15, wherein the circuitry comprises: an inverter having an input and an output coupled to the input clock; an AND logic coupled to the output of the inverter, the AND logic being for receiving a scan select signal as an input; and OR logic coupled to the input of the inverter, the OR logic being for receiving a scan select signal as an input.

[0101] Example 18: 11. The apparatus of Example 10, The data input is received directly by the transmission gate without the intervention of a buffer or inverter; Scan select based on gate clock is Controls the first transmission gate, controlling the first tri-stable inverter and the second tri-stable inverter of the memory circuit; Controlling the Tri-state Inverter of the Scan Path This is for the purpose.

[0102] Example 19: 1. A system comprising: Memory and a processor coupled to the memory, The processor has a critical timing path that includes a flip-flop; Flip-flops are a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input via a transmission gate coupled to the memory circuit; a slave latch coupled to the master latch; and a wireless interface that allows the processor to communicate with other devices.

[0103] Example 20: 20. The system of Example 19, a first inverter for receiving input data; a second inverter coupled in series with the first inverter, the second inverter coupled to the transmission gate.

[0104] An abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. The following claims are incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. 1. An apparatus for sampling data, said apparatus comprising: a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input via a transmission gate coupled to the memory circuit connected to an input terminal of the second data path; a slave latch coupled to the master latch; a circuit for generating a scan select based on a gated clock derived from an input clock and providing the scan select to the master latch based on the gated clock; The circuit comprises: an inverter having an input and an output coupled to the input clock; an AND logic having the output of the inverter coupled to an input thereof, the AND logic being for receiving a scan select signal as an input; OR logic coupled to the input of the inverter and to the output of the inverter, the OR logic for receiving the scan select signal as an input; Equipped with the OR logic comprises a p-type transistor, two n-type transistors, and another inverter, the emitter of the p-type transistor is connected to the output of the inverter, the collector of the p-type transistor, the collectors of the two n-type transistors, and the input of the other inverter are connected together, the emitters of the two n-type transistors are connected to ground, the scan select signal is connected to a gate of the p-type transistor and a gate of one of the two n-type transistors, and an input clock is connected to a gate of the other of the two n-type transistors.

2. a first inverter for receiving input data; a second inverter coupled in series with the first inverter, the second inverter being coupled to the transmission gate; The apparatus of claim 1 , comprising:

3. The memory circuit a first tristable inverter having an input coupled to said transmission gate; a second tristable inverter having an input coupled to the scan path and an output of the first tristable inverter, the output of the second tristable inverter being coupled to the transmission gate; The apparatus of claim 1 , comprising:

4. the transmission gate is a first transmission gate, the slave latch is coupled to the master latch through an inverter; the slave latch having a second transmission gate coupled to the output of the inverter; 4. The apparatus of claim 3.

5. the memory circuit is a first memory circuit; the slave latch having a second memory circuit coupled to the second transmission gate; 5. The apparatus of claim 4.

6. the scan path includes a third tristable inverter having an output coupled to the input of the second tristable inverter and an input coupled to a scan input; 5. The apparatus of claim 4.

7. The scan select based on the gated clock is Controlling the first transmission gate; controlling a first tristable inverter and a second tristable inverter of the memory circuit; Controlling the third tristable inverter of the scan path It is for the purpose of 7. The apparatus of claim 6.

8. The data input is received directly by the transmission gate without the intervening buffer or inverter.

10. The apparatus of claim 1.

9. 1. An apparatus for sampling data, said apparatus comprising: a circuit for generating a scan select based on a gated clock derived from an input clock; a vectoring flip-flop circuit for receiving a scan select based on a gated clock from said circuit; Equipped with The flip-flops of the vectored flip-flop circuit are: a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input via a transmission gate coupled to the memory circuit connected to an input terminal of the second data path; a slave latch coupled to the master latch, The memory circuit a first tristable inverter having an input coupled to said transmission gate; a second tristable inverter having an input coupled to the scan path and an output of the first tristable inverter, the output of the second tristable inverter being coupled to the transmission gate; the scan path comprises a third tristable inverter having an input coupled to a scan input and an output coupled to an input of the second tristable inverter; The circuit comprises: an inverter having an input and an output coupled to the input clock; an AND logic having the output of the inverter coupled to an input thereof, the AND logic being for receiving a scan select signal as an input; OR logic coupled to the input of the inverter and to the output of the inverter, the OR logic being for receiving the scan select signal as an input; the OR logic comprises a p-type transistor, two n-type transistors, and another inverter, the emitter of the p-type transistor is connected to the output of the inverter, the collector of the p-type transistor, the collectors of the two n-type transistors, and the input of the other inverter are connected together, the emitters of the two n-type transistors are connected to ground, the scan select signal is connected to a gate of the p-type transistor and a gate of one of the two n-type transistors, and an input clock is connected to a gate of the other of the two n-type transistors.

10. The flip-flops of the vectored flip-flop circuit are a first inverter for receiving input data; a second inverter coupled in series with the first inverter, the second inverter coupled to the transmission gate; 10. The apparatus of claim 9.

11. the transmission gate is a first transmission gate, the slave latch is coupled to the master latch through an inverter; the slave latch having a second transmission gate coupled to the output of the inverter; 11. The apparatus of claim 10.

12. the memory circuit is a first memory circuit; the slave latch having a second memory circuit coupled to the second transmission gate; 12. The apparatus of claim 11.

13. The scan select based on the gated clock is Controlling the first transmission gate; controlling the first tristable inverter and the second tristable inverter of the memory circuit; Controlling the third tristable inverter of the scan path It is for the purpose of 12. The apparatus of claim 11.

14. the data input is received directly by said transmission gate without an intervening buffer or inverter; The scan select based on the gated clock is Controlling the transmission gate; controlling a first tristable inverter and a second tristable inverter of the memory circuit; Controlling the third tristable inverter of the scan path It is for the purpose of 10. The apparatus of claim 9.

15. Memory and a processor coupled to the memory, the processor including a critical timing path including a flip-flop; a wireless interface that enables the processor to communicate with other devices; Equipped with The flip-flop is a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input via a transmission gate coupled to the memory circuit connected to an input terminal of the second data path; a slave latch coupled to the master latch; a circuit for generating a scan select based on a gated clock derived from an input clock and providing the scan select to the master latch based on the gated clock; The circuit comprises: an inverter having an input and an output coupled to the input clock; an AND logic having the output of the inverter coupled to an input thereof, the AND logic being for receiving a scan select signal as an input; OR logic coupled to the input of the inverter and to the output of the inverter, the OR logic for receiving the scan select signal as an input; Equipped with the OR logic comprises a p-type transistor, two n-type transistors, and another inverter, the emitter of the p-type transistor is connected to the output of the inverter, the collector of the p-type transistor, the collectors of the two n-type transistors, and an input of the other inverter are connected together, the emitters of the two n-type transistors are connected to ground, the scan select signal is connected to a gate of the p-type transistor and a gate of one of the two n-type transistors, and an input clock is connected to a gate of the other of the two n-type transistors.

16. a first inverter for receiving input data; a second inverter coupled in series with the first inverter, the second inverter being coupled to the transmission gate; 16. The system of claim 15, comprising:

17. The memory circuit a first tristable inverter having an input coupled to said transmission gate; a second tristable inverter having an input coupled to the scan path and an output of the first tristable inverter, the output of the second tristable inverter being coupled to the transmission gate; The system of claim 15, comprising:

18. the transmission gate is a first transmission gate, the slave latch is coupled to the master latch through an inverter; the slave latch having a second transmission gate coupled to the output of the inverter; 18. The system of claim 17.

19. the scan path includes a third tristable inverter having an output coupled to the input of the second tristable inverter and an input coupled to a scan input; 20. The system of claim 18.

20. The scan select based on the gated clock is Controlling the first transmission gate; controlling a first tristable inverter and a second tristable inverter of the memory circuit; Controlling the third tristable inverter of the scan path It is for the purpose of 20. The system of claim 19.

21. 21. A method for sampling data using an apparatus according to any one of claims 1 to 14 or a system according to any one of claims 15 to 20, comprising: providing a master latch having a first data path and a second data path, the first data path having a scan path input to a memory circuit of the master latch, and the second data path being a non-scan path input to the second data path via a transmission gate; coupling the transmission gate to the memory circuit; connecting a slave latch to the master latch. method.

22. receiving input data by a first inverter; coupling a second inverter in series with the first inverter; coupling the second inverter to the transmission gate; 22. The method of claim 21, comprising:

23. The memory circuit a first tristable inverter having an input coupled to said transmission gate; a second tristable inverter having an input coupled to said scan path and an output of said first tristable inverter, the output of said second tristable inverter being coupled to said transmission gate; 22. The method of claim 21.

24. the transmission gate is a first transmission gate, The method comprises: coupling the slave latch to the master latch through an inverter, the slave latch having a second transmission gate coupled to an output of the inverter; 24. The method of claim 23.

25. the memory circuit is a first memory circuit; the slave latch having a second memory circuit coupled to the second transmission gate; 25. The method of claim 24.

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