Electro-optical device and display device

Abstract

To provide an electro-optical device that can prevent a trouble such as display unevenness.SOLUTION: An electro-optical device comprises: a scan line 13 that is provided between a substrate 10a and a TFT 301 and a TFT 302; common wiring 18; a pixel electrode 111; a third relay electrode 831 that has an overhang part 831a overlapping the scan line 13 in plan view and projecting from the scan line 13, and electrically connects the TFT 301 and the pixel electrode 111 to each other; a capacitive element 602 that is provided between the substrate 10a and the scan line 13, and overlaps the TFT 302 in plan view; and a second relay electrode 822 that has an overhang part 822a overlapping the scan line 13 in plan view and projecting from the scan line 13, and electrically connects the capacitive element 602 and the common wiring 18 to each other. A contact hole C201 electrically connecting the pixel electrode 111 and the third relay electrode 831 to each other overlaps a contact hole C42 electrically connecting the capacitive element 602 and the second relay electrode 822 to each other in plan view.SELECTED DRAWING: Figure 5C

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and a display device including the electro-optical device. [Background technology]

[0002] Conventionally, as shown in Patent Document 1, an electro-optical device has been disclosed that includes a thin film transistor (hereinafter referred to as TFT) as a pixel switching element, a scanning line disposed between the TFT and a substrate and also serving as a light-shielding film for the TFT, and a storage capacitor having a laminated structure disposed between the scanning line and the substrate. In the storage capacitor of Patent Document 1, one of the capacitance electrodes also serves as a common wiring. That is, the first conductive layer serving as one of the capacitance electrodes has a portion arranged in a grid pattern in the display area and a portion drawn out to the outside of the display area, and a common potential is supplied to the portion drawn out to the outside of the display area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-38248 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the device described in Patent Document 1 had the problem that if the resistance value of the first conductive layer, which is one of the capacitance electrodes, becomes high due to factors such as the film thickness, wiring dimensions, and film quality of the first conductive layer, the potential of one of the capacitance electrodes becomes more susceptible to fluctuations due to the influence of other signal lines, making it more likely that problems such as uneven display will occur. Furthermore, if the first conductive layer is made thicker to reduce its resistance, the thickness of the light-transmitting region also increases, which can lead to a decrease in transmittance. [Means for solving the problem]

[0005] An electro-optical device according to one embodiment of the present application comprises a substrate, a first transistor, a second transistor adjacent to the first transistor in a first direction, a light-shielding member provided along the first direction between the substrate and the first transistor and between the substrate and the second transistor, a capacitance wiring, a pixel electrode provided corresponding to the first transistor, a first conductive member that overlaps the light-shielding member in a planar view and has a first protrusion protruding from the light-shielding member, electrically connecting the first transistor and the pixel electrode, a capacitance element provided between the substrate and the light-shielding member and overlaps with the second transistor in a planar view, and a second conductive member that overlaps the light-shielding member in a planar view and has a second protrusion protruding from the light-shielding member, electrically connecting the capacitance element and the capacitance wiring, and a first contact hole for electrically connecting the pixel electrode and the first conductive member overlaps with a second contact hole for electrically connecting the capacitance element and the second conductive member in a planar view.

[0006] An electro-optical device according to one embodiment of the present application comprises a substrate, a transistor, a light-shielding member arranged along a first direction between the substrate and the transistor, a capacitance wiring, a pixel electrode arranged corresponding to the transistor, a first conductive member that overlaps the light-shielding member in a planar view and has a first protrusion protruding from the light-shielding member, electrically connecting the transistor and the pixel electrode, a capacitance element arranged between the substrate and the light-shielding member, and a second conductive member that overlaps the light-shielding member in a planar view and has a second protrusion protruding from the light-shielding member, electrically connecting the capacitance element and the capacitance wiring, and a first contact hole for electrically connecting the pixel electrode and the first conductive member overlaps with a second contact hole for electrically connecting the capacitance element and the second conductive member.

[0007] A display device according to one aspect of the present application includes the electro-optical device described above. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of a liquid crystal device according to a first embodiment. [Figure 2] 2 is a schematic cross-sectional view taken along line AA in FIG. 1. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device. [Figure 4] FIG. [Figure 5A] 5 is a cross-sectional view taken along line YY in FIG. 4. [Figure 5B] 5 is a cross-sectional view taken along line S1-S1 in FIG. 4. [Figure 5C] 5 is a cross-sectional view taken along line S2-S2 in FIG. 4. [Figure 6] FIG. 4 is a flowchart of a manufacturing process for an element substrate. [Figure 7] 10A and 10B are plan views showing pixel states in a trench formation step of an element substrate. [Figure 8A] 8 is a cross-sectional view taken along line YY in FIG. 7. [Figure 8B] FIG. 8 is a cross-sectional view taken along line XX in FIG. [Figure 9] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 10A] 10 is a cross-sectional view taken along line YY in FIG. 9. [Figure 10B] FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. [Figure 11] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 12A] 12 is a cross-sectional view taken along line YY in FIG. 11 . [Figure 12B] FIG. 12 is a cross-sectional view taken along line XX in FIG. [Figure 12C] 12 is a cross-sectional view taken along line ZZ in FIG. 11 . [Figure 13] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 14A] 14 is a cross-sectional view taken along line YY in FIG. 13. [Figure 14B] FIG. 14 is a cross-sectional view taken along line XX in FIG. 13. [Figure 15] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 16A] 16 is a cross-sectional view taken along line YY in FIG. 15. [Figure 16B] FIG. 16 is a cross-sectional view taken along line XX in FIG. [Figure 17] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 18A] 18 is a cross-sectional view taken along line YY in FIG. 17. [Figure 18B] 18 is a cross-sectional view taken along line XX in FIG. 17. [Figure 18C] 18 is a cross-sectional view taken along line ZZ in FIG. 17. [Figure 19] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 20A] 19A and 19B are cross-sectional views taken along line YY in FIG. [Figure 20B] FIG. 20 is a cross-sectional view taken along line XX in FIG. 19. [Figure 20C] 20 is a cross-sectional view taken along line ZZ in FIG. 19. [Figure 21] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 22A] 22 is a cross-sectional view taken along line YY in FIG. 21. [Figure 22B] 22 is a cross-sectional view taken along line XX in FIG. 21. [Figure 23] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 24A] 24 is a cross-sectional view taken along line YY in FIG. 23. [Figure 24B] 24 is a cross-sectional view taken along line XX in FIG. 23. [Figure 25] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 26A] 26 is a cross-sectional view taken along line YY in FIG. 25. [Figure 26B] 26 is a cross-sectional view taken along line XX in FIG. 25. [Figure 26C] 26 is a cross-sectional view taken along line ZZ in FIG. 25. [Figure 27] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 28] FIG. 10 is a schematic configuration diagram of a projection display device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following drawings, the scale of each component is different from the actual scale in order to make each component large enough to be recognizable. In addition, in each figure, three mutually orthogonal axes, the X-axis, the Y-axis, and the Z-axis, are illustrated as necessary. Furthermore, a direction along the X-axis is referred to as the X1 direction, and a direction opposite to the X1 direction is referred to as the X2 direction. Similarly, a direction along the Y-axis is referred to as the Y1 direction, and a direction opposite to the Y1 direction is referred to as the Y2 direction. A direction along the Z-axis is referred to as the Z1 direction, and a direction opposite to the Z1 direction is referred to as the Z2 direction. Furthermore, a plane including the X-axis and the Y-axis is also referred to as the "XY plane," and viewing the XY plane in the Z1 or Z2 direction is referred to as a "planar view" or "planar," and viewing a cross section including the Z-axis from a direction perpendicular to the cross section is referred to as a "sectional view" or "sectional."

[0010] Furthermore, in the following description, for example, the expression "on the substrate" with respect to a substrate means that the substrate is placed in contact with the substrate, that the substrate is placed via an element such as another structure, or that a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed via another element. In addition, in the following description, materials and film thicknesses of elements used in the electro-optical device may be described, but these are merely examples and do not limit the materials or film thicknesses unless otherwise specified.

[0011] 1. Embodiment 1 In this embodiment, an active-drive liquid crystal device having a TFT for each pixel will be described as an example of an electro-optical device. This liquid crystal device can be suitably used as an optical modulation device in a projection display device, which will be described later.

[0012] 1.1. Overview of the structure of liquid crystal devices The structure of a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic plan view showing the configuration of a transmissive liquid crystal device as an electro-optical device according to embodiment 1. Fig. 2 is a schematic cross-sectional view showing the structure of the liquid crystal device taken along line AA in Fig. 1.

[0013] As shown in Figures 1 and 2, the liquid crystal device 100 of this embodiment has an element substrate 10, an opposing substrate 20 arranged opposite the element substrate 10, and a liquid crystal layer 5 as an electro-optical layer sandwiched between the element substrate 10 and the opposing substrate 20.

[0014] The substrate 10a of the element substrate 10 is, for example, a glass substrate, a quartz substrate, etc. The substrate 20a of the counter substrate 20 is, for example, a transparent substrate such as a glass substrate, a quartz substrate, etc.

[0015] The element substrate 10 is larger in size than the counter substrate 20 in a plan view. The element substrate 10 and the counter substrate 20 are joined via a sealant 6 arranged along the outer edge of the counter substrate 20. A liquid crystal having positive or negative dielectric anisotropy is sealed in the gap between the element substrate 10 and the counter substrate 20 to provide a liquid crystal layer 5.

[0016] A display area E including a plurality of pixels P arranged in a matrix is ​​provided inside the sealing material 6. Outside the display area E is a peripheral area F. In the peripheral area F, a parting portion 23 made of a light-blocking material is provided along the outer edge of the display area E between the sealing material 6 and the display area E. Furthermore, dummy pixels (not shown) that do not contribute to display are provided at positions overlapping the parting portion 23 in plan view.

[0017] A terminal section in which a plurality of external connection terminals 43 are arranged is provided in the peripheral region F of the element substrate 10. In the peripheral region F, a data line driving circuit 47 is provided between a first side section along the terminal section and the sealing material 6. In addition, in the peripheral region F, an inspection circuit 41 is provided between the sealing material 6 and the display region E along a second side section opposite the first side section.

[0018] In the peripheral region F, a scanning line driving circuit 45 is provided between the sealant 6 along the third and fourth sides that are perpendicular to the first side and face each other and the display region E. In addition, a plurality of wirings 49 that connect the two scanning line driving circuits 45 are provided between the sealant 6 on the second side and the inspection circuit 41.

[0019] Wiring 49 connected to the data line driving circuit 47 and scanning line driving circuit 45 is connected to a plurality of external connection terminals 43 arranged along the first side portion. Note that the arrangement of the inspection circuit 41 is not limited to the above. Here, in this specification, the direction along the first side of the substrate 10a, that is, the X1 direction along the X axis, corresponds to the first direction.

[0020] 2, on the surface of the substrate 10a facing the liquid crystal layer 5, there are provided light-transmitting pixel electrodes 11 and TFTs 30 provided for each pixel P, wiring 49, and an alignment film 12 covering these. The TFTs 30 and pixel electrodes 11 are components of a pixel P. The element substrate 10 includes the substrate 10a, the pixel electrodes 11, TFTs 30, wiring 49, and alignment film 12 provided on the substrate 10a.

[0021] On the surface of the substrate 20a facing the liquid crystal layer 5, there are provided a parting portion 23, an insulating layer 25 formed to cover the parting portion 23, a counter electrode 21 serving as a common electrode provided to cover the insulating layer 25, and an alignment film 22 covering the counter electrode 21. The counter substrate 20 in this embodiment includes at least the parting portion 23, the counter electrode 21, and the alignment film 22. Note that, although this embodiment shows an example in which the common electrode is provided on the counter substrate 20 side as the counter electrode 21, the common electrode may also be provided on the element substrate 10 side.

[0022] 1, the scanning line driving circuit 45 and the inspection circuit 41 overlap the parting portion 23 in plan view. The parting portion 23 blocks light L from a laser light source (not shown) that is incident from the counter substrate 20 side, preventing it from entering peripheral circuits such as the scanning line driving circuit 45, thereby preventing malfunction of the peripheral circuits.

[0023] The insulating layer 25 is made of an inorganic material such as silicon oxide (SiO2) that has optical transparency. The insulating layer 25 is provided so as to cover the parting portion 23 and to make the surface on the liquid crystal layer 5 side flat.

[0024] The counter electrode 21 covers the insulating layer 25 and is electrically connected to vertical conductive parts 7 provided at the four corners of the counter substrate 20. The vertical conductive parts 7 are electrically connected to common wiring 18 as capacitance wiring (described later) on the element substrate 10 side.

[0025] The pixel electrode 11 and the counter electrode 21 are made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment films 12 and 22 are selected based on the optical design of the liquid crystal device 100. Materials for forming the alignment films 12 and 22 include inorganic alignment films such as silicon oxide and organic alignment films such as polyimide.

[0026] Such a liquid crystal device 100 employs an optical design of a normally white mode in which the light transmittance of pixel P when no voltage is applied is greater than the transmittance when voltage is applied, or a normally black mode in which the light transmittance of pixel P when no voltage is applied is less than the transmittance when voltage is applied. In the liquid crystal device 100, polarizing elements are arranged on both the light incident side and the light exit side according to the optical design.

[0027] In the present embodiment, an example will be described in which the above-mentioned inorganic alignment film is used as the alignment films 12 and 22, and liquid crystal having negative dielectric anisotropy is used as the liquid crystal layer 5, and an optical design of normally black mode is applied.

[0028] 1.2. Overview of the electrical configuration of the liquid crystal device Next, the electrical configuration of the liquid crystal device 100 will be described with reference to Fig. 3. Fig. 3 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device.

[0029] As shown in Fig. 3, the liquid crystal device 100 has scanning lines 13, data lines 16, and common wiring 18 as light-blocking members on a substrate 10a of an element substrate 10. The scanning lines 13 extend in the X1 direction, which is a first direction. The data lines 16 and common wiring 18 extend in the Y1 direction. Note that, although Fig. 3 shows the common wiring 18 extending along the Y1 direction, this is not limiting.

[0030] The area defined by the scanning lines 13 and the data lines 16 is a pixel P. In the pixel P, a pixel electrode 11, a TFT 30, and a capacitance element 60 are provided. The scanning lines 13 are electrically connected to the gate electrodes of the TFTs 30, and the data lines 16 are electrically connected to the sources of the TFTs 30. The scanning lines 13 have the function of simultaneously controlling the on / off of the TFTs 30 arranged in the same row. The pixel electrodes 11 are electrically connected to the drains of the TFTs 30.

[0031] The data lines 16 are electrically connected to a data line driving circuit 47, and supply image signals D1, D2, ..., Dn supplied from the data line driving circuit 47 to the pixels P. The scanning lines 13 are electrically connected to a scanning line driving circuit 45, and supply scanning signals SC1, SC2, ..., SCm supplied from the scanning line driving circuit 45 to each pixel P.

[0032] The image signals D1 to Dn supplied from the data line driving circuit 47 to the data lines 16 may be supplied line-sequentially in this order, or may be supplied in groups to adjacent data lines 16. The scanning line driving circuit 45 supplies scanning signals SC1 to SCm to the scanning lines 13 line-sequentially at a predetermined timing.

[0033] When a scanning signal SC1 is input to the TFT 30, the TFT 30 is turned on for a certain period of time. As a result, an image signal D1 supplied from the data line 16 is written to the pixel electrode 11 at a predetermined timing. The image signal D1 of a predetermined level written to the liquid crystal layer 5 via the pixel electrode 11 is held for a certain period of time between the pixel electrode 11 and the counter electrode 21 disposed opposite the pixel electrode 11 with the liquid crystal layer 5 interposed therebetween.

[0034] In order to prevent leakage of the held image signal D1, a capacitive element 60 is electrically connected to a liquid crystal capacitance provided between the pixel electrode 11 and the counter electrode 21. One electrode of the capacitive element 60 is electrically connected to a common wiring 18 to which a constant common potential is applied, and the other electrode of the capacitive element 60 is electrically connected to the drain of the TFT 30 and the pixel electrode 11.

[0035] 3, an inspection circuit 41 is connected to the data lines 16. Therefore, during the manufacturing process of the liquid crystal device 100, it is possible to detect the image signals D1, D2, ..., Dn and check for operational defects of the liquid crystal device 100.

[0036] 1.3.Outline of the device substrate configuration Next, the planar and cross-sectional configurations of the pixel P on the element substrate 10 will be described with reference to FIGS. 4, 5A, 5B, and 5C. FIG. 4 is a plan view of the pixel, showing a cut-out region E1, which is part of the display region E in FIG. 1. FIG. 5A is a cross-sectional view taken along line YY in FIG. 4, FIG. 5B is a cross-sectional view taken along line S1-S1 in FIG. 4, and FIG. 5C is a cross-sectional view taken along line S2-S2 in FIG. 4. Also, the alignment film 12 is not shown in FIGS. 5A, 5B, and 5C.

[0037] 4, the light-shielding region SD indicated by the dashed line is provided in a grid pattern surrounding the light-transmitting region of the pixel P. Of the light-shielding region SD, the portion extending along the X axis is mainly shielded from light by the scanning line 13, and the portion extending along the Y axis is mainly shielded from light by the data line 16 and the common wiring 18. In plan view, the light-shielding region SD overlaps with the pixel electrode 11. Furthermore, a TFT 30 and a capacitance element 60 (not shown) are arranged in the light-shielding region SD, and the pixel electrode 11 is electrically connected to the TFT 30 and the capacitance element 60 via a contact hole C20 serving as a first contact hole.

[0038] Contact hole C4 as a second contact hole is disposed at a position overlapping with contact hole C20 in a plan view. Specifically, contact hole C201 as a first contact hole of pixel P1 overlaps with contact hole C42 as a second contact hole of pixel P2 adjacent to pixel P1 in the X1 direction as a first direction in a plan view, and contact hole C202 as a first contact hole of pixel P2 overlaps with contact hole C43 as a second contact hole of pixel P3 adjacent to pixel P2 in the X1 direction as a first direction in a plan view.

[0039] Here, pixels P1, P2, and P3 have similar configurations in planar and cross-sectional configurations, and therefore, the same configurations will be described using common symbols. However, when the configurations of pixels P1, P2, and P3 are to be described separately, they will be described using different symbols. Specifically, the components of pixel P1 are designated by adding 1 to the end of the common reference numeral. Similarly, the components of pixel P2 are designated by adding 2 to the end of the common reference numeral, and the components of pixel P3 are designated by adding 3 to the end of the common reference numeral. For example, in the case of pixel electrode 11, pixel electrode 111 indicates that it is a component of pixel P1, pixel electrode 112 indicates that it is a component of pixel P2, and pixel electrode 113 indicates that it is a component of pixel P3. Similarly, in the case of contact hole C20, contact hole C201 indicates that it is a component of pixel P1, and contact hole C202 indicates that it is a component of pixel P2. Other components will be described in the same manner below.

[0040] As shown in FIGS. 5A, 5B, and 5C, the element substrate 10 has a configuration in which a plurality of functional layers are stacked on a base substrate 10a. Specifically, a first conductive layer, a second conductive layer, a semiconductor layer 31 of the TFT 30, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a pixel electrode 11 are stacked in this order on the substrate 10a. The first conductive layer includes a second capacitance electrode 62 of the capacitance element 60. The second conductive layer includes a first capacitance electrode 61 of the capacitance element 60. The third conductive layer includes a scanning line 13 as a light-shielding member. The fourth conductive layer includes a gate electrode 32 of the TFT 30, and a second relay electrode 82 and a fifth relay electrode 85 as second conductive members. The fifth conductive layer includes a light-shielding film 50. The sixth conductive layer includes a data line 16, a first relay electrode 81, and a fourth relay electrode 84. The seventh conductive layer includes a common wiring 18 as a capacitance wiring and a third relay electrode 83 as a first conductive member.

[0041] A dielectric film 63 is provided between the second capacitor electrode 62 of the first conductive layer and the first capacitor electrode 61 of the second conductive layer. A first interlayer insulating layer 71 is provided between the second conductive layer and the third conductive layer. A second interlayer insulating layer 72 is provided between the third conductive layer and the semiconductor layer 31. A gate insulating film 33 is provided between the semiconductor layer 31 and the gate electrode 32 of the fourth conductive layer. A third interlayer insulating layer 73 is provided between the fourth conductive layer and the fifth conductive layer. A fourth interlayer insulating layer 74 is provided between the fifth conductive layer and the sixth conductive layer. A fifth interlayer insulating layer 75 is provided between the sixth conductive layer and the seventh conductive layer. A sixth interlayer insulating layer 76 is provided between the seventh conductive layer and the pixel electrode 11.

[0042] 5A shows the configuration of pixel P2. The TFT 302 serving as the second transistor of pixel P2 and the capacitive element 602 serving as the capacitive element are disposed between pixel P1 and pixel P2 adjacent to pixel P1 in the X1 direction in FIG. The capacitive element 602 has a first capacitive electrode 612 arranged on the scanning line 13 side and a second capacitive electrode 622 arranged on the substrate 10a side. The second capacitive electrode 622 is electrically connected to a fifth relay electrode 852 of the pixel P2 provided in the fourth conductive layer through a contact hole C32 of the pixel P2 provided in the first interlayer insulating layer 71 and the second interlayer insulating layer 72. The fifth relay electrode 852 is electrically connected to the drain 31d2 of the TFT 302 and is also electrically connected to the light-shielding film 502 of the pixel P2 through a contact hole C52 of the pixel P2 provided in the third interlayer insulating layer 73.

[0043] A trench 10c2 is provided in the substrate 10a. A part of the capacitive element 602 is provided in the trench 10c2, thereby increasing the capacitance. The data line 16 is electrically connected to the source 31s2 of the TFT 302 through a contact hole C62 of the pixel P2 provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73.

[0044] FIG. 5B shows a configuration in which the pixel electrode 111 as the pixel electrode and the capacitor element 601 are electrically connected in the pixel P1. The pixel electrode 111 is electrically connected to the protrusion 831a serving as the first protrusion of the third relay electrode 831 serving as the first conductive member of the pixel P1 provided on the seventh conductive layer via a contact hole C201 serving as the first contact hole of the pixel P1 provided on the sixth interlayer insulating layer 76. The third relay electrode 831 is electrically connected to the fourth relay electrode 841 of the pixel P1 provided in the sixth conductive layer through the contact hole C101 of the pixel P1 provided in the fifth interlayer insulating layer 75. The fourth relay electrode 841 is electrically connected to the light-shielding film 501 of the pixel P1 provided in the fifth conductive layer through the contact hole C81 of the pixel P1 provided in the fourth interlayer insulating layer 74.

[0045] The light-shielding film 501 is electrically connected to the fifth relay electrode 851 of the pixel P1 provided in the fourth conductive layer through the contact hole C51 of the pixel P1 provided in the third interlayer insulating layer 73. The fifth relay electrode 851 is electrically connected to the drain 31d1 of the TFT 301 as the first transistor of the pixel P1, and is also electrically connected to the second capacitance electrode 621 via the contact hole C31 of the pixel P1 provided in the second interlayer insulating layer 72 and the first interlayer insulating layer 71. The gate electrode 321 of the TFT 301 is electrically connected to the scanning line 13 through a contact hole C11 of the pixel P1 provided in the second interlayer insulating layer 72.

[0046] 5B shows a configuration in which the protruding portion 612a of the first capacitor electrode 612 of pixel P2 and the protruding portion 822a serving as the second protrusion of the second relay electrode 822 serving as the second conductive member are positioned to overlap in the Z1 direction in cross section. In addition, FIG. 5B shows a configuration in which the contact hole C42 serving as the second contact hole provided between the protruding portion 612a and the protruding portion 822a is positioned so as not to overlap the scanning line 13 so as to avoid the scanning line 13.

[0047] The contact hole C42 penetrates the second interlayer insulating layer 72 and the first interlayer insulating layer 71 and is provided so as to expose the protruding portion 612a of the first capacitance electrode 612 of the capacitance element 602 of the pixel P2 at the bottom of the contact hole C42. A second relay electrode 822 is formed inside the contact hole C42 and is electrically connected to the protruding portion 612a of the first capacitance electrode 612 at the bottom of the contact hole C42. The thickness of the portion of the second relay electrode 822 formed on the inner wall of the contact hole C42 is thinner than the thickness of the portion formed on the gate insulating film 332.

[0048] 5B and 5C show a configuration in which the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 are arranged at positions where they cross-sectionally overlap in the Z1 direction, and a configuration in which the protruding portion 831a of pixel P1 and the protruding portions 822a and 612a of pixel P2 are arranged at positions where they cross-sectionally overlap in the Z1 direction. Note that, as shown in FIG. 4, the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 are arranged at positions where they overlap in a plan view. Therefore, the protruding portion 831a of pixel P1 and the protruding portions 822a and 612a of pixel P2 are arranged at positions where they overlap in a plan view.

[0049] FIG. 5C shows a configuration in which the common line 18 and the capacitive element 602 of the pixel P2 are electrically connected to each other in the pixel P2. The common line 18 is electrically connected to a first relay electrode 812 of the pixel P2 provided in the sixth conductive layer through a contact hole C92 of the pixel P2 provided in the fifth interlayer insulating layer 75. The first relay electrode 812 is electrically connected to a second relay electrode 822 through a contact hole C72 of the pixel P2 provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73. The second relay electrode 822 is electrically connected to the first capacitor electrode 612 of the capacitor element 602 through a contact hole C42 of the pixel P2 that is disposed between the protruding portion 822a of the second relay electrode 822 and the protruding portion 612a of the first capacitor electrode 612 of the capacitor element 602.

[0050] 5C shows a cross-sectional view of a configuration in which the contact hole C202 of pixel P2 and the contact hole C43 of pixel P3 shown in FIG. 4 are arranged at positions that overlap in a plan view. As shown in FIG. 5C, the contact hole C202 of pixel P2 and the contact hole C43 of pixel P3 are arranged at positions that overlap in the Z1 direction in a cross-sectional view.

[0051] Similarly, the protruding portion 832a of pixel P2, the protruding portion 823a of pixel P3, and the protruding portion 613a are arranged in a position that overlaps in the Z1 direction. Therefore, the protruding portion 832a of pixel P2, and the protruding portion 823a of pixel P3 and the protruding portion 613a are arranged in a position that overlaps in a plan view.

[0052] The contact hole C43 is provided to penetrate the second interlayer insulating layer 72 and the first interlayer insulating layer 71 so as to expose the protruding portion 613a of the first capacitor electrode 613 of the pixel P3 at the bottom of the contact hole C43. The first capacitor electrode 613 is electrically connected to the second relay electrode 823 of the pixel P3 provided on the fourth conductive layer via the contact hole C43.

[0053] As shown in FIG. 5C, the gate electrode 322 of the pixel P2 is electrically connected to the scanning line 13 via the contact hole C12 and the contact hole C22 of the pixel P2 provided in the second interlayer insulating layer 72.

[0054] 1.4. Overview of Liquid Crystal Device Manufacturing Method Next, a method for manufacturing the liquid crystal device 100 according to this embodiment will be described. Note that, in the method for manufacturing the liquid crystal device 100, the manufacturing process for the element substrate 10 including the characteristic portion of this embodiment will be described below with reference to FIGS.

[0055] Fig. 6 is a flowchart of the manufacturing process of the element substrate. Fig. 7 to Fig. 27 are plan views or cross-sectional views showing pixel correspondence in the manufacturing process of the element substrate. Note that in these drawings, each plan view is a drawing showing the plan view of Fig. 4 for each manufacturing process. Furthermore, in each cross-sectional view, the positions of the XX line, YY line, and ZZ line are the same.

[0056] The element substrate 10 can basically be manufactured by a method used in known semiconductor processes, such as low-pressure CVD (Chemical Vapor Deposition), atmospheric CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization), or a combination of these. While the following mainly describes a preferred manufacturing method, other manufacturing methods may also be used as long as they can form an equivalent structure and satisfy the functions and characteristics of the configuration.

[0057] 6, in step S1, trenches 10c are formed as grooves in the substrate 10a. The trenches 10c may be formed by depositing an interlayer insulating layer on the substrate 10a and providing the trenches 10c in the interlayer insulating layer or in the interlayer insulating layer and the substrate 10a.

[0058] 7 is a plan view showing the pixel state of the element substrate in the process of step S1, FIG. 8A is a cross-sectional view taken along line YY in FIG. 7, and FIG. 8B is a cross-sectional view taken along line XX in FIG. As shown in FIG. 7, the trench 10c is formed in the light-shielding region SD in a rectangular shape that is long in the Y1 direction.

[0059] In FIG. 6, in step S2, the second capacitance electrode 62 of the capacitance element 60 is formed in the trench 10c. 9 is a plan view showing the pixel state of the element substrate in the process of step S2, FIG. 10A is a cross-sectional view taken along line YY in FIG. 9, and FIG. 10B is a cross-sectional view taken along line XX in FIG.

[0060] In step S2, a second capacitance electrode 62 made of a conductive polysilicon film is formed on the substrate 10a, including the inner wall of the trench 10c. A first conductive layer made of deposited polysilicon containing phosphorus is formed on the substrate 10a to a thickness of 50 nm to 100 nm, and then patterned by dry etching into the shape shown in FIGS. 9, 10A, and 10B, thereby forming the second capacitance electrode 62.

[0061] In step S2, after the second capacitor electrode 62 is formed, an oxide film island 71a is formed to cover a part of the second capacitor electrode 62. The oxide film island 71a is formed by depositing a silicon oxide film, such as a TEOS (Tetraethyl Orthosilicate) film or an HTO (High Temperature Oxide) film, to a thickness of about 100 nm and then patterning it. The oxide film island 71a is disposed at a position where a contact hole C3 (described later) will be provided, and functions as an etching stopper film for protecting the second capacitor electrode 62 when the first capacitor electrode 61 (described later) is patterned.

[0062] In FIG. 6, in step S3, the first capacitor electrode 61 of the capacitor element 60 is formed. Figure 11 is a plan view showing the pixel configuration of the element substrate in the process of step S3, Figure 12A is a cross-sectional view taken along line YY in Figure 11, Figure 12B is a cross-sectional view taken along line XX in Figure 11, and Figure 12C is a cross-sectional view taken along line ZZ in Figure 11.

[0063] In step S3, first, the dielectric film 63 is formed on the second capacitance electrode 62, and then the first capacitance electrode 61 is formed. On the second capacitor electrode 62, a dielectric film 63 is formed of a silicon oxide (SiO2) film, a silicon nitride (SiN) film, a metal oxide film (HfO2, ZrO2) or the like to a thickness of 20 nm.

[0064] In step S3, a first capacitor electrode 61 made of a conductive polysilicon film is then formed on the dielectric film 63. In forming the first capacitor electrode 61, a second conductive layer made of deposited polysilicon containing phosphorus is formed to a film thickness of 50 nm to 100 nm on the dielectric film 63, and then the dielectric film 63 and the first capacitor electrode 61 are patterned by dry etching to form the first capacitor electrode 61.

[0065] 11, the first capacitance electrode 61 is formed to have an area slightly larger than that of the second capacitance electrode 62, except for a portion where a contact hole C3 for providing a fifth relay electrode 85 (described later) is provided. Also, as shown in FIGS. 12A and 12B, the dielectric film 63 is formed in the same shape as the second capacitance electrode 62, and part of the outer edge portion thereof covers the second capacitance electrode 62 and is in contact with the substrate 10a.

[0066] As shown in FIG. 12A, a part of the first capacitor electrode 61 that overlaps with the oxide film island 71a is removed during patterning.

[0067] 11, the first capacitance electrode 61 has a protruding portion 61a that protrudes along the Y-axis direction. The contact hole C4 shown in FIGS. 5B and 5C is provided at the position of the protruding portion 61a, and the first capacitance electrode 61 and the second relay electrode 82 are electrically connected via the contact hole C4.

[0068] In FIG. 6, in step S4, the scanning lines 13 are formed. 13 is a plan view showing the pixel state of the element substrate in the process of step S4, FIG. 14A is a cross-sectional view taken along line YY in FIG. 13, and FIG. 14B is a cross-sectional view taken along line XX in FIG.

[0069] In step S4, first, a first interlayer insulating layer 71 is formed on the first capacitor electrode 61, and then the scanning line 13 is formed. The first interlayer insulating layer 71 is made of, for example, a silicon oxide film made of TEOS, and has a film thickness of 400 nm to 600 nm.

[0070] To form the scan lines 13, a third conductive layer made of a tungsten silicide (WSi) film is formed on the first interlayer insulating layer 71 to a thickness of 100 nm to 400 nm, and then patterned as shown in FIG. 13 to form the scan lines 13. The scan lines 13 extend along the X axis and have, at positions overlapping with the trenches 10c in a plan view, protruding portions 13a that protrude in the Y1 and Y2 directions and wide portions 13b that are wider in the X1 and X2 directions. Contact holes C1 and C2, described below, are formed at the positions of the wide portions 13b. The scan lines 13 are made of a metal material with light-shielding properties and function as light-shielding portions for the TFTs 30.

[0071] 13, the protruding portion 61a of the first capacitance electrode 61 of the capacitance element 60 protrudes from the scanning line 13 along the Y-axis direction in a plan view. In other words, the protruding portion 61a is provided in the light-transmitting region of the pixel P in a plan view.

[0072] In FIG. 6, in step S5, the semiconductor layer 31 of the TFT 30 is formed. 15 is a plan view showing the pixel state of the element substrate in the process of step S5, FIG. 16A is a cross-sectional view taken along line YY in FIG. 15, and FIG. 16B is a cross-sectional view taken along line XX in FIG.

[0073] In step S5, first, the second interlayer insulating layer 72 is formed on the scanning lines 13, and then the semiconductor layer 31 is formed. The second interlayer insulating layer 72 is made of, for example, a TEOS film, and has a film thickness of 200 nm to 600 nm. In forming the semiconductor layer 31, amorphous silicon is deposited on the second interlayer insulating layer 72, and then heat treatment is performed to form the semiconductor layer 31 made of polysilicon. As shown in FIGS. 15, 16A, and 16B, the semiconductor layer 31 is provided so that its channel overlaps the trench 10c in plan view.

[0074] In FIG. 6, in step S6, contact holes C1, C2, C3, and C4 are formed. Figure 17 is a plan view showing the pixel state of the element substrate in the process of step S6, Figure 18A is a cross-sectional view along line YY in Figure 17, Figure 18B is a cross-sectional view along line XX in Figure 17, and Figure 18C is a cross-sectional view along line ZZ in Figure 17.

[0075] In step S6, first, the gate insulating film 33 is formed on the semiconductor layer 31, then the contact holes C1 and C2 are formed, and then the contact holes C3 and C4 are formed. Specifically, the gate insulating film 33 made of an HTO film is formed on the semiconductor layer 31 to a thickness of 30 nm to 100 nm, and then the channel of the semiconductor layer 31 is selectively doped with the HTO film.

[0076] As shown in Figures 17 and 18B, the contact holes C1 and C2 are arranged on both sides of the channel of the semiconductor layer 31 at positions that overlap with the wide portions 13b of the scanning lines 13 in a planar view, and penetrate the gate insulating film 33 and the second interlayer insulating layer 72 to expose the scanning lines 13 at the bottoms of the contact holes C1 and C2.

[0077] 17 and 18A, the contact hole C3 penetrates the gate insulating film 33, the second interlayer insulating layer 72, the first interlayer insulating layer 71, and the oxide film island 71a, and exposes the second capacitance electrode 62 of the capacitance element 60 at the bottom of the contact hole C3. The drain 31d of the semiconductor layer 31 is exposed inside the contact hole C3. At the entrance of the contact hole C3, a portion of the gate insulating film 33 covering the drain 31d of the semiconductor layer 31 is peeled off, exposing the drain 31d of the semiconductor layer 31.

[0078] As shown in Figures 17 and 18C, the contact hole C4 penetrates the gate insulating film 33, the second interlayer insulating layer 72, and the first interlayer insulating layer 71, exposing the protruding portion 61a of the first capacitance electrode 61 of the capacitance element 60 at the bottom of the contact hole C4.

[0079] The inner wall of contact hole C4 is inclined at an angle of approximately 84° with respect to the surface of substrate 10a. The inner wall of contact hole C4 can be inclined to a desired angle by adjusting the etching gas. Because the inner wall of contact hole C4 is inclined at an angle of approximately 84°, the size (area) of the opening on the entrance side of contact hole C4 is larger than the size (area) of the opening on the bottom side. Therefore, the shape of contact hole C4 is an inverted truncated square pyramid, an inverted truncated cone, an inverted truncated elliptical pyramid, or an inverted truncated square pyramid with rounded corners.

[0080] By shaping the contact hole C4 in this way, when the size of the entrance side of the contact hole C4 is the same, the position where the contact hole C4 is provided can be closer to the scanning line 13 when viewed in a plane than if the shape of the contact hole C4 were a square prism or a cylinder.

[0081] In this embodiment, the inclination angle of the inner wall of contact hole C4 is made more inclined than usual. Normally, the inclination angle of the inner wall of contact hole C4 is about 88°. In this way, in this embodiment, the inclination angle of the inner wall of contact hole C4 is made more inclined than usual, at about 84°. Therefore, while ensuring a clearance between contact hole C4 and scanning line 13, the position of contact hole C4 in plan view can be made closer to scanning line 13 than usual. Furthermore, in this embodiment, the inclination angle of the inner wall of the contact hole C4 is made more inclined than usual, so that it is possible to ensure a clearance between the contact hole C4 and the scanning line 13 without relying on miniaturization in a photolithography process. Therefore, the position where the contact hole C4 is provided in a plan view can be closer to the scanning line 13 than usual.

[0082] In FIG. 6, in step S7, the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85 are formed. Figure 19 is a plan view showing the pixel state of the element substrate in the process of step S7, Figure 20A is a cross-sectional view along line YY in Figure 19, Figure 20B is a cross-sectional view along line XX in Figure 19, and Figure 20C is a cross-sectional view along line ZZ in Figure 19.

[0083] In step S7, a fourth conductive layer having a two-layer structure made of a conductive polysilicon film and a tungsten silicide film, which is a light-shielding conductive film, is formed on the gate insulating film 33 and inside the contact holes C1, C2, C3, and C4. Since the contact holes C3 and C4 are small and deep holes, i.e., high aspect ratio contact holes, a deposition polysilicon containing phosphorus is first formed in consideration of the adhesion to the inside of the contact holes C3 and C4, and then a tungsten silicide film, which is a light-shielding conductive film, is laminated on top of the deposition polysilicon. This allows the inside of the contact holes C3 and C4 to be well covered by the fourth conductive layer.

[0084] 19, the fourth conductive layer is patterned to form the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85. As a result, the gate electrode 32 is electrically connected to the scanning line 13 via the contact holes C1 and C2.

[0085] In plan view, the second relay electrode 82 has a protruding portion 82a as a second protrusion that protrudes from the scanning line 13. The protruding portion 82a and the protruding portion 61a protrude from the scanning line 13 and overlap each other in plan view. The second relay electrode 82 and the first capacitor electrode 61 of the capacitor element 60 are electrically connected via a contact hole C4.

[0086] The fifth relay electrode 85 is electrically connected to the second capacitor electrode 62 of the capacitor element 60 via a contact hole C3. As described above, the gate electrode 32 is formed on the semiconductor layer 31 and in the contact holes C1 and C2, and is arranged to surround the semiconductor layer 31 in the Z1 direction, X1 direction, and X2 direction, thereby functioning as a light-shielding portion for the semiconductor layer 31.

[0087] In FIG. 6, in step S8, the light-shielding film 50 is formed. 21 is a plan view showing the pixel state of the element substrate in the process of step S8, FIG. 22A is a cross-sectional view taken along line YY in FIG. 21, and FIG. 22B is a cross-sectional view taken along line XX in FIG.

[0088] In step S8, first, a third interlayer insulating layer 73 made of a TEOS film is formed to a thickness of 200 nm to 400 nm on the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85, and then a contact hole C5 exposing the fifth relay electrode 85 is formed in the third interlayer insulating layer 73.

[0089] Next, in step S8, the light-shielding film 50 is formed. In forming the light-shielding film 50, a fifth conductive layer made of a metal film such as a tungsten silicide film, which is a light-shielding conductive film, is formed on the third interlayer insulating layer 73 and inside the contact hole C5 to a thickness of 100 nm to 400 nm, and then the fifth conductive layer is patterned as shown in FIGS. 21, 22A, and 22B to form the light-shielding film 50. The light-shielding film 50 is electrically connected to the fifth relay electrode 85 through the contact hole C5. As a result, the light-shielding film 50 is electrically connected to the second capacitance electrode 62 of the capacitance element 60 through the fifth relay electrode 85. The film thickness of the light-shielding film 50 is approximately 100 nm. The light-shielding film 50 is disposed at a position overlapping the capacitance element 60 in plan view.

[0090] In FIG. 6, in step S9, the data lines 16 are formed. 23 is a plan view showing the pixel state of the element substrate in the process of step S9, FIG. 24A is a cross-sectional view taken along line YY in FIG. 23, and FIG. 24B is a cross-sectional view taken along line XX in FIG.

[0091] In step S9, first, a fourth interlayer insulating layer 74 made of a TEOS film is formed on the light-shielding film 50 to a thickness of 500 nm to 1000 nm, and then contact holes C6, C7, and C8 are formed.

[0092] As shown in FIG. 24A, the contact hole C6 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73 to expose the source 31s of the TFT 30 at the bottom of the contact hole C6. As shown in FIG. 24B, the contact hole C7 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73 to expose the second relay electrode 82 at the bottom of the contact hole C7. As shown in FIG. 24B, the contact hole C8 penetrates the fourth interlayer insulating layer 74 to expose the light-shielding film 50 at the bottom of the contact hole C8.

[0093] In step S9, a sixth conductive layer consisting of a multi-layer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are stacked in two to four layers is then formed on the fourth interlayer insulating layer 74 and inside the contact holes C6, C7, and C8.

[0094] In step S9, after the sixth conductive layer is formed, the sixth conductive layer is patterned as shown in FIG. 23 to form the data line 16, the first relay electrode 81, and the fourth relay electrode 84. As shown in FIG. 24A, the data line 16 is formed inside the contact hole C6 and is electrically connected to the source 31s of the semiconductor layer 31 exposed at the bottom of the contact hole C6.

[0095] As shown in FIG. 24B, the first relay electrode 81 is formed inside the contact hole C7 and is electrically connected to the second relay electrode 82 exposed at the bottom of the contact hole C7. The fourth relay electrode 84 is formed inside the contact hole C8 and is electrically connected to the light-shielding film 50 exposed at the bottom of the contact hole C8.

[0096] In FIG. 6, in step S10, the common wiring 18 is formed. Figure 25 is a plan view showing the pixel state of the element substrate in the process of step S10, Figure 26A is a cross-sectional view along line YY in Figure 25, Figure 26B is a cross-sectional view along line XX in Figure 25, and Figure 26C is a cross-sectional view along line ZZ in Figure 25.

[0097] In step S10, first, the fifth interlayer insulating layer 75 made of a TEOS film is formed on the data line 16, the first relay electrode 81, and the fourth relay electrode 84 to a thickness of 500 nm to 1000 nm.

[0098] Next, in step S10, contact holes C9 and C10 are formed. 25, the contact hole C9 is formed at a position overlapping in plan view with the protruding portion 18a protruding in the X2 direction from the common wiring 18. Furthermore, as shown in FIG. 26B, the contact hole C9 penetrates the fifth interlayer insulating layer 75 to expose the first relay electrode 81 at the bottom of the contact hole C9.

[0099] 25, the contact hole C10 is formed in the X1 direction of the common wiring 18. Furthermore, as shown in FIG. 26B, the contact hole C10 penetrates the fifth interlayer insulating layer 75 to expose the fourth relay electrode 84 at the bottom of the contact hole C10.

[0100] In contact hole C10, a seventh conductive layer is then formed on the fifth interlayer insulating layer 75 and inside contact holes C9 and C10, the seventh conductive layer being a multi-layer film in which two to four layers of aluminum alloy film or titanium nitride film and aluminum film are stacked.

[0101] In the contact hole C10, after a seventh conductive layer is formed, the seventh conductive layer is patterned as shown in FIG. 25 to form a common wiring 18 as a capacitance wiring and a third relay electrode 83 as a first conductive member.

[0102] 25, 26A, and 4, the common wiring 18 is formed at a position overlapping the data line 16 in plan view and cross section. Also, as shown in FIG. 26B, the common wiring 18 is formed inside the contact hole C9 and is electrically connected to the first relay electrode 81 exposed at the bottom of the contact hole C9.

[0103] As shown in FIG. 25, the third relay electrode 83 is disposed between two common wirings 18. Furthermore, the third relay electrode 83 has a protruding portion 83a that protrudes in the Y1 direction from the scanning line 13 in a plan view. The planar size of the protruding portion 83a is larger than that of the protruding portion 82a of the second relay electrode 82. Note that the planar size of the protruding portion 83a may be the same as that of the protruding portion 82a of the second relay electrode 82. As described above, the protruding portion 831a of the third relay electrode 831 of the pixel P1 overlaps with the protruding portion 822a of the second relay electrode 822 of the pixel P2 in a planar view. Moreover, the protruding portion 832a of the third relay electrode 832 of the pixel P2 overlaps with the protruding portion 823a of the second relay electrode 823 of the pixel P3 in a planar view. As shown in FIG. 26B, the third relay electrode 83 is formed inside the contact hole C10 and is electrically connected to the fourth relay electrode 84 exposed at the bottom of the contact hole C10.

[0104] In FIG. 6, in step S11, the pixel electrode 11 is formed. FIG. 27 is a plan view showing the pixel state of the element substrate in the process of step S11. In step S11, as shown in FIGS. 5A, 5B, and 5C, first, a sixth interlayer insulating layer 76 made of a TEOS film is formed on the common wiring 18 and the third relay electrode 83 to a thickness of 500 nm to 1000 nm.

[0105] Next, in step S11, a contact hole C20 is formed. 27 and 5C, the contact hole C20 is formed at a position overlapping, in plan view, with the protruding portion 83a of the third relay electrode 83. The contact hole C20 also penetrates the sixth interlayer insulating layer 76 to expose the third relay electrode 83 at the bottom of the contact hole C20. The contact hole C20 is formed in the shape of an inverted truncated square pyramid or an inverted truncated square pyramid with rounded corners. The dimensions of the contact hole C20 at the opening, i.e., the side where the pixel electrode 11 is provided, are 1.2 μm for the long side and 0.5 μm for the short side. The dimensions of the bottom of the hole are both 0.4 μm for the long side and the short side. In step S11, next, a pixel electrode 11 is formed for each pixel P by depositing an ITO film on the sixth interlayer insulating layer 76 and inside the contact hole C20 and patterning it.

[0106] As described above, the liquid crystal device 100 as an electro-optical device according to this embodiment can provide the following effects. The liquid crystal device 100 of this embodiment includes a substrate 10a as a substrate, a TFT 301 of a pixel P1 as a first transistor, a TFT 302 of a pixel P2 as a second transistor adjacent to the TFT 301 in the first direction, a scanning line 13 as a light-blocking member provided along the first direction between the substrate 10a and the TFT 301 and between the substrate 10a and the TFT 302 of the pixel P2, a common wiring 18 as a capacitance wiring, a pixel electrode 111 of the pixel P1 provided corresponding to the TFT 301, and a first conductive member that overlaps the scanning line 13 in a plan view and has a protruding portion 831a as a first protrusion protruding from the scanning line 13, and electrically connects the TFT 301 and the pixel electrode 111. a third relay electrode 831 of pixel P1 as a second conductive member; a capacitive element 602 that is provided between the substrate 10a and the scanning line 13 and overlaps with the TFT 302 in a planar view; and a second relay electrode 822 of pixel P2 that overlaps with the scanning line 13 in a planar view and has a protruding portion 822a that protrudes from the scanning line 13 as a second protrusion, and that electrically connects the capacitive element 602 and the common wiring 18. A contact hole C201 that serves as a first contact hole for electrically connecting the pixel electrode 111 and the third relay electrode 831 overlaps with a contact hole C42 that serves as a second contact hole for electrically connecting the capacitive element 602 and the second relay electrode 822 in a planar view.

[0107] In this manner, in the liquid crystal device 100 of this embodiment, the pixel electrode 111 of pixel P1 and the third relay electrode 831 are electrically connected via a contact hole C201 provided between the pixel electrode 111 and the protrusion 831a, and the capacitive element 602 and the second relay electrode 822 are connected via a contact hole C42 provided between the capacitive element 602 and the protrusion 822a, and in a planar view, the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 overlap.

[0108] Therefore, since the capacitive element 60 is connected to the common wiring 18 for each pixel P, the potential of the first capacitive electrode 61 connected to the common wiring 18 is stable, and problems such as display unevenness can be suppressed. Furthermore, the portion of the pixel electrode 111 that overlaps with the contact hole C201 creates a recess, making it difficult for this portion to contribute to display, and since the contact hole C42 is located at a position that protrudes from the scanning line 13, this is a portion that may have an adverse effect on transmittance. However, by locating the contact hole C42 at a position that overlaps with the contact hole C201 in a planar view, the adverse effects on display can be minimized. The light-shielding member is not limited to the scanning line 13. For example, the light-shielding member may be a signal line other than the scanning line 13, or a light-shielding film provided in the form of a wiring or an island.

[0109] Furthermore, in the liquid crystal device 100 of this embodiment, the third relay electrode 83 as the first conductive member and the common line 18 as the capacitance line are provided in the same layer. As described above, in the liquid crystal device 100 of this embodiment, the third relay electrode 83 is provided on the seventh conductive layer, which is the same layer as the common line 18, which simplifies the layout of the third relay electrode 83 and improves the utilization rate of the seventh conductive layer. Furthermore, because the seventh conductive layer is a conductive layer directly below the pixel electrode 11, it is possible to prevent the contact hole C20 from becoming a deep hole or a hole with a high aspect ratio, thereby ensuring good electrical connection between the pixel electrode 11 and the third relay electrode 83.

[0110] In the liquid crystal device 100 of this embodiment, the area of ​​the protruding portion 83a of the third relay electrode 83 as the first protrusion is greater than or equal to the area of ​​the protruding portion 82a of the second relay electrode 82 as the second protrusion in a plan view. In this way, in the liquid crystal device 100 of this embodiment, the size of the protruding portion 83a of the third relay electrode 83 on the pixel electrode 11 side is made equal to or larger than the size of the protruding portion 82a of the second relay electrode 82, so that in a planar view, the protruding portion 82a of the second relay electrode 82 can be positioned so as to completely overlap the protruding portion 83a of the third relay electrode 83, thereby minimizing any adverse effects on the display.

[0111] In the liquid crystal device 100 of this embodiment, the third relay electrode 83 as the first conductive member has a layer containing aluminum, and the second relay electrode 82 as the second conductive member has a layer containing polysilicon and a layer containing tungsten silicide. In this way, in the liquid crystal device 100 of this embodiment, the third relay electrode 83 is made of a layer containing aluminum, and therefore the influence of the second relay electrode 82, which has a transparent layer containing polysilicon and a layer containing tungsten silicide, can be hidden by the third relay electrode 83, which has light-blocking properties.

[0112] In the liquid crystal device 100 of this embodiment, the length of the long side of the contact hole C20 serving as the first contact hole on the pixel electrode 11 side is equal to or greater than the length of the long side of the contact hole C20 on the protruding portion 83a side serving as the first protrusion. In this way, in the liquid crystal device 100 of this embodiment, the shape of the contact hole C20 is such that the size of the hole on the pixel electrode 11 side, which is the entrance side of the contact hole C20, is larger than the size of the hole on the bottom side of the contact hole C20, so the depression of the pixel electrode 11 can be made gentler and the impact on the display can be reduced.

[0113] In the liquid crystal device 100 of this embodiment, a portion of the capacitive element 60 is further provided inside a trench 10c, which serves as a groove provided in the substrate 10a. As described above, in the liquid crystal device 100 of this embodiment, the capacitive element 60 has a portion provided inside the trench 10c, and therefore, unevenness in film thickness, cracks, and the like are likely to occur in the first capacitive electrode 61 of the capacitive element 60. However, even if the first capacitive electrode 61 has high resistance due to unevenness in thickness or cracks, the first capacitive electrode 61 is electrically connected to the common wiring 18, and therefore defects such as display unevenness can be suppressed.

[0114] The liquid crystal device 100 of this embodiment includes a substrate 10a as a substrate, a TFT 30 as a transistor, a scanning line 13 as a light-shielding member provided along a first direction between the substrate 10a and the TFT 30, a common wiring 18 as a capacitance wiring, a pixel electrode 11 provided corresponding to the TFT 30, a third relay electrode 83 as a first conductive member that overlaps with the scanning line 13 in a plan view and has a protruding portion 83a as a second protrusion protruding from the scanning line 13 and electrically connects the TFT 30 and the pixel electrode 11, and a third relay electrode 83 as a first conductive member that electrically connects the substrate 10a and the scanning line 13. The pixel electrode 11 includes a capacitance element 60 provided between the scanning line 13 and the common wiring 18, and a second relay electrode 82 serving as a second conductive member that overlaps the scanning line 13 in a planar view and has a protruding portion 82a that protrudes from the scanning line 13 as a second protrusion, and electrically connects the capacitance element 60 to the common wiring 18, and a contact hole C20 serving as a first contact hole for electrically connecting the pixel electrode 11 to the third relay electrode 83 overlaps with a contact hole C4 serving as a second contact hole for electrically connecting the capacitance element 60 to the second relay electrode 82.

[0115] In this way, in the liquid crystal device 100 of this embodiment, the pixel electrode 11 and the third relay electrode 83 are electrically connected via a contact hole C20 provided between the pixel electrode 11 and the protrusion 83a, and the capacitive element 60 and the second relay electrode 82 are connected via a contact hole C4 provided between the capacitive element 60 and the protrusion 82a as the second protrusion, and in a planar view, the contact hole C20 and the contact hole C4 overlap.

[0116] With this configuration, the capacitive element 60 is connected to the common wiring 18 for each pixel P, so that the potential of the first capacitive electrode 61 connected to the common wiring 18 is stable, making it possible to suppress problems such as display unevenness. Furthermore, the portion of the pixel electrode 11 that overlaps with the contact hole C20 creates a recess, making it difficult for this portion to contribute to display. Also, since the contact hole C4 is located at a position that protrudes from the scanning line 13, this is a portion that may have a negative impact on transmittance. However, by locating the contact hole C4 at a position that overlaps with the contact hole C20 in a planar view, the negative impact on display can be minimized. The light-shielding member is not limited to the scanning line 13. For example, the light-shielding member may be a signal line other than the scanning line 13, or a light-shielding film provided in the form of a wiring or an island. Furthermore, the contact hole C20 and the contact hole C4 may be components of the same pixel P. For example, by arranging the capacitive element 60 in the same pixel P, the contact hole C20 and the contact hole C4 can be components of the same pixel P.

[0117] 2. Embodiment 2 2.1. Display Device Overview 28 is a schematic diagram showing the configuration of a projection display device as a display device according to this embodiment. In this embodiment, a projection display device 1000 will be described as an example of a display device including a liquid crystal device 100 as the electro-optical device described above.

[0118] As shown in Figure 28, the projection type display device 1000 as the display device of this embodiment includes a lamp unit 1001 as a light source, dichroic mirrors 1011 and 1012 as a color separation optical system, a liquid crystal device 100B corresponding to blue light, a liquid crystal device 100G corresponding to green light, a liquid crystal device 100R corresponding to red light, three reflecting mirrors 1111, 1112, and 1113, three relay lenses 1121, 1122, and 1123, a dichroic prism 1130 as a color synthesis optical system, and a projection lens 1140 as a projection optical system.

[0119] For example, a discharge type light source is used in the lamp unit 1001. The light source type is not limited to this, and a solid-state light source such as a light-emitting diode or a laser may also be used.

[0120] Light emitted from lamp unit 1001 is separated into three colored lights of different wavelength ranges by two dichroic mirrors 1011 and 1012. The three colored lights are red light R, green light G, and blue light B.

[0121] Dichroic mirror 1011 transmits red light R and reflects green light G and blue light B, which have shorter wavelengths than red light R. Red light R that has transmitted through dichroic mirror 1011 is reflected by reflecting mirror 1111 and enters liquid crystal device 100R. Green light G that has reflected through dichroic mirror 1011 is reflected by dichroic mirror 1012 and then enters liquid crystal device 100G. Blue light B that has reflected through dichroic mirror 1011 is transmitted through dichroic mirror 1012 and emerges into relay lens system 1120.

[0122] Relay lens system 1120 has relay lenses 1121, 1122, and 1123, and reflecting mirrors 1112 and 1113. Blue light B has a longer optical path than green light G and red light R, and therefore tends to have a larger luminous flux. For this reason, relay lens 1122 is used to prevent the blue light B from expanding its luminous flux. Blue light B incident on relay lens system 1120 is reflected by reflecting mirror 1112 and converged near relay lens 1122 by relay lens 1121. Blue light B then passes through reflecting mirror 1113 and relay lens 1123 and enters liquid crystal device 100B.

[0123] In the projection display device 1000, the liquid crystal device 100 as the electro-optical device according to the first embodiment is applied to the liquid crystal devices 100R, 100G, and 100B which are light modulation devices.

[0124] Each of the liquid crystal devices 100R, 100G, and 100B is electrically connected to a higher-level circuit of the projection display device 1000. As a result, image signals Dx specifying the gradation levels of red light R, green light G, and blue light B are supplied from external circuits and processed by the higher-level circuit, thereby driving the liquid crystal devices 100R, 100G, and 100B, and modulating the respective color lights.

[0125] The red light R, green light G, and blue light B modulated by the liquid crystal devices 100R, 100G, and 100B are incident on the dichroic prism 1130 from three directions. The dichroic prism 1130 combines the incident red light R, green light G, and blue light B. The dichroic prism 1130 reflects the red light R and blue light B at a 90-degree angle, while the green light G is transmitted. Therefore, the red light R, green light G, and blue light B are combined as display light for displaying a color image and emitted toward the projection lens 1140.

[0126] The projection lens 1140 is disposed facing outward from the projection display device 1000. Display light is magnified and emitted through the projection lens 1140, and projected onto a screen 1200, which is the projection target.

[0127] In this embodiment, the projection display device 1000 is exemplified as a display device, but the display device to which the liquid crystal device 100 is applied is not limited to this. For example, the liquid crystal device 100 may be applied to a projection type HUD (Head-Up Display), HMD (Head Mounted Display), personal computer, digital camera, liquid crystal television, or other display device. As described above, according to the projection display device 1000 of this embodiment, in addition to the effects of the above-described embodiments, the following effects can be obtained. A projection display device 1000 serving as a display device preferably includes a liquid crystal device 100 serving as an electro-optical device according to any one of the above embodiments.

[0128] According to this configuration, the liquid crystal device 100 mounted on the projection display device 1000 can be made smaller and have higher resolution, so that the projection display device 1000 mounting the liquid crystal device 100 can be made smaller.Furthermore, high-resolution display can be achieved without increasing the size of the projection display device 1000, so that an excellent display device can be provided.

[0129] Furthermore, in the above embodiment, a transmissive liquid crystal device is exemplified as the liquid crystal device 100 serving as an electro-optical device, but the liquid crystal device 100 may also be a reflective liquid crystal device or an LCOS (Liquid Crystal on Silicon) type liquid crystal device. [Explanation of symbols]

[0130] 5...liquid crystal layer, 6...sealing material, 7...vertical conductive portion, 10...element substrate, 10a...substrate, 10c, 10c2...trench, 11, 111, 112, 113...pixel electrode, 12...alignment film, 13...scanning line, 13a...extension portion, 13b...wide portion, 16...data line, 18...common wiring, 18a...extension portion, 20...counter substrate, 20a...substrate, 21...counter electrode, 30, 301, 302...TFT, 31...semiconductor layer, 31d, 31d1, 31d2... Drain, 31s...source, 32,321,322...gate electrode, 33,332...gate insulating film, 43...external connection terminal, 45...scanning line driving circuit, 47...data line driving circuit, 49...wiring, 50,501,502...light-shielding film, 60,601,602...capacitor element, 61,612,613...first capacitor electrode, 61a,612a,613a...extension portion, 62,621,622...second capacitor electrode, 63...dielectric film, 71...first interlayer insulating layer, 7 1a...oxide film island, 72...second interlayer insulating layer, 73...third interlayer insulating layer, 74...fourth interlayer insulating layer, 75...fifth interlayer insulating layer, 76...sixth interlayer insulating layer, 81,812...first relay electrode, 82,822,823...second relay electrode, 82a,822a,823a...extending portion, 83,831,832...third relay electrode, 83a,831a,832a...extending portion, 84,841...fourth relay electrode, 85,851,852...fifth relay electrode, 10 0, 100B, 100G, 100R... liquid crystal device, 1000... projection display device, 1001... lamp unit, 1011, 1012... dichroic mirror, 1111, 1112, 1113... reflection mirror, 1120... relay lens system, 1130... dichroic prism, 1140... projection lens, 1200... screen, C4, C42, C43... contact hole, E... display area, F... peripheral area, P... pixel, SD... light-shielding area.

Claims

1. A substrate; a first transistor; a second transistor adjacent to the first transistor in a first direction; a light-shielding member provided along the first direction between the substrate and the first transistor and between the substrate and the second transistor; Capacitive wiring, a pixel electrode provided corresponding to the first transistor; a first conductive member that overlaps the light-shielding member in a plan view, has a first protrusion that protrudes from the light-shielding member, and electrically connects the first transistor and the pixel electrode; a capacitive element provided between the substrate and the light-shielding member and overlapping with the second transistor in a plan view; a second conductive member that overlaps the light-shielding member in a plan view, has a second protruding portion that protrudes from the light-shielding member, and electrically connects the capacitive element and the capacitance wiring; a first contact hole for electrically connecting the pixel electrode and the first conductive member overlaps, in a plan view, with a second contact hole for electrically connecting the capacitive element and the second conductive member; Electro-optical device.

2. The first conductive member and the capacitance wiring are provided in the same layer. The electro-optical device according to claim 1 .

3. The area of ​​the first protrusion is equal to or greater than the area of ​​the second protrusion in a plan view. The electro-optical device according to claim 1 .

4. the first conductive member has a layer containing aluminum, the second conductive member has a layer containing polysilicon and a layer containing tungsten silicide; The electro-optical device according to claim 1 .

5. a length of a long side of the first contact hole on the pixel electrode side is equal to or greater than a length of a long side of the first contact hole on the first protrusion side; The electro-optical device according to claim 1 .

6. a portion of the capacitance element is provided inside a groove provided in the substrate; The electro-optical device according to claim 1 .

7. A substrate; The transistor and a light blocking member provided along a first direction between the substrate and the transistor; Capacitive wiring, a pixel electrode provided corresponding to the transistor; a first conductive member that overlaps the light-shielding member in a plan view, has a first protrusion that protrudes from the light-shielding member, and electrically connects the transistor and the pixel electrode; a capacitance element provided between the substrate and the light-shielding member; a second conductive member that overlaps the light-shielding member in a plan view, has a second protruding portion that protrudes from the light-shielding member, and electrically connects the capacitive element and the capacitance wiring; a first contact hole for electrically connecting the pixel electrode and the first conductive member overlaps with a second contact hole for electrically connecting the capacitive element and the second conductive member; Electro-optical device.

8. A display device comprising the electro-optical device according to any one of claims 1 to 7.

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