DC Block Structure

Abstract

This DC block structure is constituted by: a dielectric (1); transfer lines (2a, 2b) that are formed on a surface of the dielectric (1) and that have characteristic impedances of 50 ohms; transfer lines (3a, 3b) that are so formed on the surface of the dielectric (1) as to connect to the transfer lines (2a, 2b) and that are so designed as to have characteristic impedances higher than those of the transfer lines (2a, 2b); and a capacitor (4) that is so mounted on the transfer lines (3a, 3b) as to series connect the transfer line (3a) to the transfer line (3b).

Description

[Technical Field]

[0001] The present invention relates to a DC blocking structure that utilizes a surface-mount capacitor. [Background technology]

[0002] In recent years, the amount of data transmitted over networks has been steadily increasing, and research and development is being conducted to improve data transmission speeds to cope with this increase. The trend toward higher speeds is also seen in optical communication systems, and broadband capabilities are being demanded for each device that makes up the transmitter and receiver of optical communication systems.

[0003] A DC block is inserted between multiple cascaded devices and has the function of cutting out the DC voltage component superimposed on the signal and transmitting only the AC signal component to the next stage. This function makes it possible to drive each device with an appropriate bias. In recent years, optical communications devices are required to have extremely wideband characteristics, from near DC to the near 150 GHz region. The DC blocks inserted between these devices also require wideband characteristics.

[0004] Silicon capacitors, which can form nF-order capacitance on a thin film by applying the semiconductor CMOS process, are attracting attention as a wide-band DC block. Conventionally, in the frequency range below 100 GHz, MLCCs (Multi-Layered Chip Capacitors), which are relatively inexpensive and easily available, have been used as DC blocks.

[0005] Fig. 8A is a front view of an MLCC, and Fig. 8B is a cross-sectional view of the MLCC. MLCC 100 has two electrodes 101a and 101b, and is configured by alternately laminating electrode layers 102 and high-dielectric-constant ceramic layers 103. However, MLCCs have the problem that parasitic capacitance is easily generated in electrodes 101a and 101b, making them difficult to use in the 100 GHz and higher frequency range due to degradation of characteristics.

[0006] FIG. 9A is a front view of a silicon capacitor, and FIG. 9B is a cross-sectional view of the silicon capacitor. Silicon capacitor 200 has a structure in which thin-film capacitor 202 is formed on silicon substrate 201. Furthermore, bumps 203a and 203b are formed to connect to the electrodes of thin-film capacitor 202. Because the capacitance of a silicon capacitor is formed from a thin film, it has an advantage of being similar to a transmission line structure and being less susceptible to characteristic degradation even in the high-frequency range. However, when attempting to further extend the characteristics of silicon capacitors up to around 150 GHz, there was a problem in that characteristic degradation occurred around 125 GHz with conventional mounting structures, making it impossible to achieve the desired performance.

[0007] FIG. 10A shows a plan view of a conventional DC block structure using a silicon capacitor, and FIG. 10B shows a cross-sectional view of the DC block structure. In the conventional DC block structure, a silicon capacitor 200 is inserted between transmission lines 204a and 204b. Transmission lines 204a and 204b are formed on the surface of a dielectric 205. A ground conductor 206 is formed on the back surface of dielectric 205. Silicon capacitor 200 is connected to transmission lines 204a and 204b via bumps 203a and 203b (see Non-Patent Document 1).

[0008] The inventors discovered that the conventional DC block structure has a problem in that it generates a roll-off characteristic that increases insertion loss at frequencies below 150 GHz. The equivalent circuit of the bump 203a portion indicated by the dashed line 207 in Figure 10B is shown in Figure 11. In Figure 11, L represents the inductive component, C1 represents the capacitance component generated on the silicon capacitor 200 side, and C2 represents the capacitance component generated on the transmission line 204a side. The fact that bumps 203a and 203b function as a low-pass filter in this way is the cause of the roll-off characteristic at frequencies below 150 GHz. [Prior art documents] [Non-patent literature]

[0009] [Non-Patent Document 1] C. Bunel, et al., “Ultra thin low ESL and ultra wide broadband silicon capacitors”, proceedings of 2016 International Conference on Electronics Packaging (ICEP), 2016 Summary of the Invention [Problem to be solved by the invention]

[0010] The present invention has been made to solve the above-mentioned problems, and has an object to provide a wideband DC block structure having improved frequency characteristics compared to conventional DC block structures. [Means for solving the problem]

[0011] The DC block structure of the present invention comprises a dielectric, a first transmission line formed on a surface of the dielectric, a second transmission line formed on the surface of the dielectric and designed to have the same characteristic impedance as the first transmission line, a third transmission line formed on the surface of the dielectric to connect to the first transmission line and designed to have a higher characteristic impedance than the characteristic impedances of the first and second transmission lines, a fourth transmission line formed on the surface of the dielectric to connect to the second transmission line and designed to have a higher characteristic impedance than the characteristic impedances of the first and second transmission lines, and capacitors mounted on the third and fourth transmission lines to connect the third and fourth transmission lines in series. The capacitor is a silicon capacitor having a thin film capacitance formed on a silicon substrate, and is mounted on the third and fourth transmission lines via bumps. It is characterized by the following. [Effects of the Invention]

[0012] According to the present invention, by providing the third and fourth transmission lines, it is possible to impart peaking characteristics to the frequency characteristics of the DC block structure, thereby reducing the roll-off characteristics caused by the connection between the capacitor and the transmission lines and improving the frequency characteristics of the DC block structure. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a perspective view of a DC block structure according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a plan view of a DC block structure according to a first embodiment of the present invention. [Figure 2B] FIG. 2B is a cross-sectional view of a DC block structure according to a first embodiment of the present invention. [Figure 3A] FIG. 3A is a plan view of a DC block structure according to a second embodiment of the present invention. [Figure 3B] FIG. 3B is a cross-sectional view of a DC blocking structure according to a second embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing the simulation results of the frequency characteristics of a conventional DC block structure and a DC block structure according to the second embodiment of the present invention. [Figure 5A] FIG. 5A is a plan view of a DC block structure according to a third embodiment of the present invention. [Figure 5B] FIG. 5B is a cross-sectional view of a DC block structure according to a third embodiment of the present invention. [Figure 6] FIG. 6 is a perspective view of a DC block structure according to a fourth embodiment of the present invention. [Figure 7] FIG. 7 is a perspective view showing another example of a DC block structure according to the fourth embodiment of the present invention. [Figure 8A] FIG. 8A is a front view of the MLCC. [Figure 8B] FIG. 8B is a cross-sectional view of the MLCC. [Figure 9A] FIG. 9A is a front view of a silicon capacitor. [Figure 9B] FIG. 9B is a cross-sectional view of a silicon capacitor. [Figure 10A] FIG. 10A is a plan view of a conventional DC block structure. [Figure 10B] FIG. 10B is a cross-sectional view of a conventional DC blocking structure. [Figure 11]FIG. 11 is an equivalent circuit diagram of a conventional DC block structure. DETAILED DESCRIPTION OF THE INVENTION

[0014] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a perspective view of a DC block structure according to a first embodiment of the present invention, Fig. 2A is a plan view of the DC block structure, and Fig. 2B is a cross-sectional view of the DC block structure. The DC block structure of this embodiment includes a dielectric 1, transmission lines 2a and 2b with a characteristic impedance of 50 Ω formed on the surface of the dielectric 1, a transmission line 3a formed on the surface of the dielectric 1 to connect to transmission line 2a and designed to have a higher characteristic impedance than the characteristic impedances of transmission lines 2a and 2b, a transmission line 3b formed on the surface of the dielectric 1 to connect to transmission line 2b and designed to have a higher characteristic impedance than the characteristic impedances of transmission lines 2a and 2b, a capacitor 4 mounted on transmission lines 3a and 3b to connect transmission lines 3a and 3b in series, and a ground conductor 5 formed on the back surface of the dielectric 1.

[0015] The characteristic impedance of transmission line 3b is the same as the characteristic impedance of transmission line 3a. As in conventional DC block structures, capacitor 4 is a silicon capacitor. Capacitor 4 has a structure in which thin-film capacitor 41 is formed on silicon substrate 40. Furthermore, bumps 42a and 42b are formed to connect to the electrodes of thin-film capacitor 41. One bump 42a of capacitor 4 is electrically connected to transmission line 3a, and the other bump 42b is electrically connected to transmission line 3b. In this way, capacitor 4 is flip-chip mounted on transmission lines 3a and 3b, and transmission lines 3a and 3b are connected in series via capacitor 4.

[0016] In this embodiment, the bumps 42a and 42b of the capacitor 4 also function as a low-pass filter, but the inductivity of the transmission lines 3a and 3b can impart peaking characteristics to the frequency characteristics. As a result, in this embodiment, the roll-off characteristics caused by the low-pass filter function can be reduced, and the frequency characteristics of the DC block structure can be improved.

[0017] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 3A is a plan view of a DC block structure according to the second embodiment of the present invention, and Fig. 3B is a cross-sectional view of the DC block structure. The same components as those in the first embodiment are designated by the same reference numerals. The DC block structure of this embodiment includes a dielectric 1, transmission lines 2a, 2b, 3a, and 3b, a capacitor 4, a ground conductor 5, a transmission line 6a formed on the surface of the dielectric 1 so as to be inserted between the transmission lines 2a and 3a and designed so that its characteristic impedance is a value between the characteristic impedances of the transmission lines 2a and 3a, and a transmission line 6b formed on the surface of the dielectric 1 so as to be inserted between the transmission lines 2b and 3b and designed so that its characteristic impedance is a value between the characteristic impedances of the transmission lines 2b and 3b.

[0018] The characteristic impedance of the transmission line 6b is the same as the characteristic impedance of the transmission line 6a. In this embodiment, the transmission line 2a and the transmission line 3a are connected via the transmission line 6a, and the transmission line 2b and the transmission line 3b are connected via the transmission line 6b, which makes it possible to generate multiple peaking frequencies in the frequency characteristics of the DC block structure and to flatten the frequency characteristics.

[0019] Figure 4 shows the simulation results of the frequency characteristics of a conventional DC block structure and the DC block structure of this embodiment. In Figure 4, 400 shows the frequency characteristics of the conventional DC block structure, and 401 shows the frequency characteristics of the DC block structure of this embodiment. It can be seen that this embodiment significantly improves the roll-off around 150 GHz that occurred in the conventional DC block structure.

[0020] [Third Example] Next, a third embodiment of the present invention will be described. Fig. 5A is a plan view of a DC block structure according to the third embodiment of the present invention, and Fig. 5B is a cross-sectional view of the DC block structure. The same components as those in the first embodiment are designated by the same reference numerals. The DC block structure of this embodiment includes a dielectric 1, transmission lines 2a, 2b, 3a, and 3b, a capacitor 4, a ground conductor 5, a transmission line 7a formed on the surface of the dielectric 1 so as to be inserted between the transmission lines 2a and 3a and designed so that its characteristic impedance is a value between the characteristic impedances of the transmission lines 2a and 3a, and a transmission line 7b formed on the surface of the dielectric 1 so as to be inserted between the transmission lines 2b and 3b and designed so that its characteristic impedance is a value between the characteristic impedances of the transmission lines 2b and 3b.

[0021] Transmission line 7a is a tapered transmission line in plan view whose width gradually changes from the width of transmission line 2a to the width of transmission line 3a. Similarly, transmission line 7b is a tapered transmission line in plan view whose width gradually changes from the width of transmission line 2b to the width of transmission line 3b. The characteristic impedance of transmission line 7b is the same as the characteristic impedance of transmission line 7a.

[0022] In this embodiment, the transmission line 2a and the transmission line 3a are connected via the transmission line 7a, and the transmission line 2b and the transmission line 3b are connected via the transmission line 7b, thereby making it possible to generate multiple peaking frequencies in the frequency characteristics of the DC block structure and to flatten the frequency characteristics.

[0023] [Fourth Example] In the first to third embodiments, the transmission lines 2a, 2b, 3a, 3b, 6a, 6b, 7a, and 7b are microstrip lines, but they may be coplanar lines or grounded coplanar lines.

[0024] Fig. 6 is a perspective view showing an example in which the transmission lines 2a, 2b, 3a, and 3b of the first embodiment are coplanar lines. Ground conductors 8 are formed on the dielectric 1 at positions on both outsides of the transmission lines 2a, 2b, 3a, and 3b along the propagation direction of signals propagating through the transmission lines 2a, 2b, 3a, and 3b. By using the configuration shown in Fig. 6, a DC block structure can be formed even when a ground conductor cannot be formed on the back surface of the dielectric 1, thereby increasing the degree of freedom in design.

[0025] Fig. 7 is a perspective view showing an example in which the transmission lines 2a, 2b, 3a, and 3b of the first embodiment are grounded coplanar lines. In the example of Fig. 7, ground conductors 8 are formed on the dielectric 1 at positions on both outsides of the transmission lines 2a, 2b, 3a, and 3b along the propagation direction of signals propagating through the transmission lines 2a, 2b, 3a, and 3b, and a ground conductor 5 is formed on the back surface of the dielectric 1.

[0026] 6 and 7 show configurations in which a coplanar line or a grounded coplanar line is applied to the first embodiment, but it goes without saying that they can also be applied to the second and third embodiments. That is, if ground conductors 8 are formed on both outer sides of transmission lines 2a, 2b, 3a, 3b, 6a, and 6b or on both outer sides of transmission lines 2a, 2b, 3a, 3b, 7a, and 7b, as in Fig. 6, a coplanar line configuration can be achieved. Furthermore, if a ground conductor 5 is formed on the back surface of dielectric 1, as in Fig. 7, a grounded coplanar line configuration can be achieved.

[0027] In a coplanar line or a grounded coplanar line, the characteristic impedance of each transmission line can be designed to a desired value by adjusting the distance between the transmission lines 2a, 2b, 3a, 3b, 6a, 6b, 7a, and 7b and the ground conductor 8.

[0028] [Fifth Example] In the first to fourth embodiments, the bumps 42a, 42b of the capacitor 4 may be solder bumps formed in a back-end process, or may be stud bumps formed using a wire bonder.

[0029] In the case of stud bumps, the bump height can be changed depending on the mounting conditions and bump material. By combining the bump height design with the line design, it is possible to expect further improvements in the frequency characteristics of the DC block structure. [Industrial Applicability]

[0030] The present invention can be applied to a technique for mounting a capacitor on a high-frequency line. [Explanation of symbols]

[0031] 1...dielectric, 2a, 2b, 3a, 3b, 6a, 6b, 7a, 7b...transmission lines, 4...capacitor, 5, 8...ground conductor, 40...silicon substrate, 41...thin film capacitor, 42a, 42b...bumps.

Claims

1. a dielectric; a first transmission line formed on a surface of the dielectric; a second transmission line formed on the surface of the dielectric and designed to have the same characteristic impedance as the first transmission line; a third transmission line formed on the surface of the dielectric so as to be connected to the first transmission line, the third transmission line being designed to have a characteristic impedance higher than the characteristic impedances of the first and second transmission lines; a fourth transmission line formed on the surface of the dielectric so as to be connected to the second transmission line, the fourth transmission line being designed to have a characteristic impedance higher than the characteristic impedances of the first and second transmission lines; a capacitor mounted on the third and fourth transmission lines so as to connect the third and fourth transmission lines in series; The DC block structure is characterized in that the capacitor is a silicon capacitor having a thin film capacitance formed on a silicon substrate, and is mounted on the third and fourth transmission lines via bumps.

2. 2. The DC blocking structure of claim 1, a fifth transmission line formed on the surface of the dielectric so as to be inserted between the first transmission line and the third transmission line, and designed so that its characteristic impedance is a value between the characteristic impedance of the first transmission line and the characteristic impedance of the third transmission line; a sixth transmission line formed on a surface of the dielectric so as to be inserted between the second transmission line and the fourth transmission line, the sixth transmission line being designed to have a characteristic impedance that is a value between the characteristic impedance of the second transmission line and the characteristic impedance of the fourth transmission line.

3. 3. The DC block structure of claim 2, the fifth transmission line is a transmission line having a tapered shape in a plan view, the width of which gradually changes from the width of the first transmission line to the width of the third transmission line, a sixth transmission line that is tapered in plan view and whose width gradually changes from the width of the second transmission line to the width of the fourth transmission line;

4. 4. The DC blocking structure according to claim 1, A DC blocking structure further comprising a ground conductor formed on a rear surface of the dielectric.

5. 2. The DC blocking structure of claim 1, A DC block structure further comprising a first ground conductor formed on the dielectric at a position outside both of the first, second, third, and fourth transmission lines.

6. 3. The DC block structure of claim 2, a first ground conductor formed on the dielectric at a position outside both of the first, second, third, fourth, fifth, and sixth transmission lines;

7. 7. The DC block structure according to claim 5 or 6, A DC blocking structure further comprising a second ground conductor formed on a rear surface of the dielectric.

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