Setting the upper limit of RRAM resistance

Abstract

The electronic circuit includes a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points, and a plurality of resistive change memory cells located at the plurality of grid points, each of the resistive change memory cells including an upper metal coupled to one of a corresponding one of the word lines and a corresponding one of the bit lines, a lower metal coupled to the other of the corresponding one of the word lines and the corresponding one of the bit lines, a dielectric sandwiched between the upper metal and the lower metal, and a high resistance semiconductor spacer in parallel with the dielectric and electrically connecting the upper metal and the lower metal.

Description

[Technical Field]

[0001] The present invention relates to the electrical, electronic and computer fields, and more particularly to resistive memory. [Background technology]

[0002] Resistive random access memory (ReRAM or RRAM), often referred to as memristor, is a type of non-volatile random access memory (RAM) that operates by changing the resistance of a dielectric solid material. This technology shares some similarities with conductive bridge random access memory (CBRAM) and phase change memory (PCM). One type of RRAM is formed by creating filaments in a thin oxide film. In properly fabricated RRAM, an electric field can be used to create filaments that can change between a low resistance state (LRS), where a highly conductive path is formed in the oxide film, and a high resistance state (HRS), where no conductive path is formed in the oxide film.

[0003] RRAM is useful, for example, for artificial intelligence applications (e.g., neural network training / neural network inference). Summary of the Invention

[0004] The principles of the present invention provide a technique for setting an upper limit on RRAM resistance.

[0005] In one aspect, an exemplary electronic circuit includes a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points, and a plurality of resistive change memory cells located at the plurality of grid points, each of the resistive change memory cells including an upper metal coupled to one of a corresponding one of the word lines and a corresponding one of the bit lines, a lower metal coupled to the other of the corresponding one of the word lines and the corresponding one of the bit lines, a dielectric sandwiched between the upper and lower metals, and a high-resistivity semiconductor spacer in parallel with the dielectric electrically connecting the upper and lower metals.

[0006] According to another aspect, an exemplary method for fabricating a resistive memory is provided. The method includes forming a lower metal on a base structure including a lower contact, such that the lower metal is in contact with the lower contact. The method also includes forming a dielectric on the lower metal in contact with the lower metal, forming an upper metal on the dielectric in contact with the dielectric, and forming a hard mask on the upper metal in contact with the upper metal. The method further includes forming a high-resistivity semiconductor spacer that electrically contacts the upper metal and the lower metal. The method also includes depositing an interlayer dielectric over the hard mask and the high-resistivity spacer, forming a via and a trench in the interlayer dielectric, and filling the via and the trench with metal to form an upper contact that contacts the upper metal.

[0007] According to yet another aspect, an exemplary resistive memory cell for interconnecting word lines and bit lines includes an upper metal configured to couple to one of the word lines and the bit lines, a lower metal configured to couple to the other of the word lines and the bit lines, a switchable dielectric sandwiched between the upper and lower metals and electrically connecting the upper metal to the lower metal, the switchable dielectric adapted to adopt a high resistance state in response to a first applied electric field and a low resistance state in response to a second applied electric field, and a high resistance semiconductor spacer in parallel with the dielectric and electrically connecting the upper and lower metals, the high resistance semiconductor spacer having a resistance at least equal to but not more than 100 times the designed resistance of the switchable dielectric in its high resistance state.

[0008] In view of the above, the techniques of the present invention can provide substantial and beneficial technical effects. For example, one or more embodiments may provide one or more of the following:

[0009] Highly reliable RRAM modules, even in the presence of manufacturing defects.

[0010] Improved yield of RRAM modules.

[0011] Improved stability of the RRAM filament layer by sealing it away from air exposure.

[0012] These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 shows a prior art RRAM module. [Figure 2] A prior art RRAM module without a parallel resistor is shown with and without a properly formed upper limit resistor. [Figure 3] 1 illustrates an RRAM module with parallel resistors, according to an exemplary embodiment. [Figure 4] 1 illustrates the upper limit resistance for properly formed and unformed RRAM modules with parallel resistors, according to an exemplary embodiment. [Figure 5] The process steps for fabricating an RRAM module with parallel resistors according to one exemplary embodiment are shown in (A) through (H). [Figure 6] As known from the prior art, the resistivity of a TaN film varies depending on the nitrogen / tantalum ratio (N / Ta ratio). [Figure 7] 10 shows another RRAM module with a parallel resistor and a passivating liner according to another exemplary embodiment. [Figure 8] 1 illustrates a neural network array incorporating RRAM, according to an exemplary embodiment. [Figure 9] 1 illustrates a neural network array incorporating RRAM, according to an exemplary embodiment. [Figure 10] Optional use of the exemplary embodiment in series with a field effect transistor is shown. DETAILED DESCRIPTION OF THE INVENTION

[0014] In the fabrication of RRAM modules, filaments are typically formed in thin oxide films. Proper operation of the module depends on the proper formation of the filaments. However, if the filaments are excessively formed, the RRAM module will develop a "short" (resistance too low) that prevents it from reaching its high resistance state (HRS). If the filaments are under-formed, the RRAM module will develop an "open" (resistance too high) that prevents it from reaching its low resistance state (LRS). Such shorts and opens can cause errors in matrix multiplication operations that rely on RRAM, such as in artificial intelligence applications (e.g., neural network training / inference).

[0015] A one-transistor, one-resistor (hereinafter referred to as "1T1R") configuration can be used to reduce the possibility of short circuits. In a 1T1R configuration, the transistor in series with the RRAM module does not conduct current unless it is switched on. The transistor is switched off by the same signal that sets the RRAM module to HRS, so even if the RRAM module is shorted, the transistor in the switched-off state simulates the expected HRS. In other words, the 1T1R scheme provides a lower bound on the RRAM resistance in the high-resistance state.

[0016] One or more embodiments advantageously provide an upper limit to the RRAM resistance in any state. The upper limit is provided by forming a high resistance structure (high resistance spacer) in parallel with the module, integrally with the module body. In one or more exemplary embodiments, a metal-insulator transition material (e.g., TiO) is used. x N y -titanium oxynitride) can be used in high resistance structures. In one or more embodiments, Ta x N y (Tantalum nitride) film or Ti x N y A (titanium nitride) film can be used.

[0017] For comparison, Figure 1 shows a prior art RRAM module 100 without a parallel resistor. The RRAM module 100 comprises an upper metal 102, a lower metal 104, and an oxide film 106 (typically HfO x (hafnium oxide) film, but is not limited to WO x , TaO x , TiO x , NiO x , SiO x The oxide film 106 includes a dielectric layer 108 (other materials such as Hf, GeS, and GeSe are also possible). The oxide film 106 acts as an intentionally defective dielectric, and by applying a sufficient electric field, a Hf filament (not shown in FIG. 1 ) can be tuned to conduct through the film. In this way, when the filament is properly formed, the oxide film 106 becomes a "switchable" dielectric, capable of switching between a low-resistance state and a high-resistance state. When the filament is not formed, the RRAM module 100 simply becomes a capacitor.

[0018] 2 shows the upper resistance R of the module 100 for two different scenarios: properly filamented (reference numeral 200) and unfilamented (reference numeral 210). In scenario 200, in the high resistance state, R=R HRS (Design value). In scenario 210, R is always ∞.

[0019] 3 shows an RRAM module 300 with a parallel resistor 301 according to an exemplary embodiment. The parallel resistor (high-resistivity semiconductor spacer) 301 is made of a high-resistivity semiconductor material, such as Ti. x N y , Ta x N y , TaO x N y3. In one or more embodiments, the "semiconductor" refers to a resistivity in the range of about 100 μΩ / cm to about 5000 μΩ / cm, by way of example only. In one or more embodiments, the parallel resistor has a resistivity in the range of about 500 μΩ / cm to about 2000 μΩ / cm. In addition to the upper metal 302, the lower metal 304, and the oxide film (switchable dielectric) 306 (formed similarly to the switchable dielectric 106), the parallel resistor 301 provides an additional conductive path through the module from the upper metal 302 to the lower metal 304. In this manner, even if the filament of the module 300 is not formed, there is a conductive path through the module from the upper contact 318 to the lower contact 320. Note that in typical capacitance devices, it is not desirable to include a parallel resistor 301, which would bypass the dielectric, in an electrical shunt. Note also that filaments are inherently minute and cannot be illustrated, but are well known to those skilled in the art.

[0020] 4 illustrates the upper resistance R of module 300 for two different scenarios: when the filament is properly formed (reference numeral 400) and when the filament is not formed (reference numeral 410). In scenario 400, R=R HRS ||R 301 In the high resistance state, R → R HRS Therefore, R 301 is R HRS In scenario 410, R → R is always selected. 301 Therefore, R=∞||R 301 As will be appreciated by those skilled in the art, a parallel resistor circuit is one in which multiple resistors are connected to the same two points (or nodes), and is identified by the fact that there are multiple current paths connected to a common voltage source. n In this case, the combined resistance of the parallel resistors R T is R T =(1 / R1+1 / R2+…+1 / R n ) -1 It is calculated by R 301 >>RHRS In the first case, 1 / R 301 is 1 / R HRS In the latter case, as R → ∞, 1 / R approaches zero, and 1 / R 301 becomes negligibly small compared to

[0021] As shown in FIGS. 5(A) to 5(H), forming the parallel resistor 301 involves adding a step to the process 500 for fabricating RRAM.

[0022] 5A illustrates step 502 (in reality, several steps are combined for clarity) of the RRAM stack deposition of top metal 302, oxide 306, bottom metal 304, and hard mask 308 onto base structure 310 (note also bottom contact 320). Note that conventional semiconductor fabrication techniques may be used to fabricate one or more embodiments in accordance with the teachings herein.

[0023] FIG. 5(B) shows step 504, lithography of the RRAM pillars with photoresist 312.

[0024] FIG. 5C shows step 506, reactive ion etching (RIE) of the RRAM pillars.

[0025] FIG. 5(D) shows step 508, depositing high-resistivity material 301. High-resistivity material combines metallic with non-metallic materials to produce a lower, though still more conductive, conductivity than those typically used for spacers around capacitors. Generally, the composition of high-resistivity material 301 is: A X B YFor example, A may be a metal element such as (but not limited to) Ta or Ti, and B may be an alloying material such as (but not limited to) N or O that makes the material semiconductive. Different deposition processes may be used, for example, plasma atomic layer deposition (p-ALD) or thermal atomic layer deposition (t-ALD). The selection of the appropriate deposition process will affect the resistivity and other properties of the high-resistivity material 301.

[0026] FIG. 5(E) shows step 510, a spacer metal etch of the high resistivity material 301.

[0027] FIG. 5(F) shows step 512, in which chemical mechanical polishing is performed after the deposition of the interlayer insulating film 312.

[0028] FIG. 5G illustrates step 514, which involves etching top contact vias 314 through the hard mask 308 and etching trench patterns 316 in the interlayer dielectric 312 (shown in FIG. 5F).

[0029] FIG. 5(H) shows step 516, metallization of the top contact by filling trench 316 with metal to form top contact 318.

[0030] In one or more embodiments, the high-resistivity semiconductor material 301 is a TaN or TiN film. The resistivity of such a film is a function of the nitrogen flow rate during deposition. For example, Figure 6 shows a TaN film, plotting its electrical resistivity in mΩ·cm (milliohm·centimeter) (logarithmic scale) against the N / Ta ratio determined by Rutherford backscattering spectrometry (RBS), showing that the resistivity of TaN films can vary from 100 μΩ·cm (microohm·centimeter) to 5000 μΩ·cm, as known from the prior art.

[0031] In one or more embodiments, as shown in FIG. 7, in a modified RRAM 700, Ta x O y N z The film is used for the high-resistance parallel resistor (spacer) 701. The modified RRAM includes a stack 711 of an upper metal 702, an oxide 706, a lower metal 704, and a hard mask 708 on a base structure 710. The modified RRAM also includes a passivation layer 712 between the high-resistance material 701 and the stack 711. The passivation layer 712 prevents oxygen from diffusing from the TaON film into the oxide 706, which can adversely affect the filaments of the RRAM. In one or more embodiments, the passivation layer 712 is made of Si x N y or other non-conductive material. The passivation layer 712 is thin, about 1 nm to 2 nm thick, and prevents oxygen atoms from diffusing into the switchable dielectric 706, but allows electron tunneling from the top metal 702 to the parallel resistor 701 and from the parallel resistor 701 to the bottom metal 704.

[0032] In one or more embodiments, the high-resistivity material 301 or 701 has a resistance much higher than the resistance of the switchable dielectric 306 or 706 in its high-resistivity state. For example, in one or more embodiments, the parallel resistor 301 has a resistance at least 10 times the design resistance of the switchable dielectric 306 in its high-resistivity state. In one or more embodiments, the resistance of the parallel resistor 301 is no more than 20 times the design resistance of the switchable dielectric 306 in its high-resistivity state. The thickness T of the parallel resistor 301 is selected to provide a required cross-section according to the resistance of the parallel resistor 301 and the design resistance of the switchable dielectric 306 in its high-resistivity state. For example, in one or more embodiments, the switchable dielectric is 2 nm to 10 nm thick. Depending on the circumstances, in one or more embodiments, the parallel resistor 301 or 701 is 1 nm to 50 nm thick. For example, the parallel resistor 301 or 701 is 1 nm to 25 nm thick, and in one or more embodiments, 5 nm to 15 nm thick. Thus, in one or more embodiments, the high-resistivity semiconductor spacer (parallel resistor 301 or 701) has a cross-sectional area that is 25 times or less the thickness of the switchable dielectric, and in one or more embodiments, the high-resistivity semiconductor spacer has a cross-sectional area that is half or more the thickness of the switchable dielectric.

[0033] The material composition of the parallel resistor 301 or 701 is chosen for compatibility with the switchable dielectric, e.g., oxide is not used for the parallel resistor 301. If oxide is used, as in the parallel resistor 701, it is Si x N y A passivation layer 712, such as the one shown in FIG. 7, is disposed between the parallel resistor 701 and the switchable dielectric 706. In one or more embodiments, the passivation layer 712 is very thin, between 1 nm and 5 nm, to block oxygen while being thin enough to bypass the resistor and allow tunneling. In one or more embodiments, the passivation layer 712 is between 1 nm and 2 nm thick.

[0034] In one or more embodiments, cells 300 or 700 are incorporated into a neural network array, as shown in Figures 8 and 9. The neural network array includes word lines 801-1, 801-2 and bit lines 803-1, 803-2 (only two of each are shown for simplicity). At each grid point (the intersection of a word line and a bit line), a cell is located.

[0035] Typically, neural networks are trained using a backpropagation algorithm, where training data is fed to the network at the front end and propagated "forward" through the network to the back end. The network's output at the back end is then compared to expected results, provided a priori by expert knowledge. The error between the output and the expected result is calculated and used to derive an error gradient. The error gradient is then propagated "backward" through the network (from the back end to the front end) to update the weights assigned to each neuron's input. This forward and backpropagation process is repeated to gradually reduce the error by iteratively updating the weights until a desired error value or rate (e.g., less than 3%) is achieved. Training a large neural network is typically a time-consuming, computationally intensive task, requiring data center-scale computer resources for many days. The concept of resistive crosspoint memory (RRAM) devices could potentially accelerate neural network training by orders of magnitude while using less computational power.

[0036] Training an RRAM differs from training a typical neural network processing unit. In one embodiment, an RRAM module is trained using a backpropagation method, which includes three cycles: a forward cycle, a backward cycle, and a weight update cycle (hereafter referred to as "weight update" for short). The forward and backward cycles primarily require computational computation of vector-matrix multiplications in forward and backward directions. The weights associated with an RRAM module can be updated by a simple AND operation between two voltages: one representing activity at the input to the RRAM module (e.g., on the word line) and the other representing the error calculated by the output neuron (e.g., on the bit line). When a positive or negative bit matches, the conductivity of the RRAM module increases or decreases, thereby adjusting the corresponding weight. The length of the bit stream determines the accuracy of the weight update to any given strictness. A stream with more bits moves the weight closer to the "true" value to correct the error.

[0037] Figure 8 shows the backward cycle, in which peripheral circuitry 895 applies voltage vectors to word lines 801-1, 801-2 and integrator 811 integrates the column current. The forward cycle is the same, except that voltage vectors are applied to the columns and the integrator integrates the rows. Figure 9 shows the stochastic update, in which stochastic translators (STRs) 891 apply stochastic pulses to the word lines and bit lines. Voltage source 899 and control circuitry 897 provide the operating voltages and control the application of the voltage vectors, stochastic pulses, and integration. Those skilled in the art will be familiar with the operation and control of an array of RPUs, for example, from Gokmen T. and Vlasov Y., “Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations”, Front. Neurosci. 10:333, doi: 10.3389 / fnins.2016.00333, 21 July 2016. and Gokmen T., Onen M. and Haensch W., “Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices”, Front. Neurosci. 11:538. doi: 10.3389 / fnins.2017.00538, 10 October 2017.

[0038] Referring to FIG. 10, as noted above, in some cases, a one transistor, one resistor ("1T1R") configuration can be used to reduce the likelihood of a potential short circuit. In a 1T1R configuration, transistor 1001, which is in series with RRAM module 300, 700, does not conduct current unless it is switched on. Because the transistor is switched off by the same signal that sets the RRAM module to its HRS, even if the RRAM module is shorted, the transistor in its switched-off state simulates the expected HRS. In other words, the 1T1R configuration provides a lower bound on the RRAM resistance in the high-resistance state. Modules 300, 700 can be used in this manner in accordance with aspects of the present invention, thus advantageously setting both a lower and upper bound. Note the word line WL (connected to the gate of the transistor), bit line BL, and source line SL, which connect to the source of transistor 1001 in a known manner.

[0039] Generally, the top contact 318 and bottom contact 320 are each coupled to a corresponding word line or bit line at the grid point, either directly or through an intervening element such as one or more transistors 1001 .

[0040] One or more embodiments are suitable for performing multiply-accumulate (MAC) operations, for example, for machine learning, such as turning on all word lines 801-1, 801-2 to input all information and output all results at once (i.e., using massively parallel memory computation rather than using only one word line at a time as in conventional memories).

[0041] In view of the foregoing discussion, in general, in accordance with an embodiment of the present invention, an exemplary electronic circuit includes a plurality of word lines 801-1, 801-2, a plurality of bit lines 803-1, 803-2 intersecting the plurality of word lines at a plurality of grid points, and a plurality of resistive change memory cells 300, 700 located at the plurality of grid points. Each of the resistive change memory cells includes an upper metal 302 coupled to one of a corresponding one of the word lines and a corresponding one of the bit lines, a lower metal 304 coupled to the other of the corresponding one of the word lines and the corresponding one of the bit lines, a dielectric 306 sandwiched between the upper and lower metals, and a high-resistivity semiconductor spacer 301 electrically connecting the upper and lower metals in parallel with the dielectric. References to components in FIG. 3 can be applied, and as will be understood, references to similar components in FIG. 7 can also be applied.

[0042] In one or more embodiments, dielectric 306 is a switchable dielectric adapted to assume a high resistance state in response to a first applied electric field and a low resistance state in response to a second applied electric field, and high resistance semiconductor spacer 301 has a resistance that is at least 10 times the design value of the resistance of the switchable dielectric in its high resistance state, where the design value is a value intended by the designer and can be clearly identified by the value exhibited by most of the cells in the matrix, for example, with the reasonable assumption that only a small number of cells will have manufacturing defects.

[0043] In one or more embodiments, the high-resistivity semiconductor spacer has a resistance that is 20 times or less than the design resistance of the switchable dielectric in the high-resistivity state. In one or more embodiments, the high-resistivity semiconductor spacer has a cross-sectional area that is 200 times or less than the cross-section of the design filament of the switchable dielectric. In one or more embodiments, the high-resistivity semiconductor spacer has a cross-sectional area that is 50 times or more than the cross-section of the design filament of the switchable dielectric. Again, the design value or design filament is a value intended by the designer and can be clearly identified by the value exhibited by most of the cells in the matrix, for example, with the reasonable assumption that only a small number of cells will have manufacturing defects.

[0044] In one or more embodiments, cell 700 also includes a passivation layer 712 between high-resistivity semiconductor spacer 701 and switchable dielectric 706. The passivation layer is thick enough to block oxygen diffusion and thin enough to allow electron tunneling. In one or more embodiments, high-resistivity semiconductor spacer 701 includes a metal oxide and passivation layer 712 includes one of a nitride and a carbide. In one or more embodiments, the high-resistivity semiconductor spacer includes tantalum oxide and the passivation layer includes silicon nitride.

[0045] In one or more embodiments, the switchable dielectric 306 or 706 comprises hafnium oxide and the high-resistivity semiconductor spacer 301 or 701 comprises one of titanium nitride and tantalum nitride, hi one or more embodiments, the high-resistivity semiconductor spacer comprises Ta4N5.

[0046] According to another aspect, an exemplary method 500 for fabricating a resistive memory is provided. At 502, a lower metal 304 is formed on a base structure 310 including a bottom contact 320, the lower metal 304 contacting the bottom contact, a dielectric 306 is formed on the lower metal, the upper metal 302 is formed on the dielectric, and a hard mask 308 is formed on the upper metal, the hard mask 308 is formed on the upper metal, and the upper metal is in contact with the dielectric. At 510, a high-resistivity semiconductor spacer 301 is formed to electrically contact the upper and lower metals. At 512, an interlayer dielectric 316 is deposited over the hard mask and the high-resistivity spacer. At 514, a via and a trench are formed in the interlayer dielectric. At 516, the via and the trench are filled with metal 318 to form a top contact that contacts the top metal.

[0047] In one or more embodiments, the method also includes forming the dielectric as a switchable dielectric adapted to adopt a high resistance state in response to a first applied electric field and a low resistance state in response to a second applied electric field. In one or more embodiments, the method also includes forming the high-resistivity semiconductor spacer to have a resistance at least 10 times the design value of the resistance of the switchable dielectric in the high-resistivity state. In one or more embodiments, the method also includes forming the high-resistivity semiconductor spacer to have a resistance no greater than 20 times the design value of the resistance of the switchable dielectric in the high-resistivity state. In one or more embodiments, the switchable dielectric includes hafnium oxide. In one or more embodiments, the high-resistivity semiconductor spacer includes one of titanium nitride and tantalum nitride. In one or more embodiments, the high-resistivity semiconductor spacer includes a metal oxide, and the method further includes forming a passivation layer 712 containing nitride between the switchable dielectric and the high-resistivity semiconductor spacer.

[0048] In one or more embodiments, the method also includes forming a high-resistivity semiconductor spacer having a cross-sectional area that is 200 times or less than the cross-section of the design filament of the switchable dielectric. In one or more embodiments, the method also includes forming a high-resistivity semiconductor spacer having a cross-sectional area that is 50 times or more than the cross-section of the design filament of the switchable dielectric.

[0049] According to another aspect, a resistive memory cell for interconnecting word lines 801-1, 801-2 and bit lines 803-1, 803-2 includes an upper metal 302, a lower metal 304, a switchable dielectric 306 sandwiched between the upper and lower metals and electrically connecting the upper metal to the lower metal, and a high-resistivity semiconductor spacer 301 electrically connecting the upper and lower metals. The switchable dielectric is adapted to assume a high-resistivity state in response to a first applied electric field and a low-resistivity state in response to a second applied electric field. The high-resistivity semiconductor spacer has a resistance that is at least 10 times but not more than 20 times a designed resistance of the switchable dielectric in its high-resistivity state. The upper metal is coupled to one of the word lines and the bit lines, and the lower metal is coupled to the other of the word lines and the bit lines.

[0050] As noted above, the drawings depict exemplary process steps / stages in the fabrication of exemplary structures. While the overall fabrication method and the structures formed thereby are entirely novel, certain individual process steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. Such techniques and tooling will already be familiar to those skilled in the art to which the teachings herein relate. Furthermore, one or more of the process steps and tooling used to fabricate semiconductor devices will be apparent to those skilled in the art, as they are described in many readily available publications, including, for example, more recent technical articles and / or textbooks, as well as James D. Plummer et al., Silicon VLSI Technology: “Fundamentals, Practice, and Modeling” 1st Edition, Prentice Hall, 2001. While several individual process steps are illustrated herein, it is emphasized that these steps are for illustrative purposes only, and that those skilled in the art will be familiar with several equally suitable alternatives that may be applicable.

[0051] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or to be limited to the disclosed embodiments. Various adjustments and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, their practical application to commercially recognized technologies, or technical improvements, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0052] In a preferred embodiment of the present invention, a resistance change memory cell for interconnection between word lines and bit lines is provided, comprising: an upper metal configured to couple to one of the word lines and the bit lines; a lower metal configured to couple to the other of the word lines and the bit lines; a switchable dielectric sandwiched between the upper and lower metals and electrically connecting the upper metal to the lower metal, the switchable dielectric adapted to adopt a high resistance state in response to a first applied electric field and to adopt a low resistance state in response to a second applied electric field; and a high resistance semiconductor spacer in parallel with the dielectric and electrically connecting the upper and lower metals, the high resistance semiconductor spacer having a resistance of at least 10 times and not more than 20 times a designed value of the resistance of the switchable dielectric in its high resistance state.

Claims

1. a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; a plurality of variable resistance memory cells located at the plurality of grid points; an electronic circuit comprising: an upper metal coupled to one of the corresponding one of the word lines and the corresponding one of the bit lines; a lower metal coupled to the other of the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the upper metal and the lower metal; a high-resistivity semiconductor spacer electrically connecting the upper metal and the lower metal in parallel with the dielectric; a passivation layer between the high-resistivity semiconductor spacer and the dielectric; wherein each of the resistive change memory cells is configured to change resistance by creating a conductive path in the dielectric.

2. 2. The electronic circuit of claim 1, wherein the dielectric comprises a switchable dielectric adapted to adopt a high resistance state in response to a first applied electric field and a low resistance state in response to a second applied electric field, and wherein the high resistance semiconductor spacer has a resistance at least equal to a designed value of the resistance of the switchable dielectric in its high resistance state.

3. An electronic circuit as described in claim 2, wherein the passivation layer is thick enough to block oxygen diffusion and thin enough to allow electron tunneling.

4. 4. The electronic circuit of claim 2, wherein the high-resistivity semiconductor spacer has a resistance that is no more than 20 times the design value of the resistance of the switchable dielectric in the high-resistivity state.

5. 4. The electronic circuit of claim 2, wherein the high-resistivity semiconductor spacer has a resistance that is at least 10 times the design value of the resistance of the switchable dielectric in the high-resistivity state.

6. The electronic circuit of any one of claims 1 to 5, wherein the high-resistivity semiconductor spacer comprises a metal oxide and the passivation layer comprises one of a nitride and a carbide.

7. 6. The electronic circuit of claim 1, wherein the high-resistivity semiconductor spacer comprises tantalum oxide and the passivation layer comprises silicon nitride.

8. The electronic circuit of any one of claims 2 to 5, wherein the switchable dielectric comprises hafnium oxide and the highly resistive semiconductor spacer comprises one of titanium nitride and tantalum nitride.

9. The high resistance semiconductor spacer is Ta ４ N ５ 9. The electronic circuit of claim 8, comprising:

10. A method for producing a resistance change type memory configured to change resistance by generating a conductive path in a dielectric, comprising: forming a bottom metal on a base structure including a bottom contact in contact with said bottom contact; forming a dielectric on and in contact with the lower metal; forming a top metal over and in contact with the dielectric; forming a hard mask on and in contact with the top metal; forming a high-resistivity semiconductor spacer in electrical contact with the upper metal and the lower metal; depositing an interlayer dielectric over the hard mask and the high-resistivity semiconductor spacers; forming a via and a trench in the interlayer insulating film; and filling the vias and trenches with metal to form top contacts in contact with the top metal; A method comprising:

11. 11. The method of claim 10, further comprising forming the dielectric as a switchable dielectric adapted to adopt a high resistance state in response to a first applied electric field and a low resistance state in response to a second applied electric field.

12. 12. The method of claim 11, further comprising forming the high resistance semiconductor spacer to have a resistance equal to or greater than a design resistance of the switchable dielectric in the high resistance state.

13. 13. The method of claim 12, further comprising forming the high resistance semiconductor spacer to have a resistance at least ten times the design value of the resistance of the switchable dielectric in the high resistance state.

14. 13. The method of claim 12, further comprising forming the high resistance semiconductor spacer to have a resistance that is no more than 20 times the design value of the resistance in the high resistance state of the switchable dielectric.

15. The method of claim 11 , wherein the switchable dielectric comprises hafnium oxide.

16. 16. The method of claim 15, wherein the high-resistivity semiconductor spacer comprises one of titanium nitride and tantalum nitride.

17. 17. The method of claim 16, wherein the high-resistivity semiconductor spacer comprises a metal oxide, and further comprising forming a passivation layer between the switchable dielectric and the high-resistivity semiconductor spacer that comprises a nitride.

18. A resistive memory cell for interconnecting a word line and a bit line, a top metal configured to couple to one of the word line and the bit line; a bottom metal configured to couple to the other of the word line and the bit line; a switchable dielectric sandwiched between the upper metal and the lower metal, electrically connecting the upper metal to the lower metal, the switchable dielectric adapted to assume a high resistance state in response to a first applied electric field and a low resistance state in response to a second applied electric field; a high-resistivity semiconductor spacer electrically connecting the upper metal and the lower metal in parallel with the dielectric, the high-resistivity semiconductor spacer having a resistance that is at least 10 times but not more than 20 times a design resistance of the switchable dielectric in a high-resistivity state; a passivation layer between the high-resistivity semiconductor spacer and the dielectric; wherein the resistance of the memory cell is changed by creating a conductive path in the dielectric.

19. The resistive memory cell of claim 18, wherein the passivation layer is thick enough to block oxygen diffusion and thin enough to allow electron tunneling.

Images