Heterostructure interconnects for high frequency applications.

Abstract

To provide an interconnection structure in an integrated circuit.SOLUTION: An integrated circuit 100 includes an interconnection 124, and the interconnection 124 includes a metal layer 130, a graphene layer 132 on at least one of the top surface of the metal layer 130 or the bottom surface of the metal layer 130, and a hexagonal boron nitride (hBN) layer 134 on the graphene layer 132, opposite the metal layer 130. A dielectric material 116 of the integrated circuit is in contact with the hBN layer 134. The graphene layer 132 is composed of one or more atomic layers of graphene. The hBN layer 134 has the thickness of one to three atomic layers. The interconnection 124 includes a lower hBN layer 126. The metal layer 130 has a lower graphene layer 128 on the bottom surface, an upper hBN layer 134 on the top surface, and an upper graphene layer 132 on the top surface of the metal layer 130.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application relates generally to integrated circuits, and more particularly to interconnect structures in integrated circuits. [Background technology]

[0002] Integrated circuits are being fabricated with increasingly smaller components and interconnects. Metal interconnects, including etched aluminum interconnects and copper damascene interconnects, have difficulty handling increasing current densities. It may also be desirable to reduce the thickness of the interconnects, exacerbating the current density problem. Graphene, which has very high in-plane conductivity, has been proposed as an interconnect material. However, graphene layers thicker than a few atomic layers tend to exhibit degraded conductivity. Integrating thin layers of graphene into integrated circuits has been problematic due to distortion of the graphene by dielectric materials adjacent to it. Summary of the Invention

[0003] In the described example, an integrated circuit includes an interconnect, the interconnect including a metal layer, a layer of graphene on at least one of the top surface of the metal layer or the bottom surface of the metal layer, and a layer of hexagonal boron nitride (hBN) on the graphene layer opposite the metal layer. A dielectric material of the integrated circuit contacts the layer of hBN opposite the graphene layer. The layer of graphene is comprised of one or more atomic layers of graphene. The layer of hBN is 1 to 3 atomic layers thick. [Brief explanation of the drawings]

[0004] [Figure 1] 1 is a cross-section of an example integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer, according to one embodiment.

[0005] [Figure 2A]1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2B] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2C] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2D] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2E] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2F] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2G] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 2H] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment.

[0006] [Figure 3A] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3B]1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3C] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3D] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3E] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3F] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3G] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 3H] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment.

[0007] [Figure 4] 1 is a cross-section of an example integrated circuit including a damascene copper interconnect having a lower graphene layer and an upper graphene layer, according to one embodiment.

[0008] [Figure 5A] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 5B]1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 5C] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 5D] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 5E] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 5F] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment. [Figure 5G] 1A-1C are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer illustrating successive stages of its formation according to one embodiment.

[0009] [Figure 6] 1 is a cross-section of an example integrated circuit including a Litz wire including a metal interconnect including multiple segments each having a lower graphene layer and an upper graphene layer, according to one embodiment.

[0010] [Figure 7] FIG. 1 is a perspective view of Bernal graphene. DETAILED DESCRIPTION OF THE INVENTION

[0011] The drawings are not drawn to scale. Example embodiments are not limited by the depicted order of acts or events, as some acts or events may occur in different orders and / or concurrently with other acts or events. Additionally, not all depicted acts or events may be required to implement the methodology of an example embodiment.

[0012] The integrated circuit includes an interconnect disposed in an interconnect region, the interconnect including a metal layer, a layer of graphene on at least one of the top surface of the metal layer or the bottom surface of the metal layer, and a layer of hBN on the layer of graphene opposite the metal layer. The graphene layer can be, for example, 1 to 10 atomic layers thick to maintain desired electron mobility in the graphene. The graphene layer can include Bernal graphene, as described with reference to FIG. 7. The hBN layer is 1 to 3 atomic layers thick. A dielectric material in the interconnect region of the integrated circuit contacts the hBN layer. One example is described herein in which the metal layer includes an etched aluminum layer. Another example is described herein in which the metal layer includes a damascene copper layer. The graphene layer provides a highly conductive surface layer for the interconnect, which can advantageously improve conductivity at high frequencies, e.g., millimeter-wave or terahertz frequencies. Metallic interconnects suffer from increased impedance at high frequencies due to current flowing close to the metal surface (a phenomenon sometimes referred to as the "skin effect"). Graphene layers provide highly conductive layers at the top and / or bottom surfaces of the metal layer, thus mitigating the skin effect. The interconnects can be used in RF circuits or other high-frequency applications. The conductivity of the graphene layer is improved by increasing the number of atomic layers up to approximately 10 atomic layers. Beyond 10 atomic layers, graphene's conductivity has been observed to behave similarly to that of graphite. The hBN layer should desirably be thick enough to insulate the graphene layer from degradation by contact with dielectric materials, yet thin enough to provide adequate electrical connection to the graphene through contacts or vias in integrated circuits. Having 1 to 3 atomic layers of hBN has been shown to provide the desired balance between graphene degradation and electrical connectivity to the graphene layer.

[0013] For purposes of this description, the term "lateral" refers to directions parallel to the plane of the top surface of the integrated circuit, and the term "vertical" refers to directions perpendicular to the plane of the top surface of the integrated circuit.

[0014] FIG. 1 is a cross-section of an exemplary integrated circuit including an etched aluminum interconnect with a lower graphene layer and an upper graphene layer, according to one embodiment. The integrated circuit 100 includes a substrate 102 and an interconnect region 104 disposed over the substrate 102. The substrate 102 includes a semiconductor material 106, such as silicon, gallium nitride, or the like. An active component 108 is disposed within the semiconductor material 106. The active component 108 is shown in FIG. 1 as a metal-oxide-semiconductor (MOS) transistor 108 disposed in a doped well 110 in the semiconductor material 106, with the gate extending above the semiconductor material 106. Other representations of the active component 108 are within the scope of this example. The active component 108 may be laterally separated by field oxide 112 disposed within the substrate 102. The field oxide 112 may comprise a shallow trench isolation (STI) structure, as shown in FIG. 1, or may comprise local oxidation of silicon structures (LOCOS).

[0015] The interconnect region 104 in this embodiment includes a pre-metal dielectric (PMD) layer 114 disposed directly above the substrate 102 and the active components 108, a first intra-metal dielectric (IMD) layer 116 disposed directly above the PMD layer 114, a first inter-level dielectric (ILD) layer 118 disposed directly above the first IMD layer 116, and a second IMD layer 120 disposed directly above the first ILD layer 118.

[0016] The PMD cap layer 114 may include, for example, a silicon nitride PMD layer, a silicon dioxide gap fill layer, a phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) main layer, and a silicon nitride cap layer. A contact 122 is disposed through the PMD layer 114 and makes electrical connection to the active component 108. The contact 122 may include, for example, a titanium first liner in contact with the PMD layer 114, a titanium nitride second liner on the first liner, and a tungsten fill metal on the second liner.

[0017] The first IMD layer 116 may include one or more sublayers of dielectric material, including a low-k dielectric material and a cap layer of silicon nitride, silicon carbide, or silicon nitride carbide. A first-level interconnect 124 is disposed within the first buried layer 116. The first-level interconnect 124 makes electrical connection to the top of the contact 122. In this example, the first-level interconnect 124 includes a lower hBN metal 126 disposed on the PMD layer 114, a lower graphene layer 128 disposed directly on the lower hBN metal 126, a metal layer 130 disposed directly on the lower graphene layer 128, an upper graphene layer 132 disposed directly on the metal layer 130, and an upper hBN 134 disposed directly on the upper graphene layer 132. The dielectric material of the PMD layer 114 contacts the lower hBN layer 126 opposite the lower graphene layer 128. The dielectric material of the first buried layer 116 contacts the upper hBN layer 134 opposite the upper graphene layer 132. The metal layer 130 in this example includes an aluminum layer 136 disposed on the lower graphene layer 128 and a metal cap layer 138 disposed on the aluminum layer 136. The lower hBN layer 126 and the upper hBN layer 134 are each 1 to 3 atomic layers thick. The lower graphene layer 128 and the upper graphene layer 132 are each composed of one or more atomic layers of graphene. The aluminum layer 136 may be, for example, 50 nanometers to 1 micrometer thick and may contain a few percent silicon, copper, and / or titanium. The metal cap layer 138 may be, for example, 3 nanometers to 20 nanometers thick and may include, for example, titanium nitride to provide an anti-reflective layer, or may include, for example, copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, gold, or other metals suitable for catalysis of graphene.

[0018] The first ILD layer 118 may include one or more sub-layers of dielectric material, such as, for example, an etch stop layer of silicon nitride, a main layer of a low-k dielectric material such as silicon dioxide or organosilicate glass (OSG), and a cap layer of silicon nitride. A first-level via 140 extends through the first ILD layer 118 and any portion of the first IMD layer 116 above the first-level interconnect 124 to make electrical connection to the first-level interconnect 124. The first-level via 140 may extend to the upper graphene layer 132, the metal cap layer 138, or the aluminum layer 136. The first-level via 140 may include, for example, a liner including titanium or titanium nitride in contact with the first ILD layer 118 and a fill metal of tungsten on the liner.

[0019] The second IMD layer 120 may include one or more sublayers of dielectric material, including low-k dielectric materials and cap layers. A second-level interconnect 142 is disposed within the second IMD layer 120 and makes electrical connection to the top of the first-level via 140. The second-level interconnect 142 may optionally include underlying and / or upper graphene and hBN layers, similar to the first-level interconnect 124. The integrated circuit 100 may include additional ILD and IMD layers, vias, and interconnects. The additional interconnects may optionally include underlying and / or upper graphene and hBN layers, similar to the first-level interconnect 124.

[0020] 2A-2H are cross-sections of an integrated circuit including etched aluminum interconnects with lower and upper graphene layers, illustrating successive stages of formation according to one embodiment. Referring to FIG. 2A, an integrated circuit 200 includes a substrate 202 having a semiconductor material 206. Active components 208, shown as MOS transistors 208, are formed in the semiconductor material 206. Field oxide 212 may be formed in the substrate 202 to laterally isolate the active components 208.

[0021] A PMD layer 214 in the interconnect region of integrated circuit 200 is formed over substrate 202 and active components 208. PMD layer 214 may be formed by forming a series of sub-layers, such as a PMD liner of silicon nitride using a low-pressure chemical vapor deposition (LPCVD) process, a main layer of silicon dioxide-based dielectric material using a plasma-enhanced chemical vapor deposition (PECVD) process, or an ozone-assisted high-aspect-ratio process (HARP). PMD layer 214 may be planarized, for example, by an oxide chemical-mechanical polishing (CMP) process, before forming a cap layer of silicon nitride using a PECVD process.

[0022] Contact 222 is formed through PMD layer 214 and extends to active component 208. Contact 222 can be formed by etching a contact hole through PMD layer 214 and forming a titanium liner that extends over PMD layer 214 and into the contact hole by sputtering or an ionized metal plasma (IMP) process. A titanium nitride liner is formed on the titanium liner by reactive sputtering or atomic layer deposition (ALD). A layer of tungsten is formed on the titanium nitride liner by a metalorganic chemical vapor deposition (MOCVD) process to fill the contact hole. The tungsten, titanium nitride, and titanium are removed from above the top surface of PMD layer 214 by a tungsten CMP process, leaving the tungsten fill metal, titanium nitride liner, and titanium liner in the contact hole to provide contact 222.

[0023] A lower hBN layer is formed over PMD layer 214. In this example, the lower hBN layer is formed by an ALD process. The first step of the ALD process is shown in FIG. 2A. A boron-containing reactant gas, shown in FIG. 2A as a boron reactant gas, is flowed over integrated circuit 200. The boron-containing reactant gas may include, for example, boron trichloride (BCl) or borane (BH). The boron-containing reactant gas forms a boron-containing layer 244 over PMD layer 214 and on top of contact 222. The flow of the boron-containing reactant gas is then stopped, leaving boron-containing layer 244 in place for the second step of the ALD process.

[0024] Referring to FIG. 2B, a nitrogen-containing reactant gas, shown in FIG. 2B as a nitrogen reactant gas, is flowed over integrated circuit 200. The nitrogen-containing reactant gas may include, for example, ammonia gas (NH). Nitrogen from the nitrogen-containing reactant gas reacts with boron-containing gas 244 in FIG. 2A to form an atomic layer of lower hBN layer 226 over PMD layer 214 and on top of contact 222. The flow of nitrogen-containing reactant gas is then stopped. The ALD process described with reference to FIGS. 2A and 2B can be repeated to form a desired thickness of 1 to 3 atomic layers of lower hBN layer 226.

[0025] Referring to FIG. 2C , the lower graphene layer 228 is formed on the lower hBN layer 226 by a transfer process. The lower graphene layer 228 is first formed on a growth substrate 246, which may be, for example, a silicon wafer with a catalytic surface layer. The lower graphene layer 228 may be formed on the growth substrate by a chemical vapor deposition (CVD) or PECVD process at a high temperature, for example, above 800° C., that the integrated circuit 200 can withstand. The lower graphene layer 228 is then transferred to the integrated circuit 200, for example, by inducing stress between the lower graphene layer 228 and the growth substrate 246, separating the lower graphene layer 228 from the growth substrate 246. The bond between the lower graphene layer 228 and the lower hBN layer 226 may be strengthened by a combination of heat and pressure. The lower graphene layer 228 includes one or more atomic layers of graphene.

[0026] 2D , a metal layer 230 including an aluminum layer 236 and a metal cap layer 238 is formed on the lower graphene layer 228. The aluminum layer 236 may, for example, include at least 95 percent aluminum and a few percent silicon, copper, and / or titanium. In this example, the metal cap layer 238 includes a catalyst such as copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, and / or gold. The aluminum layer 236 may be formed by a sputtering process. The metal cap layer 238 may be formed by a sputtering process or an evaporation process. Prior to forming the metal cap layer 238, a metal isolation layer (not shown) may be formed on the aluminum layer 236 to reduce diffusion of aluminum into the metal cap layer 238 and reduce diffusion of the catalyst into the aluminum layer 236. The metal isolation layer may, for example, include titanium nitride or tantalum nitride.

[0027] An etch mask 248 is formed on metal layer 230 covering areas for subsequently formed first-level interconnects. Etch mask 248 may include photoresist formed by a photolithography process and may optionally include an anti-reflective layer such as a bottom anti-reflective coat (BARC) or the like. Alternatively, etch mask 248 may include a hard mask material such as silicon nitride and / or amorphous carbon.

[0028] 2E, the metal layer 230 and the lower graphene layer 228, and optionally the lower hBN layer 226, are removed in areas exposed by the etch mask 248 by a reactive ion etching (RIE) process using halogen and oxygen radicals 250. The RIE process can vary the type and concentration of the halogen and oxygen radicals 250 to remove various materials in the metal cap layer 238, the aluminum layer 236, the lower graphene layer 228, and the lower hBN layer 226. After the RIE process is completed, the etch mask 248 is removed. Organic materials and amorphous carbon in the etch mask 248 can be removed by an oxygen plasma process. Silicon nitride or other hard mask materials in the etch mask 248 can be removed by a plasma process using fluorine and oxygen radicals.

[0029] Referring to FIG. 2F, an upper graphene layer 232 is selectively formed on the metal cap layer 238 by a graphene PECVD process. In the graphene PECVD process, the integrated circuit 200 is heated to a temperature of, for example, 200° C. to 400° C. A carbon-containing reactant gas, denoted in FIG. 2F as a carbon reactant gas, is flowed over the integrated circuit 200, and radio frequency (RF) power, denoted in FIG. 2F as RF power, is applied to the carbon-containing reactant gas to generate carbon radicals on the integrated circuit 200. The carbon-containing reactant gas may include a linear alkane, such as methane, ethane, propane, and / or butane; an alcohol, such as ethanol; and / or a cyclic hydrocarbon, such as cyclobutane or benzene. Additional gases, such as hydrogen, argon, and / or oxygen, may be flowed over the integrated circuit 200. A catalyst in the metal cap layer 238 catalyzes and reacts with the carbon radicals to selectively form the upper graphene layer 232 on the metal cap layer 238. The upper graphene layer 232 includes one or more atomic layers of graphene. No graphene is formed on the integrated circuit 200 beyond the metal cap layer 238.

[0030] Referring to FIG. 2G , an upper hBN layer 234 is formed on the upper graphene layer 232, conformally formed on the lateral surfaces of the metal layer 230 and the lower graphene layer 228, and extending over the lower hBN 226 and / or PMD layer 214. The upper hBN layer 234 is formed by a boron nitride PECVD process in this example. A boron-containing reactant gas, shown in FIG. 2G as a boron reactant gas, and a nitrogen-containing reactant gas, shown as a nitrogen reactant gas, are simultaneously flowed over the integrated circuit 200. The boron-containing reactant gas may include, for example, boron trichloride or borane. The nitrogen-containing reactant gas may include, for example, ammonia gas. Additional gases, such as hydrogen and / or argon, may be flowed over the integrated circuit 200 along with the boron-containing reactant gas and the nitrogen-containing reactant gas. RF power, shown as RF power, is applied to the boron-containing and nitrogen-containing reactive gases to generate boron and nitrogen radicals above the integrated circuit 200. The boron and nitrogen radicals react on the integrated circuit 200 to form an upper hBN layer 234. The upper hBN layer 234 is 1-3 atomic layers thick. The combination of the lower hBN 226, lower graphene layer 228, metal layer 230, upper graphene layer 232, and upper hBN layer 234 provides the first level interconnect 224 of the integrated circuit 200.

[0031] Referring to FIG. 2H, a first IMD layer 216 is formed over the first-level interconnect 224 and PMD layer 214. The first IMD layer 216 may be formed by forming an etch stop layer of silicon nitride, followed by forming a main layer of OSG or silicon dioxide. The various layers of the first IMD layer 216 may be formed by separate PECVD processes. The main layer may be planarized by an oxide CMP process, followed by forming a cap layer of silicon nitride. Formation of the integrated circuit 200 continues by forming ILD layers, additional IMD layers, vias, and interconnects. Additional interconnects may be formed over the first-level interconnect 224 by processes similar to those described with reference to FIGS. 2A-2G.

[0032] 3A-3H are cross-sections of an integrated circuit including an etched aluminum interconnect with a lower graphene layer and an upper graphene layer, illustrating successive stages of formation according to another embodiment. Referring to FIG. 3A, an integrated circuit 300 includes a substrate 302 comprising a semiconductor material 306. Active components 308, shown as MOS transistors 308, are formed in the semiconductor material 306. Field oxide 312 may be formed in the substrate 302 to laterally separate the active components 308. A PMD layer 314 in the interconnect region of the integrated circuit 300 is formed over the substrate 302 and the active components 308. A contact 322 is formed through the PMD layer 314, extending to the active components 308.

[0033] A lower hBN layer 326 is formed on the PMD layer 314. In this example, the lower hBN 326 layer may be formed by an ALD process using a boron-containing reactant gas, shown in FIG. 3A as the boron reactant gas, and a nitrogen-containing reactant gas, shown as the nitrogen reactant gas, for example, as described with reference to FIGS. 2A and 2B.

[0034] 3B , a lower graphene layer 328 is formed on the hBN 326 using an additive process 352, such as an electrostatic deposition process, an inkjet process, or the like, by dispensing graphene flakes 354, optionally in combination with a carrier fluid. The additive process 352 can form the lower graphene layer 328 in areas for subsequently formed first-level interconnects, simplifying fabrication of the integrated circuit 300. The lower graphene layer 328 includes one or more atomic layers of graphene. Because hBN has a lattice spacing and atomic pattern that closely matches graphene, the graphene flakes can match the lattice of the lower hBN 326 to produce a continuous layer of graphene in the lower graphene layer 328 with desired values ​​of electrical properties, such as sheet resistance.

[0035] 3C , a metal layer 330 including an aluminum layer 336 and an optional metal cap layer 338 is formed on the lower graphene layer 328. In this example, the metal cap layer 338 may include titanium nitride to provide an anti-reflective layer and a diffusion barrier to contain aluminum. The aluminum layer 336 may be formed by a sputtering process. The metal cap layer 338 may be formed by a sputtering process or an ALD process.

[0036] 3D, an upper graphene layer 332 is formed on the metal layer 330. The upper graphene layer 332 may be formed by a transfer process from a growth substrate 346, as shown in FIG. 3D. The upper graphene layer 332 includes one or more atomic layers of graphene. Other methods of forming the upper graphene layer 332 are also within the scope of this example.

[0037] Referring to FIG. 3E, an upper hBN layer 334 is formed on the upper graphene layer 332. The upper hBN layer 334 is 1 to 3 atomic layers thick. The upper hBN layer 334 can be formed by a PECVD process using a boron-containing reactant gas, shown in FIG. 3E as a boron reactant gas, a nitrogen-containing reactant gas, shown as a nitrogen reactant gas, and one or more other gases. The boron-containing reactant gas can include boron trichloride and / or borane. The nitrogen-containing reactant gas can include ammonia gas. Other gases can include argon, hydrogen, and / or oxygen. RF power, shown as RF power, is applied to the boron-containing reactant gas, the nitrogen-containing reactant gas, and other gases to form boron radicals and nitrogen radicals. The boron radicals and nitrogen radicals react to form the upper hBN layer 334. Other processes for forming the upper hBN layer 334 are also within the scope of this example.

[0038] Referring to FIG. 3F, an optional protective layer 356 may be formed on the upper hBN layer 334. The protective layer 356 may comprise, for example, 10 to 50 nanometers of silicon dioxide formed by a PECVD process using tetraethyl orthosilicate (TEOS). An etch mask 348 is then formed on the upper hBN layer 334 and, if present, the protective layer 356. The etch mask 348 covers areas for the later-formed first-level interconnects. The etch mask 348 may be formed by a process similar to that described with reference to FIG. 2D. In this example, the etch mask 348 is aligned with the lower graphene layer 328. In this example, the purpose of the protective layer 356 is to protect the upper hBN layer 334 during subsequent removal of the etch mask 348.

[0039] 3G, protective layer 356, if present, upper hBN layer 334, upper graphene layer 332, metal layer 330, lower graphene layer 328, and optionally lower hBN layer 326 are removed in areas exposed by etch mask 348 by an RLE process using halogen and oxygen radicals 350. The type and concentration of halogen and oxygen radicals 350 can be varied as needed to remove different materials with desired etch profiles.

[0040] 3G, after the RIE process described with reference to FIG. 3H is completed, the etch mask 348 is removed, for example, by an oxygen plasma process using oxygen radicals 358. If present, the protective layer 356 protects the upper hBN layer 334 from damage by the oxygen radicals 358 during the removal of the etch mask 348.

[0041] The combination of lower hBN layer 326, lower graphene layer 328, metal layer 330, upper graphene layer 332, and upper hBN layer 334 provides first level interconnects 324 of integrated circuit 300. Formation of integrated circuit 300 continues by forming a first IMD layer between first level interconnects 324. Formation of integrated circuit 300 continues further by subsequently forming ILD layers, additional IMD layers, vias, and additional interconnects.

[0042] 4 is a cross-section of an example integrated circuit including a damascene copper interconnect having a lower graphene layer and an upper graphene layer, according to one embodiment. The integrated circuit 400 includes a substrate 402 and an interconnect region 404 disposed over the substrate 402. The substrate 402 includes a semiconductor material 406. Disposed within the semiconductor material 406 are active components 408, shown in FIG. 4 as being disposed in doped wells 410. The active components 408 may be laterally separated by field oxide 412 disposed within the substrate 402.

[0043] The interconnect region 404 in this example includes a PMD layer 414 disposed directly above the substrate 402 and active components 408, a first IMD layer 416 disposed directly above the PMD layer 414, and a first ILD interconnect region 418 disposed directly above the first IMD layer 416. Although not shown in FIG. 4 , additional IMD and ILD layers of the integrated circuit 400 extend above the first ILD layer 418. A contact 422 is disposed through the PMD layer 414 and makes electrical connection to the active components 408. The PMD layer 414 and the contact 422 may have a structure similar to that described with reference to FIG. 1 .

[0044] The first IMD layer 416 may include one or more sub-layers, including a silicon nitride etch stop layer, a main layer of low-k dielectric material, and a cap layer of silicon nitride, silicon carbide, or silicon nitride carbide. The first level interconnect 424 is disposed in the interconnect trench within the first IMD layer 416. The first level interconnect 424 makes electrical connection to the top of the contact 422. In this example, first-level interconnect 424 includes a lower hBN layer 426 disposed on PMD layer 414 and extending up the sidewalls of the interconnect trench to the top surface of first IMD layer 416, a lower graphene layer 428 disposed directly on lower hBN layer 426 and extending up the sides of first-level interconnect 424, a metal layer 430 disposed directly on lower graphene layer 428, an upper graphene layer 432 disposed directly on metal layer 430, and an upper hBN upper side 434 disposed directly on upper graphene layer 432 and extending over first IMD layer 416 adjacent first-level interconnect 424. Metal layer 430 in this example includes a damascene liner 438 disposed on lower graphene layer 428 and extending up the sides of first-level interconnect 424. The damascene liner 438 includes a copper diffusion barrier, such as tantalum nitride or the like. The metal layer 430 in this example further includes a damascene copper layer 436 disposed on the damascene liner 438. The upper graphene layer 432 is disposed directly on the damascene copper layer 436. The lower hBN layer 426 and the upper hBN layer 434 are each 1-3 atomic layers thick. The lower graphene layer 428 and the upper graphene layer 432 each include one or more atomic layers, such as 1-10 graphene layers. The dielectric material of the PMD layer 414 contacts the lower hBN layer 426, opposite the lower graphene layer 428.

[0045] The first ILD layer 418 may have a structure similar to that described with reference to Figure 1. The dielectric material of the first ILD layer 418 contacts the upper hBN layer 434, opposite the upper graphene layer 432.

[0046] 5A-5G are cross-sections of an integrated circuit including an etched aluminum interconnect with a lower graphene layer and an upper graphene layer, illustrating successive stages of formation according to one embodiment. Referring to FIG. 5A, an integrated circuit 500 includes a substrate 502 having a semiconductor material 506. Active components 508, shown as MOS transistors 508, are formed in the semiconductor material 506. A field oxide 512 may be formed in the substrate 502 to laterally isolate the active components 508. A PMD layer 514 is formed over the substrate 502 and the active components 508. A contact 522 is formed through the PMD layer 514 to make electrical connection to the active components 508.

[0047] A first IMD layer 516 is formed over the PMD layer 514 and the contact 522. The first IMD layer 516 may be formed, for example, by a series of PECVD processes. An interconnect trench 560 is formed through the first IMD layer 516 to expose the top of the contact 522. The interconnect trench 560 may be formed by an RIE process using an etch mask.

[0048] A lower hBN layer 526 is formed on the first IMD layer 516 and extends into the interconnect trench 560 and onto the PMD layer 514 at the bottom of the interconnect trench 560. The lower hBN layer 526 may be formed by an ALD process, a PECVD process, or another method. The lower hBN layer 526 is 1 to 3 atomic layers thick.

[0049] 5B, a lower graphene layer 528 is formed on the lower hBN layer. The lower graphene layer 528 extends into the interconnect trench 560 and is continuous along the lower hBN layer 526 at the bottom of the interconnect trench 560. The lower graphene layer 528 may be formed by, for example, a PECVD process or an additive process, which may be advantageous due to the topography of the interconnect trench 560.

[0050] 5C, a damascene liner 538 is formed on the lower graphene layer 528. The damascene liner 538 may include, for example, tantalum nitride. The damascene liner 538 may be formed by an ALD process to provide continuous coverage in the interconnect trench 560.

[0051] 5D , a damascene copper layer 536 is formed on the damascene liner 538, filling the interconnect trench 560. The damascene copper layer 536 may be formed, for example, by forming a copper seed layer (not shown in FIG. 5D ) directly on the damascene liner 538 by a sputtering process, followed by forming the remainder of the damascene copper layer 536 on the seed layer by an electroplating process. The electroplating process may use a combination of brightener, suppressor, and leveler additives to the electroplating bath to fill the interconnect trench 560 with the damascene copper layer 536 while minimizing the thickness of the electroplated copper on the first IMD layer 516 adjacent to the interconnect trench 560.

[0052] 5E, the damascene copper layer 536, the damascene liner 538, the lower graphene layer 528, and the lower hBN layer 526 are removed from over the first IMD layer 516 by a copper CMP process, which is shown schematically in FIG. 5E by copper CMP pad 562. The damascene copper layer 536, the damascene liner 538, the lower graphene layer 528, and the lower hBN layer 526 are left in place in the interconnect trench 560.

[0053] 5F, an upper graphene layer 532 is formed on a damascene copper layer 536. The upper graphene layer 532 includes one or more atomic layers of graphene and does not extend onto the first IMD layer 516 adjacent the interconnect trench 560. The upper graphene layer 532 may be formed by a PECVD process in which the damascene copper layer 536 selectively catalyzes the formation of graphene in a manner similar to the PECVD process described with reference to FIG. 2F, for example. Alternatively, the upper graphene layer 532 may be formed by an additive process, for example, as described with reference to FIG. 3B. Other methods of forming the upper graphene layer 532 are also within the scope of this example.

[0054] Referring to FIG. 5G, an upper hBN layer 534 is formed on the existing top surface of the integrated circuit 500, including the upper graphene layer 532. The upper hBN layer 534 may be formed by an ALD process, a PECVD process, or other methods. The lower hBN layer 526, the lower graphene layer 528, the damascene liner 538, the damascene copper layer 536, the upper graphene layer 532, and the upper hBN layer 534 provide the first level interconnect 524 of the integrated circuit 500. Formation of the integrated circuit 500 continues with the formation of a first ILD layer, not shown in FIG. 5G, on the upper hBN layer 534. The dielectric material of the first ILD layer contacts the upper hBN layer 534.

[0055] 6 is a cross-section of an example integrated circuit including a Litz wire including a metal interconnect including multiple segments, each having a lower graphene layer and an upper graphene layer, according to one embodiment. The integrated circuit 600 includes a substrate 602 and an interconnect region 604 disposed on the substrate 602. The substrate 602 includes semiconductor material and active components, for example, as described with reference to FIG. 1. The interconnect region 604 includes a dielectric material 664, such as a stack of dielectric layers, for example, as described with reference to FIG. 1. In this example, the integrated circuit 600 includes a Litz wire 666 including multiple strands of serially connected interconnect segments 624. In this example, each interconnect layer 624 has a metal layer 630, a lower graphene layer 628 on the bottom surface of metal layer 630, a lower hBN layer 626 on the lower graphene layer 628 opposite metal layer 630, an upper graphene layer 632 on the top surface of metal layer 630, and an upper graphene layer 632 on the upper graphene layer 632 opposite metal layer 630. Dielectric material 664 contacts lower hBN layer 626 opposite lower graphene layer 628 and contacts upper hBN layer 634 opposite upper graphene layer 632. In other versions of this example, some of the interconnect segments 624 may have lower graphene layer 628 and lower hBN layer 626 without upper graphene layer 632. In other versions of this example, some of the interconnect segments 624 may have an upper graphene layer 632 and an upper hBN layer 634 without a lower graphene layer 628. The interconnect segments 624 of the Litz wire 666 are arranged in multiple interconnect levels; in this example, the Litz wire 666 includes three interconnect levels of interconnect segments 624. To more clearly show the arrangement of the interconnect segments 624 themselves, the connections between successive interconnect segments 624 in each strand are not shown in FIG. 6. Each strand is configured such that some of the interconnect segments 624 in that strand are located around the periphery of the Litz wire 666. The successive interconnect segments 624 in each strand may be connected by, for example, vias and other interconnects. Each strand includes some of the interconnect segments 624 in each interconnect level.Compared to monolithic conductors of similar nominal cross-sectional areas, Litz wire 666 can advantageously exhibit lower impedance at high frequencies due to the distribution of skin effect among interconnect segments 624. Each strand is separated from the other strands by dielectric material 664, advantageously reducing induced local currents, sometimes referred to as "proximity effect."

[0056] FIG. 7 is a perspective view of Bernal graphene. The graphene layers in the embodiments described herein may include Bernal graphene. A first atomic layer of graphene, designated as Atomic Layer 1 in FIG. 7, includes carbon atoms, designated as Carbon Atoms in FIG. 7, in a hexagonal configuration. A second atomic layer of graphene, designated as Atomic Layer 2 in FIG. 7, also includes carbon atoms in a hexagonal configuration. Half of the carbon atoms in the first atomic layer are located directly above the carbon atoms in the second atomic layer. Additional layers of graphene have a similar alignment with the graphene layer immediately below. The inclusion of Bernal graphene in a graphene layer of a graphene heterolayer may advantageously improve the conductivity of the graphene heterolayer compared to layers of graphene having other configurations.

[0057] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. An integrated circuit comprising: a substrate comprising a semiconductor material; an active component disposed on the substrate; an interconnect region disposed over the substrate, the interconnect region comprising a dielectric material and a first metal layer; an interconnect disposed in the interconnect region, a second metal layer; and a graphene layer disposed on at least one of a top surface of the second metal layer or a bottom surface of the second metal layer, the graphene layer having at least one atomic layer of graphene; a hexagonal boron nitride (hBN) layer on the graphene layer opposite the second metal layer, the hBN layer being 1 to 3 atomic layers thick; the interconnect including: Including, the dielectric material and the first metal layer contact the hBN layer opposite the graphene layer; the second metal layer comprises an aluminum layer containing primarily aluminum, and the graphene layer does not extend over a lateral surface of the aluminum layer.

2. 10. The integrated circuit of claim 1, 1. An integrated circuit, wherein the graphene layer comprises Bernal graphene.

3. 1. An integrated circuit comprising: a substrate comprising a semiconductor material; an active component disposed on the substrate; an interconnect region disposed over the substrate, the interconnect region including a first dielectric layer, a second dielectric layer, and a first metal layer; an interconnect disposed in the interconnect region, a second metal layer; and a lower graphene layer disposed on a bottom surface of the second metal layer, the lower graphene layer having at least one atomic layer of graphene; a lower hexagonal boron nitride (hBN) layer on the lower graphene layer opposite the second metal layer, the lower hBN layer being 1 to 3 atomic layers thick; an upper graphene layer disposed on a top surface of the second metal layer, the upper graphene layer having at least one atomic layer of graphene; an upper hBN layer disposed on the upper graphene layer, the upper hBN layer being 1 to 3 atomic layers thick; Including, the first dielectric layer and the first metal layer contact the lower hBN layer, and the second dielectric layer contacts the upper hBN layer.

4. 4. An integrated circuit according to claim 3, the lower graphene layer and the upper graphene layer comprise Bernal graphene.

5. 4. An integrated circuit according to claim 3, The integrated circuit wherein the second metal layer comprises a damascene copper layer disposed on a damascene liner.

6. 1. A method of forming an integrated circuit, comprising: Providing a substrate comprising a semiconductor material; forming active components within the semiconductor material; forming a lower dielectric layer and a first metal layer over the substrate; forming an interconnection, forming a lower hBN layer having a thickness of 1 to 3 atomic layers on the lower dielectric layer and on the first metal layer using an atomic layer deposition (ALD) process; forming a lower graphene layer on the lower hBN layer, the lower graphene layer having at least one atomic layer of graphene; forming a second metal layer on the lower graphene layer; forming the interconnect, Including, forming the lower graphene layer comprises a transfer process, the transfer process comprising: forming the lower graphene layer on a growth substrate separate from the integrated circuit; removing the bottom graphene layer from the growth substrate; disposing the lower graphene layer on the lower hBN layer; A method comprising:

7. 7. The method of claim 6, the atomic layer deposition (ALD) process flowing a boron-containing reactant gas onto the lower dielectric layer to form a boron-containing layer on the lower dielectric layer; stopping the flow of the boron-containing reactant gas; flowing a nitrogen-containing reactant gas over the lower dielectric layer, wherein nitrogen from the nitrogen-containing reactant gas reacts with the boron-containing layer to form an atomic layer of boron nitride of the lower hBN layer; stopping the flow of the nitrogen-containing reactant gas; A method comprising:

8. 7. The method of claim 6, forming the second metal layer; forming a damascene liner on the lower graphene layer, the lower graphene layer and the lower hBN layer being disposed in an interconnect trench in the lower dielectric layer; forming a damascene copper layer on the damascene liner; removing the damascene copper layer, the damascene liner, the lower graphene layer, and the lower hBN layer from above the lower dielectric layer adjacent to the interconnect trench; A method comprising:

9. A method for forming an integrated circuit, comprising: Providing a substrate comprising a semiconductor material; forming active components within the semiconductor material; forming a lower dielectric layer and a first metal layer over the substrate; forming an interconnection, forming a lower hBN layer having a thickness of 1 to 3 atomic layers on the lower dielectric layer and on the first metal layer using an atomic layer deposition (ALD) process; forming a lower graphene layer on the lower hBN layer, the lower graphene layer having at least one atomic layer of graphene; forming a second metal layer on the lower graphene layer; forming the interconnect, Including, forming the second metal layer; forming an aluminum layer containing primarily aluminum on the lower graphene layer by a sputtering process; forming an etch mask on the aluminum layer covering the area for the interconnect; removing the aluminum layer and the underlying graphene layer exposed by the etch mask; thereafter removing the etch mask; A method comprising:

10. 10. The method of claim 9, forming the lower graphene layer comprises a PECVD process, the PECVD process comprising: flowing a carbon-containing reactant gas over the lower hBN layer; applying RF power to the carbon-containing reactive gas; A method comprising:

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