Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of forming a suitable laminated film and a method for manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device comprises a substrate and a laminated film including a plurality of first layers and a plurality of second layers alternately provided on the substrate. The semiconductor layer further comprises a charge storage layer provided on a side surface of the laminated film via a first insulation film, and a semiconductor layer provided on a side surface of the charge storage layer via a second insulation film. In addition, one of the plurality of first layers includes a first region containing carbon with first concentration and a second region containing carbon with second concentration being greater than the first concentration and containing, an upper region provided on an upper side of the first region or a lower region provided on a lower side of the first region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device may include a laminated film including multiple layers, such as a laminated film including multiple insulating layers and multiple electrode layers, or a laminated film including multiple insulating layers and multiple sacrificial layers, etc. In this case, there is a risk that the shape of the layers in the laminated film may be deformed or that the etching resistance of the layers in the laminated film may be deteriorated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-225682 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of forming a suitable laminated film and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a substrate and a stacked film including a plurality of first layers and a plurality of second layers alternately disposed on the substrate. The device further includes a charge storage layer disposed on a side surface of the stacked film via a first insulating film, and a semiconductor layer disposed on a side surface of the charge storage layer via a second insulating film. One of the plurality of first layers further includes a first region containing carbon at a first concentration and a second region containing carbon at a second concentration higher than the first concentration, the second region including a lower region disposed below the first region or an upper region disposed above the first region. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a perspective view showing a structure of a semiconductor device according to a first embodiment; [Figure 2] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 5 is a cross-sectional view (1 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 5 is a cross-sectional view (2 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3 is a cross-sectional view (3 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 4 is a cross-sectional view (4 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 5 is a cross-sectional view (5 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 3 is a cross-sectional view showing the structure of a semiconductor device of a first comparative example of the first embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device of a second comparative example of the first embodiment. [Figure 10] 4 is a graph and a table for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Figure 13] 10 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 14] 10 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 15] 10 is a cross-sectional view (3 / 3) illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 16] 10A and 10B are plan views showing details of the method for manufacturing the semiconductor device according to the fourth embodiment. [Figure 17] 10A to 10C are cross-sectional views showing details of a method for manufacturing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 17, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) Fig. 1 is a perspective view showing the structure of a semiconductor device according to a first embodiment, which includes, for example, a three-dimensional semiconductor memory.

[0009] 1 includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a block insulating film 5, and an electrode layer 6. The block insulating film 5 includes an insulating film 5a and an insulating film 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The insulating film 5a, the tunnel insulating film 3, and the channel semiconductor layer 2 are examples of a first insulating film, a second insulating film, and a semiconductor layer, respectively.

[0010] In FIG. 1, multiple insulating layers and multiple electrode layers are alternately stacked on a substrate, and a memory hole H1 is provided in these insulating layers and electrode layers. FIG. 1 shows one of these electrode layers, electrode layer 6. These electrode layers function, for example, as word lines of a three-dimensional semiconductor memory. FIG. 1 also shows the X and Y directions, which are parallel to the surface of the substrate and perpendicular to each other, and the Z direction, which is perpendicular to the surface of the substrate. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity.

[0011] The core insulating film 1, the channel semiconductor layer 2, the tunnel insulating film 3, the charge storage layer 4, and the insulating film 5a are formed in the memory hole H1 and constitute a memory cell of the three-dimensional semiconductor memory. The insulating film 5a is formed on the surfaces of the multiple insulating layers and multiple electrode layers in the memory hole H1, and the charge storage layer 4 is formed on the surface of the insulating film 5a. The charge storage layer 4 is capable of storing signal charges of the three-dimensional semiconductor memory. The tunnel insulating film 3 is formed on the surface of the charge storage layer 4, and the channel semiconductor layer 2 is formed on the surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as a channel of the memory cell. The core insulating film 1 is formed in the channel semiconductor layer 2.

[0012] The insulating film 5a is, for example, an SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, an insulating film such as an SiN film (silicon nitride film). The charge storage layer 4 may be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 3 is, for example, an SiON film (silicon oxynitride film). The tunnel insulating film 3 may be an SiO2 film. The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulating film 1 is, for example, an SiO2 film.

[0013] The insulating film 5b, barrier metal layer 6a, and electrode material layer 6b are formed between two insulating layers adjacent to each other in the Z direction, and are formed in this order on the lower surface of the upper insulating layer, the upper surface of the lower insulating layer, and the side surface of the insulating film 5a. The insulating film 5b is, for example, a metal insulating film such as an Al2O3 film (aluminum oxide film). The barrier metal layer 6a is, for example, a TiN film (titanium nitride film). The electrode material layer 6b is, for example, a W (tungsten) layer.

[0014] FIG. 2 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0015] FIG. 2 shows a vertical cross section of the memory hole H1 shown in FIG. 1. As described with reference to FIG. 1, the semiconductor device of this embodiment includes a plurality of insulating layers 8 and a plurality of electrode layers 6 alternately stacked on a substrate 7 (FIG. 2). These insulating layers 8 and electrode layers 6 form a laminated film 9. Within the laminated film 9, these electrode layers 6 are spaced apart from one another in the Z direction. Each electrode layer 6 includes the above-described barrier metal layer 6a and electrode material layer 6b. Each electrode layer 6 is an example of the second layer. The substrate 7 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Each insulating layer 8 is, for example, a SiO2 film. Each insulating layer 8 is an example of the first layer or first insulating layer. Further details of each insulating layer 8 will be described later.

[0016] The insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are formed in this order on the side surface of the stacked film 9 in the memory hole H1, i.e., on the side surfaces of the plurality of insulating layers 8 and the plurality of electrode layers 6 in the memory hole H1. The barrier metal layer 6a and the electrode material layer 6b in each electrode layer 6 are formed in this order on the lower surface of the upper insulating layer 8, the upper surface of the lower insulating layer 8, and the side surface of the insulating layer 5a, with the insulating film 5b interposed therebetween.

[0017] Next, each insulating layer 8 of this embodiment will be described with reference to FIG.

[0018] Each insulating layer 8 of this embodiment contains silicon (Si), oxygen (O), and carbon (C), and is, for example, a SiO2 film containing carbon as an impurity. However, the concentration of C atoms in each insulating layer 8 (hereinafter referred to as "C concentration") varies depending on the region within each insulating layer 8.

[0019] Specifically, each insulating layer 8 of this embodiment includes a bulk region 8a, a lower region 8b, and an upper region 8c, as shown in FIG. 2. The bulk region 8a, the lower region 8b, and the upper region 8c are all SiO2 films containing carbon as an impurity. The bulk region 8a is an example of a first region. The lower region 8b and the upper region 8c are examples of a second region.

[0020] The bulk region 8a is located approximately in the center of each insulating layer 8. The thickness of the bulk region 8a in the Z direction is, for example, 15 to 20 nm. The C concentration in the bulk region 8a is, for example, 1.4 to 2.6 atomic %. This C concentration is an example of a first concentration. In this embodiment, the C concentration in the bulk region 8a is obtained by dividing the number of C atoms in the bulk region 8a by the number of Si atoms, O atoms, and C atoms in the bulk region 8a. This also applies to other C concentrations described later.

[0021] The lower region 8b is located below the bulk region 8a in each insulating layer 8. The thickness of the lower region 8b in the Z direction is thinner than the thickness of the bulk region 8a in the Z direction, for example, 1 nm or less. The C concentration in the lower region 8b is higher than the C concentration in the bulk region 8a, for example, 2.8 atomic % or more. This C concentration is an example of the second concentration. The lower region 8b is in contact with, for example, the upper surface of the lower insulating film 5b.

[0022] The upper region 8c is located above the bulk region 8a in each insulating layer 8. The thickness of the upper region 8c in the Z direction is thinner than the thickness of the bulk region 8a in the Z direction, for example, 1 nm or less. The C concentration in the upper region 8c is higher than the C concentration in the bulk region 8a, for example, 2.8 atomic % or more. This C concentration is also an example of the second concentration. The upper region 8c is in contact with, for example, the lower surface of the upper insulating film 5b.

[0023] In this embodiment, all of the insulating layers 8 in the stacked film 9 include a bulk region 8a, a lower region 8b, and an upper region 8c, but only some of the insulating layers 8 in the stacked film 9 may include the bulk region 8a, the lower region 8b, and the upper region 8c. Further details of the insulating layers 8 will be described later.

[0024] 3 to 7 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0025] First, a substrate 7 is prepared, and then a plurality of insulating layers 8 and a plurality of sacrificial layers 11 are alternately formed on the substrate 7 (FIG. 3). As a result, a stacked film 12 including these insulating layers 8 and sacrificial layers 11 is formed on the substrate 7. Each sacrificial layer 11 is, for example, a SiN film. Each sacrificial layer 11 is an example of a second layer or a second insulating layer.

[0026] Each insulating layer 8 of this embodiment is formed to include a bulk region 8a, a lower region 8b, and an upper region 8c. The thickness of the bulk region 8a is, for example, 15 to 20 nm. The C concentration in the bulk region 8a is, for example, 1.4 to 2.6 atomic %. The thickness of the lower region 8b and the thickness of the upper region 8c are, for example, 1 nm or less. The C concentration in the lower region 8b and the upper region 8c are, for example, 2.8 atomic % or more. Each insulating layer 8 is formed by forming the lower region 8b, forming the bulk region 8a on the lower region 8b, and forming the upper region 8c on the bulk region 8a.

[0027] Each insulating layer 8 in this embodiment is a SiO2 film containing carbon as an impurity, and is formed using a source gas containing silicon (Si source gas) and a source gas containing carbon (C source gas). The Si source gas is, for example, a silane gas such as SiH4 gas, TEOS (tetraethyl orthosilicate) gas, or a mixed gas containing one or more of these (H represents hydrogen). The C source gas is, for example, CO gas, CO2 gas, or C X H Y The source gas may be a Si source gas, a SiH3(CH3) gas (monomethylsilane gas), a SiH2(CH3)2 gas (dimethylsilane gas), a SiH(CH3)3 gas (trimethylsilane gas), a Si(CH3)4 gas (tetramethylsilane gas), or a mixed gas containing one or more of these (X represents an integer from 1 to 4, and Y represents an integer from 1 to 4). The Si source gas is an example of the second gas, and the C source gas is an example of the first gas.

[0028] In this embodiment, each insulating layer 8 is formed by setting different conditions for forming the bulk region 8a and the lower and upper regions 8b and 8c. For example, when supplying a Si source gas into a chamber containing the substrate 7, the flow rate of the Si source gas when forming the lower and upper regions 8b and 8c may be set lower than the flow rate of the Si source gas when forming the bulk region 8a. Also, when supplying a C source gas into a chamber containing the substrate 7, the flow rate of the C source gas when forming the lower and upper regions 8b and 8c may be set lower than the flow rate of the C source gas when forming the bulk region 8a. According to this embodiment, by adopting one or both of these flow rate conditions, the C concentration in the lower and upper regions 8b and 8c can be set higher than the C concentration in the bulk region 8a. Further details of these conditions will be described later.

[0029] Next, a plurality of memory holes H1 are formed in the stacked film 12 by photolithography and dry etching (FIG. 4). FIG. 4 illustrates one of these memory holes H1. Each memory hole H1 extends in the Z direction and is formed to penetrate the stacked film 12. In this embodiment, each memory hole H1 has a cylindrical shape.

[0030] Next, in each memory hole H1, an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are formed in this order (FIG. 5). As a result, the insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are formed in this order on the side surfaces of the stacked film 12, i.e., on the side surfaces of the plurality of insulating layers 8 and the plurality of sacrificial layers 11.

[0031] Next, slits (not shown) are formed in the laminated film 12, and each sacrificial layer 11 is removed by wet etching through the slits (FIG. 6). As a result, multiple cavities H2 are formed in the laminated film 12. These cavities H2 are examples of recesses. The wet etching is performed using, for example, hydrofluoric acid or phosphoric acid.

[0032] Next, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed in this order in each cavity H2 (FIG. 7). As a result, a block insulating film 5 including the insulating film 5a and the insulating film 5b, and an electrode layer 6 including the barrier metal layer 6a and the electrode material layer 6b are formed. Furthermore, a stacked film 9 including multiple insulating layers 8 and multiple electrode layers 6 alternately is formed on the substrate 7. In other words, the sacrificial layer 11 is replaced by the electrode layer 6, and the stacked film 12 is replaced by the stacked film 9.

[0033] Thereafter, the substrate 7 and various layers on the substrate 7 are annealed, and further various plug layers, wiring layers, interlayer insulating films, etc. are formed on the substrate 7. In this manner, the semiconductor device of this embodiment is manufactured.

[0034] In this embodiment, the bulk region 8a and the lower region 8b in each insulating layer 8 are made of the same insulating film (e.g., an SiO2 film), but they may be made of different insulating films. For example, the bulk region 8a may be made of an SiO2 film containing carbon as an impurity, and the lower region 8b may be made of an SiON film containing carbon as an impurity. In this case, too, it is desirable to set the C concentration in the lower region 8b higher than the C concentration in the bulk region 8a. The same applies to the bulk region 8a and the upper region 8c in each insulating layer 8.

[0035] Next, the semiconductor device of this embodiment will be compared with a semiconductor device of a comparative example with reference to FIGS.

[0036] FIG. 8 is a cross-sectional view showing the structure of a semiconductor device of a first comparative example of the first embodiment.

[0037] The semiconductor device of this comparative example has the same components as the semiconductor device of the first embodiment (FIG. 2), except that each insulating layer 8 of this comparative example includes only a bulk region 8a containing low concentrations of C atoms, and does not include a lower region 8b or an upper region 8c containing high concentrations of C atoms.

[0038] In this case, if the semiconductor device of this comparative example is manufactured by the method shown in Figures 3 to 7, the shape of insulating layer 8 may be deformed or the etching resistance of insulating layer 8 may be deteriorated at the stage shown in Figure 6. Figure 6 shows the step of removing sacrificial layer 11 by wet etching, as described above.

[0039] In FIG. 6, the insulating layer 8 is exposed to the cavity H2, which may cause the shape of the insulating layer 8 to warp. The warping of the insulating layer 8 may become more pronounced as the stacked film 12 becomes finer and the number of layers increases. This is because as the stacked film 12 becomes finer and the number of layers increases, the thickness of the insulating layer 8 becomes thinner and the stress applied to the insulating layer 8 increases. Furthermore, tapering of the shape of the insulating layer 8 during wet etching may also cause the insulating layer 8 to warp.

[0040] As a result of the investigation, it was found that these problems are less likely to occur as the C concentration in the bulk region 8a increases. For example, the higher the C concentration in the bulk region 8a, the smaller the stress applied to the insulating layer 8. Furthermore, the higher the C concentration in the bulk region 8a, the higher the resistance of the insulating layer 8 to wet etching.

[0041] FIG. 9 is a cross-sectional view showing the structure of a semiconductor device of a second comparative example of the first embodiment.

[0042] The semiconductor device of this comparative example also has the same components as the semiconductor device of the first embodiment (FIG. 2). However, each insulating layer 8 of this comparative example includes only a bulk region 8d containing a high concentration of C atoms, instead of including only a bulk region 8a containing a low concentration of C atoms. The C concentration in the bulk region 8d is, for example, 2.8 atomic % or more.

[0043] 3 to 7, deformation of the shape of insulating layer 8 at the stage shown in Fig. 6 and deterioration of the etching resistance of insulating layer 8 at the stage shown in Fig. 6 can be suppressed. However, since insulating layer 8 contains a high concentration of C atoms, there is a risk of a large leakage current being generated due to insulating layer 8 during operation of the semiconductor device. In other words, if the C concentration in bulk region 8d becomes high, there is a risk of an increase in the leakage current in the semiconductor device.

[0044] Therefore, each insulating layer 8 of this embodiment includes a bulk region 8a containing a low concentration of C atoms and a lower region 8b and an upper region 8c containing a high concentration of C atoms (FIG. 2). This reinforces and protects the surface of each insulating layer 8 with the lower region 8b and the upper region 8c, thereby preventing deformation of the shape of the insulating layer 8 and reducing the etching resistance of the insulating layer 8. Furthermore, since each insulating layer 8 includes the bulk region 8a, the average C concentration in the insulating layer 8 can be reduced, thereby reducing leakage current in the semiconductor device. Thus, this embodiment makes it possible to form a stacked film 12 (9) with favorable properties.

[0045] It is desirable to set the C concentration in the bulk region 8a, the lower region 8b, and the upper region 8c to a value that can suitably suppress deformation of the insulating layer 8, deterioration of the etching resistance of the insulating layer 8, and an increase in leakage current. According to this embodiment, by setting the C concentration in the lower region 8b and the upper region 8c to 2.8 atomic % or more, it is possible to sufficiently suppress deformation of the insulating layer 8 and deterioration of the etching resistance of the insulating layer 8. Furthermore, according to this embodiment, by setting the C concentration in the bulk region 8a to 1.4 to 2.6 atomic %, it is possible to sufficiently suppress leakage current.

[0046] Furthermore, verification results have shown that the above-mentioned problems of deformation and etching resistance can be suppressed by setting the thickness of the lower region 8b and the upper region 8c to 1 nm or less, so it is desirable to set the thickness of the lower region 8b and the upper region 8c in this embodiment to 1 nm or less, which makes it possible to suppress the above-mentioned problems of deformation and etching resistance while effectively suppressing an increase in leakage current.

[0047] FIG. 10 is a graph and a table for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0048] FIG. 10(a) is a graph for explaining the step shown in FIG. 3, i.e., the step of forming the laminated film 12. The horizontal axis of FIG. 10(a) represents time in the step of forming the laminated film 12. The vertical axis of FIG. 10(a) represents the C concentration in each portion of the laminated film 12. For example, when forming the bulk region 8a in each insulating layer 8, the C concentration in the bulk region 8a is set low, and when forming the lower region 8b or the upper region 8c in each insulating layer 8, the C concentration in the lower region 8b or the upper region 8c is set high. The C concentration in each insulating layer 8 can be set high, for example, by reducing the flow rate of the Si source gas or the flow rate of the C source gas.

[0049] 10(b) shows various parameters that can increase the C concentration in the insulating layer 8. For example, the C concentration in the insulating layer 8 can be increased by decreasing the flow rate of silane gas, which is a Si source gas. In addition, the C concentration in the insulating layer 8 can be increased by decreasing the flow rate of CO gas, which is a C source gas.

[0050] When forming the insulating layer 8, a Si source gas, a C source gas, and an inert gas may be supplied into a chamber accommodating the substrate 7. The inert gas may be, for example, a rare gas such as Ar (argon) gas or N2 (nitrogen) gas. As shown in FIG. 10(b), the C concentration in the insulating layer 8 can be increased by increasing the flow rate of Ar gas or decreasing the flow rate of N2 gas. For example, the C concentration in the lower region 8b and the upper region 8c may be made higher than the C concentration in the bulk region 8a by setting the flow rate of Ar gas higher when forming the lower region 8b and the upper region 8c than when forming the bulk region 8a.

[0051] 10(b), it is possible to increase the C concentration in the insulating layer 8 by reducing the pressure in the chamber that accommodates the substrate 7. For example, the C concentration in the lower region 8b and the upper region 8c may be made higher than the C concentration in the bulk region 8a by setting the pressure in the chamber when forming the lower region 8b and the upper region 8c lower than the pressure in the chamber when forming the bulk region 8a.

[0052] 10(b), HF and LF respectively represent high-frequency and low-frequency RF (Radio Frequency) power when forming the insulating layer 8. As shown in FIG. 10(b), it is possible to increase the C concentration in the insulating layer 8 by decreasing the high-frequency RF power or increasing the low-frequency RF power. For example, the C concentration in the lower region 8b and the upper region 8c may be made higher than the C concentration in the bulk region 8a by setting the low-frequency RF power when forming the lower region 8b and the upper region 8c higher than the low-frequency RF power when forming the bulk region 8a.

[0053] According to this embodiment, by adjusting these parameters, it is possible to easily change the C concentration in each insulating layer 8 for each region in each insulating layer 8.

[0054] As described above, each insulating layer 8 of this embodiment includes a bulk layer 8a and a lower region 8b and an upper region 8c having a higher C concentration than the C concentration in the bulk layer 8a. Therefore, according to this embodiment, it is possible to form a suitable laminated film 9 (12) that can suppress deformation of the shape of the insulating layer 8, deterioration of the etching resistance of the insulating layer 8, and an increase in leakage current.

[0055] (Second and third embodiments) FIG. 11 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment. The semiconductor device of this embodiment has the same components as the semiconductor device of the first embodiment (FIG. 2). However, each insulating layer 8 of this embodiment includes a bulk region 8a containing a low concentration of C atoms and a lower region 8b containing a high concentration of C atoms, but does not include an upper region 8c containing a high concentration of C atoms.

[0056] FIG. 12 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0057] The semiconductor device of this embodiment also includes the same components as the semiconductor device of the first embodiment (FIG. 2). However, each insulating layer 8 of this embodiment includes a bulk region 8a containing a low concentration of C atoms and an upper region 8c containing a high concentration of C atoms, but does not include a lower region 8b containing a high concentration of C atoms.

[0058] According to these embodiments, it is possible to suppress deformation of the shape of the insulating layer 8 and deterioration of the etching resistance of the insulating layer 8, compared to the first comparative example. Furthermore, according to these embodiments, it is possible to reduce leakage current, compared to the second comparative example.

[0059] (Fourth embodiment) 13 to 15 are cross-sectional views showing a method for manufacturing the semiconductor device of the fourth embodiment.

[0060] The steps shown in FIGS. 13 to 15 are modifications of the steps shown in FIGS. 5 to 7. Like FIG. 5, FIG. 13 shows a step of sequentially forming an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 in each memory hole H1. Like FIG. 6, FIG. 14 shows a step of removing each sacrificial layer 11 to form multiple cavities H2 in the laminated film 12. Like FIG. 7, FIG. 15 shows a step of sequentially forming an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b in each cavity H2. As a result, the sacrificial layer 11 is replaced by the electrode layer 6, and the laminated film 12 is replaced by the laminated film 9.

[0061] However, the process shown in FIG. 14 is performed so as to remove only a portion of each sacrificial layer 11, rather than removing the entire sacrificial layer 11. As a result, the structure shown in FIG. 15 includes not only the electrode layer 6 (laminated film 9) that has been replaced by the sacrificial layer 11 (laminated film 12), but also the sacrificial layer 11 (laminated film 12) that remains without being replaced by the electrode layer 6 (laminated film 9). Therefore, the completed semiconductor device of this embodiment includes the electrode layer 6, the insulating layer 8, and the sacrificial layer 11, and each memory hole H1 is provided in the laminated film including the electrode layer 6, the insulating layer 8, and the sacrificial layer 11. The insulating layer 8 is an example of a first layer, and the electrode layer 6 and the sacrificial layer 11 are examples of a second layer. The insulating layer 8 is an example of a first insulating layer, and the sacrificial layer 11 is an example of a second insulating layer.

[0062] The sacrificial layer 11 may remain in any part of the finished semiconductor device as long as it does not interfere with the operation of the finished semiconductor device. For example, if the finished semiconductor device has a via plug that penetrates a stacked film including the electrode layer 6, the insulating layer 8, and the sacrificial layer 11, the sacrificial layer 11 may remain near the via plug.

[0063] FIG. 16 is a plan view showing details of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0064] 16(a), the substrate (wafer) 7 of this embodiment includes a plurality of regions R1, each of which corresponds to one shot when manufacturing the semiconductor device of this embodiment.

[0065] Each region R1 includes a plurality of regions R2 as shown in Fig. 16(b), and each region R2 corresponds to one semiconductor device (chip) of this embodiment.

[0066] Each region R2 includes multiple regions R3 as shown in Fig. 16(c), and each region R3 corresponds to one plane in each chip in this embodiment.

[0067] As shown in Fig. 16(d), each region R3 includes a central portion P1 and an end portion P2. The central portion P1 is located in the region sandwiched between two slits. The end portion P2 is located in the region not sandwiched between two slits. Further details of the central portion P1 and the end portion P2 will be described later.

[0068] FIG. 17 is a cross-sectional view showing details of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0069] Fig. 17 shows a specific example of the process shown in Fig. 14. Thus, Fig. 17 shows the process of removing each sacrificial layer 11 to form a plurality of cavities H2 in the laminated film 12. In Fig. 17, each sacrificial layer 11 is not entirely removed, but only a portion of each sacrificial layer 11 is removed.

[0070] FIG. 17 shows an example of the central portion P1 and end portion P2 shown in FIG. 16 and multiple slits ST provided in the laminated film 12. Each slit ST extends in the Y and Z directions and penetrates the laminated film 12. The laminated film 12 shown in FIG. 17 includes multiple insulating layers 8 and multiple sacrificial layers 11, as well as an insulating layer 21 provided between two adjacent sacrificial layers 11 and an insulating layer 22 provided on the uppermost sacrificial layer 11. The insulating layers 21 and 22 are, for example, SiO2 films. In FIG. 17, the central portion P1 is located in the region sandwiched between the two slits ST, and the end portion P2 is located in the region not sandwiched between the two slits ST.

[0071] 17 further shows a plurality of columnar portions CL provided in the stacked film 12. Each columnar portion CL includes, in order, the insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1. Each columnar portion CL shown in FIG. 17 includes a lower columnar portion CL1 provided in the insulating layer 21 or at a position lower than the insulating layer 21, and an upper columnar portion CL2 provided in the insulating layer 21 or at a position higher than the insulating layer 21.

[0072] In the process shown in Figure 17, slits ST are formed in the laminated film 12, and each sacrificial layer 11 is removed by wet etching through the slits ST. At this time, each sacrificial layer 11 in the central portion P1 is sandwiched between two slits ST, so generally, the entire sacrificial layer 11 is removed by the wet etching. On the other hand, each sacrificial layer 11 in the end portion P2 is not sandwiched between two slits ST, so generally, only a portion of the sacrificial layer 11 is removed by the wet etching. Therefore, Figure 17 shows the sacrificial layer 11 remaining in the end portion P2.

[0073] 15 is then performed as described above. As a result, the finished semiconductor device manufactured in this case also includes the electrode layer 6, the insulating layer 8, and the sacrificial layer 11, and includes each memory hole H1 in the stacked film including the electrode layer 6, the insulating layer 8, and the sacrificial layer 11.

[0074] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0075] 1: core insulating film, 2: channel semiconductor layer, 3: tunnel insulating film, 4: charge storage layer, 5: block insulating film, 5a: insulating film, 5b: insulating film, 6: electrode layer, 6a: barrier metal layer, 6b: electrode material layer, 7: substrate, 8: insulating layer, 8a: bulk region, 8b: lower region, 8c: Upper region, 8d: Bulk region, 9: Laminated film, 11: Sacrificial layer, 12: Laminated film

Claims

1. forming a laminated film including a plurality of first layers and a plurality of second layers alternately provided on a substrate; forming a charge storage layer on a side surface of the stacked film via a first insulating film; forming a semiconductor layer on a side surface of the charge storage layer via a second insulating film; This includes: One of the plurality of first layers is a first region including a first concentration of carbon; a second region including a lower region provided below the first region or an upper region provided above the first region, the second region including carbon at a second concentration higher than the first concentration; formed to include the first and second regions are formed using a first gas containing carbon; a flow rate of the first gas when the second region is formed is set to be smaller than a flow rate of the first gas when the first region is formed; A method for manufacturing a semiconductor device.

2. forming a laminated film including a plurality of first layers and a plurality of second layers alternately provided on a substrate, wherein each of the plurality of first layers includes a first insulating layer, and each of the plurality of second layers includes a second insulating layer different from the first insulating layer; forming a charge storage layer on a side surface of the stacked film via a first insulating film; forming a semiconductor layer on a side surface of the charge storage layer via a second insulating film; removing the second layers to form a plurality of recesses; forming a plurality of electrode layers within the plurality of recesses; This includes: One of the plurality of first layers is a first region including a first concentration of carbon; a second region including a lower region provided below the first region or an upper region provided above the first region, the second region including carbon at a second concentration higher than the first concentration; formed to include the first and second regions are formed using a first gas containing carbon; a flow rate of the first gas when the second region is formed is set to be smaller than a flow rate of the first gas when the first region is formed; A method for manufacturing a semiconductor device.

3. forming a laminated film including a plurality of first layers and a plurality of second layers alternately provided on a substrate, wherein each of the plurality of first layers includes a first insulating layer, and each of the plurality of second layers includes a second insulating layer different from the first insulating layer; forming a charge storage layer on a side surface of the stacked film via a first insulating film; forming a semiconductor layer on a side surface of the charge storage layer via a second insulating film; removing the second layers to form a plurality of recesses; forming a plurality of electrode layers within the plurality of recesses; This includes: One of the plurality of first layers is a first region including a first concentration of carbon; a second region including a lower region provided below the first region and an upper region provided above the first region, the second region including carbon at a second concentration higher than the first concentration; formed to include the first and second regions are formed by forming the lower region, forming the first region on the lower region, and forming the upper region on the first region; the first and second regions are formed using a first gas containing carbon; a flow rate of the first gas when the second region is formed is set to be smaller than a flow rate of the first gas when the first region is formed; A method for manufacturing a semiconductor device.

4. The first gas is CO, CO ２ , C Ｘ H Ｙ , SiH ３ (CH ３ ), SiH ２ (CH ３ ) ２ , SiH(CH ３ ) ３ , and Si(CH ３ ) ４ (wherein C represents carbon, O represents oxygen, H represents hydrogen, Si represents silicon, X represents an integer of 1 to 4, and Y represents an integer of 1 to 4), the method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the first and second regions are formed using the first gas containing carbon and a second gas containing silicon.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein a flow rate of said second gas when said second region is formed is set to be smaller than a flow rate of said second gas when said first region is formed.

7. 7. The method for manufacturing a semiconductor device according to claim 1, wherein a chamber pressure, an RF power, or an inert gas flow rate when forming the second region is set to a value different from a chamber pressure, an RF power, or an inert gas flow rate when forming the first region.

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