Non-volatile Integrated Circuit

Abstract

The present invention aims to provide a new non-volatile integrated circuit that can significantly reduce energy overhead. The above problem was solved by a non-volatile integrated circuit that backs up and stores each bit of information stored in a plurality of flip-flops in a non-volatile memory area when power is turned off, the non-volatile integrated circuit being composed of N bits, and the non-volatile memory area being composed of N+1 magnetic tunnel junction elements.

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile integrated circuit in which a nonvolatile memory element is incorporated inside a chip. [Background technology]

[0002] The power consumption of semiconductor integrated circuits consists of dynamic power consumption and static power consumption. Dynamic power consumption is the power consumed when the circuit is operating, i.e., when transistor circuits are switching, while static power consumption is the power consumed constantly due to transistor leakage current, regardless of whether the circuit is operating or not. As circuits become more highly integrated, the proportion of static power consumption in the power consumption of semiconductor integrated circuits has been increasing in recent years, making it an issue to find ways to reduce static power consumption. In particular, in IoT technology, edge devices such as mobile terminals and in-vehicle products remain in standby mode for a while after executing processing, making reducing static power consumption an urgent issue.

[0003] A common technique used is to cut off the power supply when no computation is being performed and to save information stored in volatile memory to external non-volatile memory, thereby preventing static power consumption. This technique is called power gating technology. Figure 1 is a graph illustrating the concept of power consumption reduction in power gating technology, with the horizontal axis representing time and the vertical axis representing power consumption. Of the two graphs shown in Figure 1, the left graph shows the trend in power consumption of a conventional semiconductor circuit, and the right graph shows the trend in power consumption of a semiconductor integrated circuit using power gating technology.

[0004] The graph on the left confirms that the calculation execution period, i.e., the period in which dynamic power consumption occurs, is discrete, while the period in which static power consumption occurs due to transistor leakage current is continuous. On the other hand, the graph on the right confirms that power gating technology prevents static power consumption during the power-off period. However, even when transitioning from the calculation execution period to the power-off period, i.e., the power gating period, power consumption occurs due to the backup process that saves information stored in volatile memory to external nonvolatile memory. Similarly, when transitioning from the power gating period to the calculation execution period, power consumption occurs due to the restore process that restores information saved in external nonvolatile memory to volatile memory. The energy loss and loss of circuit utilization opportunities resulting from these power consumptions, which includes the time required for processing, are called overhead. Overhead reduces the power consumption reduction effect of power gating technology and reduces the period in which calculation operations can be performed. Previous research has shown that the energy consumed when exchanging data with memory such as DRAM is 10 times the energy consumed during calculations. 4 It is said that the overhead will double, which causes an increase in overhead. If the overhead can be reduced, the power reduction effect of power gating technology can be increased, and the period during which calculation operations can be executed can be extended.

[0005] To reduce overhead, instead of backing up data stored in volatile memory to external nonvolatile memory, nonvolatile LSIs incorporating nonvolatile memory elements within the chip have been proposed. Nonvolatile LSIs combine logic-in-memory integrated circuit technology and nonvolatile device technology. Logic-in-memory integrated circuit technology significantly reduces global wiring by distributing memory functions within the arithmetic circuit, thereby preventing transfer delays and reducing dynamic power consumption. Nonvolatile device technology eliminates the need for data transfer to external memory and enables rapid power cutoff, thereby reducing power consumption. Furthermore, nonvolatile device technology significantly reduces circuit size by directly stacking memory devices on CMOS. Nonvolatile logic circuit technology utilizing magnetic tunnel junction (MTJ) elements, a type of spintronics element, is known as a nonvolatile device.

[0006] Nonvolatile power gating using nonvolatile logic circuits makes it possible to make all modules of an integrated circuit nonvolatile and perform fine-grained power gating. This is expected to significantly reduce wasted power consumption compared to power gating that combines volatile logic circuits and external storage circuits. Figure 2 shows a schematic diagram and graphs illustrating the difference in power consumption reduction between power gating using external storage and nonvolatile power gating. The upper left diagram shows power gating that combines a volatile LSI and an external storage circuit, while the lower left diagram shows nonvolatile power gating using a nonvolatile LSI (NV-LSI). Corresponding to each diagram, a graph is shown on the right, with the horizontal axis representing time and the vertical axis representing accumulated energy.

[0007] With power gating using external storage, the difference in stored energy is small during restore processing and the overhead is not that large, but the difference in stored energy is large during backup processing, resulting in a large overhead. On the other hand, with non-volatile power gating, the difference in stored energy is small even during backup processing, resulting in a small overhead. Comparing the upper and lower graphs, it can be seen that the slope of the energy change during the dynamic power consumption period, i.e., the calculation execution period, is the same, which means that the dynamic power consumption period, i.e., the energy that can be consumed to execute calculations and the period during which calculations can be executed, is significantly larger.

[0008] Meanwhile, in IoT technology, energy harvesting, which harvests and utilizes energy from surrounding sources such as light and vibrations, has been attracting attention in recent years. Energy harvesting has the ability to supply infinite energy, making it possible to realize battery-less edge devices. However, the energy supply from energy harvesting is weak and unstable, and for edge devices to perform stable information processing, they need to accumulate energy and then, once a certain amount has accumulated, repeatedly perform tasks that consume energy. This type of step-by-step task execution using power management is called intermittent computing, and the development of this technology will be extremely important in using energy harvesting as an energy supply source.

[0009] Intermittent computing theoretically uses the same mechanism as the aforementioned power gating technology, which does not rely on energy harvesting. However, while power gating technology does not rely on energy harvesting, and data is backed up just before entering standby mode after a series of processes have been completed, intermittent computing, which executes tasks in stages, frequently requires power supply to be cut off in the middle of processing to back up data. For this reason, overhead must be minimized. To reduce overhead, development is required from both the perspective of selecting effective devices as non-volatile memory elements to be embedded inside the chip and the realization of effective circuit layouts that contribute to low energy consumption.

[0010] An effective nonvolatile memory element must have a stable resistance value in a static state, even though its resistance value changes under certain conditions. Therefore, the inventors have focused their research on magnetic tunnel junction (MTJ) elements. MTJ elements have advantageous characteristics over other nonvolatile memory elements in terms of write time, write endurance, and compatibility with CMOS. Figure 3 illustrates the characteristics of a magnetic tunnel junction (MTJ) element. An MTJ element, a type of spintronics element, has a three-layer structure with an insulating layer between two magnetic layers. In the figure, the upper magnetic layer is a free layer in which the sign of the spin current changes depending on the sign of a current of a certain magnitude, while the lower magnetic layer is a fixed layer in which the sign of the spin current remains constant regardless of the sign of the current. By applying a rewrite current above the reversal threshold, an MTJ element can be in two states: a parallel state in which the spin currents in the two magnetic layers are in the same direction, and an antiparallel state in which the spin currents in the two magnetic layers are in opposite directions. An MTJ element has low resistance (Rp) when in a parallel state and high resistance (Rap) when in an anti-parallel state. As shown in the resistance-current characteristics in Figure 3, when a current of Iap-p or more is applied when the element is in a high resistance (Rap), the resistance value changes to low resistance (Rp). However, even if the applied current is removed in this state, the resistance value remains unchanged. However, when a current of Ip-ap or more is applied in the opposite direction, the resistance value changes to high resistance (Rap). These two resistance values ​​are used as bit information. In this way, an MTJ element can be said to have the dual properties of a variable resistor and a non-volatile memory.

[0011] Regarding effective circuit layouts that contribute to low energy consumption, we will first explain the basic conventional circuit configuration. Figure 4 is a circuit diagram of a nonvolatile flip-flop (hereinafter sometimes referred to as "NV-FF") that constitutes a conventional nonvolatile register. If NV-FFs are arranged in an array with the required number of bits, they will function as a nonvolatile register. NV-FFs are flip-flops equipped with nonvolatile power gating functions. In the example shown here, a master-slave D flip-flop is given the functions of saving data to an MTJ element and restoring data from the MTJ element.

[0012] While power is supplied, data is held by two latches, just as in a normal flip-flop. Meanwhile, just before power is cut off, a backup process is performed by the backup circuit applying a rewrite current to the MTJ element. When power is subsequently restored, the slave latch acts as a sense amplifier to read the resistance difference, and a restore process is performed to restore the bit information held by the MTJ element to the D flip-flop.

[0013] In this way, the NV-FF associates two MTJ elements with the complementary outputs of a flip-flop and stores bit information based on the difference in their resistance states. Therefore, writing to both MTJ elements is performed so that they assume complementary resistance states of either Rp, Rap or Rap, Rp. However, writing to an MTJ element requires a relatively large current, which results in the backup process accounting for a large portion of the energy consumption overhead, as shown in the upper graph of Figure 2.

[0014] In addition to the energy consumption overhead issue, NV-FFs require large-sized transistors capable of applying sufficient current to the MTJ element. The inversion threshold current of an MTJ element is around 100 μA at room temperature, which cannot be achieved with transistors of normal size. Therefore, data can only be written by using multiple dedicated backup control transistors with gate widths four to twelve times larger than that of a conventional NV-FF. Thus, a nonvolatile register with a conventional NV-FF configuration (hereinafter simply referred to as the "conventional NV-FF configuration") has a large area overhead because the write transistors occupy a large portion of its area.

[0015] In order to solve the problems of energy consumption overhead and area overhead as described above, the present inventors have developed a non-volatile register based on a shared reference scheme (hereinafter sometimes referred to as "RLSS"), which holds one bit of information using a reference resistor shared by each bit and the resistance value of one data-holding MTJ element, as shown in Non-Patent Document 1. [Prior art documents] [Non-patent literature]

[0016] [Non-Patent Document 1] T. Yoshida, M. Natsui, T. Hanyu, "Design of an Energy / Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme," 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS2024), pp.1257-1261, 2024. Summary of the Invention [Problem to be solved by the invention]

[0017] This paper explains the advantages of a nonvolatile register based on a shared reference scheme (RLSS) (hereinafter referred to as the "RLSS-based configuration") over a conventional NV-FF configuration. Figure 5 is an explanatory diagram showing how the conventional NV-FF configuration and the RLSS-based configuration retain bit information. The top diagram shows the conventional NV-FF configuration, and the bottom diagram shows the RLSS-based configuration. The conventional NV-FF configuration uses two MTJ elements per bit, and writes to both MTJ elements so that they are in a complementary resistance state of either Rp and Rap or Rap and Rp, to create and compare the difference in resistance values ​​required for the restore process from the MTJ elements.

[0018] On the other hand, in a configuration using RLSS, a reference MTJ element with a resistance value intermediate between high and low resistance is prepared, and bit information is read by comparing the resistance of the reference MTJ element with the resistance of the data retention MTJ element. In a configuration using the shared reference method, the number of MTJ elements used for writing per bit is reduced from two to one compared to the conventional configuration using NV-FF. This makes it possible to significantly reduce the write energy required for the MTJ element that rewrites the value. As shown in the figure, the reference MTJ element with a resistance value intermediate between high and low resistance is structured to achieve an intermediate resistance value by combining four MTJ elements with the same resistance as the data retention MTJ element.

[0019] The RLSS configuration can significantly reduce energy consumption and area, but because the circuit configuration does not allow simultaneous write and read operations to multiple MTJ elements, sharing a reference resistor among many MTJ elements increases the time required to write and read to the MTJ elements compared to conventional configurations.

[0020] In view of the above problems, an object of the present invention is to provide a new non-volatile integrated circuit that can significantly reduce energy overhead. [Means for solving the problem]

[0021] In order to solve such problems, the present invention provides a non-volatile integrated circuit that backs up and stores each bit of information stored in a plurality of flip-flops when power is supplied to a non-volatile memory area when power is cut off, wherein the non-volatile integrated circuit is composed of N bits, and the non-volatile memory area is composed of N+1 magnetic tunnel junction elements.

[0022] Such a configuration can significantly reduce energy overhead.

[0023] Furthermore, the present invention is characterized in that one magnetic tunnel junction element is associated with a flip-flop constituting the n-th bit, and the 0 or 1 state of the flip-flop constituting the n-th bit is linked to whether the resistance value of the n-th magnetic tunnel junction element matches or does not match the resistance value of the (n+1)-th magnetic tunnel junction element.

[0024] According to this configuration, the energy overhead can be significantly reduced by a method different from RLSS.

[0025] Furthermore, the present invention is characterized in that writing to the nonvolatile storage area and reading from the nonvolatile storage area are performed in two cycles in which processing to odd-numbered magnetic tunnel junction elements and processing to even-numbered magnetic tunnel junction elements are performed alternately.

[0026] This configuration significantly reduces energy overhead while still allowing backup and restore operations to be performed in a short time, similar to the conventional configuration using NV-FFs.

[0027] Furthermore, the present invention is characterized in that writing to the n-th magnetic tunnel junction element of the nonvolatile storage area is performed based on the output of an exclusive OR circuit, and the output of the (n-1)-th exclusive OR circuit (however, a predetermined value when n=1) and the output of the n-th flip-flop are connected to the inputs of the exclusive OR circuit.

[0028] According to this configuration, the backup operation can be performed with a simple configuration.

[0029] Furthermore, the present invention is characterized in that reading from the nonvolatile storage area is performed using a magnetic tunnel junction element difference / identity reading circuit that outputs 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or mismatch.

[0030] With this configuration, the restore operation can be performed using a method different from RLSS.

[0031] The present invention also provides a nonvolatile integrated circuit with an N-bit configuration, which saves and holds each bit information stored in a plurality of flip-flops when power is supplied to a nonvolatile memory area when power is cut off, and which includes N+1 magnetic tunnel junction elements and a control unit, wherein the control unit writes to the n-th magnetic tunnel junction element in the nonvolatile memory area based on the output of an exclusive OR circuit by connecting the output of the n-1-th exclusive OR circuit (however, when n=1, a predetermined value) and the output of the n-th flip-flop to the input of the exclusive OR circuit, and the control unit reads by outputting 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or mismatch.

[0032] This configuration significantly reduces energy overhead while enabling backup and restore operations to be performed in a short time, similar to conventional NV-FF configurations, with a simple circuit configuration. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a graph for explaining the concept of power consumption reduction in power gating technology. [Figure 2] 10A and 10B are schematic diagrams and graphs for explaining the difference in power consumption reduction between power gating using external storage and non-volatile power gating; [Figure 3] 1 is a diagram illustrating the characteristics of a magnetic tunnel junction element (MTJ element). [Figure 4] FIG. 1 is a circuit diagram of a nonvolatile flip-flop that constitutes a nonvolatile integrated circuit. [Figure 5] FIG. 10 is an explanatory diagram showing how a conventional configuration using NV-FFs and a configuration using RLSSs retain bit information. [Figure 6] FIG. 10 is an explanatory diagram showing how a configuration using DISS holds bit information. [Figure 7] FIG. 10 is an explanatory diagram showing a read operation of a configuration using DISS. [Figure 8]FIG. 10 is an explanatory diagram comparing the write and read operations of a conventional configuration using NV-FF and a configuration using RLSS and DISS. [Figure 9] 1 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention; [Figure 10] FIG. 10 is a diagram illustrating a backup process of the nonvolatile integrated circuit according to the embodiment of the present invention. [Figure 11] 10A and 10B are diagrams illustrating a restore process of a nonvolatile integrated circuit according to an embodiment of the present invention. [Figure 12] FIG. 10 is a diagram for explaining the structure of a readout circuit in a configuration using DISS. [Figure 13] FIG. 10 is a diagram for explaining the operation of a readout circuit in a configuration using DISS. [Figure 14] 10 is a graph showing the verification results of a conventional configuration using NV-FF, and a configuration using RLSS and DISS. DETAILED DESCRIPTION OF THE INVENTION

[0034] The present invention is based on logic-in-memory integrated circuit technology and nonvolatile device technology, and enables high density and reduced overhead. To understand the present invention, it is first necessary to understand the differential information storage method, in which a nonvolatile storage area composed of N+1 magnetic tunnel junction elements holds bit information for an N-bit integrated circuit. This will be explained below. The following explanation will be made using drawings. However, the drawings are created for explanatory purposes, and for clarity, elements unnecessary for the explanation may be intentionally omitted. Furthermore, for explanatory purposes, elements may be intentionally enlarged or small, and are not drawn to scale.

[0035] (Difference information storage method) The present invention proposes a new storage method called the Differential Information Storing Scheme (DISS), and the circuit configuration for this purpose is a circuit configuration having a nonvolatile storage area consisting of N+1 magnetic tunnel junction elements (MTJ elements) for an N-bit integrated circuit. Figure 6 is an explanatory diagram showing how a nonvolatile register based on the differential information storage method (hereinafter referred to as a "configuration using DISS") holds bit information, with a truth table shown below. Figure 7 is an explanatory diagram showing the read operation of the configuration using DISS.

[0036] In a DISS-based architecture, as shown in Figure 6, one bit of information is stored based on the difference in the resistance state patterns of two adjacent MTJ elements. Specifically, if the resistance states match, i.e., Rp,Rp or Rap,Rap, a "0" is assigned, and if the resistance states do not match, i.e., Rp,Rap or Rap,Rp, a "1" is assigned. In this method, N bits of information are stored among N+1 MTJ elements, and if the resistance state of the first MTJ element is fixed, only N MTJ elements need to be rewritten. Therefore, a DISS-based architecture can reduce energy consumption and circuit area during data backup, similar to a RLSS-based architecture.

[0037] In a DISS configuration, each MTJ element serves both as a data storage element and as a reference resistor element during read operations. Therefore, as shown in Figure 7, by referencing odd-numbered MTJ elements when reading data stored in even-numbered MTJs and referencing even-numbered MTJ elements when reading data from odd-numbered MTJ elements, simultaneous read operations for even and odd-numbered bits are possible. For example, when reading odd-numbered bits such as the first and third bits, the resistances of the 0th and first MTJ elements and the second and third MTJ elements can be compared simultaneously, as shown in the top of Figure 7. On the other hand, when reading even-numbered bits such as the second and fourth bits, the resistances of the 1st and second MTJ elements and the third and fourth MTJ elements can be compared simultaneously, as shown in the bottom of Figure 7.

[0038] Figure 8 is an explanatory diagram comparing the write and read operations of a conventional NV-FF configuration and configurations using RLSS and DISS. An N-bit nonvolatile register configured with NV-FFs is composed of 2N MTJ elements, and writes and reads are performed in parallel. In a configuration using RLSS, an N-bit register can be configured with N+4 MTJ elements, but this method requires serial writes and reads, resulting in backup and restore operations requiring N cycles each. As the number of bits increases, the number of required cycles also increases proportionally. In contrast, a configuration using DISS can configure an N-bit register with N+1 MTJ elements, and in addition, backup and restore operations can be performed in two cycles each, regardless of the register size. In other words, backup and restore processing can be performed in a constant number of cycles regardless of the number of bits. Having explained the mechanism underlying the present invention, we will now explain specific embodiments of the present invention.

[0039] <Embodiments of the present invention> (Non-volatile register configuration) FIG. 9 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention. Here, an example of a non-volatile register is shown. The non-volatile register 100 according to an embodiment of the present invention is an N-bit register, and as can be seen from the read circuit 2 and backup circuit 4 shown in FIG. 9, it is configured with 1 / 2N 2-bit sub-register blocks (hereinafter sometimes referred to as "SRBs") arranged side by side. That is, the non-volatile register 100 according to an embodiment of the present invention includes N flip-flops 1, 1 / 2N read circuits 2, one controller circuit 3, 1 / 2N backup circuits 4, N+1 MTJ elements (MTJ0 to MTJN), and an initialization circuit 5 for MTJ0.

[0040] Furthermore, each SRB has two flip-flops, two XOR gate circuits, two MTJ elements, one read circuit 2, and one backup circuit 4. The XOR gate circuit is used to convert the information held by the flip-flops into differential information, and the backup circuit 4 applies a rewrite current to both MTJ elements based on the converted information. In this way, the information held by the nth flip-flop is maintained between the (n-1)th MTJ element and the nth MTJ element. Therefore, the read circuit connected to these MTJ elements via the selection NMOS transistor reads the value and returns it to the flip-flop.

[0041] A non-volatile register 100 according to an embodiment of the present invention does not write values ​​to the first MTJ element (MTJ0), but includes a read-only MTJ element (MTJ0), its initialization circuit 5, and a controller circuit 3. The controller circuit 3 receives two external control signals related to backup and restore, and controls the selection of even and odd bits. In the non-volatile register 100 according to an embodiment of the present invention, only flip-flop 1 operates when power is supplied, but this operation is the same as that of a typical flip-flop. However, due to intermittent computing, the processing operations when transitioning to a power gating period and when returning from the power gating period to an operation execution period, i.e., the backup and restore processes, are completely different from those of conventional NV-FF configurations and configurations using RLSSs. These operations are described below.

[0042] (Data backup processing) The data backup process will now be described. FIG. 10 is a diagram illustrating the backup process of a nonvolatile integrated circuit (nonvolatile register) according to an embodiment of the present invention. When a power supply voltage monitoring means (not shown) detects that the voltage has dropped below a threshold, a power cutoff process is executed by power management aimed at intermittent computing. In the nonvolatile register 100 according to an embodiment of the present invention, the backup process is executed immediately before the power is cut off.

[0043] The data held in flip-flop 1 is encoded into differential information through an XOR gate circuit, as shown in the first speech bubble at the top right of Figure 10. This operation is performed by taking the exclusive OR of the previous converted value and the value held by flip-flop 1. As a result of this operation, the matches and mismatches of two adjacent bits in the converted data become the same as the "0" and "1" of the original data.

[0044] The backup circuit 4 determines the direction of the current to be passed according to the converted data and writes the value to the MTJ element. That is, as shown in the second speech bubble at the top right of Figure 10, if the converted data is "0", the MTJ element is rewritten to Rp, and if the converted data is "1", the MTJ element is rewritten to Rap. This value writing is performed for both even and odd bits, so the write process takes two cycles.

[0045] (Data restoration process) The data restore process will now be described. FIG. 11 is a diagram illustrating the restore process of a nonvolatile integrated circuit (nonvolatile register) according to an embodiment of the present invention. When energy is accumulated by energy harvesting and a power supply voltage monitoring means (not shown) detects that the voltage has recovered to a certain level, an open process is executed by power management aimed at intermittent computing. After recovering from the power-off state, the nonvolatile register 100 according to an embodiment of the present invention performs a recovery operation.

[0046] The read circuit 2, which is specially prepared for the DISS configuration and will be described later, is connected to the two MTJ elements via NMOS transistors. A read current is then passed through the two MTJ elements to determine whether their resistance states match or mismatch. The read circuit 2 outputs "0" if the resistance states match, and "1" if the resistance states mismatch. This means that the data stored in the flip-flop 1 has been decoded to the original data. The restore operation is completed by returning this decoded value directly to the two corresponding flip-flops 1. This operation is also performed separately for even and odd bits, so it takes two cycles to complete.

[0047] (Readout circuit) In conventional NV-FF configurations and configurations using RLSS, information can be read by amplifying the voltage difference that arises from the difference in current due to the resistance between two MTJ elements, but in configurations using DISS, a special circuit is required to determine whether the resistance states match or mismatch. Figure 12 is a diagram explaining the structure of the read circuit in a configuration using DISS, and Figure 13 is a diagram explaining the operation of the read circuit in a configuration using DISS.

[0048] When a normal precharge sense amplifier is used for a state where the resistance values ​​match, no voltage difference occurs and proper amplification is not possible. Therefore, the readout circuit 2 in the nonvolatile register 100 according to an embodiment of the present invention has a circuit configuration in which two latches with asymmetric characteristics, created by appropriately adjusting the transistor sizes, are connected complementarily. The resistance states of the two MTJ elements can take four combinations: (Rp, Rap), (Rp, Rp), (Rap, Rap), and (Rap, Rp). The first latch distinguishes between the resistance state (Rp, Rap) and the other three states and outputs a "0" or a "1" to B1 or B2. The second latch distinguishes between the resistance state (Rap, Rp) and the other three states and outputs a "0" or a "1" to B3 or B4. By dually connecting these two latches, it becomes possible to detect when the resistance state pattern is Rp, Rap and when it is Rap, Rp.

[0049] The two latches detect two patterns of mismatched resistance values, and the voltages at the four output terminals are different in each of the following cases: (1) when the resistance values ​​match, (2) when MTJ1 has a higher resistance value, and (3) when MTJ2 has a higher resistance value. Then, by performing a NAND operation on the outputs of terminals B1 and B4 of the two latch outputs, a "0" is output when the resistance states of the MTJ elements match, and a "1" is output when the resistance states do not match, as shown in the truth table in Figure 13.

[0050] (Performance evaluation) We designed and verified nonvolatile registers ranging from 2 bits to 32 bits for the conventional configuration using NV-FF, the configuration using RLSS, and the configuration using DISS. Specifically, we designed them using 55nm CMOS / MTJ hybrid process technology and evaluated them using the circuit simulator "HSPICE." Figure 14 is a graph showing the verification results for the conventional configuration using NV-FF, the configuration using RLSS, and the configuration using DISS. Note that the legend for the graph of the conventional configuration using NV-FF is written as "Conventional" (Conv.).

[0051] The graph on the left in Figure 14 shows the energy consumption per bit. Most of the energy consumed during data backup is the energy required to write to the MTJ elements. The number of MTJ elements used for rewriting was 2N in the conventional NV-FF configuration, but is reduced to N in the configurations using RLSS and DISS. This allows for a reduction in energy consumption during data backup.

[0052] The graph in the middle of Figure 14 shows the circuit area. In the configuration using RLSS or DISS, as the register size increases, the scale of the shared reference MTJ element, controller, etc. increases, so the circuit area per bit decreases.

[0053] On the other hand, as shown in the graph on the right of Figure 14, the time required for data backup and restoration in a configuration using RLSS increases in proportion to the size of the register. In contrast, a configuration using DISS can execute data backup and restoration processing in a constant time regardless of the size of the register.

[0054] When configuring a 32-bit register, the configurations using RLSS and DISS reduced energy consumption during backup by 49% compared to the conventional configuration, and the circuit area was also reduced by 34% compared to the conventional configuration.On the other hand, while the configuration using RLSS required time for data standby recovery processing, the configuration using DISS confirmed that the time was the same as the conventional configuration.

[0055] Although the nonvolatile integrated circuit according to the embodiment of the present invention has been described in detail above, the specific configuration is not limited to these embodiments, and the present invention also includes design changes within the scope of the present invention. For example, a static random access memory (SRAM) may be used instead of a register, the NMOS described as a transistor switch configuration may be configured with a CMOS, and the flip-flop described as a D flip-flop may be configured with an RS flip-flop or a JK flip-flop. Furthermore, the read-only MTJ element may be the last MTJ element (MTJN+1) instead of the first MTJ element (MTJ0). [Explanation of symbols]

[0056] 1 flip-flop 2 Readout circuit 3 Controller circuit 4 Backup circuit 5 Initialization circuit 100 Non-volatile Registers

Claims

1. A nonvolatile integrated circuit that saves and holds each bit information stored in a plurality of flip-flops when power is supplied to a nonvolatile storage area when power is cut off, The nonvolatile integrated circuit is configured with N bits, The nonvolatile storage area is composed of N+1 magnetic tunnel junction elements. A non-volatile integrated circuit comprising:

2. One magnetic tunnel junction element is associated with a flip-flop constituting the n-th bit, and The 0 or 1 state of the flip-flop constituting the n-th bit is linked to the match or mismatch between the resistance value of the n-th magnetic tunnel junction element and the resistance value of the (n+1)-th magnetic tunnel junction element.

2. The nonvolatile integrated circuit according to claim 1.

3. Writing to and reading from the nonvolatile storage area is performed in two cycles in which processing to odd-numbered magnetic tunnel junction elements and processing to even-numbered magnetic tunnel junction elements are performed alternately.

3. The nonvolatile integrated circuit according to claim 2.

4. Writing to the n-th magnetic tunnel junction element in the nonvolatile storage area is performed based on the output of an exclusive OR circuit, and the output of the (n-1)-th exclusive OR circuit (however, a predetermined value when n=1) and the output of the n-th flip-flop are connected to the inputs of the exclusive OR circuit.

4. The nonvolatile integrated circuit according to claim 3.

5. Reading from the nonvolatile storage area is performed using a magnetic tunnel junction element difference state reading circuit that outputs 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or mismatch.

4. The nonvolatile integrated circuit according to claim 3.

6. A nonvolatile integrated circuit having an N-bit configuration, in which bit information stored and held in a plurality of flip-flops when power is supplied is saved in a nonvolatile storage area when power is cut off, N+1 magnetic tunnel junction elements and a control unit; The control unit writes data to the n-th magnetic tunnel junction element of the nonvolatile memory area based on the output of the exclusive OR circuit, by connecting the output of the (n-1)th exclusive OR circuit (however, when n=1, a predetermined value) and the output of the n-th flip-flop to the input of the exclusive OR circuit, and The control unit performs reading by outputting 0 or 1 depending on whether the resistance values ​​of adjacent magnetic tunnel junction elements match or mismatch. A non-volatile integrated circuit comprising:

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