Etching Method

Abstract

To provide an etching method capable of reducing processing defects in etching using a catalyst.SOLUTION: According to an embodiment, there is provided an etching method for etching a surface 1 comprising a semiconductor by contacting an etching agent 5 with a surface 1 on which a catalyst layer 3 containing a precious metal is formed and comprising a semiconductor. The etching agent includes an oxidizing agent, a corrosive agent, and an N-containing polymer additive.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION An embodiment of the present invention relates to an etching method. [Background technology]

[0002] Etching is a known method for forming holes and grooves in semiconductor wafers. One known etching method is MacEtch (Metal-Assisted Chemical Etching). MacEtch is a method for etching a semiconductor substrate using, for example, a precious metal as a catalyst. When a semiconductor wafer is immersed in a MacEtch solution for a long period of time to form a high-aspect-ratio trench in the semiconductor wafer, minute hole-like processing defects occur on the wall surface at the top of the trench. This can result in problems such as the collapse of the trench due to a decrease in strength and difficulty in forming a dielectric film in the trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-50365 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-60846 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the embodiment, an etching method is provided that can reduce processing defects in etching using a catalyst. [Means for solving the problem]

[0005] According to an embodiment, a catalyst layer containing a precious metal is formed, and Contains silicon The surface made of a semiconductor is etched by bringing an etching agent into contact with the surface made of a semiconductor. forming a recess byAn etching method is provided, in which the etching agent includes an oxidizing agent, a caustic agent, and an N-containing surfactant. The N-containing surfactant is selected from the group consisting of polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetraamine, tetraethylenepentamine, pentaethylenehexamine, polyoxyethylenealkylamine, and the like. N, and and ethylenediaminetetrakis(propoxylate-block-ethoxylate)tetrol. The process is carried out in a state where a protective layer containing an N-containing surfactant is present on the upper end of the recess. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic diagram showing a step of a method according to an embodiment. [Figure 2] Schematic diagram of an enlarged view of part A in Figure 1. [Figure 3] FIG. 1 is a graph showing the relationship between pH and the zeta potential of Si oxide. [Figure 4] 1 is a scanning electron microscope photograph showing a cross section of a trench formed by a method according to an embodiment of the present invention. [Figure 5] 10 is a scanning electron microscope photograph showing a cross section near the upper end of a trench formed by a method according to an embodiment of the present invention. [Figure 6] 10 is a scanning electron microscope photograph showing a cross section of a trench formed by a method of a comparative example. [Figure 7] 10 is a scanning electron microscope photograph showing a cross section near the top end of a trench formed by a method of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that components that perform the same or similar functions are designated by the same reference numerals throughout the drawings, and redundant explanations will be omitted. (First embodiment) According to a first embodiment, there is provided an etching method. The etching method is an etching method for etching a surface made of a semiconductor, on which a catalyst layer containing a noble metal is formed, by bringing an etching agent into contact with the surface made of a semiconductor. The etching agent includes an oxidizing agent, a corrosive agent, and an N-containing polymer additive.

[0008] When a catalytic layer containing a noble metal is formed and an etching agent comes into contact with a semiconductor surface, the oxidizing agent oxidizes the portion of the surface adjacent to the noble metal, and the corrosive agent dissolves and removes the oxide. Therefore, under the action of the catalytic layer, the etching agent can etch the semiconductor surface in a direction perpendicular to the surface. This allows for the formation of recesses such as trenches in the semiconductor surface.

[0009] It is believed that hole-like processing defects occurring on the wall near the top of recesses such as trenches are caused by the dissolution of oxides of the semiconductor material in this area by the corrosive action of the etching agent. These oxides tend to have a positive zeta potential in the etching agent. On the other hand, N-containing polymer additives have a lone pair of electrons from the nitrogen atom. Therefore, N-containing polymer additives tend to adsorb easily to oxides of the semiconductor material in the etching agent, but are less likely to adsorb to the catalyst surface, which has a negative zeta potential. Therefore, N-containing polymer additives can selectively adsorb near the top of the recess and protect it from the etching agent. As a result, processing defects near the top of the recess can be suppressed, even when the surface is immersed in the etching agent for a long time to form recesses with a high aspect ratio.

[0010] The method of the embodiment will now be described in detail.

[0011] The semiconductor may be selected from silicon (Si); germanium (Ge); semiconductors made of compounds of group III and group V elements, such as gallium arsenide (GaAs) and gallium nitride (GaN); and silicon carbide (SiC). In one example, the semiconductor substrate includes silicon. Note that the term "group" as used herein refers to a group in the short periodic table.

[0012] The surface made of a semiconductor may be, for example, the main surface of a semiconductor substrate. The semiconductor substrate may be, for example, a semiconductor wafer. The semiconductor wafer may be doped with impurities, and may have semiconductor elements such as transistors and diodes formed thereon. The main surface of the semiconductor wafer may be parallel to any crystal plane of the semiconductor. For example, the semiconductor wafer may be a silicon wafer whose main surface is a (100) plane or a silicon wafer whose main surface is a (110) plane.

[0013] When forming a pattern having recesses such as trenches on a semiconductor surface, a mask layer having openings may be formed on the semiconductor surface. The surface exposed through the openings is then etched. The mask layer may be formed from an inorganic material such as a silicon nitride compound. The mask layer may also be prepared, for example, by a method including the following steps: First, a mask layer is formed on the semiconductor surface. A resist layer is formed on the mask layer. The resist layer may be formed from, for example, photoresist. The resist layer is processed into a desired pattern shape to form openings. The pattern is formed, for example, by photolithography. The mask layer is processed into a desired pattern shape, for example, by etching, to form openings in the mask layer. Then, the resist layer is removed.

[0014] A catalyst layer containing a noble metal is formed on the surface of the semiconductor, which may be formed after a mask layer is formed on the surface of the semiconductor.

[0015] In the catalyst layer, the noble metal may be present as noble metal particles, for example, one or more metals selected from the group consisting of Au, Ag, Pt, Pd, Ru, and Rh.

[0016] The thickness of the catalyst layer is preferably in the range of 0.01 μm to 0.3 μm, and more preferably in the range of 0.05 μm to 0.2 μm. If the catalyst layer is too thick, the etching agent has difficulty reaching the semiconductor, and etching proceeds slowly. If the catalyst layer is too thin, the ratio of the total surface area of ​​the precious metal particles to the area to be etched is too small, and etching proceeds slowly.

[0017] The thickness of the catalyst layer is the distance from one main surface of the catalyst layer to the opposite main surface in an image of a cross section parallel to the thickness direction thereof observed with a scanning electron microscope (SEM).

[0018] The catalyst layer may have discontinuous portions.

[0019] The noble metal particles are preferably spherical in shape, but may also have other shapes, such as rods or plates, and act as catalysts for the oxidation reaction of the semiconductor surface in contact with them.

[0020] The particle size of the noble metal particles is preferably in the range of 0.001 μm to 1 μm, and more preferably in the range of 0.01 μm to 0.5 μm.

[0021] Here, the "particle size" is a value obtained by the following method. First, the main surface of the catalyst layer is photographed using a scanning electron microscope. The magnification is set to a range of 10,000 to 100,000 times. Next, the area of ​​each precious metal particle is determined from the image. Next, assuming that each precious metal particle is spherical, the diameter of the precious metal particle is determined from the area. This diameter is defined as the "particle size" of the precious metal particle.

[0022] The catalyst layer may be a porous catalyst layer.

[0023] The catalyst layer can be formed by, for example, electrolytic plating, reduction plating, or displacement plating. The catalyst layer may be formed by applying a dispersion containing precious metal particles or by a vapor-phase deposition method such as vapor deposition or sputtering. Among these methods, displacement plating is particularly preferred because it allows the precious metal to be deposited directly and uniformly on the semiconductor surface. The formation of a porous catalyst layer by displacement plating will be described below as an example.

[0024] For example, an aqueous solution of tetrachloroaurate (III) or silver nitrate can be used to deposit a precious metal by displacement plating. An example of this process is described below.

[0025] The displacement plating solution is, for example, a mixture of an aqueous solution of tetrachloroauric acid (III) tetrahydrate and hydrofluoric acid, which has the effect of removing native oxide films from semiconductor surfaces.

[0026] When a semiconductor substrate is immersed in a displacement plating solution, the native oxide film on the surface of the semiconductor substrate is removed and a precious metal, in this case gold, is deposited on the surface of the semiconductor substrate, thereby forming a porous catalyst layer.

[0027] The concentration of tetrachloroauric(III) acid tetrahydrate in the displacement plating solution is preferably in the range of 0.0001 mol / L to 0.01 mol / L, and the concentration of hydrogen fluoride in the displacement plating solution is preferably in the range of 0.1 mol / L to 6.5 mol / L.

[0028] The displacement plating solution may further contain a sulfur-based complexing agent, or may further contain glycine and citric acid.

[0029] The etching agent includes a corrosive agent, an oxidizing agent, and an N-containing polymer additive.

[0030] The etchant can dissolve the oxide of the semiconductor material. The oxide is, for example, SiO2. The etchant can be, for example, hydrofluoric acid or ammonium fluoride. One or more types of etchant can be used. In consideration of the etching rate and the ease of adsorption of the N-containing polymer additive, a etchant containing hydrofluoric acid is preferred.

[0031] The hydrogen fluoride concentration in the etching agent is preferably in the range of 0.4 mol / L to 20 mol / L, more preferably in the range of 0.8 mol / L to 16 mol / L, and even more preferably in the range of 2 mol / L to 10 mol / L. If the hydrogen fluoride concentration is too low, it is difficult to achieve a high etching rate. If the hydrogen fluoride concentration is too high, there is a possibility that the controllability of etching in the processing direction (e.g., the thickness direction of the semiconductor substrate) will decrease.

[0032] The oxidizing agent in the etching agent may be at least one selected from the group consisting of hydrogen peroxide, nitric acid, AgNO3, KAuCl4, HAuCl4, K2PtCl6, HPtCl6, Fe(NO3)3, Ni(NO3)2, Mg(NO3)2, Na2S2O8, K2S2O8, KMnO4, and K2Cr2O7. Hydrogen peroxide is preferred as the oxidizing agent because it does not produce harmful by-products and does not contaminate semiconductor elements.

[0033] The concentration of the oxidizing agent, such as hydrogen peroxide, in the etching agent is preferably in the range of 0.2 mol / L to 8 mol / L, more preferably in the range of 0.5 mol / L to 5 mol / L, and even more preferably in the range of 0.5 mol / L to 4 mol / L. If the oxidizing agent concentration is too low, it is difficult to achieve a high etching rate. If the oxidizing agent concentration is too high, excessive side etching may occur.

[0034] The N-containing polymer additive is not particularly limited as long as it is a polymer containing a nitrogen atom, and examples thereof include N-containing surfactants. The N-containing surfactant is preferably an N-containing nonionic surfactant and / or an N-containing cationic surfactant.

[0035] Examples of N-containing cationic surfactants include polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetraamine, tetraethylenepentamine, pentaethylenehexamine, and polyoxyethylene alkylamine. Examples of N-containing nonionic surfactants include ,workman ethylenediaminetetrakis(propoxylate-block-ethoxylate)tetrol.

[0036] The type of N-containing polymeric additive used may be one or more types. A preferred N-containing polymeric additive is one containing polyethyleneimine.

[0037] The content of the N-containing polymer additive in the etching solution can be, for example, 0.0001% by volume or more and 0.01% by volume or less. By setting the content to 0.0001% by volume or more, it is expected that processing defects on the wall surfaces defining the recesses can be suppressed. Furthermore, by setting the content to 0.01% by volume or less, it is possible to prevent the etching rate from becoming extremely slow. A preferred range can be 0.005% by volume or more and 0.01% by volume or less.

[0038] The etchant may include water as a solvent. The etchant may be an aqueous solution.

[0039] The etching agent may be an aqueous solution having a pH in the range of, for example, 1 to 2. By adjusting the pH to this range, it is possible to promote the adsorption of the N-containing polymer additive onto the oxide of the semiconductor material while maintaining a practical etching rate.

[0040] An example of an etching method according to an embodiment will be described with reference to FIGS.

[0041] FIG. 1 is a schematic diagram showing a process for etching a trench in a principal surface of a semiconductor substrate 1 along the xy plane. The semiconductor substrate 1 may be, for example, a silicon wafer. A trench is formed in the principal surface of the semiconductor substrate 1 along the xy plane. The trench extends along the y-axis direction. A catalyst layer 3 containing, for example, Au particles is formed on the bottom surface that defines the trench in the principal surface of the semiconductor substrate 1 along the xy plane. The surface near the upper end of the partition wall portion 2 that defines the trench is covered with a protective layer 4 containing an N-containing polymer additive. The N-containing polymer additive may be, for example, polyethyleneimine. The principal surface of the semiconductor substrate 1 along the xy plane and the partition wall portion 2 are entirely immersed in an etching solution 5 as an etchant.

[0042] Etching is performed, for example, after forming a mask layer having a desired pattern on the main surface of the semiconductor substrate 1. As the etching progresses, a portion of the mask layer dissolves or peels off in the etching agent 5. As a result, a portion of the upper end surface of the partition wall 2 comes into direct contact with the etching agent 5. Therefore, as illustrated in FIG. 2, the upper end of the partition wall 2 is partially oxidized, forming a silicon oxide 6 such as SiO2 in that portion. The silicon oxide 6 such as SiO2 can have a positive zeta potential in the etching solution. FIG. 3 shows the relationship between the zeta potential of the SiO2 particle surface and pH. The horizontal axis of FIG. 3 represents pH, and the vertical axis represents zeta potential (mV). As shown in FIG. 3, the zeta potential of the SiO2 particle surface is positive at pH 4 or below. Note that the zeta potential of the silicon surface is negative at pH 4 or below.

[0043] On the other hand, N-containing polymer additives such as polyethyleneimine have many lone electron pairs and therefore are easily adsorbed to silicon oxide 6, which has a positive zeta potential in etching solution 5. On the other hand, N-containing polymer additives such as polyethyleneimine cannot be adsorbed to catalyst surfaces or semiconductor surfaces, which can have negative zeta potentials in etching solution 5, and therefore do not impede processing. For example, the zeta potential of Au is -20.4 mV at pH 1 to 2.

[0044] As described above, the protective layer 4 containing the N-containing polymer additive can selectively adsorb to the Si oxide 6 present near the upper end of the partition wall 2, thereby protecting the upper end of the partition wall 2 from the etching solution 5 while etching. Therefore, even when forming trenches with high aspect ratios, processing defects of the partition wall 2 can be suppressed. This effect cannot be obtained when polyethyleneimine is contained in the catalyst layer 3 rather than in the etching agent. For example, if the catalyst layer 3 is formed by applying a dispersion containing Au particles and polyethyleneimine to the main surface of the semiconductor substrate 1 and drying it, etching does not proceed perpendicular to the semiconductor main surface even when the substrate is immersed in the etching solution for a long time, and a trench with a high aspect ratio cannot be obtained. The maximum depth of trenches that can be processed perpendicularly is approximately several tens of micrometers.

[0045] The method of the embodiment may include a step of removing the N-containing polymer additive from the semiconductor surface (semiconductor surface) after the etching step. Examples of removal methods include, for example, washing the semiconductor surface with an alkaline aqueous solution or an organic solvent. The method of the embodiment may also include a step of removing the catalyst layer from the semiconductor surface, if necessary, after the etching step. If there is a mask layer residue, the method of the embodiment may include a step of removing the mask layer from the semiconductor surface. When the method of the embodiment includes a step of removing the catalyst layer from the semiconductor surface or a step of removing the mask layer from the semiconductor surface, the N-containing polymer additive can be removed in these steps. Aqua regia, for example, can be used to remove the catalyst layer. Meanwhile, hot phosphoric acid, for example, can be used to remove the mask layer.

[0046] The method of the embodiment can be applied to, for example, a pattern formation method for forming recesses such as trenches or through-holes in a semiconductor substrate. Furthermore, according to the method of the embodiment, a semiconductor device can be manufactured by forming a conductive layer by plating in the recesses or through-holes formed in the semiconductor substrate, or by forming a dielectric film by chemical vapor deposition (CVD), or by forming a wiring layer above the semiconductor substrate. [Example]

[0047] Examples and comparative examples will be described below. (Example) A trench was formed in a semiconductor substrate by etching using the following method, and after etching, it was confirmed whether or not pore-like damage occurred on the wall surface of the trench.

[0048] A silicon wafer was used as the semiconductor substrate. First, a mask layer made of a silicon nitride compound was formed on the first main surface of the semiconductor substrate. The mask layer had openings at regular intervals.

[0049] A 50 mL plating solution containing an aqueous solution of tetrachloroauric acid (III) tetrahydrate and hydrofluoric acid was prepared. The semiconductor substrate with the mask layer formed thereon was immersed in the plating solution at room temperature for 60 seconds to form a catalyst layer on the first principal surface exposed through the openings in the mask layer.

[0050] An aqueous solution containing 5 mol / L hydrogen fluoride, 4 mol / L hydrogen peroxide, and 0.0001% by volume of polyethyleneimine was prepared as an etching solution. A semiconductor substrate having a mask layer and a catalyst layer formed thereon was immersed in this etching solution for 50 minutes at 25°C to etch it. The pH of the etching solution was 1 or less. Figure 4 shows a scanning electron microscope image of the semiconductor substrate after etching. Figure 5 shows a magnified scanning electron microscope image of the vicinity of the upper end of the partition wall defining the trench of the semiconductor substrate shown in Figure 4.

[0051] As shown in Figure 4, no processing defects were observed on the surface of the partition wall that defines the trench in the semiconductor substrate. Furthermore, as shown in Figure 5, even when the vicinity of the upper end of the partition wall was observed under magnification, no processing defects were found on the surface of the partition wall.

[0052] (Comparative Example) An etching solution was prepared with the same composition and pH as in the Examples, except that it did not contain polyethyleneimine. Etching was performed in the same manner as in the Examples, except that this etching solution was used. FIG. 6 shows a scanning electron microscope image of the semiconductor substrate after etching. FIG. 7 shows an enlarged scanning electron microscope image of the vicinity of the upper end of the partition wall defining the trench in the semiconductor substrate shown in FIG. 6.

[0053] As shown in Figure 6, processing defects were confirmed on the surface of the partition wall that defines the trench in the semiconductor substrate. Furthermore, as shown in Figure 7, when the area near the top end of the partition wall was observed under magnification, it was confirmed that the entire area near the top end of the partition wall was processing defects.

[0054] According to at least one of the above-described embodiments or examples, in a method for etching a semiconductor surface by bringing an etching agent into contact with a semiconductor surface on which a catalyst layer containing a noble metal is formed, an etching method can be provided in which the etching agent contains an oxidizing agent, a corrosive agent, and an N-containing polymer additive, and therefore processing defects can be reduced.

[0055] The invention of the embodiment will be described below.

[0056] According to an embodiment, there is provided an etching method for etching a surface made of a semiconductor, on which a catalyst layer containing a noble metal is formed, by bringing an etching agent into contact with the surface made of the semiconductor, wherein the etching agent contains an oxidizing agent, a corrosive agent, and an N-containing polymer additive.

[0057] According to an embodiment, there is provided a pattern formation method in which a catalyst layer containing a noble metal is formed on a surface made of a semiconductor, and recesses are formed on the surface made of the semiconductor by bringing an etching agent into contact with the surface, wherein the etching agent contains an oxidizing agent, a corrosive agent, and an N-containing polymer additive.

[0058] According to an embodiment, a semiconductor substrate having a catalyst layer containing a noble metal formed thereon is brought into contact with an etching agent containing an oxidizing agent, a corrosive agent, and an N-containing polymer additive to form a recess in the semiconductor substrate; forming a wiring layer above the semiconductor substrate; A method for manufacturing a semiconductor device is provided, including:

[0059] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. The inventions described in the original claims of this application are set forth below. [1] An etching method for etching a surface made of a semiconductor having a catalyst layer containing a noble metal formed thereon by bringing an etching agent into contact with the surface made of the semiconductor, the method comprising: The etching method, wherein the etching agent comprises an oxidizing agent, a caustic agent, and an N-containing polymeric additive. [2] The etching method according to [1], wherein the N-containing polymer additive is an N-containing surfactant. [3] The etching method according to [1], wherein the N-containing polymer additive is an N-containing nonionic surfactant and / or an N-containing cationic surfactant. [4] The etching method according to [1], wherein the N-containing polymer additive is at least one selected from the group consisting of polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetraamine, tetraethylenepentamine, pentaethylenehexamine, polyoxyethylenealkylamine, poly(oxyethylene)octylphenyl ether, and ethylenediaminetetrakis(propoxylate-block-ethoxylate)tetrol. [5] The etching method according to any one of [1] to [4], wherein the semiconductor contains silicon. [6] The etching method according to any one of [1] to [5], wherein the noble metal includes gold. [7] The etching method according to any one of [1] to [6], wherein the catalyst layer containing a noble metal is porous. [8] The etching method according to any one of [1] to [7], wherein the catalyst layer containing a noble metal is formed by displacement plating. [9] The etching method according to any one of [1] to [8], wherein the oxidizing agent is hydrogen peroxide and the corrosive agent is hydrogen fluoride. [Explanation of symbols]

[0060] 1...semiconductor substrate, 2...partition wall portion, 3...catalyst layer, 4...protective layer, 5...etchant, 6...Si oxide

Claims

1. 1. An etching method comprising: a step of contacting an etching agent with a surface of a semiconductor including silicon, on which a catalyst layer including a noble metal has been formed, to etch the surface of the semiconductor, thereby forming a recess; the etching agent includes an oxidizing agent, a caustic agent, and an N-containing surfactant; the N-containing surfactant is at least one selected from the group consisting of polyethyleneimine, ethylenediamine, diethylenetriamine, triethylenetetraamine, tetraethylenepentamine, pentaethylenehexamine, polyoxyethylenealkylamine, and ethylenediaminetetrakis(propoxylate-block-ethoxylate)tetrol; The etching method is performed in a state where a protective layer containing the N-containing surfactant is present on an upper end of the recess.

2. The etching method of claim 1 , wherein the N-containing surfactant comprises polyethyleneimine.

3. 3. The etching method according to claim 1, wherein the noble metal includes gold.

4. 4. The etching method according to claim 1, wherein the catalyst layer containing a noble metal is porous.

5. 5. The etching method according to claim 1, wherein the catalytic layer containing a noble metal is formed by displacement plating.

6. 6. The etching method according to claim 1, wherein the oxidizing agent is hydrogen peroxide and the corrosive agent is hydrogen fluoride.

7. 7. The etching method according to claim 1, wherein the etching agent is an aqueous solution having a pH in the range of 1 to 2.

8. 8. The etching method according to claim 1, wherein the content of the N-containing surfactant in the etching agent is 0.0001% by volume or more and 0.01% by volume or less.

9. 8. The etching method according to claim 1, wherein the content of the N-containing surfactant in the etching agent is 0.005% by volume or more and 0.01% by volume or less.

Images