Pattern inspection method, resist pattern manufacturing method, target substrate selection method, and target substrate manufacturing method

Abstract

This pattern inspection method comprises: a coordinate measurement step for measuring coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, in a target substrate which is one of a printed wiring board and a semiconductor package substrate for mounting thereon a semiconductor element having formed therein the pattern; and an inspection step for inspecting the pattern on the basis of the coordinates. This target substrate selection method comprises: a coordinate measurement step for measuring coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, in a target substrate which is one of a printed wiring board and a semiconductor package substrate for mounting thereon a semiconductor element having formed therein the pattern; an inspection step for inspecting the pattern on the basis of the measured coordinates; and an evaluation step for evaluating the pattern on the basis of the inspection result in the inspection step.

Description

[Technical Field]

[0001] The present disclosure relates to a method for inspecting a pattern, which is either a resist pattern or a conductor pattern, formed on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, a method for manufacturing a resist pattern formed on a target substrate, a method for selecting target substrates, and a method for manufacturing target substrates. [Background technology]

[0002] In the manufacture of semiconductor devices, a scanning microscope is used to inspect resist patterns or conductor patterns formed on silicon wafers, which are the substrates of the semiconductor devices (see, for example, Patent Documents 1 and 2). Inspection of the resist patterns or conductor patterns formed on the silicon wafers is carried out by determining the roughness index of the resist patterns or conductor patterns through pattern observation using a scanning microscope.

[0003] Meanwhile, resist patterns or conductor patterns are also formed on semiconductor package substrates or printed wiring boards for mounting semiconductor elements (see, for example, Patent Document 3). However, the pitch of the resist patterns or conductor patterns formed on the semiconductor package substrates or printed wiring boards is much larger than the pitch of the resist patterns or conductor patterns formed on the semiconductor element substrates. Therefore, the impact of the roughness of the resist patterns or conductor patterns formed on the semiconductor package substrates or printed wiring boards on their electrical characteristics is much smaller than the impact of the roughness of the resist patterns or conductor patterns formed on the semiconductor element substrates. Examples of such electrical characteristics include biased highly accelerated stress tests (insulation reliability) and transmission loss. For this reason, in the past, the roughness of resist patterns or conductor patterns formed on semiconductor package substrates or printed wiring boards was not inspected, or only qualitative inspections using a microscope or visual inspection were performed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-215020 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-251743 [Patent Document 3] Japanese Patent Application Laid-Open No. 2005-207802 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, there has been a demand for finer conductor patterns in semiconductor package substrates or printed wiring boards. In addition, along with the demand for finer conductor patterns, there has also been a demand for finer resist patterns for forming the conductor patterns. When the resist pattern or the conductor pattern is made finer, there is a possibility that defects such as a decrease in the electrical properties of the manufactured semiconductor package may occur.

[0006] If it were possible to inspect the resist pattern or conductor pattern formed on a semiconductor package substrate or a printed wiring board, it would be possible to discover the above-mentioned defects at an earlier stage in the manufacture of semiconductor packages, etc. Furthermore, evaluating the yield of the resist pattern formation or conductor pattern formation on the semiconductor package substrate or printed wiring board can lead to improvements in the resist pattern formation or conductor pattern formation on the semiconductor package substrate or printed wiring board.

[0007] However, as described above, in the past, resist patterns or conductor patterns formed on semiconductor package substrates or printed wiring boards have not been inspected, or have only been inspected qualitatively using a microscope or visually. Furthermore, because semiconductor package substrates or printed wiring boards differ from semiconductor elements in terms of the width of the inspection range, the uniformity of the thickness of the inspection target, and the distortion and warpage of the inspection target substrate, it has been difficult or impossible to inspect resist patterns or conductor patterns formed on semiconductor package substrates or printed wiring boards. For this reason, in the past, when resist patterns or conductor patterns formed on semiconductor package substrates or printed wiring boards are miniaturized, it has been completely unknown how to evaluate the resist patterns or conductor patterns formed on semiconductor package substrates or printed wiring boards.

[0008] Therefore, the present disclosure aims to provide a pattern inspection method that can evaluate a pattern, which is either a resist pattern or a conductor pattern formed on a target substrate, which is either a semiconductor package substrate or a printed wiring board, even if the pattern is miniaturized, a resist pattern manufacturing method, a target substrate selection method, and a target substrate manufacturing method. [Means for solving the problem]

[0009] As a result of intensive research into the above-mentioned problems, the inventors have found that it is possible to measure the coordinates of the contour of a pattern formed on a target substrate and evaluate the pattern based on the measurement results. The present disclosure is based on this finding.

[0010] [1] The disclosed pattern inspection method is a method for inspecting a pattern that is either a resist pattern or a conductor pattern formed on a target substrate that is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board. This pattern inspection method includes a coordinate measurement step of measuring the coordinates of the outline of the pattern, and an inspection step of inspecting the pattern based on the measured coordinates.

[0011] This pattern inspection method measures the coordinates of the contour of a pattern formed on a target substrate and inspects the pattern based on these measured coordinates. Therefore, even if the pattern formed on the target substrate is miniaturized, the pattern can be evaluated. Moreover, the pattern can be evaluated with higher accuracy than when inspected visually.

[0012] [2] In the pattern inspection method described in [1], the inspection step may include calculating the roughness of the pattern based on the measured coordinates as part of the pattern inspection. In this pattern inspection method, the roughness of the pattern is calculated based on the coordinates of the measured contour as part of the pattern inspection. This allows the pattern formation state to be appropriately evaluated.

[0013] [3] In the pattern inspection method according to [1] or [2], the inspection step may include calculating the variation in the pattern contour based on the measured coordinates as part of the pattern inspection. In this pattern inspection method, the variation in the pattern contour is calculated based on the coordinates of the measured contour as part of the pattern inspection. This allows the pattern formation state to be appropriately evaluated.

[0014] [4] In the pattern inspection method according to [1] or [2], the inspection step may include calculating the line width and line width variation of the pattern based on the measured coordinates as part of the pattern inspection. In this pattern inspection method, the line width and line width variation of the pattern are calculated based on the measured coordinates of the contour as part of the pattern inspection. This allows the pattern formation state to be appropriately evaluated.

[0015] [5] In the pattern inspection method according to any one of [1] to [4], the inspection step may include comparing the measured coordinates with a pattern for forming the pattern as the pattern inspection. In this pattern inspection method, the measured coordinates of the contour are compared with pattern data for forming the pattern as the pattern inspection. This allows the pattern formation state to be evaluated with high accuracy.

[0016] [6] In the pattern inspection method according to any one of [1] to [5], the target substrate may have an inorganic component including at least one of silica filler and glass cloth, and an organic component including at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin. In this pattern inspection method, the target substrate has an inorganic component including at least one of silica filler and glass cloth, which are not used in semiconductor element substrates, and an organic component including at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin. Therefore, compared to inspecting a pattern formed on a substrate of a semiconductor device, there are problems and difficulties such as distortion and warpage of the inspection target. However, by providing the coordinate measurement process and inspection process described above, it is possible to evaluate the pattern formed on the target substrate.

[0017] [7] In the pattern inspection method according to any one of [1] to [6], the target substrate may have at least one of a core layer and a build-up layer. In this pattern inspection method, the target substrate has at least one of a core layer and a build-up layer that is different in structure from the substrate of the semiconductor element. Therefore, compared to inspecting a pattern formed on a substrate of a semiconductor element, there are problems and difficulties such as distortion and warpage of the inspection target. However, by including the above-mentioned coordinate measurement process and inspection process, it is possible to evaluate the pattern formed on the target substrate.

[0018] [8] In the pattern inspection method according to any one of [1] to [7], the thickness of the target substrate may be 50 μm or more and 3000 μm or less. In this pattern inspection method, the thickness of the target substrate is 50 μm or more and 3000 μm or less, which is different from the thickness of the substrate of the semiconductor element. Therefore, compared to inspecting a pattern formed on a substrate of a semiconductor element, there are problems and difficulties such as the focal position of the inspection target changing significantly depending on the observation location due to distortion and warpage of the inspection target and variations in the thickness of the inspection target, making it impossible to focus on the resist pattern and conductors. However, by including the above-mentioned coordinate measurement process and inspection process, it is possible to evaluate the pattern formed on the target substrate.

[0019] [9] In the pattern inspection method according to any one of [1] to [8], the pattern may be a resist pattern, and the resist pattern may contain a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator. In this pattern inspection method, the resist pattern formed on the target substrate contains a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator that are different from the resist pattern formed on the semiconductor element substrate. Because semiconductor element substrates lack a support and have a thin film thickness, using a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator in the manufacture of semiconductor element substrates can cause problems and difficulties, such as the influence of oxygen in the exposure atmosphere inhibiting resin curing, making it difficult to form a pattern. However, when forming a resist pattern on a target substrate, even if the resist pattern contains a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator, it is possible to form a resist pattern on the target substrate. Therefore, by providing the coordinate measurement step and inspection step described above, it is possible to evaluate the resist pattern formed on the target substrate.

[0020]

[10] In the pattern inspection method according to any one of [1] to [9], the pattern may be a resist pattern, a resin film may be provided on the resist pattern, and the coordinate measurement step may measure the coordinates of the contour of the pattern through the resin film. In this pattern inspection method, a resin film may be provided on the resist pattern, which is not provided on the resist pattern formed on the substrate of the semiconductor element, and the coordinates of the contour of the pattern may be measured through this resin film. Therefore, compared to inspecting a resist pattern formed on the substrate of the semiconductor element, there are problems and difficulties involved in inspecting the resist pattern through the resin film. However, by providing the above-described coordinate measurement step and inspection step, it is possible to evaluate the resist pattern formed on the target substrate.

[0021]

[11] In the pattern inspection method according to any one of [1] to

[10] , the pattern may be a resist pattern, and the thickness of the resist pattern may be 3 μm or more and 200 μm or less. In this pattern inspection method, the resist pattern formed on the target substrate has a different thickness from the resist pattern formed on the semiconductor element substrate. This presents problems and difficulties, such as the detection contrast between the resist pattern and the substrate being likely to be lower than when inspecting a resist pattern formed on a semiconductor element substrate. However, by including the coordinate measurement step and inspection step described above, it is possible to evaluate the resist pattern formed on the target substrate.

[0022]

[12] In the pattern inspection method according to any one of [1] to

[11] , the coordinate measuring step may measure coordinates of the pattern contour based on light reflected from the target substrate. In a semiconductor device, the substrate is made of silicon, and a resist pattern is formed on an oxide film or nitride film of this silicon. Therefore, even if light reflected from the substrate of the semiconductor device is detected, it is not possible to obtain a contrast between the substrate (silicon oxide film or nitride film) and the resist pattern that is sufficient to identify the boundary between the substrate and the resist pattern from this reflected light. In contrast, in the target substrate, the resist pattern is formed on a conductor layer such as copper. Therefore, when light reflected from the target substrate is detected, it is possible to obtain a contrast between the substrate (conductor layer) and the resist pattern that is sufficient to identify the boundary between the substrate and the resist pattern from this reflected light. Therefore, in this pattern inspection method, the coordinates of the pattern contour are measured based on light reflected from the target substrate. This allows the coordinates of the pattern contour to be measured appropriately with high accuracy.

[0023]

[13] In the pattern inspection method according to any one of [1] to

[11] , the coordinate measuring step may measure coordinates of the pattern contour based on fluorescence from the target substrate. In a semiconductor device, the substrate is formed of silicon, and a resist pattern is formed on an oxide film or nitride film of this silicon. Therefore, even if fluorescence from the substrate of the semiconductor device is detected, it is not possible to obtain a contrast between the substrate (silicon oxide film or nitride film) and the resist pattern that is sufficient to identify the boundary between the substrate and the resist pattern from this fluorescence. In contrast, in the target substrate, the resist pattern is formed on a conductor layer such as copper. Therefore, when fluorescence from the target substrate is detected, it is possible to obtain a contrast between the substrate (conductor layer) and the resist pattern that is sufficient to identify the boundary between the substrate and the resist pattern from this fluorescence. Therefore, in this pattern inspection method, the coordinates of the pattern contour are measured based on fluorescence from the target substrate. This allows the coordinates of the pattern contour to be measured appropriately with high accuracy.

[0024]

[14] In the pattern inspection method according to any one of [1] to

[11] , the coordinate measuring step may measure coordinates of the contour of the pattern based on an electron beam from the target substrate. In this pattern inspection method, the coordinates of the contour of the pattern are measured based on the electron beam from the target substrate. This makes it possible to appropriately measure the coordinates of the contour of the pattern with high accuracy.

[0025]

[15] The method for manufacturing a resist pattern disclosed herein includes a resist pattern formation process for forming a resist pattern on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, and a coordinate measurement process for measuring the coordinates of the contour of the resist pattern after the resist pattern formation process, and an inspection process for inspecting the resist pattern based on the coordinates.

[0026] In this resist pattern manufacturing method, after forming a resist pattern on a target substrate, the coordinates of the outline of the resist pattern formed on the target substrate are measured, and the resist pattern is inspected based on these measured coordinates. This makes it possible to evaluate the resist pattern even if the resist pattern formed on the target substrate is miniaturized. As a result, it is possible to manufacture a resist pattern with a small degree of roughness.

[0027]

[16] In the resist pattern manufacturing method according to

[15] , the coordinate measuring step may measure the coordinates of the contour of the resist pattern based on light reflected from the target substrate, fluorescence from the target substrate, or an electron beam from the target substrate. In this resist pattern manufacturing method, the coordinates of the contour of the resist pattern are measured based on light reflected from the target substrate, fluorescence from the target substrate, or an electron beam from the target substrate. This allows the coordinates of the contour of the pattern to be measured appropriately with high accuracy.

[0028]

[17] The presently disclosed method for selecting target substrates is a method for selecting target substrates that are either semiconductor package substrates for mounting semiconductor elements or printed wiring boards. This method for selecting target substrates includes a coordinate measurement step for measuring the coordinates of the outline of a pattern formed on the target substrate, an inspection step for inspecting the pattern based on the measured coordinates, and an evaluation step for evaluating the pattern based on the inspection results of the inspection step.

[0029] In this method for selecting target substrates, the coordinates of the contours of either a resist pattern or a conductor pattern formed on the target substrate are measured, the pattern is inspected based on the measured coordinates, and the pattern is evaluated based on the inspection results, which allows for more accurate pattern evaluation than visual inspection.

[0030]

[18] In the method for selecting target substrates according to

[17] , the inspection step may include calculating the roughness of the pattern based on the measured coordinates as the pattern inspection, and the evaluation step may include evaluating the pattern based on the roughness of the pattern. In this method for selecting target substrates, the pattern is evaluated based on the roughness calculated based on the coordinates of the measured contour, so that the pattern formation state can be appropriately evaluated.

[0031]

[19] In the method for selecting target substrates according to

[17] or

[18] , the inspection step may include calculating a variation in contour based on the measured coordinates as a pattern inspection, and the evaluation step may include evaluating the pattern based on the variation in contour. In this method for selecting target substrates, the pattern is evaluated based on the variation in contour calculated based on the coordinates of the measured contour, so that the pattern formation state can be appropriately evaluated.

[0032]

[20] In the method for selecting target substrates according to any one of

[17] to

[19] , the inspection step may include calculating the line width and the line width variation of the pattern based on the measured coordinates as the pattern inspection, and the evaluation step may include evaluating the pattern based on the line width variation. In this method for selecting target substrates, the pattern is evaluated based on the line width variation calculated based on the coordinates of the measured contour, so that the pattern formation state can be appropriately evaluated.

[0033]

[21] In the method for selecting target substrates according to any one of

[17] to

[20] , the inspection step may include comparing measured coordinates with pattern data for forming the pattern as a pattern inspection, and the evaluation step may include evaluating the pattern based on the comparison result between the measured coordinates and the pattern data. In this method for selecting target substrates, the pattern is evaluated based on the comparison result between the measured coordinates of the outline and the pattern data for forming the pattern, so that the pattern formation state can be appropriately evaluated.

[0034]

[22] In the target substrate sorting method according to any one of

[17] to

[21] , the coordinate measuring step may measure the coordinates of the contour of the pattern based on reflected light from the target substrate, fluorescence from the target substrate, or an electron beam from the target substrate. In this target substrate sorting method, by measuring the coordinates of the contour of the pattern based on reflected light from the target substrate, fluorescence from the target substrate, or an electron beam from the target substrate, it is possible to appropriately measure the coordinates of the contour of the pattern with high accuracy.

[0035]

[23] The manufacturing method of the target substrate of the present disclosure includes a conductor pattern forming step of etching or plating a target substrate on which a resist pattern has been formed, the resist pattern of which satisfies the criteria in the method for selecting a target substrate described in any one of

[17] to

[22] , to form a conductor pattern.

[0036] In this method of manufacturing a target substrate, among target substrates on which a resist pattern has been formed, those whose resist pattern evaluation in the above-mentioned method of selecting target substrates meets the criteria are etched or plated to form a conductor pattern, thereby preventing defects such as poor formation of the conductor pattern and deterioration of the electrical properties of the manufactured semiconductor package. [Effects of the Invention]

[0037] According to the present disclosure, even if a pattern, which is either a resist pattern or a conductor pattern formed on a target substrate, which is either a semiconductor package substrate or a printed wiring board, is miniaturized, the pattern can be evaluated. [Brief explanation of the drawings]

[0038] [Figure 1] FIG. 1(a) is a schematic perspective view for explaining the photosensitive layer forming step in the resist pattern forming step, FIG. 1(b) is a schematic perspective view for explaining the exposure step in the resist pattern forming step, and FIG. 1(c) is a schematic perspective view for explaining the development step in the resist pattern forming step. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an example of a target substrate. [Figure 3] FIG. 3 is a schematic cross-sectional view showing another example of the target substrate. [Figure 4] FIG. 4 is a schematic cross-sectional view showing another example of the target substrate. [Figure 5] FIG. 5 is a schematic cross-sectional view showing another example of the target substrate. [Figure 6] FIG. 6 is a schematic perspective view for explaining the coordinate measuring step. [Figure 7] FIG. 7 is a schematic plan view showing an enlarged portion of a pattern formed on a target substrate. [Figure 8] 8(a), 8(b), and 8(c) are schematic perspective views for explaining the formation of the conductor patterns. [Figure 9] FIG. 9 is a photograph of Example 1. [Figure 10] FIG. 10 is a plot diagram of the coordinates of the contour of the resist pattern of Example 1. [Figure 11] FIG. 11 is a diagram in which the plot diagram of FIG. 10 is superimposed on the photograph of FIG. 9 with a shift. [Figure 12] 1 is a table showing the evaluation of Examples 1 and 2. DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, with reference to the drawings, embodiments of the pattern inspection method, resist pattern manufacturing method, target substrate selection method, and target substrate manufacturing method of the present disclosure will be described. Note that the same or corresponding parts throughout the drawings will be designated by the same reference numerals. Furthermore, "A or B" may include either A or B, or may include both. Furthermore, either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board is referred to as the target substrate, and either a resist pattern or a conductor pattern is referred to as the pattern.

[0040] [Pattern inspection method] The pattern inspection method according to the embodiment is an inspection method for inspecting a pattern that is either a resist pattern or a conductor pattern formed on a target substrate that is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board. The pattern inspection method includes a resist pattern inspection method for inspecting a resist pattern and a conductor pattern inspection method for inspecting a conductor pattern.

[0041] [Resist pattern inspection method] The resist pattern inspection method includes a coordinate measurement step of measuring the coordinates of the contour of a resist pattern formed on a target substrate, and an inspection step of inspecting the resist pattern based on the coordinates measured in the coordinate measurement step. The resist pattern inspection method may include a resist pattern formation step of forming a resist pattern on the target substrate before the coordinate measurement step. The resist pattern inspection method may also include other steps. In this specification, the term "step" includes not only an independent step, but also a step that cannot be clearly distinguished from other steps, as long as the intended effect of the step is achieved. The resist pattern may also be referred to as a photocured product pattern of a photosensitive resin composition, or a relief pattern.

[0042] <Resist pattern formation process> 1, the resist pattern forming process includes a photosensitive layer forming process (see FIG. 1(a)) of laminating a photosensitive layer 2 on a target substrate 1, an exposure process (see FIG. 1(b)) of irradiating predetermined portions of the photosensitive layer 2 with active light rays to form photocured portions, and a development process (see FIG. 1(c)) of removing regions of the photosensitive layer 2 other than the predetermined portions from the target substrate 1. The resist pattern forming process may include other processes as necessary.

[0043] The target substrate 1 has, for example, an inorganic component including at least one of silica filler and glass cloth, and an organic component including at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin.

[0044] The thickness of the target substrate 1 may be, for example, 50 μm or more, 100 μm or more, 300 μm or more, or 1000 μm or more. The thickness of the target substrate 1 may also be, for example, 3000 μm or less, 2000 μm or less, or 1500 μm or less. These minimum and maximum thickness values ​​of the target substrate 1 can be appropriately combined. For example, the thickness of the target substrate 1 may be 50 μm or more and 3000 μm or less, 100 μm or more and 2000 μm or less, 300 μm or more and 1500 μm or less, or 1000 μm or more and 3000 μm or less. The thickness of the target substrate 1 is the dimension of the target substrate 1 in a direction perpendicular to the main surface of the target substrate 1. The thickness of the substrate of the semiconductor element mounted on the semiconductor package substrate is, for example, 25 μm or more and 200 μm or less.

[0045] (Photosensitive layer formation process) As shown in FIG. 1(a), in the photosensitive layer forming step, a photosensitive layer 2 and a support 3 are formed on a target substrate 1. Note that the support 3 does not necessarily have to be formed on the target substrate 1. Furthermore, if the support 3 is formed on the target substrate 1, the support 3 may be peeled off from the target substrate 1 at any time. The target substrate 1 includes, for example, an insulating layer 1a and a conductor layer 1b formed on the insulating layer 1a. The insulating layer 1a is, for example, a core material, a build-up material, or polyethylene terephthalate (PET).

[0046] For example, as shown in Fig. 2, the insulating layer 1a may be composed of a core layer 11 and a pair of buildup layers 12 formed on both sides of the core layer 11. Alternatively, for example, as shown in Fig. 3, the insulating layer 1a may be composed of a core layer 11 and a buildup layer 12 formed on one side of the core layer 11. Alternatively, for example, as shown in Fig. 4, the insulating layer 1a may be composed only of the core layer 11 without any buildup layer. Alternatively, for example, as shown in Fig. 5, the insulating layer 1a may be composed only of the buildup layer 12 without any core layer.

[0047] The core layer 11 is a layer that becomes the core of the target substrate 1. In some cases, the core layer 11 has through holes 11a or the like formed therein.

[0048] The buildup layer 12 is a layer built up on the target substrate 1. The buildup layer 12 may be composed of one layer or multiple layers. In the example shown in FIG. 2, three buildup layers 12 are formed on each side of the core layer 11. In the example shown in FIG. 3, three buildup layers 12 are formed on one side of the core layer 11. In the example shown in FIG. 5, three buildup layers 12 are formed. The buildup layer 12 includes, for example, copper wiring 12a, vias 12b, pads 12c, etc.

[0049] The conductor layer 1b is, for example, copper formed on the insulating layer 1a by electroless plating or sputtering.

[0050] The photosensitive layer 2 is formed on the conductor layer 1b of the target substrate 1. In the substrate of the semiconductor element mounted on the semiconductor package substrate, the photosensitive layer is formed not on the conductor layer but on an insulating layer, which is a silicon oxide film or a silicon nitride film.

[0051] The photosensitive layer 2 is a layer formed using a negative-type photosensitive resin composition that hardens (photocures) when irradiated with light. A positive-type photosensitive resin composition is used for the substrate of the semiconductor element mounted on the semiconductor package substrate. The photosensitive resin composition forming the photosensitive layer 2 contains, for example, a binder polymer such as a binder polymer having a carboxyl group, a photopolymerizable compound such as a radically polymerizable compound having an ethylenically unsaturated bond, and a photopolymerization initiator such as a photoradical polymerization initiator. The photosensitive resin composition forming the photosensitive layer 2 may contain a photosensitizer, a polymerization inhibitor, or other components as needed. The photosensitive resin composition that forms the photosensitive layer 2 may contain additives such as dyes such as malachite green, Victoria Pure Blue, brilliant green, and methyl violet, photocoloring agents such as tribromophenyl sulfone, leuco crystal violet, diphenylamine, benzylamine, triphenylamine, diethylaniline, and o-chloroaniline, thermal color-developing inhibitors, plasticizers such as p-toluenesulfonamide, pigments, fillers, antifoaming agents, flame retardants, adhesion promoters, leveling agents, release promoters, antioxidants, fragrances, imaging agents, and thermal crosslinking agents.

[0052] The support 3 may be made of a resin film (support film). The resin film constituting the support 3 may be a polymer film having heat resistance and solvent resistance, such as polyesters such as polyethylene terephthalate (PET), or polyolefins such as polypropylene and polyethylene. The resin film constituting the support 3 may also be a film having gas barrier properties, such as polyvinyl alcohol (PVA). The resin film constituting the support 3 may also be a polymer film having heat resistance and solvent resistance, such as an acrylic resin or a styrene resin. However, the substrate of the semiconductor element mounted on the semiconductor package substrate does not have such a support (resin film).

[0053] One method for forming the photosensitive layer 2 and support 3 on the target substrate 1 is to use, for example, a film-like photosensitive element (not shown). The film-like photosensitive element includes, for example, a support, a photosensitive layer, and a protective layer, in this order. After removing the protective layer, the photosensitive layer of the photosensitive element is heated and pressed onto the target substrate 1, thereby forming the photosensitive layer 2 and support 3 on the target substrate 1. This results in a laminate 4 including, in this order, the target substrate 1, the photosensitive layer 2, the support 3, and a support film (not shown). Note that an intermediate layer or the like may be disposed between the support 3 and the photosensitive layer 2. Note that for substrates of semiconductor elements to be mounted on semiconductor package substrates, a liquid resist is used without using a film-like photosensitive element. Therefore, without such a support and protective layer, the photosensitive layer is formed on the substrate by spin coating and post-baking.

[0054] (Exposure process) As shown in FIG. 1(b), in the exposure step, the photosensitive layer 2 is exposed to actinic rays through a support 3. This photocures the exposed areas, forming photocured areas 2a (latent images). Known exposure methods can be used, including a mask exposure method (imagewise exposure of actinic rays through a photomask 5 called artwork), an LDI (Laser Direct Imaging) exposure method, and a projection exposure method (imagewise exposure of actinic rays projected from a photomask through a lens). Note that the substrate of a semiconductor device mounted on a semiconductor package substrate does not have such a support, and therefore the photosensitive layer is exposed without a support. Furthermore, the projection exposure method is the mainstream method for exposing the photosensitive layer of a semiconductor device mounted on a semiconductor package substrate, and the LDI exposure method is not used.

[0055] (Development process) As shown in Figure 1(c), in the development step, uncured portions 2b of the photosensitive layer 2 are removed from the target substrate 1. Through the development step, a resist pattern 6 consisting of photocured portions 2a formed by photocuring the photosensitive layer 2 is formed on the target substrate 1. Note that, since a positive photosensitive resin composition is used as the photosensitive layer in the substrate of the semiconductor element mounted on the semiconductor package substrate, the unexposed portions become the resist pattern.

[0056] The thickness of the resist pattern 6 formed on the target substrate 1 may be, for example, 3 μm or more, 5 μm or more, or 10 μm or more. The thickness of the resist pattern 6 formed on the target substrate 1 may be, for example, 200 μm or less, 100 μm or less, or 60 μm or less. These minimum and maximum thickness values ​​of the resist pattern 6 can be appropriately combined. For example, the thickness of the resist pattern 6 formed on the target substrate 1 may be 3 μm or more and 200 μm or less, 5 μm or more and 100 μm or less, or 10 μm or more and 60 μm or less. The thickness of the resist pattern 6 is the height relative to the target substrate 1 in a direction perpendicular to the main surface of the target substrate 1.

[0057] <Coordinate measurement process> In the coordinate measurement process, the coordinates of the contour of the resist pattern formed on the target substrate are measured, for example, based on reflected light from the target substrate, fluorescence from the target substrate, or an electron beam from the target substrate.

[0058] In a semiconductor device mounted on a semiconductor package substrate, the substrate is made of silicon, and a resist pattern is formed on the silicon oxide or nitride film. Therefore, even if reflected light or fluorescence from the semiconductor device substrate is detected, the reflected light or fluorescence does not provide sufficient contrast between the substrate (silicon oxide or nitride film) and the resist pattern to identify the boundary between the substrate and the resist pattern. Therefore, it is extremely difficult and impractical to detect the coordinates of the contour of the resist pattern formed on the semiconductor device substrate based on the reflected light or fluorescence from the semiconductor device substrate. In contrast, in the target substrate 1, a resist pattern 6 is formed on a conductor layer 1b, such as copper. Therefore, when reflected light or fluorescence from the target substrate 1 is detected, the reflected light or fluorescence provides sufficient contrast between the substrate (conductor layer 1b) and the resist pattern 6 to identify the boundary between the substrate and the resist pattern 6. Therefore, it is possible to detect the coordinates of the resist pattern 6 formed on the target substrate 1 based on the reflected light or fluorescence from the target substrate 1.

[0059] FIG. 6 shows an example of the coordinate measurement process in which the coordinates of the contour 61 (see FIG. 7) of the resist pattern 6 are measured based on the light reflected from the target substrate 1. As shown in FIG. 6, when measuring the coordinates of the contour 61 of the resist pattern 6 based on the light reflected from the target substrate 1, first, inspection light is emitted to the target substrate 1 on which the resist pattern 6 is formed, and the reflected light from the target substrate 1 is received. The wavelength of the inspection light may be, for example, 380 nm or more, 430 nm or more, or 600 nm or more. The wavelength of the inspection light may also be, for example, 830 nm or less, 780 nm or less, or 700 nm or less. The minimum and maximum values ​​of these wavelengths can be appropriately combined. For example, the wavelength of the inspection light may be 380 nm or more and 830 nm or less, 430 nm or more and 780 nm or less, or 600 nm or more and 700 nm or less. The inspection light may be white light using a laser excitation light source or the like. The light receiving area of ​​the target substrate 1 that receives the reflected light in the coordinate measurement process may be, for example, 100 μm 2 More than 2500cm 2 Below, 500μm2 More than 1200cm 2 Below, 1000μm 2 More than 600cm 2 The light receiving area is also the area where the inspection light is irradiated onto the target substrate 1 in one measurement. The method of irradiating the inspection light may be, for example, either specular reflected light or diffuse reflected light, or a combination of specular reflected light and diffuse reflected light.

[0060] Next, the contour 61 of the resist pattern 6 is identified based on the contrast between the light reflected from the resist pattern 6 and the light reflected from an area other than the resist pattern 6. For example, a boundary where the contrast of brightness, chromaticity, or the like increases in the received image of the reflected light is detected. Then, this detected boundary is identified as the contour 61 of the resist pattern 6, and the coordinates of this identified contour 61 are measured. The coordinates of the measured contour 61 are coordinates in an XY coordinate system (two-axis coordinate system) on the main surface of the target substrate 1. Then, in measuring the coordinates of the contour 61, coordinates at multiple measurement points on the contour 61 are measured. To identify the contour 61 of the resist pattern 6 based on the light reflected from the target substrate 1 and measure the coordinates of the contour 61, for example, a Computer Numerical Control image measurement system such as NEXIV VMZ-R4540 (manufactured by Nikon Corporation, product name) or OPTELICS HYBRID+ (manufactured by Lasertec Corporation, product name) can be used.

[0061] When measuring the coordinates of the contour 61 of the resist pattern 6 based on the fluorescence from the target substrate 1, for example, similar to when measuring the coordinates of the contour 61 of the resist pattern 6 based on reflected light from the target substrate 1, the contour 61 of the resist pattern 6 is identified based on the contrast between the fluorescence from the resist pattern 6 and the fluorescence from an area other than the resist pattern 6. Then, the coordinates of this identified contour 61 are measured. To measure the coordinates of the contour 61 of the resist pattern 6 based on the fluorescence from the target substrate 1, for example, a fluorescence microscope such as ECLIPS L300N (trade name, manufactured by Nikon Corporation) can be used.

[0062] When measuring the coordinates of the contour 61 of the resist pattern 6 based on the electron beam from the target substrate 1, for example, similarly to when measuring the coordinates of the contour 61 of the resist pattern 6 based on light reflected from the target substrate 1, the contour 61 of the resist pattern 6 is identified based on the contrast between the electron beam from the resist pattern 6 and the electron beam from an area other than the resist pattern 6. Then, the coordinates of this identified contour 61 are measured. To measure the coordinates of the contour 61 of the resist pattern 6 based on the electron beam from the target substrate 1, for example, a CD-SEM (Critical Dimension Scanning Electron Microscope) such as CS4800 (trade name, manufactured by Hitachi High-Technologies Corporation) can be used.

[0063] The number and spacing of measurement points of the contour 61 whose coordinates are to be measured are not particularly limited. However, from the viewpoint of enabling highly accurate evaluation of the resist pattern 6, the more measurement points of the contour 61 whose coordinates are to be measured, the better, and the narrower the spacing between the measurement points of the contour 61 whose coordinates are to be measured, the better. From this viewpoint, for example, the spacing between the measurement points of the contour 61 whose coordinates are to be measured may be 0.5 μm or less, 0.3 μm or less, or 0.2 μm or less. On the other hand, if the number of measurement points of the contour 61 whose coordinates are to be measured is too large or the spacing between the measurement points of the contour 61 whose coordinates are to be measured is too narrow, measuring the coordinates of the contour 61 will take too much time. From this viewpoint, for example, the spacing between the measurement points of the contour 61 whose coordinates are to be measured may be 0.001 μm or more, 0.005 μm or more, or 0.01 μm or more. These minimum and maximum spacings of the measurement points can be combined as appropriate. For example, the interval between measurement points on the contour 61 whose coordinates are measured may be 0.001 μm or more and 0.5 μm or less, 0.005 μm or more and 0.3 μm or less, or 0.01 μm or more and 0.2 μm or less.

[0064] <Inspection process> In the inspection step, the resist pattern is inspected based on the coordinates measured in the coordinate measurement step.

[0065] Here, the resist pattern formed on the target substrate will be described in detail. As shown in FIG. 7, the resist pattern 6 formed on the target substrate 1 has a certain degree of roughness. That is, the contour 61a on one side of the resist pattern 6 and the contour 61b on the other side of the resist pattern 6 do not extend in a completely straight or curved shape in the extending direction of the resist pattern 6, but often extend in the extending direction of the resist pattern 6 while fluctuating (having projections and depressions) in the width direction of the resist pattern 6. As a result, the contour 61 (the contour 61a on one side or the contour 61b on the other side) of the resist pattern 6 becomes rough, or the line width W of the resist pattern 6 varies. Therefore, in the inspection process, the roughness of the resist pattern 6 is inspected based on the coordinates measured in the coordinate measurement process.

[0066] The inspection of the resist pattern 6 involves, for example, calculating the variation in the contour 61 of the resist pattern 6, calculating the line width W of the resist pattern 6 and the variation in the line width W, and comparing the results with the pattern data for forming the resist pattern 6.

[0067] In calculating the variation of the contour 61 of the resist pattern 6, the variation of the contour 61 of the resist pattern 6 in the width direction of the resist pattern 6 is calculated from the coordinates of multiple measurement points of the contour 61 measured in the coordinate measurement process. As the variation of the contour 61 of the resist pattern 6, for example, 3σ of the contour 61 of the resist pattern 6 is calculated based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process. In other words, 3σ of the contour 61 of the resist pattern 6 is calculated from the coordinates of multiple measurement points of the contour 61 measured in the coordinate measurement process. σ is the standard deviation, and 3σ is also called the detection limit value. 3σ of the contour 61 of the resist pattern 6 is also called LER (Line Edge Roughness).

[0068] In calculating the line width W of the resist pattern 6 and the variation in the line width W, the line width W at multiple positions on the resist pattern 6 is calculated from the coordinates of multiple measurement points on the contour 61 measured in the coordinate measurement process. Then, the variation in the line width W of the resist pattern 6 in the width direction of the resist pattern 6 is calculated from these calculated multiple line widths W. As the variation in the line width W of the resist pattern 6, for example, 3σ of the line width W of the resist pattern 6 is calculated based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process. In other words, the line width W at multiple positions on the resist pattern 6 is calculated from the coordinates of multiple measurement points on the contour 61 measured in the coordinate measurement process. Then, the 3σ of the line width W of the resist pattern 6 is calculated from these calculated multiple line widths W. The 3σ of the line width W of the resist pattern 6 is also called LWR (Line Width Roughness). The resist pattern 6 and the space (the gap between adjacent resist patterns 6) can be distinguished, for example, by comparing with the pattern data for forming the resist pattern 6, or by the difference in brightness of the reflected light from the target substrate 1, etc.

[0069] In the comparison with the pattern data for forming the resist pattern 6, for example, the coordinates of the multiple measurement points on the contour 61 of the resist pattern 6 measured in the coordinate measurement process are used to plot the multiple measurement points on the contour 61 of the resist pattern 6 measured in the coordinate measurement process. Then, the line formed by this plot is compared with the pattern data for forming the resist pattern 6, and from the comparison results, defects in the resist pattern 6 are detected and the number of detected defects is calculated.

[0070] [Conductor pattern inspection method] The conductor pattern inspection method includes a coordinate measurement step of measuring the coordinates of the outline of a conductor pattern formed on a target substrate, and an inspection step of inspecting the conductor pattern based on the coordinates measured in the coordinate measurement step. The conductor pattern inspection method may include a conductor pattern formation step of etching or plating the target substrate on which a resist pattern has been formed, to form a conductor pattern on the target substrate, before the coordinate measurement step. The conductor pattern inspection method may also include other steps.

[0071] <Coordinate measurement process> In the coordinate measurement step, coordinates of the contour of the conductor pattern formed on the target substrate are measured. The coordinate measurement step of the conductor pattern inspection method can be performed in the same manner as the coordinate measurement step of the resist pattern inspection method, for example. That is, in the coordinate measurement step of the resist pattern inspection method, the resist pattern (resist pattern 6) and contour (contour 61) are replaced with the conductor pattern (conductor pattern 7) and contour (contour 71), thereby enabling the coordinate measurement step of the conductor pattern inspection method to be performed.

[0072] Note that etching the target substrate reduces the line width of the conductor pattern. Therefore, when inspecting the conductor pattern by comparing it with the pattern data for forming the conductor pattern 7 after etching the target substrate, the conductor pattern may be inspected by comparing it with the pattern data for forming the conductor pattern, taking into account that the line width of the conductor pattern is reduced by the etching process.

[0073] <Inspection process> In the inspection step, the conductor pattern is inspected based on the coordinates measured in the coordinate measurement step. The inspection step of the conductor pattern inspection method can be performed in the same manner as the inspection step of the resist pattern inspection method, for example. That is, in the inspection step of the resist pattern inspection method, the resist pattern (resist pattern 6) and contour (contour 61) are replaced with the conductor pattern (conductor pattern 7) and contour (contour 71), thereby enabling the inspection step of the conductor pattern inspection method to be performed.

[0074] [Method of manufacturing resist pattern] A resist pattern manufacturing method according to an embodiment includes a resist pattern forming step of forming a resist pattern on a target substrate, a coordinate measurement step of measuring the coordinates of the contour of the resist pattern on the target substrate after the resist pattern forming step, and an inspection step of inspecting the resist pattern based on the coordinates measured in the coordinate measurement step. The resist pattern forming step of the resist pattern manufacturing method may be, for example, the same as the resist pattern forming step of the resist pattern inspection method described above. Furthermore, the coordinate measurement step of the resist pattern manufacturing method may be, for example, the same as the coordinate measurement step of the resist pattern inspection method described above. Therefore, the coordinate measurement step of the resist pattern manufacturing method measures the coordinates of the contour of the pattern based on reflected light from the target substrate, fluorescence from the target substrate, or an electron beam from the target substrate, similar to the coordinate measurement step of the resist pattern inspection method described above. Furthermore, the inspection step of the resist pattern manufacturing method may be, for example, the same as the inspection step of the resist pattern inspection method described above. The resist pattern manufacturing method may include other steps.

[0075] [How to select target boards] The target substrate sorting method according to this embodiment is a method for sorting target substrates on which a pattern is formed. This target substrate sorting method includes a resist pattern-based target substrate sorting method for sorting target substrates on which a resist pattern is formed, and a conductor pattern-based target substrate sorting method for sorting target substrates on which a conductor pattern is formed.

[0076] [Method for selecting target substrates based on resist patterns] The method for selecting target substrates based on resist patterns includes a coordinate measurement step of measuring the coordinates of the contour of a resist pattern formed on the target substrate, an inspection step of inspecting the resist pattern based on the coordinates measured in the coordinate measurement step, and an evaluation step of evaluating the resist pattern based on the inspection result of the inspection step.The coordinate measurement step of the method for selecting target substrates based on resist patterns may be, for example, the same as the coordinate measurement step of the above-mentioned method for inspecting resist patterns.The inspection step of the method for selecting target substrates based on resist patterns may be, for example, the same as the inspection step of the above-mentioned method for inspecting resist patterns.The method for selecting target substrates based on resist patterns may include other steps.

[0077] <Evaluation process> In the evaluation step, the resist pattern is evaluated based on the inspection results of the inspection step.

[0078] As shown in Figure 7, for example, in the inspection process, when the resist pattern 6 is inspected for roughness based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process, the resist pattern 6 is evaluated based on the roughness of the resist pattern 6 in the evaluation process.

[0079] Furthermore, for example, in the inspection process, when the variation of the outline 61 of the resist pattern 6 is calculated based on the coordinates of the outline 61 of the resist pattern 6 measured in the coordinate measurement process, the resist pattern 6 is evaluated in the evaluation process based on the degree of variation of this outline 61. That is, if the degree of variation of the outline 61 is below a standard, the resist pattern 6 is evaluated as good, and if the degree of variation of the outline 61 is above the standard, the resist pattern 6 is evaluated as bad. For example, if the 3σ of the outline 61 of the resist pattern 6 is calculated as the variation of the outline 61 of the resist pattern 6 in the inspection process, the resist pattern 6 is evaluated as good if the 3σ of the outline 61 of the resist pattern 6 is below a predetermined standard value, and if the 3σ of the outline 61 of the resist pattern 6 is above the predetermined standard value, the resist pattern 6 is evaluated as bad.

[0080] Furthermore, for example, in the inspection process, when the variation in the line width W of the resist pattern 6 is calculated based on the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process, the resist pattern 6 is evaluated in the evaluation process based on the degree of variation in this line width W. That is, if the degree of variation in the line width W is below a standard, the resist pattern 6 is evaluated as good, and if the degree of variation in the line width W1 is above the standard, the resist pattern 6 is evaluated as bad. For example, if the 3σ of the line width W of the resist pattern 6 is calculated as the variation in the line width W of the resist pattern 6 in the inspection process, the resist pattern 6 is evaluated as good in the evaluation process if the 3σ of the line width W of the resist pattern 6 is below a predetermined standard value, and if the 3σ of the line width W of the resist pattern 6 is above the predetermined standard value, the resist pattern 6 is evaluated as bad.

[0081] Furthermore, for example, in the inspection process, when the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process are compared with pattern data for forming the resist pattern 6 as an inspection of the resist pattern 6, the evaluation process evaluates the resist pattern 6 based on the comparison results. For example, in the inspection process, when the number of defects in the resist pattern 6 is calculated by comparing the coordinates of the contour 61 of the resist pattern 6 measured in the coordinate measurement process with pattern data for forming the resist pattern 6, the evaluation process evaluates the resist pattern 6 as good if the number of defects in the resist pattern 6 is below a predetermined reference value, and evaluates the resist pattern 6 as bad if the number of defects in the resist pattern 6 is above the predetermined reference value.

[0082] [Method for selecting target boards based on conductor patterns] The method for selecting target substrates based on conductor patterns includes a coordinate measurement step of measuring coordinates of the contours of conductor patterns formed on the target substrates, an inspection step of inspecting the conductor patterns based on the coordinates measured in the coordinate measurement step, and an evaluation step of evaluating the conductor patterns based on the inspection results of the inspection step.The coordinate measurement step of the method for selecting target substrates based on conductor patterns may be, for example, the same as the coordinate measurement step of the above-mentioned method for inspecting conductor patterns.The inspection step of the method for selecting target substrates based on conductor patterns may be, for example, the same as the inspection step of the above-mentioned method for inspecting conductor patterns.The method for selecting target substrates based on conductor patterns may include other steps.

[0083] <Evaluation process> In the evaluation step, the conductor patterns are evaluated based on the inspection results of the inspection step. The evaluation step of the target substrate selection method based on conductor patterns can be performed in the same manner as the evaluation step of the target substrate selection method based on resist patterns, for example. That is, in the evaluation step of the target substrate selection method based on resist patterns, the resist pattern (resist pattern 6) and contour (contour 61) can be replaced with the conductor pattern (conductor pattern 7) and contour (contour 71), thereby enabling the evaluation step of the target substrate selection method based on conductor patterns to be performed.

[0084] [Method of manufacturing target substrate] The target substrate manufacturing method according to this embodiment includes a conductor pattern forming step of etching or plating a target substrate on which a resist pattern has been formed, and which satisfies the criteria for evaluation of the resist pattern in the target substrate selection method described above. In other words, in the conductor pattern forming step, target substrates on which a resist pattern has been formed and for which the evaluation of the resist pattern in the target substrate selection method does not satisfy the criteria are not subjected to etching or plating to form a conductor pattern. An example of a case in which the evaluation of the resist pattern in the target substrate selection method does not satisfy the criteria is when the target substrate is evaluated as defective in the evaluation step. The target substrate manufacturing method according to this embodiment may include other steps, such as a resist pattern removal step, as needed.

[0085] In the etching process, the resist pattern formed on the target substrate having a conductor layer is used as a mask to etch away the conductor layer of the target substrate that is not covered with resist. After the etching process, the resist is removed by removing the resist pattern 6 to form the conductor pattern.

[0086] As shown in Figure 8(a), in the plating process, a resist pattern 6 formed on a target substrate 1 having a conductor layer 1b is used as a mask to plate copper, solder, or the like onto the conductor layer 1b of the target substrate 1 that is not covered by the resist. After the plating process, the resist is removed by removing the resist pattern 6 as shown in Figure 8(b), and the conductor layer 1b that was covered by the resist is etched as shown in Figure 8(c), forming a conductor pattern 7. The plating method may be electrolytic plating or electroless plating, but electrolytic plating is particularly preferred.

[0087] As described above, in the pattern inspection method according to this embodiment, the coordinates of the outline 61 of the resist pattern 6 or the outline 71 of the conductor pattern 7 formed on the target substrate 1 are measured, and the resist pattern 6 or the conductor pattern 7 is inspected based on these measured coordinates. Therefore, even if the resist pattern 6 or the conductor pattern 7 formed on the target substrate 1 is miniaturized, the resist pattern 6 or the conductor pattern 7 can be evaluated. Moreover, the resist pattern 6 or the conductor pattern 7 can be evaluated with higher accuracy than when inspected visually.

[0088] Furthermore, in this pattern inspection method, the roughness of the resist pattern 6 or the conductor pattern 7 is calculated based on the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 in order to inspect the resist pattern 6 or the conductor pattern 7. Therefore, the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0089] Furthermore, in this pattern inspection method, the resist pattern 6 or the conductor pattern 7 is inspected by calculating the variation in the contour 61 of the resist pattern 6 or the contour 61 of the conductor pattern 7 based on the coordinates of the measured contour 61 or contour 71. Therefore, the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0090] Furthermore, in this pattern inspection method, the resist pattern 6 or the conductor pattern 7 is inspected by calculating the line width W and the variation in line width W of the resist pattern 6 or the conductor pattern 7 based on the coordinates of the measured contour 61 or contour 71. Therefore, the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0091] Furthermore, in this pattern inspection method, the coordinates of the measured contour 61 or contour 71 are compared with the pattern data for forming the resist pattern 6 or the conductive pattern 7 to inspect the resist pattern 6 or the conductive pattern 7. Therefore, the formation state of the resist pattern 6 or the conductive pattern 7 can be evaluated with high accuracy.

[0092] Furthermore, in this pattern inspection method, the target substrate 1 contains an inorganic component containing at least one of silica filler and glass cloth, which are not used in semiconductor device substrates, and an organic component containing at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin. Therefore, compared to inspecting patterns formed on semiconductor device substrates, there are problems and difficulties such as distortion and warping of the inspection target. However, by including the above-mentioned coordinate measurement process and inspection process, it is possible to evaluate the resist pattern 6 or conductor pattern 7 formed on the target substrate 1.

[0093] Furthermore, in this pattern inspection method, the target substrate 1 has at least one of a core layer 11 and a build-up layer 12, which are different in structure from the substrate of a semiconductor element. Therefore, compared to inspecting a pattern formed on a substrate of a semiconductor element, there are problems and difficulties such as distortion and warpage of the inspection target. However, by including the coordinate measurement process and inspection process described above, it is possible to evaluate the pattern formed on the target substrate 1.

[0094] Furthermore, in this pattern inspection method, the thickness of the target substrate 1 is 50 μm or more and 3000 μm or less, which is different from the thickness of the substrate of the semiconductor element. Therefore, compared to inspecting a pattern formed on the substrate of a semiconductor element, there are problems and difficulties such as the focal position of the inspection target changing significantly depending on the observation point due to distortion and warpage of the inspection target and variations in the thickness of the inspection target, making it difficult to focus on the resist pattern and conductors. However, by including the above-mentioned coordinate measurement process and inspection process, it is possible to evaluate the pattern formed on the target substrate 1.

[0095] Furthermore, in this pattern inspection method, the resist pattern 6 formed on the target substrate 1 contains a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator, which are different from the resist pattern formed on the semiconductor element substrate. Because the semiconductor element substrate has no support and is thin, using a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator in the manufacture of the semiconductor element substrate presents problems and difficulties, such as the influence of oxygen in the exposure atmosphere inhibiting resin curing and making it difficult to form a pattern. However, when forming the resist pattern 6 on the target substrate 1, even if the resist pattern 6 contains a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator, it can still be formed on the target substrate 1. Therefore, by including the above-mentioned coordinate measurement process and inspection process, the resist pattern 6 formed on the target substrate 1 can be evaluated.

[0096] Furthermore, in this pattern inspection method, a support 3 made of a resin film is provided on the resist pattern 6, which is not provided on the resist pattern formed on the substrate of the semiconductor element, and the coordinates of the pattern contour are measured through this resin film. Therefore, compared to inspecting a resist pattern formed on the substrate of the semiconductor element, there are problems and difficulties involved in inspecting the resist pattern 6 through the resin film. However, by providing the coordinate measurement process and inspection process described above, it is possible to evaluate the resist pattern 6 formed on the target substrate 1.

[0097] Furthermore, in this pattern inspection method, the resist pattern 6 formed on the target substrate 1 is a pattern with a thickness of 3 μm or more and 200 μm or less, which is different from the resist pattern formed on the substrate of the semiconductor element. Therefore, there are problems and difficulties such as the detection contrast between the resist pattern and the substrate being likely to be lower compared to when inspecting a resist pattern formed on the substrate of the semiconductor element. However, by including the coordinate measurement process and inspection process described above, it is possible to evaluate the resist pattern formed on the target substrate 1.

[0098] Furthermore, in this pattern inspection method, the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 are measured based on the light reflected from the target substrate 1. This makes it possible to appropriately measure the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 with high accuracy.

[0099] Furthermore, in this pattern inspection method, the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 are measured based on the fluorescence from the target substrate 1. This makes it possible to appropriately measure the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 with high accuracy.

[0100] Furthermore, in this pattern inspection method, the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 are measured based on the electron beam from the target substrate 1. This makes it possible to appropriately measure the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 with high accuracy.

[0101] In the method for manufacturing a resist pattern according to this embodiment, after forming a resist pattern 6 on a target substrate 1, the coordinates of the contour 61 of the resist pattern 6 are measured, and the resist pattern 6 is inspected based on these measured coordinates. This makes it possible to evaluate the resist pattern 6 even if the resist pattern 6 formed on the target substrate 1 is miniaturized. This makes it possible to manufacture a resist pattern 6 with a small degree of roughness.

[0102] Furthermore, in this resist pattern manufacturing method, the coordinates of the contour 61 of the resist pattern 6 are measured based on the reflected light from the target substrate 1, the fluorescence from the target substrate 1, or the electron beam from the target substrate 1. This makes it possible to appropriately measure the coordinates of the contour 61 of the resist pattern 6 with high accuracy.

[0103] In the method for selecting target substrates according to this embodiment, the coordinates of the outline 61 of the resist pattern 6 or the outline 71 of the conductor pattern 7 formed on the target substrate 1 are measured, the resist pattern 6 or the conductor pattern 7 is inspected based on the measured coordinates, and the resist pattern 6 or the conductor pattern 7 is evaluated based on the inspection results. Therefore, the resist pattern 6 or the conductor pattern 7 can be evaluated with higher accuracy than when inspected visually.

[0104] Furthermore, in this method for selecting target substrates, the resist pattern 6 or the conductor pattern 7 is evaluated based on the roughness of the resist pattern 6 or the conductor pattern 7, which is calculated based on the coordinates of the measured contour 61 or contour 71, so that the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0105] Furthermore, in this method for selecting target substrates, the resist pattern 6 or the conductor pattern 7 is evaluated based on the variation in the contour 61 or the contour 71 calculated based on the coordinates of the measured contour 61 or the contour 71, so that the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0106] Furthermore, in this method for selecting target substrates, the resist pattern 6 or the conductor pattern 7 is evaluated based on the line width W and the variation in line width W calculated based on the coordinates of the measured contour 61 or contour 71, so that the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0107] Furthermore, in this method for selecting target substrates, the resist pattern 6 or the conductor pattern 7 is evaluated based on the comparison results between the coordinates of the measured contour 61 or contour 71 and the pattern data for forming the resist pattern 6 or the conductor pattern 7, so that the formation state of the resist pattern 6 or the conductor pattern 7 can be appropriately evaluated.

[0108] Furthermore, in this method for selecting target substrates, the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 are measured based on reflected light from the target substrate 1, fluorescence from the target substrate 1, or an electron beam from the target substrate 1, thereby enabling the coordinates of the contour 61 of the resist pattern 6 or the contour 71 of the conductor pattern 7 to be appropriately measured with high accuracy.

[0109] In the target substrate manufacturing method of this embodiment, among the target substrates 1 on which a resist pattern 6 has been formed, target substrates 1 whose evaluation of the resist pattern 6 in the above-mentioned target substrate selection method meets the criteria are etched or plated to form a conductor pattern 7, thereby preventing defects such as poor formation of the conductor pattern 7 and deterioration of the electrical properties of the manufactured semiconductor package.

[0110] The present disclosure is not limited to the above-described embodiments, and modifications can be made as appropriate without departing from the spirit of the present disclosure. [Example]

[0111] Next, examples of the present disclosure will be described, but the present disclosure is not limited to the following examples.

[0112] Example 1 A substrate with copper sputtered onto a polyethylene terephthalate film was heated to 80°C, and a photosensitive element was laminated onto the copper surface of the substrate. Lamination was performed using a 110°C heat roll at a pressure of 0.4 MPa and a roll speed of 1.0 m / min, with the photosensitive layer of the photosensitive element in contact with the copper surface of the substrate while peeling off the protective layer. This resulted in a laminate comprising a substrate, a photosensitive layer, and a support, in that order. The resulting laminate was used as a semiconductor package substrate for the following tests.

[0113] In Example 1, a resist pattern with L / S=3.0 / 7.0 μm was formed on a semiconductor package substrate. Then, a 73 μm × 55 μm area of ​​the semiconductor package substrate was imaged using a NEXIV VMZ-R4540. The photograph taken with the NEXIV VMZ-R4540 is shown in FIG.

[0114] In addition, scanning measurements using the NEXIV VMZ-R4540 were performed to identify the contours of the resist pattern on the semiconductor package substrate and measure the coordinates of the contours of the resist pattern for each of the six lines of the resist pattern. Coordinate measurements were performed on 260 points, each 52 μm long and in 0.2 μm increments, on one side of the contour and the other side of the line. These measurements were also performed at three locations on each of the six lines. This resulted in a total of 9,360 coordinates being measured. Figure 10 shows a plot of the coordinates of these 3,120 measured points. Figure 11 shows the plot of Figure 10 overlaid on the photograph in Figure 9, with the plot shifted.

[0115] (Consideration 1) 9 to 11, the plotted diagrams of the measured coordinates roughly matched the contours of the resist pattern in the photographs taken with the NEXIV VMZ-R4540. This result demonstrated that it was possible to inspect and evaluate the resist pattern based on the measured coordinates.

[0116] Example 2 In Example 2, a resist pattern with an L / S ratio of 3.0 / 7.0 μm was formed on a semiconductor package substrate. Then, a 73 μm × 55 μm area of ​​the semiconductor package substrate was imaged using a NEXIV VMZ-R4540. The photograph taken with the NEXIV VMZ-R4540 is shown in FIG. 12.

[0117] In addition, the contour of the resist pattern on the semiconductor package substrate was identified by scanning measurement using the NEXIV VMZ-R4540, and the coordinates of the contour of the resist pattern were measured for six lines. The coordinate measurement was performed in the same manner as in Example 1. Then, based on the coordinates of the measured 9,360 points, the average line width of the resist pattern, the variation (3σ) of the line width of the resist pattern, and the variation (3σ) of the contour of the resist pattern were calculated. The calculation results are shown in Figure 12.

[0118] Example 3 In Example 3, a resist pattern with an L / S ratio of 3.0 / 7.0 μm was formed on a semiconductor package substrate. Then, a 73 μm × 55 μm area of ​​the semiconductor package substrate was imaged using a NEXIV VMZ-R4540. The photograph taken with the NEXIV VMZ-R4540 is shown in FIG. 12.

[0119] In addition, the contour of the resist pattern on the semiconductor package substrate was identified by scanning measurement using the NEXIV VMZ-R4540, and the coordinates of the contour of the resist pattern were measured for six lines. The coordinate measurement was the same as in Example 1. Then, based on the coordinates of the 9,360 measured points, the average line width of the resist pattern and the roughness of the resist pattern were calculated. The roughness of the resist pattern was calculated as the variation (3σ) of the line width of the resist pattern and the variation (3σ) of the contour of the resist pattern. The calculation results are shown in Figure 12.

[0120] (Consideration 2) As shown in FIG. 12, from the photographs of Example 2 and Example 3, it can be seen that the roughness of the resist pattern in Example 2 is rougher than that in Example 3. Furthermore, the roughness of the resist pattern calculated based on the coordinates of the 9,360 measured points is also rougher in Example 2 than in Example 3. Specifically, both the variation in the line width of the resist pattern (3σ) and the variation in the contour of the resist pattern (3σ) are larger in Example 2 than in Example 3. From these results, it was found that the inspection and evaluation of the resist pattern based on the measured coordinates is valid. It was also found that the roughness of the resist pattern can be quantified by inspecting the resist pattern based on the measured coordinates. [Industrial Applicability]

[0121] The present disclosure can be used as a pattern inspection method, a resist pattern manufacturing method, a target substrate selection method, and a target substrate manufacturing method. [Explanation of symbols]

[0122] 1...target substrate, 1a...insulating layer, 1b...conductor layer, 2...photosensitive layer, 2a...photocured portion, 2b...uncured portion, 3...support, 4...laminated body, 5...photomask, 6...resist pattern, 61...contour, 61a...contour on one side, 61b...contour on the other side, 7...conductor pattern, 71...contour, W...line width.

Claims

1. A method for inspecting a pattern, which is either a resist pattern or a conductor pattern, formed on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of the pattern; an inspection step of inspecting the pattern based on the measured coordinates, In the inspection step, the inspection of the pattern includes calculating a variation in the contour of the pattern based on the measured coordinates. How to inspect the pattern.

2. A method for inspecting a pattern, which is either a resist pattern or a conductor pattern, formed on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of the pattern; an inspection step of inspecting the pattern based on the measured coordinates, In the inspection step, the inspection of the pattern includes calculating a line width of the pattern and a variation in the line width based on the measured coordinates. How to inspect the pattern.

3. A method for inspecting a pattern, which is either a resist pattern or a conductor pattern, formed on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of the pattern; an inspection step of inspecting the pattern based on the measured coordinates, In the inspection step, the measured coordinates are compared with pattern data for forming the pattern as the inspection of the pattern. How to inspect the pattern.

4. A method for inspecting a pattern, which is either a resist pattern or a conductor pattern, formed on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of the pattern; an inspection step of inspecting the pattern based on the measured coordinates, the pattern is the resist pattern, a resin film is provided on the resist pattern, In the coordinate measuring step, coordinates of the outline of the pattern are measured through the resin film. How to inspect the pattern.

5. A method for inspecting a pattern, which is either a resist pattern or a conductor pattern, formed on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of the pattern; an inspection step of inspecting the pattern based on the measured coordinates, In the coordinate measuring step, coordinates of the contour of the pattern are measured based on the fluorescence from the target substrate. How to inspect the pattern.

6. In the inspection step, the roughness of the pattern is calculated based on the measured coordinates as the inspection of the pattern.

6. The pattern inspection method according to claim 1.

7. the target substrate comprises an inorganic component including at least one of a silica filler and a glass cloth, and an organic component including at least one of a maleimide resin, a bismaleimide-triazine resin, an epoxy resin, a phenolic resin, a cyanate resin, an isocyanate resin, a benzoxazine resin, an oxetane resin, an amino resin, an unsaturated polyester resin, an allyl resin, a dicyclopentadiene resin, a triazine resin, a melamine resin, and a polyethylene terephthalate resin; 6. The pattern inspection method according to claim 1.

8. the target substrate has at least one of a core layer and a build-up layer; 6. The pattern inspection method according to claim 1.

9. The thickness of the target substrate is 50 μm or more and 3000 μm or less.

6. The pattern inspection method according to claim 1.

10. the pattern is the resist pattern, the resist pattern comprises a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator; 6. The pattern inspection method according to claim 1.

11. the pattern is the resist pattern, The thickness of the resist pattern is 3 μm or more and 200 μm or less.

6. The pattern inspection method according to claim 1.

12. In the coordinate measuring step, coordinates of the contour of the pattern are measured based on reflected light from the target substrate.

5. The pattern inspection method according to claim 1.

13. In the coordinate measuring step, coordinates of the contour of the pattern are measured based on an electron beam from the target substrate.

5. The pattern inspection method according to claim 1.

14. a resist pattern forming step of forming a resist pattern on a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board; a coordinate measuring step of measuring coordinates of a contour of the resist pattern after the resist pattern forming step; an inspection step of inspecting the resist pattern based on the coordinates. A method for producing a resist pattern.

15. In the inspection step, the inspection of the resist pattern includes calculating a variation in the contour of the resist pattern based on the measured coordinates. The method for producing a resist pattern according to claim 14 .

16. In the inspection step, the inspection of the pattern includes calculating a line width of the pattern and a variation in the line width based on the measured coordinates. The method for producing a resist pattern according to claim 14 .

17. In the inspection step, the measured coordinates are compared with pattern data for forming the pattern as the inspection of the pattern. The method for producing a resist pattern according to claim 14 .

18. A resin film is provided on the resist pattern, In the coordinate measuring step, coordinates of the outline of the resist pattern are measured through the resin film. The method for producing a resist pattern according to claim 14 .

19. In the coordinate measuring step, coordinates of the contour of the pattern are measured based on the fluorescence from the target substrate. The method for producing a resist pattern according to claim 14 .

20. In the coordinate measuring step, coordinates of the contour of the resist pattern are measured based on light reflected from the target substrate or an electron beam from the target substrate. The method for producing a resist pattern according to any one of claims 14 to 18.

21. A method for selecting a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, formed on the target substrate; an inspection step of inspecting the pattern based on the measured coordinates; an evaluation step of evaluating the pattern based on the inspection result of the inspection step, In the inspection step, the inspection of the pattern includes calculating a variation in the contour based on the measured coordinates; In the evaluation step, the pattern is evaluated based on the variation in the contour. How to select target boards.

22. A method for selecting a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, formed on the target substrate; an inspection step of inspecting the pattern based on the measured coordinates; an evaluation step of evaluating the pattern based on the inspection result of the inspection step, In the inspection step, the inspection of the pattern includes calculating a line width of the pattern and a variation in the line width based on the measured coordinates; In the evaluation step, the pattern is evaluated based on the calculated variation in the line width. How to select target boards.

23. A method for selecting a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, formed on the target substrate; an inspection step of inspecting the pattern based on the measured coordinates; an evaluation step of evaluating the pattern based on the inspection result of the inspection step, In the inspection step, the measured coordinates are compared with pattern data for forming the pattern as the inspection of the pattern; In the evaluation step, the pattern is evaluated based on a comparison result between the measured coordinates and the pattern data. How to select target boards.

24. A method for selecting a target substrate which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, formed on the target substrate; an inspection step of inspecting the pattern based on the measured coordinates; an evaluation step of evaluating the pattern based on the inspection result of the inspection step, the pattern is the resist pattern, a resin film is provided on the resist pattern, In the coordinate measuring step, coordinates of the outline of the pattern are measured through the resin film. How to select target boards.

25. A method for selecting a target substrate, which is either a semiconductor package substrate for mounting a semiconductor element or a printed wiring board, comprising: a coordinate measuring step of measuring the coordinates of the contour of a pattern, which is either a resist pattern or a conductor pattern, formed on the target substrate; an inspection step of inspecting the pattern based on the measured coordinates; an evaluation step of evaluating the pattern based on the inspection result of the inspection step, In the coordinate measuring step, coordinates of the contour of the pattern are measured based on the fluorescence from the target substrate. How to select target boards.

26. In the inspection step, the roughness of the pattern is calculated based on the measured coordinates as the inspection of the pattern; In the evaluation step, the pattern is evaluated based on the roughness of the pattern. The method for selecting target substrates according to claim 21.

27. In the coordinate measuring step, coordinates of the contour of the pattern are measured based on light reflected from the target substrate or an electron beam from the target substrate. The method for selecting target substrates according to claim 21.

28. The method for selecting a target substrate according to any one of claims 21 to 27 further comprises a conductor pattern forming step of etching or plating the target substrate on which the resist pattern has been formed, the evaluation of which satisfies a standard, to form the conductor pattern. A manufacturing method for the target substrate.

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