semiconductor integrated circuit

Abstract

To provide semiconductor integrated circuits capable of suppressing antenna damage in a mixed analog-digital circuit.SOLUTION: A digital domain 120 of a semiconductor integrated circuit 100 is designed by automatically arranging and routing a plurality of standard cells. An input port Pi of the digital domain 120 is connected to an analog domain. A power supply line VDD and a ground line VSS are laid along a boundary with the analog domain 110. A diode cell D is connected to the input port Pi. A buffer cell BUF is connected to the input port Pi. The diode cell D and the buffer cell BUF are disposed at a portion close to the input port Pi in the standard cell disposition region 124.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] EDA tools that perform automatic layout play an important role in the design of semiconductor integrated circuits. When EDA tools input connection information (logic circuit design results, called a netlist) for cells and macrocells (hereinafter collectively referred to as standard cells), they automatically determine (place) the positions of the standard cells on the chip and automatically connect the wires between them. This function is also called P&R (Place and Route). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-266108 Summary of the Invention [Problem to be solved by the invention]

[0004] As semiconductor integrated circuits become smaller, antenna damage can cause reliability problems. Figure 1 is a cross-sectional view of a semiconductor integrated circuit 10. A transistor 12 has a source region S, a drain region D, and a gate region G. A gate oxide film 14 and a gate electrode 16 are formed in the gate region G. A metal wiring 18 is connected to the gate electrode 16.

[0005] In the manufacturing process of a semiconductor integrated circuit, plasma etching causes an electric charge Q to be charged in the metal wiring 18 connected to the gate electrode 16. If this electric charge Q flows into the gate oxide film 14, the reliability of the gate oxide film 14 will decrease. Antenna damage can cause an increase in the threshold voltage of the transistor 12 and an increase in leakage current, leading to deterioration of the transistor characteristics and a decrease in yield.

[0006] To prevent antenna damage, process rules are established. For example, process rules regarding antenna damage (hereinafter referred to as antenna rules) vary depending on the IC (Integrated Circuit) manufacturer, but are basically defined based on the relationship between the area of ​​the gate electrode 16 and the area of ​​the metal wiring 18 (also called the antenna ratio).

[0007] The present inventors have studied antenna damage in analog-digital mixed circuits and have come to recognize the following problem.

[0008] FIG. 2 is a diagram illustrating the design of an analog-digital mixed circuit 20. The analog-digital mixed circuit 20 has an analog area 22 and a digital area 24. The layout and wiring of the digital area 24 are automatically generated by inputting a netlist describing the equivalent circuit of the digital circuit into a design support tool (P&R tool). The design support tool automatically places multiple standard cells according to the netlist and automatically wires them to generate a mask layout of the semiconductor integrated circuit. Antenna rules are defined as P&R constraints imposed by the design support tool.

[0009] Generally, the analog-digital mixed circuit 20 is designed in the following procedure. First, the analog area 22 and the digital area 24 are designed separately. The digital area 24 has an input port Pi connected to the analog area 22 and a logic gate LG that processes the input signal input via the input port Pi. The antenna rules for the digital area 24 are satisfied.

[0010] When the design of the analog area 22 and the digital area 24 is completed, the input port Pi of the digital area 24 is connected to the corresponding output port Po of the analog area 22 via metal wiring 26. At this time, the metal wiring 26 is connected to the first-stage logic gate LG, which is connected to the input port Pi of the digital area 24. If the area of ​​this metal wiring 26 is large, an antenna rule violation occurs in the transistor that constitutes the logic gate LG. If an antenna rule violation occurs, a redesign is required to resolve the rule violation.

[0011] The present disclosure has been made in view of the above-mentioned problems, and one exemplary purpose of an embodiment thereof is to provide a semiconductor integrated circuit capable of suppressing antenna damage in an analog-digital mixed circuit. [Means for solving the problem]

[0012] A semiconductor integrated circuit according to an embodiment of the present disclosure includes a digital area designed by automatically placing and routing a plurality of standard cells, and an analog area connected to the digital area. The digital area includes an input port connected to the analog area, a power supply line and a ground line laid along the boundary with the analog area, a diode cell connected to the input port, and a buffer cell connected to the input port. The diode cell and the buffer cell are placed in a location close to the input port within the standard cell placement area.

[0013] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Effects of the Invention]

[0014] According to an aspect of the present disclosure, antenna damage in an analog-digital mixed circuit can be suppressed. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor integrated circuit. [Figure 2] FIG. 2 is a diagram illustrating the design of an analog-digital mixed circuit. [Figure 3] FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to the embodiment. [Figure 4] FIG. 4 is a diagram showing the layout of the digital area of ​​the semiconductor integrated circuit of FIG. [Figure 5] FIG. 5 is a diagram illustrating the advantages of a semiconductor integrated circuit. [Figure 6] FIG. 6 is a diagram showing an equivalent circuit of a buffer cell. [Figure 7] FIG. 7 is a diagram showing the layout of the buffer cell of FIG. [Figure 8] FIG. 8 is a diagram showing a layout of a diode cell. [Figure 9] FIG. 9 is an equivalent circuit diagram of another diode cell. [Figure 10] FIG. 10 is a diagram showing a layout of the diode cell of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0016] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0017] A semiconductor integrated circuit according to one embodiment includes a digital area designed by automatically placing and routing a plurality of standard cells, and an analog area connected to the digital area. The digital area includes an input port connected to the analog area, a power supply line and a ground line laid along the boundary with the analog area, a diode cell connected to the input port, and a buffer cell connected to the input port. The diode cell and the buffer cell are placed in a location adjacent to the input port within the standard cell placement area.

[0018] With this configuration, by placing the diode cell and buffer cell close to the input port, the length of the metal wiring connected to the logic gate next to the buffer cell is determined, so the design of the internal circuit in the digital area can be determined while satisfying the antenna rule, regardless of the connection form with the analog area. Also, by designing the size of the diode cell and buffer cell based on the maximum area of ​​the metal wiring connecting the analog area and the digital area, the antenna rule can be satisfied even when connected to the analog area.

[0019] In one embodiment, the standard cell placement area may be divided into a plurality of rows extending in a first direction and adjacent to each other in a second direction, and the diode cells and buffer cells connected to the same input port may be arranged adjacent to each other in the same row.

[0020] In one embodiment, the input ports may be arranged on one side of the digital area extending in a first direction, and the diode cells and buffer cells connected to the same input port may be arranged in a row adjacent to a pair of power supply and ground lines.

[0021] In one embodiment, the input ports may be arranged on one side of the digital area extending in a first direction, and the diode cells and buffer cells connected to the same input port may be arranged in rows spaced apart by one row with respect to the power supply line and the ground line.

[0022] In one embodiment, the placement of cells that make up the actual circuit may be prohibited in rows where diode cells and buffer cells are placed.

[0023] In one embodiment, the standard cell placement area is divided into multiple rows extending in a first direction and adjacent in a second direction, the input ports are arranged on two sides of the digital area extending in the second direction, low-end cells are arranged at the ends of each row, and diode cells and buffer cells may be arranged in areas adjacent to the low-end cells.

[0024] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0025] In addition, the dimensions (thickness, length, width, etc.) of each component shown in the drawings may be enlarged or reduced as appropriate for ease of understanding. Furthermore, the dimensions of multiple components do not necessarily represent their relative sizes, and even if a component A is depicted as being thicker than another component B in the drawings, it is possible that component A is thinner than component B.

[0026] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0027] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0028] 3 is a circuit diagram of a semiconductor integrated circuit 100 according to an embodiment. The semiconductor integrated circuit 100 is an analog-digital mixed circuit including an analog area 110 and a digital area 120, and is a functional IC integrated on a single semiconductor substrate.

[0029] The analog area 110 has a plurality of output ports Po1 to Po n The digital domain 120 has a plurality of input ports Pi1 to Pi n The jth (j=1, 2, . . . n) analog domain 110 output port Po j and the corresponding input port Pi in the digital domain 120 j is the metal wiring ML j The metal wiring ML1 to ML n The wiring layout must be determined manually by the designer of the semiconductor integrated circuit 100.

[0030] The digital domain 120 includes a plurality of input ports Pi1 to Pi n , multiple buffers BUF1~BUF n , a plurality of diodes D1 to D n , and an internal circuit 122. The digital area 120 is designed by automatically placing and routing a plurality of standard cells using a P&R tool.

[0031] The internal circuit 122 is a combinational circuit, a sequential circuit, a combinational sequential circuit, or the like, and its function is not particularly limited and is designed according to the function of the semiconductor integrated circuit 100. The internal circuit 122 has a plurality of input ports Pi1 to Pi n Multiple logic gates LG1 to LG nIn this example, the logic gate LG1 is an AND (logical product) gate, the logic gate LG2 is a multiplexer (selector), and the n-th logic gate LG n are buffers, but the types of logic gates are not limited to these and may be NAND (negative logical AND) gates, inverters, OR (logical OR) gates, NOR (negative logical OR) gates, XOR (exclusive OR) gates, or XNOR (exclusive NOT OR) gates.

[0032] Diode D j corresponds to the input port Pi j Specifically, the diode D j The cathode of the corresponding input port Pi j and is connected.

[0033] Buffer BUF j The input node of the corresponding input port Pi j and connected to the buffer BUF j The output node of the buffer BUF is connected to the internal circuit 122. j The output node of the corresponding logic gate LG j is connected to the input node of

[0034] The above is the circuit diagram of the semiconductor integrated circuit 100. Next, the layout will be described. Fig. 4 is a diagram showing the layout of the digital area 120 of the semiconductor integrated circuit 100 of Fig. 3.

[0035] The power supply line VDD and the ground line GND are laid along the boundary between the analog area 110 (not shown in FIG. 4) and the digital area 120. For example, the digital area 120 may be rectangular, and the power supply line VDD and the ground line GND may be ring wiring that surrounds the standard cell placement area 124 of the rectangular digital area 120.

[0036] In the standard cell placement area 124, standard cells are automatically laid out by a P&R tool.

[0037] The buffer BUF and the diode D are prepared as standard cells (S / C) registered in a standard library, and the standard cell of the buffer BUF is called a buffer cell, and the standard cell of the diode D is called a diode cell.

[0038] 4 shows six input ports Pi1 to Pi6. The j-th input port Pi j In the area adjacent to the input port Pi j and the corresponding buffer cell BUF j and diode cell D j "Proximity" means that diode cells and buffer cells are preferentially placed in an area closer to the input port than other cells. In other words, no cells other than diode cells and buffer cells (excluding low-end cells) are placed between a combination of diode cells and buffer cells and the corresponding input port.

[0039] The plurality of buffer cells BUF1 to BUF6 and the plurality of diode cells D1 to D6 are concentrated in the outermost peripheral portion of the standard cell placement region 124, and the standard cells that constitute the internal circuit 122, which is the actual circuit, are not placed in this outermost peripheral portion.

[0040] The standard cell placement area 124 extends in a first direction (the x-axis direction in FIG. 4) and is divided into a plurality of rows ROW1, ROW2, ... adjacent to each other in a second direction (the y-axis direction in FIG. 4). Standard cells are configured in units of rows ROW.

[0041] Same input port Pi j Diode cell D connected to j and buffer cell BUF j are placed adjacent to each other in the same row. In other words, such a constraint is imposed on the P&R tool by the software program.

[0042] The input ports Pi may be arranged in the row direction (first direction, x-axis direction) or in the column direction (second direction, y-axis direction). The input ports arranged in the row direction will be described below.

[0043] 4, the input ports Pi1 to Pi3 are aligned in the row direction and arranged on one side extending in the first direction (x-axis direction) of the digital area 120. The diode cell D1 and buffer cell BUF1 connected to the input port Pi1 are arranged adjacent to the first row ROW1, which is adjacent to the power supply line VDD and the ground line GND. Similarly, the diode cell D3 and buffer cell BUF3 connected to the input port Pi3 are arranged adjacent to the first row ROW1.

[0044] Input port P i If the spacing between the input ports Pi is narrow and it is not possible to arrange all of the diode cells and buffer cells in the first row ROW1, the diode cells D and buffer cells BUF connected to some of the input ports Pi can be arranged in the second row ROW2, which is one row away from the power supply line VDD and the ground line GND. In the example of Figure 4, the diode cell D2 and buffer cell BUF2 connected to the input port Pi2 are arranged adjacent to the second row ROW2.

[0045] In rows ROW1 and ROW2 in which diode cells D1 to D3 and buffer cells BUF1 to BUF3 associated with a plurality of input ports Pi1 to Pi3 adjacent to each other in the row direction are arranged, arrangement of cells constituting the actual circuit may be prohibited.

[0046] The input ports arranged in the column direction will now be described. In the example of Fig. 4, the input ports Pi4 to Pi6 are aligned in the column direction and arranged on one side extending in the second direction (y-axis direction) of the digital area 120. The diode cell D4 and buffer cell BUF4 connected to the input port Pi4 are arranged in row ROW2 close to the input port Pi4, and close to the input port Pi4.

[0047] A low-end cell is placed at the end (head) of each row ROW. In this case, a diode cell D4 and a buffer cell BUF4 can be placed in an area adjacent to the low-end cell.

[0048] Similarly, the diode cell D5 and buffer cell BUF5 connected to the input port Pi5 are arranged in the row ROW3 close to the input port Pi5 and close to the input port Pi5.

[0049] Similarly, the diode cell D6 and buffer cell BUF6 connected to the input port Pi6 are arranged in the row ROW4 close to the input port Pi6 and close to the input port Pi6.

[0050] The above is the configuration of the semiconductor integrated circuit 100. Next, the advantages of the semiconductor integrated circuit 100 will be described.

[0051] Fig. 5 is a diagram illustrating the advantages of the semiconductor integrated circuit 100. Fig. 5 shows only the configuration related to one input port Pi.

[0052] By placing the diode cell D and the buffer cell BUF close to the input port Pi, the length of the metal wiring ML1 connected to the logic gate next to the buffer cell BUF is determined. Therefore, the design of the internal circuit 122 in the digital area 120 can be determined while satisfying the antenna rule, regardless of the connection topology with the analog area 110.

[0053] Furthermore, by designing the sizes of the diode cell D and the buffer cell BUF assuming the maximum area of ​​the metal wiring ML2 connecting the analog area 110 and the digital area 120, the antenna rules can be satisfied even when connected to the analog area 110.

[0054] Next, examples of the configuration of the buffer cell and the diode cell will be described.

[0055] 6 is a diagram showing an equivalent circuit of a buffer cell. The buffer cell BUF includes two stages of CMOS inverters INV1 and INV2. The first stage CMOS inverter INV1 includes a PMOS transistor MP1 and an NMOS transistor MN1. The second stage CMOS inverter INV2 includes a PMOS transistor MP2 and an NMOS transistor MN2.

[0056] 7 is a diagram showing the layout of the buffer cell of FIG. 6. At the upper and lower ends of the buffer cell, line wirings branching from the ring wirings VDD and GND of FIG. 4 extend in the horizontal direction. Above the center of the cell, a diffusion region p + This diffusion region p + In the second region, two PMOS transistors MP1 and MP2 are formed adjacent to each other in the x direction.

[0057] Below the center of the cell, there is a diffusion region n on the p-well. + This diffusion region n + In the second region, two NMOS transistors MN1 and MN2 are formed adjacent to each other in the x direction.

[0058] The gate electrode G1 is connected to the gates (G) of the transistors MP1 and MN1 of the first-stage inverter INV1, and the gate electrode G2 is connected to the gates (G) of the transistors MP2 and MN2 of the next-stage inverter INV2.

[0059] The drain electrode D1 is connected to the drains (D) of the transistors MP1 and MN1 of the first-stage inverter INV1 and also to the gate electrode G2, and the drain electrode D2 is connected to the drains (D) of the transistors MP2 and MN2 of the next-stage inverter INV2.

[0060] The sources (S) of the PMOS transistors MP1 and MP2 are connected to the power supply line VDD, and the sources (S) of the NMOS transistors MN1 and MN2 are connected to the ground line VSS.

[0061] 8 is a diagram showing the layout of a diode cell. This diode cell D has n + It consists of a PN junction between the diffusion region and the p-type substrate. + is the cathode of the diode, which is connected to the input port Pi. The anode of the diode is connected to the substrate.

[0062] Figure 9 is an equivalent circuit diagram of another diode cell. Diode cell D is a special diode with a gate, and includes a PMOS transistor MP3 and an NMOS transistor MN3. The NMOS transistor MN3 is a MOS diode with its drain and gate wired together. The drain and source regions of the PMOS transistor MP3 are open, and it does not actually function as a transistor. The gates of the PMOS transistor MP3 and NMOS transistor MN3 are commonly connected.

[0063] Figure 10 is a diagram showing the layout of the diode cell of Figure 9. The diode cell includes a PMOS transistor MP3 and an NMOS transistor MN3. The gate electrodes G3 and G4 of the transistors MP3 and MN3 are connected via a metal wiring M5. The gate and drain of the transistor MN3 are also connected via the metal wiring M5.

[0064] The advantages of the diode cells of FIGS. 9 and 10 will be explained. The antenna rule is determined by the relationship between the gate area and the size of the metal wiring connected to it, and the larger the gate area, the larger the allowable size of the metal wiring. Since the diode cell D of FIGS. 9 and 10 has a gate, the antenna rule is determined by the sum of the area of ​​the first stage gate of the buffer cell BUF and the area of ​​the gate of the diode cell D. Therefore, the allowable size of the metal wiring ML of FIG. 3 can be made larger than that of the gate-less diode cell of FIG. 8.

[0065] The present invention has been described above based on the embodiments. However, it goes without saying that the embodiments merely illustrate the principles and applications of the present invention, and that many modifications and changes in arrangement are possible to the embodiments without departing from the spirit of the present invention as defined in the claims. [Explanation of symbols]

[0066] 100 Semiconductor Integrated Circuit 110 Analog Domain Pi Input Port VDD power line VSS ground line 120 Digital Domain Po output port 122 Internal circuit 124 Standard Cell Placement Area

Claims

1. The digital area is designed by automatically placing and routing multiple standard cells. an analog domain connected to the digital domain; Equipped with The digital domain comprises: an input port connected to the analog domain; a power supply line and a ground line laid along the boundary with the analog area; a diode cell connected to the input port; a buffer cell connected to the input port; Equipped with The semiconductor integrated circuit, wherein the diode cell and the buffer cell are arranged in a standard cell arrangement area in proximity to the input port.

2. the standard cell layout area is divided into a plurality of rows extending in a first direction and adjacent to each other in a second direction; 2. The semiconductor integrated circuit according to claim 1, wherein the diode cells and the buffer cells connected to the same input port are arranged adjacent to each other in the same row.

3. the input port is disposed on one side of the digital area extending in the first direction, 3. The semiconductor integrated circuit according to claim 2, wherein the diode cell and the buffer cell connected to the same input port are arranged in a row adjacent to the pair of the power supply line and the ground line.

4. the input port is disposed on one side of the digital area extending in the first direction, 3. The semiconductor integrated circuit according to claim 2, wherein said diode cells and said buffer cells are arranged in rows spaced apart by one row with respect to said power supply line and said ground line.

5. 5. The semiconductor integrated circuit according to claim 3, wherein cells constituting an actual circuit are prohibited from being placed in rows in which said diode cells and said buffer cells are placed.

6. the standard cell layout area is divided into a plurality of rows extending in a first direction and adjacent to each other in a second direction; the input ports are arranged on two sides of the digital area extending in the second direction, Low-end cells are placed at the end of each row, 3. The semiconductor integrated circuit according to claim 1, wherein the diode cell and the buffer cell are arranged in a region adjacent to the low-end cell.

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