MEMORY STRUCTURE AND CONTROL METHOD FOR MEMORY DEVICE - Patent application

Abstract

To provide a memory structure capable of reducing a circuit area without arranging a capacitance in order to store data.SOLUTION: A memory structure 100 contains a plurality of first transistors T1 and a plurality of second transistors T2 that are arranged onto a substrate SUB. The first transistors are arranged to a first array, and first ends of the first transistors are respectively coupled to a plurality of first bit lines WBL, and gates of the first transistors are respectively coupled to a plurality of first word lines WWL. The second transistors are arranged to a second array, and gates of the second transistors are respectively coupled to second ends of the first transistors. Second ends and first ends of the second transistors are respectively coupled to second bit lines RBL and second word lines RWL. The first word lines or the first bit lines are extended along a normal direction of a flat surface of the substrate, and the second word lines or the bit lines are extended along the normal direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory structure and a control method for a memory device, and more particularly to a memory structure for a dynamic random access memory and a control method for a memory device. [Background technology]

[0002] In the conventional technology field, memory cells of dynamic random access memories are often constructed using 1T1C architecture. In this technology, the complexity of the process for forming capacitance poses a major obstacle when adjusting the circuit scale of memory cells. As the memory dimensions decrease, the area ratio of capacitance increases significantly.

[0003] By constructing dynamic random access memory using three-dimensional stacking, the memory capacity of the dynamic random access memory can be effectively increased. However, in the conventional 1T1C architecture, the capacitance in the three-dimensional stacking structure occupies a large circuit area, which increases the manufacturing cost of the memory. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a memory structure that does not require the placement of capacitance for storing data and can effectively reduce the circuit area. [Means for solving the problem]

[0005] A memory structure according to the present disclosure includes a plurality of first transistors and a plurality of second transistors. The first transistors are arranged in a first array. First ends of the first transistors are respectively coupled to a plurality of first bit lines, and gates of the first transistors are respectively coupled to a plurality of first word lines. The second transistors are arranged in a second array. Gates of the second transistors are respectively coupled to second ends of the first transistors, second ends of the second transistors are respectively coupled to second bit lines, and first ends of the second transistors are respectively coupled to second word lines. The first transistors and the second transistors are arranged on a substrate. One of each of the first word lines and each of the first bit lines extends along a normal direction to a plane of the substrate, and one of each of the second word lines and each of the second bit lines extends along the normal direction.

[0006] A method of controlling a memory device includes: arranging a plurality of first transistors arranged in a first array, wherein first ends of the first transistors are respectively coupled to a plurality of first bit lines and gates of the first transistors are respectively coupled to a plurality of first word lines; arranging a plurality of second transistors arranged in a second array, wherein gates of the second transistors are respectively coupled to second ends of the first transistors, second ends of the second transistors are respectively coupled to a plurality of second bit lines and first ends of the second transistors are respectively coupled to a plurality of second word lines; extending each of the first word lines and one of the first bit lines along a direction normal to a plane of a substrate to provide a first signal; and extending each of the second word lines and one of the second bit lines along a direction normal to the plane of the substrate to provide a second signal. [Effects of the Invention]

[0007] Based on the above, in the memory structure according to the present disclosure, a memory cell comprises a first transistor and a second transistor. The coupling terminals of the first transistor and the second transistor can be used as a data storage node. In this way, the memory cell can be used to perform dynamic random access to the memory cell, and the memory cell can effectively reduce the layout area of ​​the circuit without providing a storage capacitor. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic three-dimensional structural diagram of a memory structure according to one embodiment of the present invention;

[0009] [Figure 2] 2 is an equivalent circuit diagram of a memory cell in a memory structure according to an embodiment of the present invention.

[0010] [Figure 3] 2 is a circuit schematic diagram of a memory cell array formed by the memory structure of FIG. 1 according to one embodiment of the present invention.

[0011] [Figure 4] FIG. 2 is a schematic three-dimensional structural diagram of a memory structure according to another embodiment of the present invention.

[0012] [Figure 5] FIG. 5 is a circuit schematic diagram of a memory cell array formed by the memory structure of FIG. 4 according to one embodiment of the present disclosure.

[0013] [Figure 6] FIG. 2 is a schematic three-dimensional structural diagram of a memory structure according to another embodiment of the present invention.

[0014] [Figure 7] FIG. 7 is a circuit schematic diagram of a memory cell array formed by the memory structure of FIG. 6 according to one embodiment of the present disclosure.

[0015] [Figure 8] FIG. 2 is a schematic three-dimensional structural diagram of a memory structure according to another embodiment of the present invention.

[0016] [Figure 9] FIG. 9 is a circuit schematic diagram of a memory cell array formed by the memory structure of FIG. 8 according to one embodiment of the disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] Please refer to FIG. 1. FIG. 1 is a schematic three-dimensional structural diagram of a memory structure according to one embodiment of the present invention. The memory structure 100 is disposed on a plane of a substrate SUB. The plane of the substrate SUB is formed on the XY-axis plane and has the same normal direction as the Z-axis. The memory structure 100 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistors T1 are arranged in a first array having an N×M shape, and the second transistors T2 are arranged in a second array having an N×M shape. In this embodiment, N and M can both be equal to 4. In other embodiments of the present disclosure, N and M can be any other positive integers.

[0018] In this embodiment, the first array has a plurality of channel pillars 110 and a plurality of conductive structures WWL1 to WWL4. The channel pillars 110 are arranged in a 4×4 pattern. For example, assuming that the X-axis direction is the row direction and the Z-axis direction is the column direction, each of the conductive structures WWL1 to WWL4 may extend along the row direction, and the conductive structures WWL1 to WWL4 may be arranged vertically along the column direction. Each of the conductive structures WWL1 to WWL4 surrounds the channel pillars 110 arranged in the same row. In this embodiment, each of the conductive structures WWL1 to WWL4 surrounds four channel pillars 110, thereby forming a common gate line and word line for the four first transistors T1 corresponding to the four surrounded channel pillars 110. Note that, taking the conductive structure WWL1 as an example, a gate oxide layer GOX may be provided between the conductive structure WWL1 and the surrounded channel pillar 110.

[0019] In this embodiment, the first end of the channel pillar 110 can be coupled to the second transistor T2, and the second end of the channel pillar 110 can be coupled to bit lines WBL1 to WBL4, each formed by a conductive structure. In this embodiment, each of the bit lines WBL1 to WBL4 can extend along the Z-axis and be coupled to the second ends of multiple channel pillars 110 arranged in the same column. The bit lines WBL1 to WBL4 can be arranged continuously along the X-axis. In this embodiment, the extension direction of each of the bit lines WBL1 to WBL4 can be substantially perpendicular to the extension direction of each of the conductive structures WWL1 to WWL4, which form the word lines. It is worth noting that the extension directions of each of the bit lines WBL1 to WBL4 and each of the conductive structures WWL1 to WWL4 may not be exactly perpendicular to each other due to tolerances caused by the manufacturing process, and therefore form a substantially orthogonal state.

[0020] Meanwhile, the second array includes a plurality of gate structures, a plurality of conductive structures 120, and RWL1 to RWL4. In this embodiment, the channel pillars 110 may extend along the Y-axis within the second array to form corresponding gate structures. That is, each channel pillar 110 and each corresponding gate structure may have the same structure. In this embodiment, since the channel pillars 110 are arranged in a 4×4 pattern, the gate structures are also arranged in a 4×4 pattern. The plurality of conductive structures 120 correspond to the gate structures, extend along the Y-axis direction to surround the corresponding gate structures, and form gates of the plurality of second transistors T2. Similarly, a gate oxide layer (not shown) may be provided between each conductive structure 120 and each surrounded gate structure.

[0021] Furthermore, each of the conductive structures RWL1 to RWL4 extends along the X-axis direction. The conductive structures RWL1 to RWL4 are arranged vertically along the Z-axis direction. Each of the conductive structures RWL1 to RWL4 covers four conductive structures 120 arranged in the same row and forms a common word line for the multiple second transistors T2 arranged in the same row. Each of the bit lines RBL1 to RBL4 extends along the Z-axis direction and can be coupled to one end of the multiple conductive structures 120 arranged in the same column. The bit lines RBL1 to RBL4 are arranged along the Z-axis direction.

[0022] It is worth mentioning that in this embodiment, a channel (e.g., a channel CH between the conductive structure RWL4 and the bit line RBL1) can be formed on the conductive structure 120 between each of the conductive structures RWL1 to RWL4 and each of the bit lines RBL1 to RBL4.

[0023] In this embodiment, the extension direction of each of the bit lines RBL1 to RBL4 can be substantially perpendicular to the extension direction of each of the conductive structures RWL1 to RWL4 that form the word lines. It is worth noting that the extension directions of each of the bit lines RBL1 to RBL4 and each of the conductive structures RWL1 to RWL4 may not be exactly perpendicular to each other due to tolerances caused by the manufacturing process, and therefore form a substantially perpendicular state.

[0024] In this embodiment, due to manufacturing tolerances, the extending directions of the conductive structures WWL1 to WWL4 and the conductive structures RWL1 to RWL4 are substantially the same, and the extending directions of the bit lines WBL1 to WBL4 and the bit lines RBL1 to RBL4 are substantially the same.

[0025] It is worth mentioning that in this embodiment, the material of the channel pillar 110 can be silicon, gallium arsenide, silicon carbide, or other suitable semiconductor channel materials, and the conductive structures 120, WWL1 to WWL4, and RWL1 to RWL4 can be any conductive structures in a semiconductor manufacturing process, and the present disclosure is not limited thereto. The first transistor T1 in this embodiment can be a gate-all-around (GAA) transistor, and the second transistor T2 can be a channel-all-around (CAA) transistor.

[0026] In the following description, please refer to FIG. 2, which is an equivalent circuit diagram of a memory cell in a memory structure according to one embodiment of the present invention. The memory cell 200 includes a first transistor T1 and a second transistor T2. A first end of the first transistor T1 is coupled to a bit line WBL, a second end of the first transistor T1 is coupled to a data storage node SN, and a gate of the first transistor T1 is coupled to a word line formed by a conductive structure WWL. A first end of the second transistor T2 is coupled to a bit line RBL, a second end of the second transistor T2 is coupled to a word line formed by a conductive structure RWL, and a gate of the second transistor T2 is coupled to the data storage node SN.

[0027] In a data write mode, the first transistor T1 can be turned on according to a control signal transmitted by the conductive structure WWL, and a first end of the first transistor T1 can receive write data through the bit line WBL and write the write data to the data storage node SN through the turned-on first transistor T1.

[0028] In a data read mode, the first transistor T1 can be turned off. The second end of the second transistor T2 can receive a selected voltage via the conductive structure RWL to initiate a read operation. At the same time, the second transistor T2 can be turned on or off based on the data stored in the data storage node SN. For example, if the data stored in the data storage node SN is a high logic value, the second transistor T2 can be turned on. In this manner, the second transistor T2 can supply a corresponding read current to the bit line RBL. By configuring a sense amplifier to sense the read current, it can be determined that the data stored in the data storage node SN is a high logic value. Conversely, if the data stored in the data storage node SN is a low logic value, the second transistor T2 can be turned off. As a result, the corresponding read current supplied by the second transistor T2 to the bit line RBL is substantially equal to zero. By sensing the read current substantially equal to zero, the sense amplifier can determine that the data stored in the data storage node SN is a low logic value.

[0029] Please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 1 according to one embodiment of the present invention. The memory cell array 300 has a plurality of memory cell slices 301-30n. Each of the memory cell slices 301-30n includes a memory cell array including a plurality of memory cells MC (only one of which is shown in the figure for illustrative purposes), each of which includes a first transistor T1 and a second transistor T2. The memory cell slice 301 has a plurality of bit lines WBL_00-WBL_0n extending along the Z-axis and a plurality of bit lines RBL_00-RBL_0n extending along the Z-axis. The bit lines WBL_00-WBL_0n are coupled to the first transistor T1, and the bit lines RBL_00-RBL_0n are coupled to the second transistor T2. Similarly, memory cell slice 30n has a plurality of bit lines WBL_n0 to WBL_nn extending along the Z-axis and a plurality of bit lines RBL_n0 to RBL_nn extending along the Z-axis. Bit lines WBL_n0 to WBL_nn are coupled to a first transistor T1, and bit lines RBL_n0 to RBL_nn are coupled to a second transistor T2.

[0030] Conductive structures WWL_00 to WWL_nn and RWL_00 to RWL_nn for forming word lines extend along the X-axis and are cross-connected among the memory cell slices 301 to 30n. The conductive structures WWL_00 to WWL_nn are coupled to a first transistor T1, and the conductive structures RWL_00 to RWL_nn are coupled to a second transistor T2.

[0031] During a data write mode, for a selected memory cell, a selected write word line (at least one of the conductive structures WWL_00 to WWL_nn) may provide a word line signal equal to voltage V1, and a write bit line (at least one of the bit lines WBL_00 to WBL_nn) corresponding to the selected memory cell may provide a bit line signal equal to voltage V1 or voltage V2 according to the logic value 0 or 1 of the data to be written, where voltage V1 may be 3V and voltage V2 may be 0V. In comparison, for an unselected memory cell, unselected word lines and bit lines may provide a signal of 0V. During a retention mode, all voltages on the bit lines and word lines are 0V. During a data read mode, a read word line (at least one of the conductive structures RWL_00 to RWL_nn) may provide a word line signal equal to voltage V3, and a voltage RV of a read bit line (at least one of the bit lines RBL_00 to RBL_nn) may be determined by the stored logic value of the corresponding selected memory cell. Here, the voltage V3 may be smaller than the voltage V1, for example, the voltage V3 may be 1 V. Details of the operation can be seen in the truth table below. [Table 1]

[0032] Please refer to FIG. 4. FIG. 4 is a schematic three-dimensional structural diagram of a memory structure according to another embodiment of the present invention. The memory structure 400 is disposed on a plane of a substrate SUB. The plane of the substrate SUB is formed on the XY-axis plane and has the same normal direction as the Z-axis. The memory structure 400 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistors T1 are arranged in a first array having an N×M shape, and the second transistors T2 are arranged in a second array having an N×M shape. In this embodiment, N and M can both be equal to 4. In other embodiments of the present disclosure, N and M can be any other positive integers.

[0033] In the following description, the X-axis direction is the row direction, and the Z-axis direction is the column direction. The structures of the first transistor T1 and the second transistor T2 in this embodiment are similar to those in the embodiment of FIG. 1. It is noteworthy that in this embodiment, each of the multiple bit lines WBL1 to WBL4 coupled to the first transistor T1 extends along the X-axis and is coupled to multiple channel pillars 410 arranged in the same row. The bit lines WBL1 to WBL4 are arranged vertically along the Z-axis direction. Each of the conductive structures WWL1 to WWL4 extends along the Z-axis direction and surrounds multiple channel pillars 410 arranged in the same column, forming a common gate for the multiple first transistors T1 arranged in the same column. The conductive structures WWL1 to WWL4 are arranged along the X-axis direction.

[0034] Furthermore, each of the multiple bit lines RBL1 to RBL4 coupled to the second transistor T2 extends along the Z-axis direction. The bit lines RBL1 to RBL4 are arranged along the X-axis direction. Each of the bit lines RBL1 to RBL4 is coupled to one end of multiple conductive structures 420 arranged in the same column. Each of the conductive structures RWL1 to RWL4 extends along the X-axis direction and covers multiple conductive structures 420 arranged in the same row, forming a word line for the multiple second transistors T2 arranged in the same row. The conductive structures RWL1 to RWL4 are arranged vertically along the Z-axis direction.

[0035] In this embodiment, a plurality of word lines formed by the conductive structures WWL1 to WWL4 and the bit lines RBL1 to RBL4 extend along the normal direction to the plane of the substrate SUB (ie, the Z-axis direction).

[0036] Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 4 according to one embodiment of the present disclosure. The memory cell array 500 includes a plurality of memory cell slices 501-50n. Each of the memory cell slices 501-50n includes a memory cell array including a plurality of memory cells MC, each including a first transistor T1 and a second transistor T2. The memory cell slice 501 includes a plurality of conductive structures WWL_00-WWL_0n extending along the Z-axis to form word lines, and a plurality of bit lines RBL_00-RBL_0n extending along the Z-axis. The conductive structures WWL_00-WWL_0n are coupled to the control end of the first transistor T1, and the bit lines RBL_00-RBL_0n are coupled to the second transistor T2. Similarly, memory cell slice 50n has a plurality of conductive structures WWL_n0-WWL_nn extending along the Z-axis to form word lines, and a plurality of bit lines RBL_n0-RBL_nn extending along the Z-axis. The conductive structures WWL_n0-WWL_nn are coupled to the control end of first transistor T1, and the bit lines RBL_n0-RBL_nn are coupled to second transistor T2.

[0037] The bit lines WBL_00 to WBL_nn and the conductive structures RWL_00 to RWL_nn for forming the word lines extend along the X-axis direction and can be cross-connected among the memory cell slices 501 to 50n. The bit lines WBL_00 to WBL_nn are coupled to a first transistor T1, and the conductive structures RWL_00 to RWL_nn are coupled to a second transistor T2.

[0038] Please refer to FIG. 6. FIG. 6 is a schematic three-dimensional structural diagram of a memory structure according to another embodiment of the present invention. The memory structure 600 is disposed on a plane of a substrate SUB. The plane of the substrate SUB is formed on the XY-axis plane and has the same normal direction as the Z-axis. The memory structure 600 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistors T1 are arranged in a first array having an N×M shape, and the second transistors T2 are arranged in a second array having an N×M shape. In this embodiment, N and M can both be equal to 4. In other embodiments of the present disclosure, N and M can be any other positive integers.

[0039] In the following description, the X-axis direction is the row direction, and the Z-axis direction is the column direction. The structures of the first transistor T1 and the second transistor T2 in this embodiment are similar to those in the embodiments of FIGS. 1 and 4. It is noteworthy that in this embodiment, each of the multiple bit lines WBL1 to WBL4 coupled to the first transistor T1 extends along the X-axis and is coupled to multiple channel pillars 610 arranged in the same row. The bit lines WBL1 to WBL4 are arranged vertically along the Z-axis direction. Each of the conductive structures WWL1 to WWL4 extends along the Z-axis direction and surrounds multiple channel pillars 610 arranged in the same column, forming a common gate for the multiple first transistors T1 arranged in the same column. The conductive structures WWL1 to WWL4 are arranged continuously along the X-axis direction.

[0040] Furthermore, each of the multiple bit lines RBL1 to RBL4 coupled to the second transistor T2 extends along the X-axis direction. The bit lines RBL1 to RBL4 are arranged vertically along the Z-axis direction. Each of the bit lines RBL1 to RBL4 is coupled to one end of the multiple conductive structures 620 arranged in the same row. Each of the conductive structures RWL1 to RWL4 extends along the Z-axis direction and covers and surrounds the multiple conductive structures 620 arranged in the same row, forming a word line for the multiple second transistors T2 arranged in the same column. The conductive structures RWL1 to RWL4 are arranged consecutively along the X-axis direction.

[0041] In this embodiment, each of the plurality of word lines formed by the conductive structures WWL1 to WWL4 and RWL1 to RWL4 extends along the normal direction to the plane of the substrate SUB (ie, the Z-axis direction).

[0042] Please refer to FIG. 7. FIG. 7 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 6 according to one embodiment of the present disclosure. The memory cell array 700 includes a plurality of memory cell slices 701-70n. Each of the memory cell slices 701-70n includes a memory cell array including a plurality of memory cells MC, each including a first transistor T1 and a second transistor T2. The memory cell slice 701 includes a plurality of conductive structures WWL_00-WWL_0n extending along the Z-axis to form word lines, and a plurality of conductive structures RWL_00-RWL_0n extending along the Z-axis to form word lines. The conductive structures WWL_00-WWL_0n are coupled to the control terminal of the first transistor T1, and the conductive structures RWL_00-RWL_0n are coupled to the control terminal of the second transistor T2. Similarly, memory cell slice 70n has a plurality of conductive structures WWL_n0 to WWL_nn extending along the Z-axis to form word lines, and a plurality of conductive structures RWL_n0 to RWL_nn extending along the Z-axis to form word lines. Conductive structures WWL_n0 to WWL_nn are coupled to the control terminal of first transistor T1, and conductive structures RWL_n0 to RWL_nn are coupled to the control terminal of second transistor T2.

[0043] The bit lines WBL_00 to WBL_nn and the conductive structures RWL_00 to RWL_nn for forming the word lines extend along the X-axis direction and can be cross-connected among the memory cell slices 701 to 70n. The bit lines WBL_00 to WBL_nn are coupled to a first transistor T1, and the conductive structures RWL_00 to RWL_nn are coupled to a second transistor T2.

[0044] Please refer to FIG. 8. FIG. 8 is a schematic three-dimensional structural diagram of a memory structure according to another embodiment of the present invention. The memory structure 800 is disposed on a plane of a substrate SUB. The plane of the substrate SUB is formed on the XY-axis plane and has the same normal direction as the Z-axis. The memory structure 800 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistors T1 are arranged in a first array having an N×M shape, and the second transistors T2 are arranged in a second array having an N×M shape. In this embodiment, N and M can both be equal to 4. In other embodiments of the present disclosure, N and M can be any other positive integers.

[0045] In the following description, the X-axis direction is the row direction, and the Z-axis direction is the column direction. The structures of the first transistor T1 and the second transistor T2 in this embodiment are similar to those in the embodiments of FIGS. 1, 4, and 6. It is noteworthy that in this embodiment, each of the multiple bit lines WBL1 to WBL4 coupled to the first transistor T1 extends along the Z-axis and is coupled to multiple channel pillars 810 arranged in the same row. The bit lines WBL1 to WBL4 are arranged continuously along the X-axis direction. Each of the conductive structures WWL1 to WWL4 extends along the X-axis direction and surrounds multiple channel pillars 810 in the same column to form a common gate for the multiple first transistors T1 arranged in the same row. The conductive structures WWL1 to WWL4 are arranged vertically along the Z-axis direction.

[0046] Furthermore, each of the multiple bit lines RBL1 to RBL4 coupled to the second transistor T2 extends along the X-axis direction. The bit lines RBL1 to RBL4 are arranged vertically along the Z-axis direction. Each of the bit lines RBL1 to RBL4 is coupled to one end of the multiple conductive structures 820 arranged in the same row. Each of the conductive structures RWL1 to RWL4 extends along the Z-axis direction and covers and surrounds the multiple conductive structures 820 arranged in the same row, forming a word line for the multiple second transistors T2 arranged in the same column. The conductive structures RWL1 to RWL4 are arranged consecutively along the X-axis direction.

[0047] In this embodiment, each of the word lines formed by the bit lines WBL1 to WBL4 and the conductive structures RWL1 to RWL4 extends along the normal direction to the plane of the substrate SUB (ie, the Z-axis direction).

[0048] Please refer to FIG. 9. FIG. 9 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 8 according to one embodiment of the disclosure. The memory cell array 900 includes a plurality of memory cell slices 901-90n. Each of the memory cell slices 901-90n includes a memory cell array including a plurality of memory cells MC, each including a first transistor T1 and a second transistor T2. The memory cell slice 901 includes a plurality of bit lines WBL1_00-WBL_0n extending along the Z-axis and a plurality of conductive structures RWL_00-RWL_0n extending along the Z-axis to form word lines. The bit lines WBL1_00-WBL_0n are coupled to the first transistor T1, and the conductive structures RWL_00-RWL_0n are coupled to the control end of the second transistor T2. Similarly, memory cell slice 90n has a plurality of bit lines WBL1_n0 to WBL_nn extending along the Z-axis and a plurality of conductive structures RWL_n0 to RWL_nn extending along the Z-axis to form word lines. The bit lines WBL1_n0 to WBL_nn are coupled to a control terminal of a first transistor T1, and the conductive structures RWL_n0 to RWL_nn are coupled to a control terminal of a second transistor T2.

[0049] The bit lines RBL_00 to RBL_nn and the conductive structures WWL_00 to WWL_nn for forming the word lines extend along the X-axis direction and can be cross-connected between the memory cell slices 901 to 90n. The bit lines RBL_00 to RBL_nn are coupled to the second transistor T2, and the conductive structures WWL_00 to WWL_nn are coupled to the first transistor T1.

[0050] In summary, the memory structure according to the present disclosure forms a memory cell using two transistors. This eliminates the need for a storage capacitor for each memory cell, effectively saving circuit area. Furthermore, the memory structure according to the present disclosure has word lines or bit lines arranged vertically. In the manufacturing process, the vertically arranged word lines or bit lines do not need to be defined layer by layer, and the process for the vertically arranged word lines or bit lines can be completed with a single etching, effectively reducing process complexity and manufacturing costs. [Industrial Applicability]

[0051] The memory structure and control method of the present invention can be applied to a DRAM device without providing a storage capacitor, thereby saving circuit area. [Explanation of symbols]

[0052] 100: Memory Structure 110, 410, 610, 810: Channel pillar 120, 420, 620, 820, RWL1~RWL4, WWL1~WWL4, RWL, WWL, WWL_00~WWL_nn, RWL_00~RWL_nn: Conductive structure CH: Channel RBL1~RBL4, WBL1~WBL4, WBL, RBL, WBL_00~WBL_nn, RBL_00~RBL_nn: bit lines SUB: Subtraction SN: Data Storage Node T1: first transistor T2: second transistor 300, 500, 700, 900: Memory cell array 301~30n, 501~50n, 701~70n, 901~90n: Memory cell slices MC: Memory cell X, Y, Z: Axes

Claims

1. a plurality of first transistors arranged in a first array, first ends of the first transistors coupled to a plurality of first bit lines, respectively, and gates of the first transistors coupled to a plurality of first word lines, respectively; a plurality of second transistors arranged in a second array, the gates of the second transistors being respectively coupled to second ends of the first transistors, the second ends of the second transistors being respectively coupled to a plurality of second bit lines, and the first ends of the second transistors being respectively coupled to a plurality of second word lines; Equipped with the first transistors and the second transistors are disposed on a substrate, one of each of the first word lines and each of the first bit lines extends along a normal direction to a plane of the substrate, and one of each of the second word lines and each of the second bit lines extends along the normal direction; The first array comprises: N×M channel pillars (N and M are positive integers); M first conductive structures; each of the first conductive structures surrounds N channel pillars, and each of the first conductive structures forms a common gate and each of the first word lines of the first transistors corresponding to the N channel pillars; The second array comprises: N×M gate structures each formed by extending a portion of the N×M channel pillars; N×M second conductive structures surrounding the N×M gate structures, respectively; M third conductive structures; wherein each of the third conductive structures overlies N of the second conductive structures, and the third conductive structures respectively form the second word lines.

2. 2. The memory structure of claim 1, wherein the extension directions of each of the first word lines and each of the first bit lines are substantially perpendicular to each other, and the extension directions of each of the second word lines and each of the second bit lines are substantially perpendicular to each other.

3. The memory structure of claim 1 , wherein each of the first bit lines is coupled to a first end of a corresponding one of the channel pillars.

4. 2. The memory structure of claim 1, wherein each of said second bit lines is coupled to a second end of a corresponding one of said gate structures.

5. 5. The memory structure of claim 4, wherein a channel of each of said second transistors is formed over each of said second conductive structures between each of said third conductive structures and each of said second bit lines.

6. 10. The memory structure of claim 1, wherein each of the gate structures and each of the corresponding channel pillars are identical structures.

7. 2. The memory structure of claim 1, wherein the extension directions of each of the first word lines and each of the second word lines are substantially the same, and the extension directions of each of the first bit lines and each of the second bit lines are substantially the same.

8. The second array comprises: N×M gate structures each having a plurality of first ends coupled to a corresponding first end of the N×M channel pillars; N×M second conductive structures each surrounding the gate structure; N third conductive structures; each of the third conductive structures surrounds M of the second conductive structures; 2. The memory structure of claim 1, wherein said third conductive structures respectively form said second word lines.

9. 9. The memory structure of claim 8, wherein the extension directions of each of the first word lines and each of the second word lines are substantially perpendicular to each other, and the extension directions of each of the first bit lines and each of the second bit lines are substantially perpendicular to each other.

10. 2. The memory structure of claim 1, wherein the coupled end of each of the first transistors and each of the second transistors is a data storage node.

11. 11. The memory structure of claim 10, wherein in a write mode, each of the first transistors is turned on and write data received by the first end of each of the transistors is written to the corresponding data storage node.

12. 11. The memory structure of claim 10, wherein in a read mode, each of the second transistors is turned on or off according to data stored in a corresponding one of the data storage nodes, and the second end of each of the transistors is configured to provide read data.

13. 2. The memory structure of claim 1, wherein each of said first transistors is a gate-all-around (GAA) transistor and each of said second transistors is a channel-all-around (CAA) transistor.

14. disposing a plurality of first transistors arranged in a first array, first ends of the first transistors respectively coupled to a plurality of first bit lines and gates of the first transistors respectively coupled to a plurality of first word lines; In the first array, N×M channel pillars (N and M are positive integers) are arranged; disposing M first conductive structures; each of the first conductive structures surrounds N channel pillars, and each of the first conductive structures forms a common gate and each of the first word lines of the first transistors corresponding to the N channel pillars; arranging a plurality of second transistors arranged in a second array, wherein gates of the second transistors are respectively coupled to second ends of the first transistors, second ends of the second transistors are respectively coupled to a plurality of second bit lines, and first ends of the second transistors are respectively coupled to a plurality of second word lines; In the second array, disposing N×M gate structures each formed by extending a portion of the N×M channel pillars; disposing N×M second conductive structures surrounding the N×M gate structures, respectively; disposing M third conductive structures; each of the third conductive structures overlies N of the second conductive structures, and the third conductive structures respectively form the second word lines; extending one of each of the first word lines and each of the first bit lines along a direction normal to a plane of a substrate to provide a first signal; extending one of each of the second word lines and each of the second bit lines along a direction normal to a plane of the substrate to provide a second signal; A method for controlling a memory device, comprising:

15. each of the first word lines provides a first word line signal that is the first signal; each of the second word lines provides a second word line signal that is the second signal; each of the first bit lines provides a first bit line signal that is the first signal; 15. The control method of claim 14, wherein each of the second bit lines provides a second bit line signal that is the second signal.

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