A method for tuning threshold voltage via selective deposition of high-K metal gate (HKMG) film stacks

Abstract

A method for microfabrication of three-dimensional transistor stacks with gate-all-around field-effect transistor devices is disclosed. Channels extend between source / drain regions. Each channel is selectively deposited, with layers of material designed to tune the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials, and metallization. The three-dimensional transistor stack forms an array of high-threshold voltage and low-threshold voltage devices within a single package.

Description

[Technical Field]

[0001] This application claims priority to U.S. Provisional Application No. 62 / 872,943, filed July 11, 2019, entitled "Method for Tuning Threshold Voltage via Selective Deposition of High-K Metal Gate (HKMG) Film Stacks," which is incorporated herein by reference in its entirety.

[0002] This application relates to microelectronic devices having semiconductor devices, transistors, and integrated circuits, including microfabrication methods for tuning the threshold voltage (Vt) of transistors through selective deposition processes. [Background technology]

[0003] The fabrication of semiconductor devices (especially at a microscopic scale) requires the execution of various fabrication processes, such as film deposition, etch mask formation, patterning, material etching and removal, and doping. These processes are performed repeatedly to form the desired semiconductor device elements on a substrate. Historically, microfabrication has involved the formation of transistors on one side and the formation of wiring / metallization above the active device surface, thus characterizing it as two-dimensional (2D) circuits or 2D processing. While scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, scaling efforts still face greater challenges as scaling enters single-digit nanometer semiconductor device processing nodes. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits, in which transistors are stacked on top of each other.

[0004] 3D integration, i.e., the vertical stacking of multiple devices, aims to overcome the scaling limitations experienced by planar devices by increasing transistor density in volume rather than area. While device stacking has been successfully demonstrated and implemented by the flash memory industry where 3D nanotechnology has been adopted, its application to random logic designs is substantially more challenging.

[0005] A threshold voltage (Vt) is the minimum voltage required to activate a transistor in a CMOS (complementary metal-oxide semiconductor) device. As CMOS devices shrink, the number of different threshold voltages used within a given design increases. Using different threshold voltages allows designers to optimize specific portions of the chip to operate at higher performance or, if desired, lower power. Conventional devices fabricated on the conventional Foundry N5 technology node can incorporate up to five different threshold voltages, but this requires significant complexity in the chip manufacturing process.

[0006] Threshold voltages (Vt) can be "tuned" or shaped using several different approaches. One approach is to use channel doping to achieve different threshold voltages. As devices scale down in size and channel width, approaching 50 Å in advanced FINFET devices and channel heights in nanowire / nanosheet devices, channel doping is no longer a viable option for Vt tuning, given the significant degradation in mobility due to the doped channel coupled with smaller dimensions. At such small channel dimensions, a single dopant atom can adversely affect device performance. Furthermore, dopant variations within the channel are extremely difficult to statistically control, and these variations on an atomic scale can significantly affect the device's threshold voltage. Therefore, the application of channel doping can result in multiple Vt tuning "flavors" or values, which are undesirable in the corresponding devices.

[0007] Another approach to Vt tuning in CMOS devices is via work function metal (WFM) stack engineering, for example, by adding multiple metal stack films surrounding the channel or by increasing the thickness of the work function metal stack. Because the work function of a WFM stack is highly dependent on the thickness variation within each film in the work function metal stack, complex integration processes using etch stop layers (ESLs) and atomic layer deposition (ALO) of work function metals (WFMs), multiple masking steps using expensive lithography operations, and wet etching have been developed to add controlled variations in the work function metal stack and control the threshold voltage. While this approach has become the primary approach for threshold voltage tuning at advanced technology nodes, it has increased integration and fabrication complexity in an attempt to achieve multiple threshold voltage requirements. Summary of the Invention [Problem to be solved by the invention]

[0008] It is therefore an object of the present disclosure to provide methods and systems capable of tuning threshold voltage (Vt) through selective deposition processes that can be employed across FINFET, nanowire / nanosheet, complementary FET, and vertical FET devices. [Means for solving the problem]

[0009] In an aspect of the present disclosure, a method for tuning the threshold voltage (Vt) of a transistor via a selective deposition process is described.

[0010] In one embodiment, a microfabrication method is disclosed. A substrate having channels for a gate-all-around field-effect transistor device is used. The channels have a vertical stack of channels arranged adjacent to each other, with each channel extending horizontally between source / drain regions. In the vertical stack of channels, at least one channel is arranged above a second channel. The channels have at least four designated channel types, including a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel.

[0011] In one embodiment, a first high-k dielectric is selectively deposited around the entire periphery of the uncovered channels, including the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel. A first work function metal is selectively deposited on the high-voltage NMOS channel and the low-voltage NMOS channel, while leaving the high-voltage PMOS channel and the low-voltage PMOS channel covered. A second work function metal is selectively deposited on the high-voltage PMOS channel and the low-voltage PMOS channel, while leaving the high-voltage NMOS channel and the low-voltage NMOS channel covered. A third work function metal is selectively deposited on the high-voltage PMOS channel and the high-voltage NMOS channel, while leaving the low-voltage PMOS channel and the low-voltage NMOS channel covered. After depositing the work function metal, a conductive metal material is deposited on the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel.

[0012] In another embodiment, a method for microfabrication of vertical stacks of nanochannels is disclosed, each vertical stack having a different voltage threshold.

[0013] In another embodiment, a three-dimensional transistor stack is disclosed, the three-dimensional transistor stack comprising: a substrate having channels of a gate-all-around field effect transistor device, the channels having a vertical stack of channels disposed adjacent to one another, each channel extending horizontally between source / drain regions, and in each vertical stack of channels, at least one channel being disposed above a second channel; a first vertical stack of high-voltage NMOS channels, each channel surrounded by a first high-k dielectric, a first work function metal, a third work function metal, and a conductive metal material; a second vertical stack of low-voltage NMOS channels, each channel surrounded by a first high-k dielectric, a first work function metal, and a conductive metal material; a third vertical stack of high-voltage PMOS channels, each channel surrounded by a first high-k dielectric, a second work function metal, a third work function metal, and a conductive metal material; a fourth vertical stack of low-voltage PMOS channels, each channel surrounded by a first high-k dielectric, a second work function metal, and a conductive metal material; a capping material on the conductive metal material; an input gate contact connected to a conductive metal material; It has.

[0014] For clarity, different steps are presented herein. Generally, these steps can be performed in any suitable order. Also, although different features, techniques, configurations, etc. described herein may each be described in different parts of this disclosure, it is intended that each concept may be practiced independently of one another or in combination with one another. Thus, the present invention can be realized and visualized in many different ways.

[0015] The foregoing general description and the following detailed description of example embodiments are merely exemplary aspects of the teachings of the present disclosure and are not intended to be limiting.

[0016] A more complete understanding of the present invention and many of the attendant advantages thereof will be readily obtained by reference to the following detailed description considered in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0017] [Figure 1] Cross-sections through the common gate after nanosheet release for high and low threshold voltage conditions. [Figure 2] FIG. 1 shows the growth of an interfacial silicon oxide layer around a silicon nanosheet channel. [Figure 3] FIG. 1 shows atomic layer deposition of high-k films on top of an interfacial layer of silicon nanosheets. [Figure 4] FIG. 1 shows an isotropically deposited TiN cap on top of a high-k film. [Figure 5] FIG. 10 illustrates isotropic deposition of a TaN etch stop layer over the top of a TiN cap film. [Figure 6] FIG. 1 illustrates isotropic deposition of TiN work function metal across NMOS and PMOS gates. [Figure 7] FIG. 10 illustrates patterning of filler material. [Figure 8] FIG. 10 illustrates wet etch removal of TiN work function metal from open portions of the Vt mask. [Figure 9] FIG. 10 shows TiN work function metal remaining only in the high threshold voltage PMOS gate. [Figure 10] FIG. 1 shows isotropic deposition of TaN over both the NMOS and PMOS gates. [Figure 11] FIG. 1 illustrates patterning of fill material. [Figure 12] FIG. 10 shows wet etching of a TaN etch stop layer selective to a TiN cap on top of a high-k film for low threshold voltage NMOS and PMOS gates. [Figure 13] FIG. 10 illustrates the removal of fill material exposing the remaining TaN layer for the high threshold voltage NMOS and PMOS gates. [Figure 14] FIG. 1 illustrates isotropic deposition of NMOS work function metal over the top of NMOS and PMOS gates. [Figure 15] FIG. 1 illustrates patterning of fill material. [Figure 16] FIG. 10 illustrates wet etching of NMOS work function metal from a low threshold voltage PMOS gate. [Figure 17] FIG. 10 illustrates the removal of the spin-on carbon pattern fill layer, showing the NMOS work function metal removed from the low threshold voltage PMOS gate while remaining on the other gates. [Figure 18] FIG. 10 illustrates the isotropic deposition of liner material prior to the deposition of highly conductive metal fill to complete the HKMG stack. [Figure 19] FIG. 10 illustrates the filling of highly conductive metallic material to complete the HKMG structure. [Figure 20] FIG. 10 shows recessing of HKMG metal in the gate, formation of a SiN cap, and formation of an input gate contact to the common gate. [Figure 21] Cross-sections through the common gate after nanosheet release for the high threshold voltage condition (left) and the low threshold voltage condition (right). [Figure 22] FIG. 10 illustrates selective deposition of high-k dielectric directly on exposed nanosheets or nanowires in replacement gate trenches. [Figure 23] FIG. 1 illustrates selective deposition of a TiN cap over the top of a high-k film. [Figure 24] FIG. 1 illustrates patterning of fill material. [Figure 25] FIG. 1 illustrates selective deposition of NMOS work function metal over both high and low threshold voltage conditions. [Figure 26] FIG. 10 shows the device after the filler has been removed. [Figure 27] FIG. 10 shows the TiN capping metal for PMOS patterning the fill material to keep the NMOS gate effectively "blocked" while keeping the gate open. [Figure 28] FIG. 1 illustrates selective deposition of PMOS work function metals over both high and low threshold voltage conditions. [Figure 29] FIG. 10 illustrates the removal of filler material. [Figure 30] FIG. 1 illustrates patterning of fill material. [Figure 31] FIG. 10 illustrates selective deposition of additional NMOS work function metal across both NMOS high threshold voltage conditions. [Figure 32] FIG. 10 illustrates the removal of filler material. [Figure 33] FIG. 10 illustrates the isotropic deposition of liner material prior to the deposition of highly conductive metal fill to complete the HKMG stack. [Figure 34] FIG. 10 illustrates the filling of highly conductive metallic material to complete the HKMG structure. [Figure 35] FIG. 10 illustrates recessing of HKMG metal in the gate, formation of a SiN cap, and then formation of an input gate contact to the common gate. DETAILED DESCRIPTION OF THE INVENTION

[0018] In the drawings, the same reference numerals designate the same or corresponding parts throughout the several views. Furthermore, as used herein, the terms "a," "an," and the like generally have the meaning of "one or more," unless otherwise specified. The drawings are generally drawn to scale or illustrate schematic structures or flow charts unless otherwise specified.

[0019] Additionally, the terms "generally," "about," "approximately," and similar terms generally refer to ranges that include the stated value within a margin of 20%, 10%, or preferably 5%, and any value therebetween.

[0020] Aspects of the present disclosure relate to methods for microfabrication of vertical stacks of nanochannels, each with a different voltage threshold, resulting in a three-dimensional transistor stack with channels having different voltage thresholds.

[0021] A multi-gate MOSFET refers to a metal-oxide-semiconductor field-effect transistor in which two or more gates are incorporated into a single device. The multiple gates may be controlled by a single gate electrode, and the multiple gate surfaces may function electrically as a single gate or may be controlled by independent gate electrodes.

[0022] A FinFET (fin field-effect transistor) is a type of non-planar, or "2D," transistor. A FinFET is a variation of the traditional MOSFET, distinguished by the presence of a thin silicon "fin" inversion channel on top of a substrate, allowing two contact points to be made to the gate, one on the left side and one on the right side of the fin. The thickness of the fin (measured in the source-to-drain direction) defines the effective channel length of the device. The wraparound gate structure provides better electrical control over the channel, suppressing leakage current and overcoming other short-channel effects.

[0023] A gate-all-around (GAA) FET, or GAAFET for short, is conceptually similar to a FinFET, except that the gate material surrounds the channel region on all sides. Depending on the design, a gate-all-around FET can have two or four effective gates. A gate-all-around FET can utilize a stack of silicon nanowires, which the gate completely surrounds.

[0024] The gate-all-around assembly resembles a MOSFET, with the gate sandwiched between the source and drain, and has fins similar to those of a FinFET. However, unlike a conventional FinFET, the fins are arranged vertically, and the FinFET is rotated on its side in a gate-all-around configuration.

[0025] A gate-all-around FET may incorporate three or more nanowires. The nanowire that forms the channel is suspended and extends from the source to the drain. A high-k / metal gate structure, which controls the current flow, fills the gap between the source and drain.

[0026] A typical high-k metal gate (HKMG) integration process for FinFET CMOS devices is (a) removing polysilicon or amorphous silicon in the replacement gate via a wet etching process; (b) removing the chemical oxide protecting the FIN structure in the replacement gate; (c) forming an interfacial silicon oxide layer on the cleaned FIN, the interfacial oxide having a thickness in the range of 8-12 Å for the core logic section for current state-of-the-art devices and exceeding 12 Å for high voltage portions of the chip, such as the I / O region; (d) depositing a high-k (HK) dielectric material, such as hafnium oxide (HfO), over the interfacial layer via an atomic layer deposition process, where the thickness of the high-k film can vary from 10 A to 20 A in the core logic section; (e) depositing a titanium nitride (TiN) capping layer on the HK film via atomic layer deposition or conformal chemical vapor deposition (CVD); (f) depositing an etch stop layer such as tantalum nitride (TaN) via atomic layer deposition or conformal CVD deposition; (g) depositing polysilicon or amorphous silicon on the replacement gate via a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process; (h) High temperature annealing to improve the reliability of the HK film; (i) Removal of polysilicon or amorphous silicon fill from the replacement gate; (j) deposition of a p-type work function metal across both the NMOS and PMOS gates via atomic layer deposition or conformal CVD, where conventional p-type work function metals include TiN; (k) blocking the NMOS and PMOS gates with a fill material such as spin-on carbon (SOC); (i) patterning a "blocking" mask, which opens only the NMOS portion of the replacement gate while blocking the PMOS portion; (m) Once the NMOS portion of the replacement gate is opened and the SOC material is etched away from within only the NMOS portion of the replacement gate, the TiN is wet etched and the underlying TaN etch stop layer (ESL) prevents any removal of the TiN cap deposited over the top of the HK. If necessary, a second wet etch is used to selectively remove the TaN without etching the underlying TiN. (n) then removing the SOC from the PMOS portion of the replacement gate, freeing both the NMOS and PMOS portions; (o) then depositing an n-type work function metal, such as TiAl, TiAlN, or TiAlC, over both the NMOS and PMOS gates using atomic layer deposition or conformal CVD; (p) Next, a liner material such as TiN or TaN is deposited within both the NMOS and PMOS gates via atomic layer deposition or conformal CVD to provide good barrier and adhesion for subsequent deposition of a highly conductive filler metal such as tungsten, cobalt, ruthenium, or aluminum, or an aluminum co-alloy. The barrier layer is then placed within the replacement gate trench, and the metal and barrier film are removed using wet etching, opening the replacement gate trench with a topology-patterned mask. Patterned masks cannot be used for atomic layer deposition of the work function and barrier metal processes because the deposition process itself is isotropic, depositing along the channel and into the sidewalls of the replacement gate, as well as along the topology-blocking mask, making it difficult to remove the blocking mask pattern without removing the deposition around the intended channel. Incorporating the topology-blocking mask pattern into the wet etching process provides selectivity to the subtractive metal etching process, allowing the desired film to be removed without interfering with the pattern-blocking mask.

[0027] This approach to threshold voltage tuning presents challenges when multiple threshold voltages are required. In the previous example, there was a single threshold voltage for NMOS and PMOS. If there are two different threshold voltages for NMOS and PMOS, process integration becomes more extensive when using work function metal stacks and thicknesses for tuning. An NMOS device with a low threshold voltage requirement looks similar to the NMOS from the previous example. In this case, an n-type work function metal is deposited directly on top of a TiN cap covering the HK film. For high threshold voltage requirements for NMOS, the work function metal stack can include a TaN barrier layer, which is not wet etched during the Vt tuning step. For PMOS low-voltage conditions, the work function metal stack looks similar to the previous example, where TaN is deposited on a TiN cap covering HK, followed by the deposition of work function metal titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or aluminum-doped titanium carbide (TiAlC) on top of the TiN. For high-threshold voltage PMOS work function metal stacks, the TaN barrier layer may not yet be removed, some kind of continuous TiN-on-TiN deposition without any TaN ESL, or multiple sets of TaN / TiN depositions from integration, which also have a final n-type work function metal deposited over the top. Adding a single special threshold voltage condition to both NMOS and PMOS drives the increase in etch stop layer deposition steps, lithographic "block" patterning processes, and many additional wet etching steps to remove unwanted films from the low threshold voltage condition. The integration process is optimized, reducing the associated blocking and etching steps that are eliminated. However, this comes at the expense of adding a lot of additional metal to the high Vt work function metal stack, especially the PMOS gate.

[0028] The following figures show the integration of two threshold voltage conditions, NMOS and PMOS. Each step sequence shows two separate sequences, which are parallel to each other, with the left sequence showing high threshold voltage integration and the right sequence showing low threshold voltage integration. In both sequences, the high-k metal gate (HKMG) shown is a common gate, with the PMOS gate on the left side of each individual image and the NMOS gate on the right side of each individual image.

[0029] Figure 1 shows a cross section taken at a plane through the common gate of a gate-all-around transistor block following nanosheet release for high threshold voltage condition 110 and low threshold voltage condition 120. The common gate is processed to have a high-voltage PMOS stack (114), a high-voltage NMOS stack (116), a low-voltage PMOS stack, and a low-voltage NMOS stack. The stacks have vertical stacks of adjacent channels (e.g., 112a, 112b, and 112c of stack 114), each extending horizontally between the source / drain regions. In the vertical stack, at least one channel (e.g., 112c) is positioned on top of a second channel (112b). The final processed stack has at least four designated channel types, including a high-voltage PMOS channel 114, a high-voltage NMOS channel 116, a low-voltage PMOS channel 124, and a low-voltage NMOS channel 126.

[0030] Figure 2 shows an interfacial silicon oxide layer (one shown as 230) grown on the outer surface of each silicon nanosheet channel. Reference numeral 232 represents the lower silicon block, which is the unetched portion of the gate structure. Each channel stack is separated from adjacent channel stacks by a dielectric material, which is not shown for clarity.

[0031] Figure 3 shows atomic layer deposition of a high-k film 334 over the interfacial layer of silicon nanosheets. The high-k deposition of hafnium oxide is done via atomic layer deposition so that the deposit covers the sidewalls and bottom of the replacement gate trench with a thickness comparable to that of the deposition around the nanosheets. Deposition of optional dipole-forming materials, such as aluminum or hafnium oxide, is done in-situ or as a secondary deposition after the high-k film.

[0032] 4 shows the isotropic deposition of a TiN cap 435 over the high-k film 334, after which a subsequent annealing step is performed.

[0033] 5 shows the isotropic deposition of a TaN etch stop layer 536 over the TiN cap film 435. This is used to prevent removal of the TiN cap film during subsequent metal removal for threshold voltage adjustment, with additional TiN used as the work function metal.

[0034] FIG. 6 shows the isotropic deposition of TiN work function metal 638 across the NMOS and PMOS gates.

[0035] 7 shows the patterning of a fill material 740 such as spin-on carbon (SOC). The high threshold voltage PMOS gate 714 is effectively "blocked" while the TiN work function metal of the low threshold voltage PMOS 724 and all NMOS gates (716, 726) is removed and opened by wet etching.

[0036] 8 shows the device after wet etch removal of the TiN work function metal 638 from the open portions of the Vt mask. The TaN layer 536 is an etch stop layer that prevents removal of the TiN cap 435 over the top of the high-k film 334. Alternatively, after this step, the wet etch may then be modified to focus on removing TaN 536 selectively to TiN 435, in order to remove the etch stop layer as a means of reducing the overall HKMG stack thickness. However, in this integration scheme, the TaN stop layer is maintained as a means of reducing the number of Vt adjustment masks applied in subsequent integration flows.

[0037] 9 shows the high voltage PMOS gate 914 with the SOC fill material 740 removed, thus showing that the TiN work function metal 638 remains only within the high threshold voltage PMOS gate 914 and has been stripped elsewhere.

[0038] Figure 10 shows the isotropic deposition of TaN1044 over the top of both the NMOS and PMOS gates. An etch stop layer is provided to protect the TiN work function metal of the high threshold voltage PMOS gate. Note that the deposition on the NMOS and low threshold voltage PMOS gates effectively enhances the amount of TaN deposited on these gates. Also, note that since these are isotropic depositions by atomic layer deposition or conformal chemical vapor deposition, the deposition along the sidewalls and bottom of the replacement gate trench mirror is deposited on the actual channel.

[0039] 11 shows the selective patterning of a fill material such as spin-on carbon 1146. The high threshold voltage PMOS 1114 and NMOS 1116 gates are effectively "blocked." The low threshold voltage PMOS 1124 and NMOS 1126 gates are opened by removing the TaN etch stop metal 1044 via a wet etch.

[0040] FIG. 12 shows the wet etch of the TaN etch stop layer 1044 selective to the TiN cap 435 over the high-k film 334 for the low threshold voltage PMOS 1224 and NMOS 1226 gates.

[0041] 13 shows the removal of fill material 1146, revealing the TiN work function material 638 for the high threshold voltage PMOS gate 1314 and the remaining TaN 1044 for the high threshold voltage NMOS gate 1316.

[0042] FIG. 14 shows the isotropic deposition of NMOS work function metal 1448 (TiAlN is shown as an example) over the top of the NMOS and PMOS gates.

[0043] 15 shows the patterning of a fill material such as spin-on carbon (SOC) 1550. This effectively maintains a "block" of the high threshold voltage PMOS 1514 and NMOS 1516 gates, as well as the low threshold voltage NMOS 1526. The low threshold voltage PMOS gate 1524 is opened up for the NMOS work function metal 1448 (assumed here to be TiAlN), which is removed via wet etching.

[0044] FIG. 16 shows the wet etching of the work function metal 1448 (assumed to be TiAlN in this case) from the low threshold voltage PMOS gate 1624 .

[0045] 17 shows the removal of the spin-on carbon patterned fill layer 1650. The NMOS work function metal 1448 (assumed here to be TiAlN) is shown removed from the low threshold voltage PMOS gate 1724, exposing the TaN layer 536 while leaving behind the low threshold NMOS gate 1726 and both the high threshold voltage NMOS 1716 and PMOS 1714 gates.

[0046] Figure 18 shows the isotropic deposition of a liner material 1852 before the highly conductive metal fill is deposited to complete the HKMG stack. The liner is deposited on the trench sidewalls and around the nanowire channel. The liner is extremely thin (on the order of 1 nm) and does not appreciably increase the thickness of the trench walls and floor. Typically, TiN or TaN is used as the liner material when a highly conductive fill material such as tungsten or cobalt is used. Ruthenium may also be used as the highly conductive fill material, in which case a liner material is not required. However, ruthenium tends to be a p-type metal, which requires extensive physical simulations.

[0047] Figure 19 shows the filling of a highly conductive (HC) metal material 1954 (assumed tungsten in this example) to complete the HKMG structure. The highly conductive metal material fills all open spaces within the transistor (gate), thus filling the sides of the trench and nanowire. Note that for lateral nanosheets in the high threshold voltage regime, the work function metal begins to integrate between adjacent nanosheets and the floor of the replacement gate trench. The design used conservative estimates for the liner / stop layer / work function thickness, with a final vertical separation of 15 nm between stacked nanosheets, but in reality, the margins are worse.

[0048] Figure 20 shows the recessing of the HKMG metal stack in the gate, the formation of a SiN cap 2056, and then the formation of an input gate contact 2058 to the common gate. The two stacks on the left represent the case of a high threshold voltage for PMOS 2014 and NMOS 2016. The two stacks on the right represent the case of a low threshold voltage for PMOS 2024 and NMOS 2026. It is noted that the nanowires (212 a,b,c, Figure 2) in the high voltage PMOS stack 2014 may coalesce with each other and the bottom wall may damage the high voltage stack.

[0049] The integration flow of the following steps has several additional steps for a simple NMOS / PMOS work function metal stack formation: (a) removing polysilicon or amorphous silicon via a wet etching process in the replacement gate; (b) removing the chemical oxide protecting the FIN structure in the replacement gate; (c) forming an interfacial silicon oxide layer over the FIN, where for current devices in the core logic section, the interfacial oxide has a thickness of about 8-12 Å, and in high voltage parts of the chip, such as the input / output (I / O) section, it has a thickness greater than 12 Å; and (d) depositing a high-k (HK) dielectric material, such as HfO, over the interfacial layer via an atomic layer deposition process, where the thickness of the high-k film varies between 10 Å and 20 Å in the core logic section. (e) deposition of a TiN capping layer over the HK film via atomic layer deposition or conformal CVD deposition; (f) deposition of an etch stop layer such as TaN via atomic layer deposition or conformal CVD deposition; (g) deposition of polysilicon or amorphous silicon on the replacement gate via a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process; (h) high temperature anneal to improve the reliability of the HK film; (i) removal of the polysilicon or amorphous silicon fill from the replacement gate; and (j) deposition of a p-type work function metal across both the NMOS and PMOS gates via atomic layer deposition or conformal CVD.

[0050] A common such p-type work function metal is TiN; (k) blocking the NMOS and PMOS gates with a fill material such as spin-on carbon (SOC); (l) patterning a "blocking" mask, leaving the low Vt portion of the PMOS blocked, while opening the NMOS-only portion and the high Vt PMOS portion of the replacement gate (an additional step); (m) once the NMOS portion and the low Vt PMOS portion of the replacement gate are open (an additional step), the TiN is wet etched, and an underlying TaN etch step layer (ESL) prevents any removal of the TiN cap deposited on top of the HK; if necessary, a second wet etch is then used to selectively remove the TaN, preventing etching of the underlying TiN; (n) the SOC is then removed from the PMOS portion of the replacement gate, opening both the NMOS and PMOS portions.

[0051] Additional steps include: (n+1) then depositing a second ESL such as TaN by atomic layer deposition or conformal CVD; (n+2) blocking the high threshold voltage portions of both the NMOS and PMOS by filling with a material such as spin-on carbon (SOC) and topographically patterning the blocking mask to open only the low Vt portions of both the NMOS and PMOS; (n+3) wet-etching TaN selective to TiN in the open areas of the Vt adjustment mask. If multiple TaN films exist on top of each other, both TaN films are removed by wet etching. In areas where TaN + TiN + TaN exist, only the topmost TaN film is removed; and (n+4) removing the SOC and the topographically patterned material that blocks the high Vt portions of both the NMOS and PMOS gates.

[0052] The integration flow continues as follows: (o) an n-type work function metal such as TiAl, TiAlN, or TiAlC is then deposited across both the NMOS and PMOS gates using atomic layer deposition or conformal CVD; (p) a liner material such as TiN or TaN is then deposited within both the NMOS and PMOS gates via atomic layer deposition or conformal CVD as a means of providing a good barrier and adhesion for the subsequent deposition of a highly conductive filler metal such as tungsten, cobalt, ruthenium, aluminum, or an aluminum co-alloy.

[0053] There are some issues with threshold voltage tuning using only the work function metal stack and thickness. The thickness of the entire HKMG stack is excessive, making the integration process relatively complex, even for just two Vt conditions: NMOS and PMOS. Typically, the TaN etch stop layer must be on the order of at least 10–20 Å, and for high Vt conditions in PMOS, repeating the TiN / TaN stack adds significant thickness to the HKMG stack. A larger work function metal stack ultimately limits the fin pitch, and can indirectly limit the p / n junction and the distance between the fin and any gate cut. Because fin pitch typically works in concert with the critical metal pitch, any increase in fin pitch corresponding to a larger HKMG stack can lead to a larger standard cell size via a compensatory increase in the critical metal pitch or by adding additional tracks in the critical metal layer. Because the etch stop layer typically used has a much lower conductivity compared to the final gate fill metal, the ESL occupying a large portion of the added HKMG stack limits the amount of highly conductive fill metal that can be used, thus significantly increasing gate resistance. Conversely, another option is to reduce the number of FINs in the design, which reduces the drive current and adversely affects device performance.

[0054] A second problem with this approach is that as the number of available threshold voltages increases, additional ESL layers must be deposited. Therefore, for the highest threshold voltage conditions, there may not be adequate space between adjacent FIN structures or between the FIN and the cut structure in the gate to prevent metal merging. As more threshold voltage conditions are added, integration becomes even more complex in terms of the number of lithography block steps and etch stop layer (ESL) layers required. To address the increased number of layers associated with placing low-conductivity metals in the bulk of open transistors and their impact on gate resistance, atomic layer direct etching of work function metals must consider selectively etching specific crystallographic orientations of the work function metal with respect to the desired crystal structure. The risks of such processing arise from thickness variations, especially when transitioning from FINFETs to nanosheet devices. In nanosheet devices, this etch must be highly isotropic, often requiring the ability to etch the bottom of nanosheets that are significantly wider than the top and sides to control threshold voltage.

[0055] This problem is not isolated to FINFET devices but also occurs in nanowires and nanosheets, as well as in complementary FET devices where transistors are stacked on top of each other in a common-gate fashion, where NMOS and PMOS coexist within the same common gate, or in a split-gate or stacked-transistor fashion, where the NMOS and PMOS gates overlap each other but are separated by a dielectric film. In the case of nanowire and nanosheet processes, the concern is not fin-to-fin merging of metals within a workfunction metal stack, but rather vertical merging from one nanowire or nanosheet to another. Whether in FINFETs or nanowires / nanosheets, once any merging of a particular metal film between two adjacent channels occurs, or if the available spacing between adjacent channels is significantly reduced, subsequent deposition of the next metal in the stack is inhibited from being deposited over the top of the channel.

[0056] U.S. Patent Publication No. 2019 / 0172828, entitled "Semiconductor Device Having a Stacked Gate and Method for Manufacturing the Same," which is incorporated herein by reference in its entirety, describes a technique in which a work function metal stack is deposited via atomic layer selective deposition or CVD selective deposition, exposing a channel material. The channel material is either silicon, silicon germanium (SiGe), or germanium. An interfacial silicon oxide layer is then formed at the interface between the channel material and the high-k selectively deposited film. This process is then repeated, and another metal-containing film is then selectively deposited over the top of the surface of another metal-containing film or conductive material. These additional selectively deposited films include dipole forming species for high-k films such as hafnium oxide or aluminum oxide, capping materials for high-k films such as TiN, work function metals such as TiN, TiON, TiAl, TiAlN, TiC and TiAlC, etch stop layers such as TaN, and liner materials such as TiN and TaN to aid in the filling of highly conductive fill metals such as aluminum, tungsten, cobalt or ruthenium.

[0057] Self-assembled monolayers (SAMs) are one-molecule-thick layers of material that bond to a surface in an ordered manner as a result of physical or chemical forces during the deposition process. Silanes can form SAMs through solution or vapor-phase deposition processes. Most commonly, chlorosilanes or alkoxysilanes are used. Once deposition occurs, chemical (oxane or Si-OM) bonds are formed at the surface, resulting in permanent modification of the substrate.

[0058] In one aspect of the present disclosure, a self-assembled monolayer (SAM) is selectively attached to a dielectric film (e.g., a low-k spacer) to form the outer boundary of a conventional replacement gate after the polysilicon or amorphous silicon is extracted from the replacement gate. The use of the self-assembled monolayer prevents deposition along the sidewalls of the open replacement gate trench, allowing a metal oxide high-k film, such as hafnium oxide, to be selectively deposited around the channel material.

[0059] The application of selective deposition offers several advantages and features. The process provides a mechanism for forming "split gate" complementary FET (CFET) devices. In this architecture, the NMOS and PMOS devices within the complementary device are aligned opposite each other and stacked laterally or vertically on top of each other, as is done in conventional CMOS devices. Selective deposition of liner, barrier, etch stop, and work function metal deposition along the sidewalls of the replacement gate trench, along the channel alone, results in reduced gate resistance. This "freed" or removed metal volume is then occupied with a highly conductive metal, such as tungsten, aluminum, cobalt, or ruthenium. Features include reduced contact poly pitch (CPP), or gate pitch, because the work function metal, liner, barrier, or etch stop layer is deposited at the interface between the replacement gate inner sidewall and the gate-channel terminal within the gate structure. Selective deposition allows for a smaller gate length (Lg), thereby enabling a reduction in the physical replacement gate size. Advantages include reduced FET capacitance, selective deposition of a dielectric-on-dielectric of a low-k material such as silicon oxide, SiOCH, SiCN, SiOCN, or SiOC is performed on the sidewalls of the replacement gate trench, which allows for an increase in the size of the gate spacer without changing the size of the physical gate, or can be combined with a selective conductor-on-conductor deposition process without changing the actual gate length (Lg). A more detailed description of these techniques can be found in the references.

[0060] Aspects of the present disclosure include processes in which the threshold voltage (Vt) of the channel is tuned through selective deposition processes. Such processes can be employed across FINFET, nanowire / nanosheet, complementary FET, and vertical FET devices. Both nanowires and nanosheets can be A "nanochannel" can be considered a gate-all-around channel, i.e., a channel with a gate stack surrounding the entire cross section of the channel. The channel cross section can be circular, square, rectangular, with rounded ends, etc. Although the embodiments use nanosheet devices as the implementation method, this is non-limiting and can be applied to additional device architectures and designs, as well as any nanochannel.

[0061] Embodiments include semiconductor device manufacturing and integration processes.

[0062] In one embodiment, the threshold voltage of current CMOS devices is controlled via a high-k metal gate (HKMG) stack for each intended threshold voltage requirement of the PMOS and NMOS transistors. In current devices, channel doping dependence is undesirable as the size of the channel decreases. The HKMG stack can include several components or layers. These layers include: (a) an interfacial oxide layer, (b) a high-k dielectric film with an in-situ dipole-forming material, (c) a capping layer, (d) a separate dipole-forming layer on the high-k dielectric, (e) an etch stop layer, (e) NMOS and PMOS work function metals, (f) a liner material, and (g) a highly conductive metal fill.

[0063] In another embodiment, thickness variation is achieved by both adjusting the thickness of the work function metal and incorporating a metal stack containing a specific thickness of work function metal by introducing a second metal on top (the latter approach is commonly used to set a higher threshold voltage for PMOS transistors).

[0064] The thickness variation itself can cause large threshold voltage shifts, so the traditional way to set a specific work function thickness for threshold voltage tuning is via an "additive and subtractive" process, where the work function is deposited via atomic layer deposition or a highly controlled chemical vapor deposition process, then some type of etch stop layer is deposited, another metal layer is deposited on top of the etch stop layer, and the second metal film is removed at a threshold voltage condition lower than the intended value.

[0065] However, aspects of the present disclosure integrate selective deposition atomic layer deposition or selective deposition chemical vapor deposition processes in an "additive" manner, where a set work function metal thickness can be applied across all threshold voltage conditions, and additional work function metal can be deposited at higher threshold voltage conditions via a common lithography block process, and therefore an etch stop layer is not required.

[0066] Furthermore, selective deposition methods for threshold voltage tuning allow a significant number of different threshold voltages to be incorporated into CMOS designs, even at current dimensions. This can be achieved through the selective deposition process described herein, or by forming a block mask to open each NMOS and PMOS, one at a time, to a threshold voltage condition, and growing part or the entire HKMG stack at a time on a single processing tool for each threshold voltage condition. Once one threshold voltage "HKMG stack" is completed, the lithographic blocking material is removed, and then the process is repeated, patterning a new block mask to open the next threshold voltage condition.

[0067] The elimination of the etch stop layer in the additive and subtractive method for threshold voltage tuning described herein has several advantages and features. Low-conductivity films from the HKMG stack can be replaced with highly conductive metal fillers, such as tungsten, aluminum, cobalt, or ruthenium. This reduces the total number of films required to line the periphery of the gate channel. For device performance, it is desirable to pack the nanowires / nanosheets as closely together as possible. However, this relatively dense packing is often limited by the number of metal films that line the periphery of the channel. As a result, at some point, metal from a densely packed deposition begins to coalesce with two adjacent overlapping nanowires / nanosheets, affecting transistor performance. Therefore, the addition of multiple threshold voltages is significantly limited by such an "additive and subtractive" approach. Higher threshold voltages require the inclusion of multiple etch stop layers within the stack. While it is possible to employ a subsequent etch stop layer removal step, such as a selective wet etch in conventional processes, the additional removal step adds further process complexity and requires careful confirmation that this selectivity does not etch either the capping or the work function metal in the process.

[0068] Another advantage is a way to reduce the overall thickness of the HKMG stack while increasing the number of available threshold voltages. This allows for a smaller lateral pitch of the nanowires and nanosheets, providing significant benefits to transistor performance. Another advantage is a way to reduce the likelihood of metal coalescence before the final highly conductive metal fills at high threshold voltages. This provides better electrostatic control of the individual channels.

[0069] Another aspect of the present disclosure provides an integrated process that reduces the total number of lithographic masking steps used. A common work function thickness for low and high threshold voltages can be deposited at once, and then additional selective deposition can be performed by opening up different threshold voltage conditions. Therefore, selective deposition can be "additive" only. By enabling the PMOS threshold voltage to be achieved through the addition of NMOS work function material over the top of the NMOS work function metal, additional lithographic masking steps can be minimized. The following figure shows how the elimination of the subtractive etch step leads to significant step sequence savings.

[0070] The step sequence savings arise by bypassing existing "additive and subtractive" methodologies that employ depositions performed in atomic layer deposition or chemical vapor deposition tools for the work function metal, etch stop layer deposition, and second work function metal deposition, followed by removal from the corresponding tools and transfer to a wet etch tool to remove the second work function metal from the lower threshold voltage condition, where this sequence is repeated for each increasing number of threshold voltage conditions. In the selective deposition process of the present disclosure, all depositions within a common threshold voltage range can be performed sequentially in the same deposition tool.

[0071] Because the work function thickness can be controlled very precisely in selective deposition processes, with atomic layer deposition (ALD)-like precision, this method of setting the threshold voltage not only significantly increases the number of available threshold voltages that can be used while keeping the thickness of the HKMG stack around the channel constant or even smaller, but also provides finer increments of threshold voltage now possible within a design.

[0072] The described features and advantages are based on the threshold voltage conditions of two NMOS and two PMOS. Therefore, the advantages of the present technique are amplified when the threshold voltage conditions for the NMOS and PMOS exceed two. Therefore, multiple threshold voltages can be realized for each of the NMOS and PMOS. The application of threshold voltage conditions can be applied to a single stack of channels, two stacks of channels, three stacks of channels, or four stacks of channels, such as the high-voltage PMOS and NMOS channels and the low-voltage PMOS and NMOS channels of FIG. 1. The selective threshold voltage technique of the present disclosure is not limited to one, two, three, or four stacks of channels, but may be applied to multiple channels as needed.

[0073] An exemplary embodiment is presented below. For ease of explanation, the embodiment is a single example that keeps the overall mask count the same as the current process, but reduces the thickness of the entire HKMG stack using selective deposition to reduce complexity. It is clear that many variations are possible with regard to target masking and deposition.

[0074] To overcome the coalescence thickness problem, selective deposition is used to bypass some of the etch stop layer. For ease of explanation, the embodiment is a single example that keeps the overall mask count the same as in current processes, as previously described, but demonstrates the reduced complexity and overall HKMG stack thickness achieved using the selective deposition method of the present disclosure. Clearly, many variations in the subject masking and deposition are possible.

[0075] Figure 21 shows cross-sectional views through the common gates after nanosheet release for the high threshold voltage condition 2110 and the low threshold voltage condition 2120. Each common gate consists of a PMOS gate (2114, 2124) on the left and an NMOS stack (2116, 2126) on the right.

[0076] Figure 22 shows the selective deposition of a high-k dielectric 2232 (assumed to be hafnium oxide in this case) directly on top of exposed nanosheets or nanowires in a replacement gate trench. An interfacial silicon oxide layer is grown at the interface between the hafnium oxide and the nanowire / nanosheet structure, and the high-k film can be doped in-situ with dipole-forming species.

[0077] Figure 23 shows the selective deposition of a TiN cap 2334 over the high-k film, followed by an anneal. Because all threshold voltage tuning is done via selective deposition, as opposed to the "additive and then subtractive" process typically used for high-end devices, etch stop layers such as low-conductivity TaN, which occupy a significant volume of the entire HKMG stack, are no longer necessary. By removing these low-conductivity films, significant improvements in overall gate resistance are achieved, especially for CFET devices where gates are stacked on top of each other and must share a common gate contact connection to M1.

[0078] Figure 24 shows the patterning of a fill material, such as spin-on carbon 2440 (SOC), which effectively keeps the PMOS gate (for both high and low threshold conditions) "blocked" and opens up the TiN capping metal 2334 for the NMOS gate (for both high and low threshold conditions).

[0079] Figure 25 shows the selective deposition of NMOS work function metal 2538 across both the high and low threshold voltage conditions. SOC 2440 "blocks" the surfaces of the PMOS gates (2514, 2524), preventing deposition along these nanowires / nanosheets. In this case, a common thickness of NMOS work function metal 2538 is deposited across both threshold voltage conditions, with the intention of adding additional work function thickness to the high threshold voltage condition after the integration process. This approach minimizes the total number of threshold voltage lithography modules, which should be implemented in this process as a means of reducing overall complexity and cost. Alternatively, to achieve the desired HKMG stack deposition, each individual threshold voltage condition can be opened one at a time, then each individual Vt adjustment condition can be closed, and this process can be repeated for a large number of threshold voltage conditions. The incorporation of selective deposition capabilities for Vt adjustment may be optimized by the designer for the number of Vt "flavors" required, the overall cost, and the efficiency required by the integration flow.

[0080] FIG. 26 shows the HKMG stack after the SOC fill material 2440 has been removed.

[0081] 27 shows the patterning of a fill material 2740, such as spin-on carbon (SOC), which effectively keeps the NMOS gates (both high threshold 2716 and NMOS low threshold 2726 conditions) in a "blocked" state, while the TiN capping metal 2334 for the PMOS gates (both high threshold 2714 and PMOS low threshold 2724 conditions) is opened.

[0082] Figure 28 shows the selective deposition of PMOS work function metal 2858 across both the high 2814 and low 2824 threshold voltage conditions. SOC 2740 "blocks" the surfaces of the NMOS gates (2816, 2826), preventing any deposition along these nanowires / nanosheets. A common thickness of PMOS work function metal, preferably TiN, is deposited across both threshold voltage conditions (2814, 2824) with the intention of adding additional work function thickness to the high threshold voltage condition later in the integration process. This approach minimizes the total number of threshold voltage lithography modules, which should be implemented in this process as a means of reducing overall complexity and cost. Alternatively, to achieve the required HKMG stack deposition, each individual threshold voltage condition can be opened one at a time, then closed for each individual Vt tuning condition, and so on, for a large number of threshold voltage conditions. The incorporation of selective deposition capabilities for Vt adjustment may be optimized by the designer for the number of Vt "flavors" required, the overall cost, and the efficiency required by the integrated flow.

[0083] FIG. 29 shows the HKMG stack after the SOC fill material 2740 has been removed.

[0084] 30 shows the patterning of a fill material such as spin-on carbon 3040 (SOC). The low threshold voltage condition of both the "blocked" NMOS 3026 and PMOS 3024 is effectively maintained, while the high threshold voltage condition of both the NMOS 3016 and PMOS 3014 is opened in the replacement gate trench.

[0085] 31 shows the selective deposition of additional NMOS work function metal 3138 across the high threshold voltage regime of both the PMOS 3114 and NMOS 3116 stacks. In this way, NMOS threshold voltage tuning is easily achieved simply by the difference in work function metal thickness, while the combined stack of PMOS work function metal with the deposition of NMOS work function metal 3138 for the PMOS transistor is used to tune the threshold voltage of the PMOS gate.

[0086] FIG. 32 shows the HKMG stack after the SOC fill material 3040 has been removed.

[0087] Figure 33 shows the isotropic deposition of a liner material 3352 before depositing a highly conductive metal fill to complete the HKMG stack. Typically, when a highly conductive fill material such as tungsten or cobalt is used, TiN or TaN is used as the liner material. In this case, selective deposition of a TiN liner is not used because it is used as a "glue" layer for the subsequent metal fill; therefore, the liner must be isotropically deposited within the trench. Ruthenium can be used as a highly conductive fill material, in which case a liner material is not required. However, ruthenium tends toward p-type metals, requiring extensive physical simulation.

[0088] Figure 34 shows the filling of a highly conductive metal material 3454 (assumed tungsten in this example) to complete the HKMG structure. The highly conductive metal material fills all unoccupied areas within the trench and surrounds the nanowire channel. Note that in the case of lateral nanosheets at high threshold voltage conditions, the work function metal no longer begins to coalesce between adjacent nanosheets and the floor of the replacement gate trench, as would be the case with isotropic deposition of the HKMG stack. Thus, the ability to tune the threshold voltage via work function metal thickness tuning without the need to incorporate multiple etch stop layers allows the overall thickness of the HKMG stack surrounding the channel to be reduced. This can provide a means to constrain the lateral pitch of the nanowires / nanosheets, which can provide transistor performance benefits as well as improved electrostatic characteristics of the individual channels at high threshold voltage conditions.

[0089] 35 shows the HKMG metal filled recess in the gate, the formation of a SiN cap 3556, and then the formation of an input gate contact 3558 to the common gate. On the left side, the high threshold voltage case for PMOS 3514 (left) and NMOS 3516 (right) is shown. On the right side, the low threshold voltage case for PMOS 3524 (left) and NMOS 3526 (right) is shown.

[0090] A comparison of high voltage PMOS nanowires 2012a-c in FIG. 20 with high voltage PMOS nanowires 3512a-c in FIG. 35 shows the improved isolation of each of the nanowires according to the embodiments shown in FIGS.

[0091] 21-35, gate-all-around nanowire / nanosheet transistor stacks are provided having high-voltage PMOS and NMOS stacks and low-voltage PMOS and NMOS stacks, each with a different threshold voltage Vt.

[0092] 21 to 35 illustrate a first embodiment. The first embodiment relates to a microfabrication method, comprising: receiving a substrate having channels of a gate-all-around field-effect transistor device, the channels having vertical stacks of channels arranged adjacent to one another, each extending horizontally between source / drain regions; and in each vertical stack of channels, at least one channel is arranged above a second channel, the channels including at least four designated channel types, including a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel. The method also includes selectively depositing a first high-k dielectric around all uncovered channels, the first high-k dielectric including a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel; and depositing a first high-k dielectric over each high-voltage NMOS channel and each low-voltage PMOS channel, while leaving the high-voltage PMOS channel and the low-voltage PMOS channel covered. workselectively depositing a functional metal over each of the high-voltage PMOS channels and each of the low-voltage PMOS channels while leaving the high-voltage NMOS channel and the low-voltage NMOS channel covered; work selectively depositing a third work function metal on each of the high-voltage PMOS channel and each of the high-voltage NMOS channels while leaving the low-voltage PMOS channel and the low-voltage NMOS channel covered; and depositing a conductive metal material on the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel after depositing the first, second, and third work function metals.

[0093] The method further comprises covering a portion of the high-voltage NMOS channel and selectively depositing a second high-k dielectric on the uncovered portion of the high-voltage NMOS channel to produce different threshold voltages between the high-voltage NMOS channels, the second high-k dielectric being the same or a different material from the first high-k dielectric.

[0094] The method further comprises covering a portion of the high-voltage PMOS channel and selectively depositing a second high-k dielectric on the uncovered portion of the high-voltage PMOS channel to produce different threshold voltages between the high-voltage PMOS channels, the second high-k dielectric being the same or a different material from the first high-k dielectric.

[0095] The method further includes covering a portion of the high-voltage NMOS channel and selectively depositing a specific work function metal on the uncovered portion of the high-voltage NMOS channel to produce different threshold voltages between the high-voltage NMOS channels.

[0096] The method further includes, after depositing the first high-k dielectric, selectively depositing a first capping material over the first high-k dielectric.

[0097] The method further includes depositing the first high-k dielectric around all of the periphery of the uncovered channel, the first high-k dielectric being deposited on all sides of a cross section of the uncovered channel without depositing the first high-k dielectric on sidewalls of the replacement gate.

[0098] The method further includes forming high-voltage channels with different gate stack thicknesses, which results in different threshold voltages in the high-voltage channels.

[0099] The method further includes forming low-voltage channels with different gate stack thicknesses, which results in different threshold voltages in the low-voltage channels.

[0100] The method further includes selectively depositing a first titanium nitrite (TiN) capping material on the first high-k dielectric after depositing the first high-k dielectric.

[0101] The method further includes the steps of heat treating the vertical stack of channels after depositing the first capping material, and heat treating the vertical stack of channels after depositing the first titanium nitrite capping material.

[0102] The method further includes the steps of: patterning a fill material around all of the portions of the high-voltage NMOS channel, the fill material being spin-on carbon; and selectively depositing a first high-k dielectric on the uncovered portions of the high-voltage NMOS channel, followed by removing the fill material.

[0103] The method further includes the steps of covering the high-voltage PMOS channel and the low-voltage PMOS channel with a fill material before selectively depositing a first work function metal on each of the high-voltage NMOS channel and each of the low-voltage NMOS channel; removing the fill material by wet etching after selectively depositing the first work function metal on each of the high-voltage NMOS channel and each of the low-voltage NMOS channel; and covering the high-voltage NMOS channel and the low-voltage NMOS channel with the fill material before selectively depositing a second work function metal on each of the high-voltage PMOS channel and each of the low-voltage PMOS channel. selectively depositing a second work function metal on each of the high-voltage PMOS channels and each of the low-voltage PMOS channels, and then removing the fill material by wet etching; coating the low-voltage PMOS channels and each of the low-voltage NMOS channels with the fill material by wet etching before selectively depositing a third work function metal on each of the high-voltage PMOS channels and each of the high-voltage NMOS channels; and selectively depositing the third work function metal on each of the high-voltage PMOS channels and each of the high-voltage NMOS channels, and then removing the fill material.

[0104] The method further includes isotropically depositing a liner material over the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel before depositing the conductive metal material; selectively depositing each work function metal by one of atomic layer deposition (ALD) or chemical vapor deposition (CVD); selecting the liner material from the group consisting of tantalum nitrate (TaN) and titanium nitrate (TiN); selecting the conductive metal material from the group consisting of tungsten, cobalt, ruthenium, aluminum, and alloys of aluminum; and selecting the work function metal from the group consisting of titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium carbide (TiC), and aluminum-doped titanium carbide (TiAlC).

[0105] A second embodiment is shown in Figures 21 to 35. The second embodiment relates to a method for microfabrication of vertical stacks of nanochannels, each vertical stack having a different voltage threshold. The method includes the steps of receiving a substrate having channels of a gate-all-around field effect transistor device, the channels having vertical stacks of nanochannels arranged adjacent to one another, each nanochannel extending horizontally between source / drain regions, and in each vertical stack of channels, at least one nanochannel is arranged on top of a second nanochannel, the nanochannels including at least four designated nanochannel types including a high-voltage PMOS nanochannel, a high-voltage NMOS nanochannel, a low-voltage PMOS nanochannel, and a low-voltage NMOS nanochannel; depositing a high-k film on each nanochannel; selectively depositing a titanium nitride (TiN) cap layer on the high-k film; heat-treating the substrate; patterning a first fill material over the vertical stacks of the high-voltage PMOS nanochannel and the low-voltage PMOS nanochannel; and depositing a TiN cap layer on the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel to form an NMOS nanochannel. selectively depositing a PMOS work function metal on the TiN cap layer of the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel; selectively depositing a PMOS work function metal on the TiN cap layer of the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel; selectively depositing a PMOS work function metal on the TiN cap layer of the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel; selectively depositing a PMOS work function metal on the TiN cap layer of the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel; selectively depositing a PMOS work function metal on the TiN cap layer of the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel; selectively depositing a PMOS work function metal on the vertical stack of the PMOS low-voltage and NMOS low-voltage nanochannel; selectively depositing a PMOS work function metal on the vertical stack of the PMOS high-voltage and NMOS high-voltage nanochannel; selectively depositing a PMOS work function metal on the vertical stack of the PMOS low-voltage and NMOS low-voltage nanochannel; selectively depositing a PMOS work function metal on the vertical stack of the PMOS high-voltage and NMOS high-voltage nanochannel;The method includes filling each vertical stack with a highly conductive metal material, forming a first silicon nitride (SiN) cap over the high voltage stack and a second silicon nitride (SiN) cap over the low voltage stack, and forming a first input gate contact on the first silicon nitride cap and a second input gate contact on the second silicon nitride cap.

[0106] A second embodiment of the method comprises selectively depositing each work function metal by one of atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0107] A third embodiment is shown in Figures 21 to 35. The third embodiment relates to a three-dimensional transistor stack having a substrate with a vertical stack of channels of gate-all-around field effect transistor devices, the vertical stack of channels being arranged adjacent to each other, with the individual channels extending horizontally between source / drain regions, and in each vertical stack of channels, at least one channel being arranged on top of a second channel. The three-dimensional transistor stack also includes a first vertical stack of high-voltage NMOS channels, each channel surrounded by a first high-k dielectric, a first work function metal, a third work function metal, and a conductive metal material; a second vertical stack of low-voltage NMOS channels, each channel surrounded by a first high-k dielectric, a first work function metal, and a conductive metal material; a third vertical stack of high-voltage PMOS channels, each channel surrounded by a first high-k dielectric, a second work function metal, a third work function metal, and a conductive metal material; a fourth vertical stack of low-voltage PMOS channels, each channel surrounded by a first high-k dielectric, a second work function metal, a third work function metal, and a conductive metal material; a capping layer on top of the conductive metal material; and an input gate contact connected to the conductive metal material.

[0108] Obviously, many modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

[0109] In the foregoing description, specific details have been described, such as the particular configuration of the processing system, and the various components and processes used therein. However, it should be understood that the technology of the present application may be practiced in other embodiments that deviate from these specific details, and such details are for illustrative purposes and not limiting. The described embodiments are described with reference to the accompanying drawings. Similarly, specific symbols, materials, and configurations are set forth to provide a thorough understanding for illustrative purposes. However, embodiments may be practiced without including such specific details. Components having substantially equivalent functional configurations are represented by similar reference symbols, and therefore, any redundant description may be omitted.

[0110] To facilitate understanding of various embodiments, various techniques have been described as multiple separate operations. The order of description should not be interpreted to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order described. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0111] As used herein, "substrate" or "target substrate" refers generically to anything processed by the present invention. A substrate may include any material portion or structure, particularly of a device such as a semiconductor or other electronic device, and may be a base substrate structure, such as a semiconductor wafer, a reticle, or a layer disposed on a base substrate structure such as a thin film. Thus, a substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or unpatterned, but rather is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. While the description references a particular type of substrate, this is for illustrative purposes only.

[0112] There may be many variations in the operation of the above-described techniques that can achieve the same objectives of the present invention. Such variations are intended to be covered by the scope of the present disclosure. Accordingly, the foregoing description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are expressed in the following claims.

Claims

1. 1. A method of microfabrication, the method comprising: receiving a substrate having channels of a gate-all-around field effect transistor device, the channels having a vertical stack of channels disposed adjacent to one another, each channel extending horizontally between source / drain regions, and for each vertical stack of channels, at least one channel is disposed above a second channel, the channels having at least four designated channel types including a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel; selectively depositing a first high-k dielectric around all of the uncovered channels, including the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel; selectively depositing a first work function metal on each of the high-voltage NMOS channels and each of the low-voltage NMOS channels while leaving the high-voltage PMOS channel and the low-voltage PMOS channel covered; selectively depositing a second work function metal on each of the high-voltage PMOS channels and each of the low-voltage PMOS channels while leaving the high-voltage NMOS channel and the low-voltage NMOS channel covered; selectively depositing a third work function metal on each of the high-voltage PMOS channels and each of the high-voltage NMOS channels while leaving the low-voltage PMOS channel and the low-voltage NMOS channel covered; depositing a conductive metal material on the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel after depositing the first, second, and third work function metals; A method comprising:

2. further comprising the steps of covering a portion of the high-voltage NMOS channel and selectively depositing a second high-k dielectric on an uncovered portion of the high-voltage NMOS channel to produce different threshold voltages between the high-voltage NMOS channels; The method of claim 1 , wherein the second high-k dielectric is the same or a different material as the first high-k dielectric.

3. further comprising the steps of covering a portion of the high-voltage PMOS channel and selectively depositing a second high-k dielectric on an uncovered portion of the high-voltage PMOS channel to produce different threshold voltages within the high-voltage PMOS channel; The method of claim 2 , wherein the second high-k dielectric is the same or a different material as the first high-k dielectric.

4. 10. The method of claim 1, further comprising: covering a portion of the high-voltage NMOS channel and selectively depositing a specific work function metal on an uncovered portion of the high-voltage NMOS channel to produce different threshold voltages in the high-voltage NMOS channel.

5. 10. The method of claim 1, further comprising selectively depositing a first capping material on the first high-k dielectric after depositing the first high-k dielectric.

6. 2. The method of claim 1, wherein depositing the first high-k dielectric around an entire periphery of an uncovered channel comprises depositing the first high-k dielectric on all sides of a cross section of the uncovered channel without depositing the first high-k dielectric on sidewalls of a replacement gate.

7. 10. The method of claim 1, further comprising forming high-voltage channels with different gate stack thicknesses, thereby achieving different threshold voltages in the high-voltage channels.

8. The method of claim 1 , further comprising forming low-voltage channels with different gate stack thicknesses, thereby achieving different threshold voltages in the low-voltage channels.

9. 10. The method of claim 1, further comprising selectively depositing a first titanium nitride (TiN) capping material on the first high-k dielectric after depositing the first high-k dielectric.

10. The method of claim 5 , further comprising the step of heat treating the channel vertical stack after depositing the first capping material.

11. 10. The method of claim 9, further comprising heat treating the channel vertical stack after depositing the first titanium nitride capping material.

12. covering the portion of the high-voltage NMOS channel comprises patterning a fill material around the portion of the high-voltage NMOS channel; The method of claim 4 , wherein the fill material is spin-on carbon.

13. 13. The method of claim 12, further comprising removing the fill material after selectively depositing the first high-k dielectric on the high-voltage NMOS channel.

14. moreover, covering the high-voltage PMOS channel and the low-voltage PMOS channel with a fill material before selectively depositing the first work function metal on each of the high-voltage NMOS channel and each of the low-voltage NMOS channel, and removing the fill material by wet etching after selectively depositing the first work function metal on each of the high-voltage NMOS channel and each of the low-voltage NMOS channel; covering the high-voltage NMOS channel and the low-voltage NMOS channel with the fill material before selectively depositing the second work function metal on each of the high-voltage PMOS channel and each of the low-voltage PMOS channel, and removing the fill material by wet etching after selectively depositing the second work function metal on each of the high-voltage PMOS channel and each of the low-voltage PMOS channel; covering the low-voltage PMOS channel and the low-voltage NMOS channel with the fill material by wet etching before selectively depositing the third work function metal on each of the high-voltage PMOS channel and each of the high-voltage NMOS channel, and removing the fill material after selectively depositing the third work function metal on each of the high-voltage PMOS channel and each of the high-voltage NMOS channel; 2. The method of claim 1, comprising:

15. 10. The method of claim 1, further comprising isotropically depositing a liner material over the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel before depositing the conductive metal material.

16. 10. The method of claim 1, further comprising selectively depositing each work function metal by one of atomic layer deposition (ALD) or chemical vapor deposition (CVD).

17. moreover, selecting the liner material from the group consisting of tantalum nitride (TaN) and titanium nitride (TiN); selecting said conductive metallic material from the group consisting of tungsten, cobalt, ruthenium, aluminum, and alloys of aluminum; selecting the third work function metal from the group consisting of titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium carbide (TiC), and aluminum doped titanium carbide (TiAlC); 16. The method of claim 15, comprising:

18. 1. A method for microfabrication of vertical stacks of nanochannels, comprising: Each vertical stack has a different voltage threshold; The method comprises: receiving a substrate having channels of a gate-all-around field effect transistor device, the channels having vertical stacks of nanochannels arranged adjacent to one another, each nanochannel extending horizontally between source / drain regions, and for each vertical stack of channels, at least one nanochannel is arranged on top of a second nanochannel, the nanochannels having at least four designated nanochannel types including a high-voltage PMOS nanochannel, a high-voltage NMOS nanochannel, a low-voltage PMOS nanochannel, and a low-voltage NMOS nanochannel; depositing a high-k film over each nanochannel; selectively depositing a titanium nitride (TiN) cap layer over the high-k film; heat treating the substrate; patterning a first fill material across the vertical stack of the high-voltage PMOS nano-channel and the low-voltage PMOS nano-channel; selectively depositing an NMOS work function metal on the TiN cap layer of the high-voltage NMOS nano-channel and the low-voltage NMOS nano-channel; removing the first fill material from the vertical stack of the high-voltage PMOS nano-channel and the low-voltage PMOS nano-channel; patterning a second fill material across the vertical stack of the high-voltage NMOS nano-channel and the low-voltage NMOS nano-channel; selectively depositing a PMOS work function metal on the TiN cap layer of the high-voltage PMOS nano-channel and the low-voltage PMOS nano-channel; removing the second fill material from the vertical stack of the high-voltage NMOS nano-channel and the low-voltage NMOS nano-channel; patterning a third fill material across the vertical stack of the low-voltage PMOS nano-channel and the low-voltage NMOS nano-channel; selectively depositing an NMOS work function metal across the vertical stack of the high-voltage PMOS nano-channel and the high-voltage NMOS nano-channel; removing the third fill material from the vertical stack of the low-voltage PMOS nano-channel and the low-voltage NMOS nano-channel; filling each vertical stack with a liner material; filling each vertical stack with a highly conductive metallic material; forming a first silicon nitride (SiN) cap on the high-voltage NMOS nano-channel and a second silicon nitride (SiN) cap on the low-voltage NMOS nano-channel; forming a first input gate contact on the first silicon nitride cap and a second input gate contact on the second silicon nitride cap; A method comprising:

19. 20. The method of claim 18, further comprising selectively depositing each work function metal by one of atomic layer deposition (ALD) or chemical vapor deposition (CVD).

20. A three-dimensional transistor stack, comprising: a substrate having a vertical stack of channels of a gate-all-around field effect transistor device, the vertical stacks of channels being disposed adjacent to one another, with individual channels extending horizontally between source / drain regions, each vertical stack of channels being disposed on top of a respective lower block of substrate material and having at least one channel disposed on top of a second channel; a first vertical stack of high-voltage NMOS channels, each channel surrounded by a first high-k dielectric, a first work function metal, a third work function metal, and a first conductive metal material; a second vertical stack of low-voltage NMOS channels, each channel surrounded by the first high-k dielectric, the first work function metal, and a second conductive metal material; a third vertical stack of high-voltage PMOS channels, each channel surrounded by the first high-k dielectric, a second work function metal, a third work function metal, and a third conductive metal material; a fourth vertical stack of low-voltage PMOS channels, each channel surrounded by the first high-k dielectric, the second work function metal, and a fourth conductive metal material; a capping material on the first through fourth conductive metallic materials; an input gate contact connected to the first through fourth conductive metal materials, wherein a lower block of each of at least one of the first, second, third, and fourth vertical stacks does not include the first high-k dielectric thereon; and A three-dimensional transistor stack having:

21. The three-dimensional transistor stack of claim 20 , wherein a lower block of each of the first, second, third and fourth vertical stacks does not include the first high-k dielectric thereon.

22. The three-dimensional transistor stack of claim 20, wherein the lower block of each of at least one of the first, second, third and fourth vertical stacks does not include a work function metal at the top.

23. 22. The three-dimensional transistor stack of claim 21, wherein a lower block of each of the first, second, third and fourth vertical stacks does not include a work function metal thereon.

24. further comprising a first common gate structure; The first common gate structure comprises: all of the high-voltage NMOS channel and the high-voltage PMOS channel; and All of the low-voltage NMOS channel and the low-voltage PMOS channel 21. The three-dimensional transistor stack of claim 20, surrounding one of

25. Further, a second common gate structure is provided, The second common gate structure comprises: all of the high-voltage NMOS channel and the high-voltage PMOS channel; and All of the low-voltage NMOS channel and the low-voltage PMOS channel The three-dimensional transistor stack of claim 24 , wherein the other of the transistors is surrounded by the other of the transistors.

26. 21. The three-dimensional transistor stack of claim 20, wherein each of the first, second, third, and fourth vertical stacks has three or more channels disposed above one another and vertically aligned.

27. 21. The three-dimensional transistor stack of claim 20, wherein the first high-k dielectric is HfO.

28. 21. The three-dimensional transistor stack of claim 20, wherein at least one of the first, second, third, and fourth vertical stacks has an interfacial oxide provided between a channel and the first high-k dielectric.

29. 21. The three-dimensional transistor stack of claim 20, wherein at least one of the first, second, third, and fourth vertical stacks comprises a cap layer, the cap layer being disposed between the first high-k dielectric and a work function metal provided on the first high-k dielectric.

30. 30. The three-dimensional transistor stack of claim 29, wherein the cap layer is TiN.

31. 21. The three-dimensional transistor stack of claim 20, wherein the first work function metal is an NMOS work function metal.

32. 32. The three-dimensional transistor stack of claim 31 , wherein the NMOS work function metal comprises TiAlN.

33. 21. The three-dimensional transistor stack of claim 20, wherein the third work function metal is an NMOS work function metal.

34. 34. The three-dimensional transistor stack of claim 33, wherein the NMOS work function metal comprises TiN.

35. 21. The three-dimensional transistor stack of claim 20, wherein the second work function metal is a PMOS work function metal.

36. 36. The three-dimensional transistor stack of claim 35, wherein the PMOS work function metal comprises TiN.

37. 21. The three-dimensional transistor stack of claim 20, wherein at least one of the first, second, third, and fourth vertical stacks has a liner provided between a work function metal and a conductive metal, the liner comprising at least one of TiN and TaN.

38. 21. The three-dimensional transistor stack of claim 20, wherein at least one of the first through fourth conductive metallic materials comprises tungsten or cobalt.

39. 21. The three-dimensional transistor stack of claim 20, wherein none of the first, second, third, and fourth vertical stacks includes an etch stop layer.

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