Multi-level ferroelectric field-effect transistor devices

Abstract

The device includes a nonvolatile memory and a control system. The nonvolatile memory includes an array of nonvolatile memory cells, at least one of which includes a ferroelectric field effect transistor (FeFET) device. The FeFET device includes a gate structure including first and second source / drain regions, a ferroelectric layer, and a gate electrode disposed over the ferroelectric layer. The ferroelectric layer includes a first region adjacent to the first source / drain region and a second region adjacent to the second source / drain region. The control system is operatively coupled to the nonvolatile memory to program the FeFET device to have one of a plurality of distinct logic states. At least one of the plurality of distinct logic states corresponds to a polarization state of the FeFET device, in which the first and second regions of the ferroelectric layer have respective remnant polarizations of opposite polarities.

Description

[Technical Field]

[0001] The present disclosure generally relates to ferroelectric field effect transistor (FeFET) devices and their implementation for nonvolatile memory applications. In the field of solid-state electronics, the use of ferroelectric materials is becoming increasingly popular for various applications implementing ferroelectric devices such as FeFET devices, negative capacitance FETs, etc., as well as for low-voltage logic and nonvolatile memory applications. Ferroelectric materials are materials that have the ability to spontaneously polarize in the presence of an electric field (referred to as a coercive field) and retain a remnant polarization when unbiased. Remnant polarization refers to the positive or negative polarization charge that remains in a ferroelectric material after the external bias is removed. The stability of the remnant polarization charge in ferroelectric materials allows FeFET devices to retain their logic state even when power is removed, making them suitable candidates for nonvolatile applications. In addition, FeFET devices have fast switching, long retention, and reasonable endurance characteristics that make them suitable candidates for nonvolatile memory applications. Summary of the Invention

[0002] Embodiments of the present disclosure include multi-level FeFET devices, methods for reading and programming multi-level FeFET devices, and non-volatile memory systems implementing multi-level FeFET devices.

[0003] An exemplary embodiment includes an apparatus comprising a nonvolatile memory and a control system. The nonvolatile memory includes an array of nonvolatile memory cells, at least one of the nonvolatile memory cells comprising an FeFET device. The FeFET device comprises first and second source / drain regions disposed within an upper surface of a substrate, a ferroelectric layer disposed over the substrate, and a gate structure comprising a gate electrode disposed over the ferroelectric layer. The ferroelectric layer comprises a first region adjacent to the first source / drain region and a second region adjacent to the second source / drain region. The control system is operatively coupled to the nonvolatile memory to program the FeFET device of at least one of the nonvolatile memory cells to have one of a plurality of distinct logic states. At least one of the plurality of distinct logic states corresponds to a polarization state of the FeFET device, with the first and second regions of the ferroelectric layer having respective remanent polarizations of opposite polarities.

[0004] Other embodiments are described in the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic diagram of an FeFET device according to an exemplary embodiment of the present disclosure. [Figure 2A] FIG. 1 is a schematic diagram of a plurality of different polarization states of an FeFET device for implementing a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 2B] FIG. 1 is a schematic diagram of a plurality of different polarization states of an FeFET device for implementing a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 2C] FIG. 1 is a schematic diagram of a plurality of different polarization states of an FeFET device for implementing a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 2D]FIG. 1 is a schematic diagram of a plurality of different polarization states of an FeFET device for implementing a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 3A] FIG. 1 is a schematic diagram of a method for performing a read operation to determine the state of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 3B] FIG. 1 is a schematic diagram of a method for performing a read operation to determine the state of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 3C] FIG. 1 is a schematic diagram of a method for performing a read operation to determine the state of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 3D] FIG. 10 is a schematic diagram of a method for performing a read operation to determine the state of a multi-level FeFET device, according to another exemplary embodiment of the present disclosure. [Figure 3E] FIG. 10 is a schematic diagram of a method for performing a read operation to determine the state of a multi-level FeFET device, according to another exemplary embodiment of the present disclosure. [Figure 4A] FIG. 1 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 1 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 4C] FIG. 1 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 4D] FIG. 1 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 4E] FIG. 10 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to another exemplary embodiment of the present disclosure. [Figure 4F] FIG. 10 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to another exemplary embodiment of the present disclosure. [Figure 5A] FIG. 10 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to another exemplary embodiment of the present disclosure. [Figure 5B] FIG. 10 is a schematic diagram of a method for programming one of a plurality of different states of a multi-level FeFET device, according to another exemplary embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram of a memory device comprising non-volatile memory cells implemented using multi-level FeFET devices, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] Exemplary embodiments of the present disclosure will now be described in further detail with respect to multi-level FeFET devices, methods for reading and programming multi-level FeFET devices, and non-volatile memory systems implementing multi-level FeFET devices. It should be understood that the various layers, structures, and regions of FeFET devices shown in the accompanying drawings are schematic representations that are not drawn to scale. Additionally, for ease of illustration, one or more layers, regions, and regions of the type commonly used to form FeFET devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure.

[0007] Moreover, the same or similar reference symbols are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures are not repeated for each of the drawings. It should be understood that the terms "about" or "substantially" as used herein with respect to thickness, width, proportion, range, etc., are intended to indicate close or approximation, rather than exactness. For example, the terms "about" or "substantially" as used herein imply the existence of a small tolerance for error, such as 1% or less of the stated amount.

[0008] The term "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not to be construed as preferred or advantageous over other embodiments or designs. The word "over" as used herein to describe the orientation of a given feature relative to another feature means that the given feature may be positioned or formed "directly on" (i.e., directly adjacent to) the other feature, or that the given feature may be positioned or formed "indirectly on" the other feature, with one or more intermediate features disposed between the given feature and the other feature.

[0009] FIG. 1 is a schematic diagram of an FeFET device 100 according to an exemplary embodiment of the present disclosure. The FeFET device 100 comprises a substrate 110, a first source / drain region 112, a second source / drain region 114, and a gate structure 115. The gate structure 115 comprises an interfacial layer 120, a ferroelectric layer 130, and a gate electrode 140. The substrate 110 comprises a "channel region" disposed below the gate structure 115 between the first source / drain region 112 and the second source / drain region 114. The FeFET device 100 has a structure similar to a metal-oxide-semiconductor field-effect transistor (MOSFET) device, except that the gate stack of the FeFET device 100 comprises a ferroelectric layer 130 disposed between the gate electrode 140 and the top surface of the substrate 110. As described in further detail below, FeFET device 100 is structurally configured and programmable to allow ferroelectric layer 130 to be polarized to a plurality of different polarization states to obtain a plurality of different threshold voltages that define a multi-level FeFET device having at least four different states to store at least two bits of information.

[0010] The substrate 110 is formed from silicon or other suitable semiconductor material. The substrate 110 shown in FIG. 1 represents an active semiconductor layer of a semiconductor substrate. By way of example, the substrate 110 may be, for example, the top surface of a bulk substrate, the active semiconductor layer of a semiconductor-on-insulator (SOI) substrate, a doped well formed within the top surface of a semiconductor layer, etc. The substrate 110 may be doped to have a first conductivity type (e.g., N-type) or a second conductivity type (e.g., P-type). The first source / drain region 112 and the second source / drain region 114 are doped regions within the substrate 110 that have a conductivity type opposite that of the substrate 110. For example, for an N-type FeFET device, the substrate 110 comprises P-type conductivity, while the first source / drain region 112 and the second source / drain region 114 each have N-type conductivity (e.g., N +For a P-type FeFET device, the substrate 110 comprises N-type conductivity, while the first source / drain region 112 and the second source / drain region 114 each comprise P-type conductivity (e.g., P + doping).

[0011] For illustrative purposes, the exemplary, non-limiting embodiments of the present disclosure will be discussed in the context of an N-type FeFET device operating in enhancement mode. It should be understood that the term "source / drain region" as used herein means that a given source / drain region can be either a source region or a drain region, depending on the application or circuit configuration. For illustrative purposes, the first source / drain region 112 is labeled as a source region, and the second source / drain region 114 is labeled as a drain region. In some embodiments, the substrate 110 (i.e., body) comprises a separate "body terminal" that allows an appropriate bias voltage (e.g., ground voltage) to be applied to the substrate 110 during programming operations to write data to the FeFET device 100 and during read operations to read data from the FeFET device 100. For example, during a read operation, a voltage difference between the source and body of the FeFET device may ensure that there is zero voltage across the source / substrate junction, resulting in a threshold voltage (V T To eliminate the "body effect" which can change the MOSFET's resistance, the bias voltage applied to the substrate 110 will be the same voltage as the source region 112.

[0012] In some embodiments, the interfacial layer 120 comprises a thin layer of insulating material, including, but not limited to, a silicon oxide material (e.g., silicon dioxide), a silicon nitride material (e.g., SiN, SiON), or other suitable types of insulating material. The ferroelectric layer 130 comprises a ferroelectric material, including, but not limited to, polycrystalline alloy thin films of hafnium oxide (HfO), zirconium oxide (ZrO), hafnium-zirconium oxide (HfZrO), and other types of high-k dielectric materials (e.g., hafnium oxide doped with aluminum, silicon, or yttrium), which can be formed with a crystalline microstructure that exhibits ferroelectric properties (e.g., an orthorhombic ferroelectric phase). The interfacial layer 120 is an optional layer utilized for various purposes, such as providing a buffer layer to improve the quality of the interface between the surface of the substrate 110 and the ferroelectric layer 130, reducing the amount of charge trapping, and preventing reactions between various materials of the ferroelectric layer 130 and the substrate 110. In some non-limiting embodiments, the ferroelectric layer 130 has a thickness in a range from about 2 nanometers (nm) to about 20 nm. In some embodiments, the ferroelectric layer 130 is formed directly on the surface of the silicon substrate 110 (e.g., a highly doped Si substrate).

[0013] The gate electrode 140 may comprise a conductive material, including, but not limited to, titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tantalum nitride (TaN), tungsten (W), tungsten silicide (WSi), ruthenium (Ru), rhenium (Re), nickel (Ni), platinum (Pt), iridium (Ir), or other types of conductive materials suitable for a given application. In some embodiments, the material of the gate electrode 140 is selected to achieve a given work function that affects the coercive voltage of the ferroelectric layer 130, e.g., to improve the performance of the FeFET device 100 when used as a ferroelectric memory cell.

[0014] It should be understood that FIG. 1 is a high-level schematic diagram of a FeFET device presented for ease of illustration and discussion. The FeFET device 100 may include other elements, such as, for example, one or more insulating layers (e.g., gate sidewall spacers, gate capping layers, pre-metal dielectric (PMD) layers, etc.) encapsulating the gate structure 115, a gate contact formed in contact with the top surface of the gate electrode 140, source / drain contacts formed in contact with the first source / drain region 112 and the second source / drain region 114, a body region formed in the substrate 110, and a body contact formed in contact with the body region. In addition, the gate electrode 140 may include a multi-layer structure including a first gate electrode layer (e.g., a work function metal layer) formed on the ferroelectric layer 130 and a second gate electrode layer (e.g., a low-resistivity metal layer) formed on the first gate electrode layer. In some embodiments, the channel region of the FeFET device 100 may include a high channel doping concentration (e.g., >1E19 cm -3 The high channel doping enhances the ability to determine the logic state of the FeFET device when performing a read operation (as discussed below in conjunction with FIGS. 3A-3E) to determine the logic state of the FeFET device 100, where the FeFET device 100 is configured to operate in saturation mode (with a pinched-off inversion channel) to generate a read current that is used to determine the logic state of the FeFET device 100.

[0015] As mentioned above, the FeFET device 100 is structurally and ferroelectrically configured to allow the ferroelectric layer 130 to be polarized to multiple different polarization states to achieve a multi-level FeFET device. For example, the ferroelectric layer 130 is structurally configured to have a polycrystalline microstructure, as shown schematically in FIG. 1. In some embodiments, the polycrystalline microstructure comprises a mosaic of small crystallites (or grains) of various sizes randomly dispersed without preferred orientation (i.e., random texture and no grain direction). In some embodiments, various conditions and parameters of the fabrication process for the ferroelectric layer 130 can be selected to grow the grains (or crystallites) of the ferroelectric layer 130 with a desired alignment, resulting in a grain texture.

[0016] In some embodiments, the gate length (GL) of the gate structure 115 of the FeFET device 100 is at least twice (2X) the average grain size of the polycrystalline microstructure of the ferroelectric layer 130. It should be understood that the term "average grain size" as used herein is a well-known term in the art and refers to a parameter that can be estimated using known techniques. For example, one technique for estimating the average grain size of a given material is known as the "intercept" method. According to this method, a line of a given length (L) is drawn through a micrograph (e.g., a TEM (Transmission Electron Microscope) or STEM (Scanning Transmission Electron Microscope) microstructural image) of the crystalline structure of a given material. The number (N) of grains that the line intersects is counted. The average grain size is then determined as (L) / (N).

[0017] Further, with regard to the ferroelectric properties of the ferroelectric layer 130, in some embodiments, the ferroelectric layer 130 is formed with multiple ferroelectric domains, such as region R1 and region R2 (FIGS. 2A-2D). In the context of the exemplary embodiments described herein, the term "ferroelectric domain" refers to a region of the ferroelectric layer 130 in which a permanent, directional spontaneous polarization can be obtained by applying a coercive electric field (e.g., a coercive voltage) to that given region. As mentioned above, a ferroelectric material can be spontaneously polarized in the presence of a coercive electric field. Persistent spontaneous polarization includes the remnant polarization (or remnant polarization charge), whether positive or negative, that remains in the ferroelectric material after the coercive electric field is removed. A coercive electric field indicates the magnitude of the electric field that, when applied to a ferroelectric material, is sufficient to induce a switch from positive polarization charge to negative polarization charge and vice versa. Generally, the coercive voltage is a function of the thickness of the ferroelectric thin film multiplied by the coercive electric field value.

[0018] In some embodiments, the ferroelectric layer 130 is structurally and ferroelectrically configured (using domain engineering techniques when forming the ferroelectric layer 130) to include at least two ferroelectric domains: a first ferroelectric domain disposed in a region of the ferroelectric layer 130 adjacent to the first source / drain region 112 (e.g., region R1), and a second ferroelectric domain disposed in a region of the ferroelectric layer 130 adjacent to the second source / drain region 114 (e.g., region R2). Through domain engineering, various regions (or ferroelectric domains) can be formed with desired sizes. In some embodiments, the ferroelectric domains of the ferroelectric layer 130 have the same or substantially the same spontaneous polarization due to the coercive field. In this regard, the polarization states of the ferroelectric domains in various regions of the ferroelectric layer 130 can be controlled by the same (or substantially the same) coercive voltage. In other embodiments, ferroelectric layer 130 is formed to have many ferroelectric domains that arise naturally, for example, from different grains or groups of grains in the polycrystalline microstructure of ferroelectric layer 130 .

[0019] Moreover, in some embodiments, the first source / drain region 112 and the second source / drain region 114 are formed to have a target amount of overlap with the gate structure 115 such that the channel length (CL) of the channel region between the inner edge of the first source / drain region 112 and the inner edge of the second source / drain region 114 is less than the gate length (GL). The amount of overlap between the gate structure 115 and the first and second source / drain regions 112, 114 should allow a sufficient amount of electric field strength to exist between the gate structure 115 and the first and second source / drain regions 112, 114 to program polarization polarities in different regions R1 and R2 of the ferroelectric layer 130 in response to programming voltages applied to the gate electrode 140 and the first and second source / drain regions 112, 114 during a programming operation (as discussed below) for writing data (e.g., two bits of data) to the FeFET device 100.

[0020] For example, in some embodiments, the amount of overlap between the gate structure 115 and each of the first and second source / drain regions 112, 114 is on the order of at least one average grain size of the ferroelectric layer 130. In other embodiments, the amount of overlap between the gate structure 115 and each of the first and second source / drain regions 112, 114 can be less than the average grain size of the ferroelectric layer 130, in situations where the sum of the electric fields, including fringing electrical fields between the inner edges of the first and second source / drain regions 112, 114 and the gate structure 115, is sufficient to program the polarization in the various regions R1 and R2 of the ferroelectric layer 130.

[0021] In other embodiments, there is no overlap between the gate structure 115 and the first and second source / drain regions 112, 114. More specifically, in some embodiments, the inner edges of the first and second source / drain regions 112, 114 are substantially aligned with the sidewalls of the gate structure 115, resulting in a gate length (GL) that is the same as or substantially the same as the channel length (CL). The FeFET device 100 can have such a "non-overlapping" structural configuration in situations where a fringing electric field between the first source / drain region 112 and the first region R1 of the ferroelectric layer 130 is sufficient to switch (and thereby program) the polarization polarity in the first region R1, and where a fringing electric field between the second source / drain region 114 and the second region R2 of the ferroelectric layer 130 is sufficient to switch (and thereby program) the polarization polarity in the second region R2. In this regard, it should be understood that the term "adjacent" as used in the context of the relative positions of the first and second source / drain regions 112, 114 and the gate structure 115 should be interpreted broadly to include overlapping and non-overlapping structural configurations.

[0022] Further, with regard to the ferroelectric properties of the ferroelectric layer 130, in some embodiments, the ferroelectric layer 130 is formed to have multiple ferroelectric domains, such as region R1 and region R2 (FIGS. 2A-2D). In the context of the exemplary embodiments described herein, the term "ferroelectric domain" refers to a region of the ferroelectric layer 130 in which a permanent, directional spontaneous polarization can be obtained by applying a coercive electric field (e.g., a coercive voltage) to that given region. As mentioned above, a ferroelectric material can be spontaneously polarized in the presence of a coercive electric field. Persistent spontaneous polarization includes the remnant polarization (or remnant polarization charge), whether positive or negative, that remains in the ferroelectric material after the coercive field is removed. A coercive field indicates the magnitude of the electric field that, when applied to a ferroelectric material, is sufficient to induce a switch from positive polarization charge to negative polarization charge and vice versa. Generally, the coercive voltage is a function of the thickness of the ferroelectric thin film multiplied by the coercive field value.

[0023] In some embodiments, the ferroelectric layer 130 is structurally and ferroelectrically configured to include at least two ferroelectric domains, where a first ferroelectric domain is disposed in a region of the ferroelectric layer 130 adjacent to the source region 112 (e.g., region R1) and a second ferroelectric domain is disposed in a region of the ferroelectric layer 130 adjacent to the drain region 114 (e.g., region R2). In some embodiments, the ferroelectric domains of the ferroelectric layer 130 have the same or substantially the same spontaneous polarization due to the coercive field. In this regard, the polarization states of the ferroelectric domains in various regions of the ferroelectric layer 130 can be controlled by the same (or substantially the same) coercive voltage.

[0024] 2A, 2B, 2C, and 2D schematically illustrate multiple different polarization states of a FeFET device for implementing a multi-level FeFET device, according to exemplary embodiments of the present disclosure. In particular, FIGS. 2A-2D schematically illustrate multiple different polarization states (200-1, 200-2, 200-3, 200-4) of the ferroelectric layer 130 of the FeFET device 100 of FIG. 1, each corresponding to a different threshold voltage of the FeFET device 100 for implementing a multi-level FeFET device. In some embodiments, the FeFET device 100 is structurally and electrically configured to have at least four different polarization states corresponding to at least four different threshold voltages, thereby obtaining at least four binary logic states (e.g., storing at least two bits of information) encoded into the different threshold voltages of the FeFET device 100. In the exemplary embodiments of FIGS. 2A, 2B, 2C, and 2D, the FeFET device 100 is assumed to include an N-type FeFET. The threshold voltage V T is the minimum gate-source voltage (V) required to create a conductive path (inversion channel) in the channel region between the source region 112 and the drain region 114. GS ) is shown.

[0025] More specifically, FIG. 2A schematically illustrates a first polarization state 200-1 in which all regions R1 and R2 (e.g., ferroelectric domains) of the ferroelectric layer 130 have a remanent polarization having a "first polarity" (e.g., a net negative ferroelectric polarization), where the electric dipoles across the ferroelectric layer 130 are oriented such that the positive pole is directed toward the gate electrode 140 and the negative pole is directed toward the channel region of the substrate 110. The first polarization state 200-1 illustrated in FIG. 2A presents a net negative charge to the top surface of the substrate 110 in the channel region, thereby causing positive (majority) charge carriers from the substrate 110 to accumulate at the surface of the substrate 110 in the channel region. The net effect of the first polarization state 200-1 is an increase in the threshold voltage of the FeFET device 100, resulting in the FeFET device 100 reaching a first threshold voltage V T In some embodiments, the first threshold voltage V of the FeFET device 100 T1 represents the binary logic state of (0,0).

[0026] Next, FIG. 2B schematically illustrates a second polarization state 200-2 in which all regions R1 and R2 of the ferroelectric layer 130 have a remanent polarization with a "second polarity" (e.g., a net positive ferroelectric polarization), where the electric dipoles across the ferroelectric layer 130 are oriented such that the negative pole is directed toward the gate electrode 140 and the positive pole is directed toward the channel region of the substrate 110. The second polarization state 200-2 shown in FIG. 2B presents a net positive charge to the top surface of the substrate 110 in the channel region, thereby causing negative (minority) charge carriers from the substrate 110 to accumulate at the surface of the substrate 110 in the channel region (and inverting the channel region). This results in the formation of an N-type inversion channel in the top surface of the P-type substrate 110 in the channel region, which exists during equilibrium conditions (when no gate, drain, or source voltages are applied to the FeFET device 100). The net effect of the second polarization state 200-2 is that the threshold voltage of the FeFET device 100 is increased (relative to the first threshold voltage V T 1), resulting in a reduction of V T 1>V T 2, the FeFET device 100 has a second threshold voltage V T In some embodiments, the second threshold voltage V of the FeFET device 100 T 2 represents the binary logic state of (1,1).

[0027] 2C next schematically illustrates a third polarization state 200-3 (e.g., a partial polarization state) in which a first region R1 of the ferroelectric layer 130 (adjacent the source region 112) has a remnant polarization with a first polarity (net negative ferroelectric polarization) and a second region R2 of the ferroelectric layer 130 (adjacent the drain region 114) has a remnant polarization with a second polarity (net positive ferroelectric polarization). In this exemplary embodiment, the negative ferroelectric polarization in the first region R1 of the ferroelectric layer 130 presents a net negative charge to the portion of the channel region adjacent to the source region 112, thereby causing positive (majority) charge carriers from the substrate 110 to accumulate at the surface of the substrate 110 in the portion of the channel region adjacent to the source region 112 and aligned with the first region R1. In addition, the positive ferroelectric polarization in the second region R2 of the ferroelectric layer 130 presents a net positive charge to the portion of the channel region adjacent to the drain region 114, thereby causing negative (minority) charge carriers to accumulate at the surface of the substrate 110 in the portion of the channel region adjacent to the drain region 114 and aligned with the second region R2.

[0028] The net effect of the third polarization state 200-3 is that regions R1 and R2 each have a different threshold voltage V T _R1 and V T _R2, and V T _R1 is V T 1 and V T _R2 is V T 2. In this case, the net effect of the third polarization state 200-3 is that the FeFET device 100 has a different threshold voltage V T _R1 and V T The "effective" third threshold voltage V due to the variation in charge distribution along the channel region caused by R2 T 3. As will be explained in more detail below, the "effective" third threshold voltage V T3 is primarily based on the polarization polarity (first polarity) in the first region R1, which is aligned with the pinched-off inversion channel 150-3 created when the FeFET device 100 is operated in saturation mode to read out the state of the FeFET device 100. In this case, the third polarization state 200-3 results in the threshold voltage of the FeFET device 100 being lower than the first threshold voltage V T 1), resulting in a reduction of V T 1>V T 3>V T 2, the effective third threshold voltage V T 3 is V T 1 and V T 2. In some embodiments, the effective third threshold voltage V of the FeFET device 100 T 3 represents the binary logic state of (0,1).

[0029] 2D next schematically illustrates a fourth polarization state 200-4 (e.g., a partial polarization state) in which a first region R1 of the ferroelectric layer 130 (adjacent the source region 112) has a remnant polarization having a second polarity (net positive ferroelectric polarization) and a second region R2 of the ferroelectric layer 130 (adjacent the drain region 114) has a remnant polarization having a first polarity (net negative ferroelectric polarization). In this exemplary embodiment, the positive ferroelectric polarization in the first region R1 of the ferroelectric layer 130 presents a net positive charge to the portion of the channel region adjacent to the source region 112, thereby causing negative (minority) charge carriers from the substrate 110 to accumulate at the surface of the substrate 110 in the portion of the channel region adjacent to the source region 112 and aligned with the first region R1. In addition, the negative ferroelectric polarization in the second region R2 of the ferroelectric layer 130 presents a net negative charge to the portion of the channel region adjacent to the drain region 114, thereby causing positive (majority) charge carriers to accumulate at the surface of the substrate 110 in the portion of the channel region adjacent to the drain region 114 and aligned with the second region R2.

[0030] The net effect of the fourth polarization state 200-4 is that regions R1 and R2 each have a different threshold voltage V T _R1 and VT _R2, and V T _R1 is V T 2 and V T _R2 is V T 1. In this case, the net effect of the fourth polarization state 200-4 is that the FeFET device 100 has a different threshold voltage V T _R1 and V T The "effective" fourth threshold voltage V due to the variation in charge distribution along the channel region caused by R2 T 4. As will be explained in more detail below, an "effective" fourth threshold voltage V T 4 is primarily based on the polarization polarity (second polarity) in the first region R1, which is aligned with the pinched-off inversion channel 150-4 created when the FeFET device 100 is operated in saturation mode to read out the state of the FeFET device 100. In this case, the fourth polarization state 200-4 results in the threshold voltage of the FeFET device 100 being lower than the first threshold voltage V T 1 and the effective third threshold voltage V T 3) and as a result, V T 1>V T 3>V T 4>V T 2, the effective fourth threshold voltage V T 4 is V T 2 and V T In some embodiments, the effective fourth threshold voltage V of the FeFET device 100 has a value between 0.01 and 0.3. T 4 represents the binary logic state of (1,0).

[0031] In the exemplary embodiment of FIGS. 2A-2D, the first threshold voltage V T 1 and the second threshold voltage V T 2 defines the maximum "memory window" (MW) of the FeFET device 100 (i.e., MW = V T 1-V T 2), V T 1 represents the maximum threshold voltage, and V T2 represents the minimum threshold voltage of the FeFET device 100. The exemplary embodiment of Figures 2A and 2B shows the "fully polarized state" (or fully polarized state) of the FeFET device 100, where the entire ferroelectric layer 130 of the FeFET device 100 has a net positive or net negative polarization. On the other hand, the effective threshold voltage V T 3 and V T 4 is the threshold voltage V T 1~V T 2, so that V T 3>V T 4, and as a result, V T 1>V T 3>V T 4>V T 2. The exemplary embodiment of FIGS. 2C and 2D illustrates a "partially polarized state" (or partial polarization state) of the FeFET device 100, in which different regions R1 and R2 of the ferroelectric layer 130 of the FeFET device 100 have different net polarization polarities (e.g., net positive polarization or net negative polarization). In this regard, modulation of the threshold voltage of the FeFET device 100 is achieved by the polarity of the ferroelectric polarization distribution along the channel region. The different polarization states illustrated in FIGS. 2A-2D are obtained by performing programming operations as discussed in more detail below.

[0032] In some embodiments, the binary logic states (e.g., (0,0), (0,1), (1,0), or (1,1)) of the FeFET device 100 are determined by applying a first voltage (VG_Read) to the gate terminal, a second voltage (VD_Read) to the drain terminal, and grounding the source and substrate body terminals, resulting in a drain current (I D ) as a "read current." In some embodiments, the sensed drain current is compared to a number of different reference current levels corresponding to different polarization states of the FeFET device 100 to determine the binary logic state of the FeFET device 100 (e.g., (0,0), (0,1), (1,0), or (1,1)).

[0033] In some embodiments, a read operation is performed in which FeFET device 100 operates in a "saturation mode" where there is a "pinch-off" of the inversion channel within the channel region. For example, Figures 2A, 2B, 2C, and 2D schematically illustrate FeFET device 100 operating in a saturation mode (during a read operation) where respective "pinch-off" inversion channels 150-1, 150-2, 150-3, and 150-4 (more generally, inversion channels 150) are formed within the channel region between source region 112 and drain region 114. "Pinch-off" inversion channels 150-1, 150-2, 150-3, and 150-4 are schematically illustrated as extending from source region 112 a distance less than channel length CL, thereby creating a "pinch-off region" between the end of inversion channel 150 and drain region 114. As shown schematically in Figures 2A, 2B, 2C, and 2D, each of the "pinch-off" inversion channels 150-1, 150-2, 150-3, and 150-4 has a different size (e.g., different length), resulting in "pinch-off regions" where the channel regions have different lengths PL1, PL2, PL3, and PL4, respectively, where PL1>PL3>PL4>PL2.

[0034] Thus, when a read operation is performed, the threshold voltage V T (For example, V T 1. V T 2. V T 3, or V T 4) is modulated based at least in part on the polarization polarity of the region (e.g., region R1) of the ferroelectric layer 130 that is aligned with the "pinch-off" inversion channel 150 adjacent the source region 112. This modulation of the threshold voltage is particularly relevant to the polarization state as shown schematically in FIGS. 2C and 2D, where the polarization distribution within different regions (e.g., regions R1 and R2) of the ferroelectric layer 130 along the channel region, for example, modulates the effective threshold voltage V of the FeFET device 100 depending on the polarity of the regions (e.g., R1 and R2) of the ferroelectric layer 130 that are aligned or not aligned with the "pinch-off" inversion channel 150.T 3 and V T 4 (and therefore the level of drain current generated during a read operation in saturation mode).

[0035] For example, as shown schematically in Figures 2C and 2D, operating FeFET device 100 in saturation mode during a read operation results in each "pinch-off" inversion channel 150-3 and 150-4 being substantially aligned with or overlapping first region R1 of ferroelectric layer 130 (adjacent source region 112). In this regard, the effective third threshold voltage V of FeFET device 100 in different polarization states 200-3 and 200-4 as shown in Figures 2C and 2D may be T 3 and the effective fourth threshold voltage V T 4 (e.g., between logic states (0,1) and (1,0)) will be more pronounced (more modulated) depending on the polarization polarity of region R1 of ferroelectric layer 130 that is substantially aligned with or otherwise overlapping the respective "pinch-off" inversion channels 150-3 and 150-4, compared to the polarization polarity of second region R2 of ferroelectric layer 130 adjacent to drain region 114 that is not substantially aligned with the respective "pinch-off" inversion channels 150-3 and 150-4. When FeFET device 100 is not operated in saturation mode during a read operation, the effective third threshold voltage V of FeFET device 100 between the different polarization states 200-3 and 200-4 will be T 3 and the effective fourth threshold voltage V T The difference of 4 will be reduced (or eliminated).

[0036] For example, when FeFET device 100 is operated in the triode (linear) region during a read operation, the resulting inversion channel extends along the entire channel length (CL) of the channel region (without pinch-off), and therefore the entire inversion channel is modulated by the polarization in regions R1 and R2 of ferroelectric layer 130. In this case, despite the different polarization polarities of regions R1 and R2 as shown schematically in Figures 2C and 2D, both polarization states 200-3 and 200-4 have a similar modulation effect on the entire inversion channel, and therefore the effective threshold voltage V of FeFET device 100 for the different polarization states 200-3 and 200-4 is T 3 and V T On the other hand, as noted above, when operating FeFET device 100 in a saturation mode where pinch-off occurs, the different polarization states 200-3 and 200-4 play different roles in modulating the respective inversion channels 150-3 and 150-4, resulting in FeFET device 100 exhibiting an effective threshold voltage V for each of polarization states 200-3 and 200-4 (e.g., logic states (0,1) and (1,0)). T 3 and V T 4 exhibits greater differences and discriminability.

[0037] 3A, 3B, and 3C schematically illustrate a method for performing a read operation to determine the state of a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. In particular, FIGS. 3A-3C illustrate a method for reading data (e.g., two bits of data) from a multi-level FeFET device. In some embodiments, FIG. 3A illustrates a method for determining the polarization states and associated threshold voltages (e.g., V) shown in FIGS. 2A-2D. T 1. V T 2. V T 3, or V T3A schematically illustrates a read operation 300 performed on an N-type FeFET device 100, which may have any one of the following configurations: (1) a gate electrode 140 connected to a word line (WL), (2) a drain region 114 connected to a bit line (BL), and (3) a source region 112 connected to a source line (SL), which is connected to ground GND 302 (e.g., V=0). Additionally, although not specifically shown in FIG. 3A, it is assumed that the body terminal (or well terminal) of substrate 110 is connected to ground GND 302. Furthermore, for purposes of discussion, the drain current I in the channel region of FeFET device 100, as shown in FIG. 3A, is D (minority carriers) are assumed to flow from the source region 112 to the drain region 114 .

[0038] As mentioned above, in some embodiments, a read operation is performed by applying a first voltage VG_Read to the word line and a second voltage VD_Read to the bit line BL. The first voltage VG_Read (or gate-source / substrate voltage (V GS )) is the maximum possible threshold voltage V of FeFET device 100 being programmed to ensure that FeFET device 100 is "on" for all logic states (encoded in the threshold voltage) of FeFET device 100. T (For example, V T 1) and VG_Read. Additionally, the magnitude of the first voltage VG_Read should be less than the magnitude of the "coercive voltage" for switching the polarization state of the ferroelectric domains in the ferroelectric layer 130 of the FeFET device 100, so that the read operation does not result in a change in the logic state of the FeFET device 100.

[0039] Additionally, a second voltage VD_Read (or drain-source voltage V DS )) indicates that during a read operation, the FeFET device 100 is at all threshold voltages (e.g., V T 1. V T 2. Effective V T 3, or effective V T 4) and is dimensioned to ensure operation in saturation mode. As is known in the art, MOSFET devices operate in saturation mode with respect to V GS >V T And V DS ≧(V GS -V T ) is in a saturated mode of operation. In some embodiments, the magnitude of VD_Read is determined by the minimum threshold voltage of the FeFET device 100, e.g., V T 2 (FIG. 2B). More specifically, during a read operation, FeFET device 100 determines whether the magnitude of the second voltage VD_Read is greater than or equal to VD_Read>(VG_Read-V T 2), operates in saturation mode for all logic states. Thus, during a read operation, FeFET device 100 is configured to operate in saturation mode for all possible polarization states, or threshold voltages V T 1. V T 2. V T 3, and V T 4, operating in saturation mode.

[0040] For illustrative purposes, FIG. 3B illustrates increasing values ​​of gate-source / substrate (V GS ) Voltage (V GS =V T MOSFET drain current (I D ) vs. drain-source voltage (V DS ) are shown in graph form. GS <V T (V T =V T 1. V T 2. VT 3, or V T 4), the FeFET device 100 has a drain current I D 3B, the FeFET device 100 is in a "cut-off" or "subthreshold" mode where no current flows from the source region 112 to the drain region 114. GS >V T And V DS <V GS -V T In the linear region, an inversion channel is created in the channel region between the source region 112 and the drain region 114, where the drain current I D is V DS As further shown in FIG. 3B, the FeFET device 100 GS >V T And V DS ≧(V GS -V T ) enters the "saturation mode" or "active mode." The boundary between the linear and saturated regions is depicted in FIG. 3B by an upwardly pointing parabolic curve 312. GS The curve is V DS =(V GS -V T ) in saturation mode. GS and V T Regarding the drain current I D is V DS remains essentially constant regardless of

[0041] In the linear region, the inversion channel 150 extends the entire channel length (CL) of the channel region between the source region 112 and the drain region 114. The FeFET device 100 first enters the saturation region V DS =(V GS -V T ), the inversion channel 150 exhibits tapering and channel pinching adjacent to the drain region 114. However, VDS As increases (e.g., V DS >V GS -V T ), the length of the inversion channel 150 shortens (known as channel length modulation (CLM)), creating a "pinch-off region" between the end of the inversion channel 150 and the drain region 114, as shown schematically in FIG. 3A, where the "pinch-off region" includes a depletion region with non-inverted semiconductor material (e.g., non-inverted silicon).

[0042] The FeFET device 100 is turned on and V GS >V T , charge accumulates in and across the channel region (creating an inversion channel) due to the gate-source / substrate voltage (assuming the substrate 110 and source region 112 are connected to the same potential). DS When V is applied, the induced charge density of the inversion channel changes along the channel region. DS V DS_sat =V GS -V T When the effective gate-substrate voltage (V EFF ) is V EFF =V GS -V DS_sat =V T , which is just enough to form an inversion channel layer 150 adjacent to the drain region 114 (by initiating "pinch-off" of the inversion channel 150). DS_sat , the gate-substrate voltage near the drain region 114 increases beyond V T , resulting in the creation of a pinch-off region where an inversion channel does not form. In the pinch-off region, the gate-substrate voltage is insufficient to form an inversion layer, and therefore the pinch-off region becomes a depletion region lacking mobile minority carriers. However, minority charge carriers entering the pinch-off region from the inversion channel 150 are transported across the voltage potential (V DS) across the pinch-off region and into the drain region 114.

[0043] As noted above, the process of operating the FeFET device 100 in saturation mode during a read operation allows for greater modulation and differentiation between different threshold voltages of the FeFET device 100 based, for example, on the polarity of the remnant polarization in a region (e.g., R1) of the ferroelectric layer 130 that is substantially aligned to the shortened inversion channel 150 adjacent the source region 112. In particular, as explained above, the modulation and differentiation between threshold voltages of the FeFET device 100 is more significant in the partially polarized state of the FeFET device 100, as shown in FIGS. 2C and 2D, where the polarity of the remnant polarization in a first region R1 of the ferroelectric layer 130 adjacent the source region 112 (substantially aligned to the "pinch-off" inversion channel 150) and the polarity of the remnant polarization in a second region R2 of the ferroelectric layer 130 adjacent the drain region 114 (substantially aligned to the pinched-off region) result in an effective threshold voltage V T 3 and V T 4, which has minimal modulation effect on the effective threshold voltage V T 3 and V T 4, providing a larger modulation effect and greater differentiation between them. In other words, the polarity of the remanent polarization in the second region R2 of the ferroelectric layer 130 adjacent to the drain region 114 determines the threshold voltage V of the FeFET device 100. T While the polarity of the remanent polarization in the first region R1 of the ferroelectric layer 130 adjacent the source region 112 has some modulation effect on the threshold voltage V of the FeFET device 100 when a read operation is performed with the FeFET device 100 in saturation mode, T has a larger modulation effect than

[0044] 3C includes a table 320 illustrating operating conditions and parameters associated with performing a read operation on a multi-level FeFET device, according to an exemplary embodiment of the present disclosure. More specifically, FIG. 3C illustrates (i) different threshold voltages V that correlate with different polarization states of the FeFET device 100 as shown in FIGS. 2A-2D. T 1. V T 2. Effective V T 3, and effective V T 4, (ii) the respective threshold voltages V T 1. V T 2. Effective V T 3, and effective V T 4 correlated to different reference currents I D 1, I D 2. I D 3, and I D 4, and (iii) the respective threshold voltages V of the FeFET devices 100. T 1. V T 2. Effective V T 3, and effective V T 4. In some embodiments, the reference current I D 1, I D 2. I D 3, and I D 4 shows the different threshold voltages V when the FeFET device 100 is operated in saturation mode during a read operation with a fixed VG_Read applied to the gate / WL, a fixed VD_Read applied to the drain / BL, and the source / substrate connected to ground (0V). T 1. V T 2. Effective V T 3, and effective V T 4, the expected drain current I generated by the FeFET device 100 D Represents.

[0045] In some embodiments, during a read operation, the logic state of FeFET device 100 is determined by the drain current I generated by FeFET device 100 when operating in saturation mode. D Then, the detected drain current ID is the reference current I D 1, I D 2. I D 3, and I D 4, the sensed current I D The comparison process can be performed using known techniques, such as, for example, a current mode sense amplifier implementation, and other known methods. D is determined to be the same or similar (within a given margin) to the magnitude of a given reference current. D is a given reference current I D 1, I D 2. I D 3, or I D This is done so that it is considered to match 4.

[0046] V T 1> Effective V T 3> Effective V T 4>V T In the exemplary embodiment, the magnitude of the reference current is I D 2>I D 4>I D 3>I D The magnitudes of the different reference currents differ by 1. The magnitudes of the different reference currents are proportional to the drain current I generated during a read operation as a result of the different polarization states of FeFET device 100 (FIGS. 2A-2D) when FeFET device 100 is operated in saturation mode during a read operation. D represents the expected magnitude of the drain current I generated as a result of performing a single read operation with the FeFET device 100 in saturation mode. D 2C and 2D) to sufficiently distinguish between different partial polarization states of the FeFET device 100 (e.g., different partial polarization states 200-3 and 200-4 as shown in FIGS. 2C and 2D). T 3 and V TThere may be instances where the margin or difference between the four is insufficient (e.g., system noise, or variations in the amount of partial polarization in different regions R1 and R2 due to programming, etc.).

[0047] In such cases, in other embodiments, the partial polarization states (or binary logic states) of the FeFET device may be determined by determining the different threshold voltages (e.g., V) present within the first and second regions R1 and R2 of the multi-level FeFET device by performing two read operations in which read voltages of opposite polarity are applied to the first and second source / drain regions 112 and 114. T _R1 and V T For example, to read the partial polarization state of the FeFET device 100, the FeFET device 100 is in saturation mode and the first region R1 (threshold voltage V T The first drain current I is generated by the pinched-off inversion channel that is substantially aligned with the D A first read operation (first read polarity) is performed to sense the threshold voltage V_R1. The FeFET device 100 is in saturation mode and the second region R2 (threshold voltage V T The second drain current I is generated by the pinched-off inversion channel that is substantially aligned with the D A second read operation (second read polarity) is performed to sense the first drain current I D _R1 and the second drain current I D The magnitude of the first drain current I D When it is determined that the magnitude of R1 is smaller than the magnitude of the second drain current (I D _R1 D _R2), V T _R1>V T _R2, and it can be determined that the FeFET device 100 has a partial polarization state 200-3 as shown in FIG. 2C. On the other hand, the first drain current I D When it is determined that the magnitude of R1 is greater than the magnitude of the second drain current (I D ​_R1>I D _R2), V T _R1 <V T _R2, and it can be determined that the FeFET device 100 has a partial polarization state 200-4 as shown in FIG. 2D.

[0048] For example, Figures 3D and 3E schematically illustrate a method for performing a read operation to determine the state of a multi-level FeFET device according to another exemplary embodiment of the present disclosure. For illustrative purposes, Figures 3D and 3E schematically illustrate a method for performing a read operation to determine a third polarization 200-3 (e.g., partial polarization state) of the FeFET device shown in Figure 2C, in which a first region R1 of the ferroelectric layer 130 (adjacent to the first source / drain region 112) has a remnant polarization with a first polarity (e.g., net negative ferroelectric polarization) and a second region R2 of the ferroelectric layer 130 (adjacent to the second source / drain region 114) has a remnant polarization with a second polarity (e.g., net positive ferroelectric polarization). According to the partial polarization state 200-3, the first region R1 has a threshold voltage V corresponding to the first polarity of the remnant polarization in the first region R1. T a second region R2 having a threshold voltage V corresponding to a second polarity of the remanent polarization in the second region; T _R2, V T _R1>V T _R2.

[0049] To read the partial polarization state of the FeFET device 100, the FeFET device 100 is in saturation mode and the first region R1 (threshold voltage V T The first drain current I is generated by the pinched-off inversion channel that is substantially aligned with the D3D, in the first read configuration, the first source / drain region 112 is configured as a source region (connected to a source line SL) and the second source / drain region 114 is configured as a drain region (connected to a bit line BL), where a positive voltage VG_Read is applied to the word line WL (resulting in a positive V GS is applied between the gate electrode 140 and the first source / drain region 112), a positive voltage VD_Read is applied to the bit line BL (resulting in a positive voltage V DS is applied to the second source / drain region 114). According to the first read configuration shown in FIG. 3D, the read operation detects the threshold voltage V of the first region R1, which is aligned with the resulting pinched-off inversion channel 150-3 extending from the first source / drain region 112. T Based mainly on R1, the read current I D Generate _R1.

[0050] Next, the FeFET device 100 is in saturation mode and enters the second region R2 (threshold voltage V T The second drain current I is generated by the pinched-off inversion channel that is substantially aligned with the D A second read operation (second read polarity) is performed to sense _R2. For example, as shown in FIG. 3E, in the second read configuration, the first source / drain region 112 is configured as a drain region (connected to a source line SL) and the second source / drain region 114 is configured as a source region (connected to a bit line BL), where a positive voltage VG_Read is applied to the word line WL (resulting in a positive V GS is applied between the gate electrode 140 and the second source / drain region 114), a positive voltage VD_Read is applied to the source line SL (as a result, the positive voltage VDS is applied to the first source / drain region 112). According to the second read configuration shown in FIG. 3E, the read operation detects the threshold voltage V of the second region R2, which is aligned with the resulting pinched-off inversion channel 150-3' extending from the second source / drain region 114. T Based mainly on R2, the read current I D Generate _R2.

[0051] According to an exemplary read operation shown in FIGS. 3D and 3E, the FeFET device 100 detects the threshold voltage V T R1 is the threshold voltage V of the second region R2 T _R2, the read current I generated by the first read operation D R1 is the read current I generated by the second read operation. D _Becomes smaller than R2. I D _R1 D If R2, then V T _R1>V T _R2, and it can be determined that the FeFET device 100 has a partial polarization state 200-3 as shown in FIG. 2C.

[0052] ​It should be understood that if the first read operation (the read configuration of FIG. 3D) results in a sensed drain current corresponding to one of the reference currents defined for the partial polarization states 200-3 and 200-4 (see FIG. 3C) when the FeFET device 100 has a partial polarization state (e.g., 200-3 or 200-4) as shown in FIGS. 2C and 2D, then a dual read operation as shown in FIGS. 3D and 3E is not required. Moreover, it should be understood that when the FeFET device 100 has a full polarization state (e.g., 200-1 or 200-2) as shown in FIGS. 2A and 2B, then a dual read operation as shown in FIGS. 3D and 3E is not required. In such a situation, performing a read operation with the first configuration (e.g., FIGS. 3A and 3D) produces a drain current that is the same or substantially the same as the drain current produced by performing a second read operation with the second configuration (e.g., FIG. 3E).

[0053] In particular, for the polarization state 200-1 shown in FIG. 2A, by performing a dual read operation with different read polarities, the first threshold voltage V of the FeFET device 100, which is the same in both regions R1 and R2, can be obtained. T 1, the same (or substantially the same) sensed drain current I D Similarly, for polarization state 200-2 shown in FIG. 2B, performing a dual read operation with different read polarities results in a second threshold voltage V of FeFET device 100 that is the same in both regions R1 and R2. T 2, the same (or substantially the same) sense drain current I D2 results. In some embodiments, even if the FeFET device has a full polarization state, a dual read operation with opposite read polarities can be performed to confirm that the FeFET device 100 has a full polarization state (e.g., a (0,0) state or a (1,1) state). In such a situation, if a dual read operation is performed and the magnitudes of the first drain current and the second drain current are determined to be substantially equal, the first current and the second current are compared to reference currents corresponding to the respective logic states of the FeFET device to determine the logic state of the FeFET device 100. The FeFET device 100 has a logic state corresponding to the reference currents that are determined to be the same or substantially the same as the first drain current and the second drain current.

[0054] 4A, 4B, 4C, and 4D schematically illustrate a method for programming multiple different states of a multi-level FeFET device according to an exemplary embodiment of the present disclosure. More specifically, FIGS. 4A, 4B, 4C, and 4D schematically illustrate methods 400-1, 400-2, 400-3, and 400-4 for programming different polarization states 200-1, 200-2, 200-3, and 200-4 (as shown in FIGS. 2A-2D) of FeFET device 100 using a first programming voltage VP1, where different regions R1 and R2 of ferroelectric layer 130 can be independently programmed. FIGS. 4A-4D also illustrate a method for writing data (e.g., two bits of data) to FeFET device 100.

[0055] For example, FIG. 4A schematically illustrates an exemplary method 400-1 for programming the FeFET device 100 to have a first polarization state 200-1 (FIG. 2A). In some embodiments, the programming method 400-1 includes connecting the gate electrode 140 (or word line WL) to a ground voltage GND (e.g., V=0) and applying a first programming voltage +VP1 to both the source region 112 (or source line SL) and the drain region 114 (or bit line BL), where +VP1 has a magnitude and duration (pulse width) sufficient to change the ferroelectric polarization in all regions (e.g., R1 and R2) to a first polarity, as shown in FIG. 4A. In this method, the magnitude of the first programming voltage VP1 is equal to or greater than the coercive voltage of the ferroelectric domains (e.g., regions R1 and R2) of the ferroelectric layer 130. As noted above, regions R1 and R2 may comprise ferroelectric domains of distinct spontaneous polarizations, but in some embodiments, the ferroelectric domains are configured to have the same or substantially the same coercive field characteristics, such that the ferroelectric polarization states of both regions R1 and R2 can be switched simultaneously (i.e., in the same programming cycle) by applying +VP1 to source region 112 and drain region 114 with gate electrode 140 connected to ground voltage GND. In another embodiment, programming FeFET device 100 to have first polarization state 200-1 (FIG. 2A) can be achieved, for example, by connecting both source region 112 and drain region 114 to ground voltage GND and applying a negative programming voltage −VP1 to gate electrode 140 (or word line WL) for a given duration.

[0056] Next, FIG. 4B schematically illustrates an exemplary method 400-2 for programming the FeFET device 100 to have a second polarization state 200-2 (FIG. 2B). In some embodiments, the programming method 400-2 includes connecting both the source region 112 (or source line SL) and the drain region 114 (or bit line BL) to ground voltage GND and applying a first programming voltage +VP1 to the gate electrode 140 (or word line), where +VP1 has a magnitude and duration (pulse width) sufficient to change the ferroelectric polarization in all regions (e.g., R1 and R2) to a second polarity, as shown in FIG. 4B. In this method, the ferroelectric polarization states of both regions R1 and R2 are switched simultaneously (i.e., in the same programming cycle) by applying the first programming voltage +VP1 to the gate electrode 140 with both the source region 112 and the drain region 114 connected to ground voltage GND.

[0057] Next, FIG. 4C schematically illustrates an exemplary method 400-3 for programming the FeFET device 100 to have a third polarization state 200-3 (FIG. 2C). In particular, for illustrative purposes, FIG. 4C illustrates programming operations that can be performed to change the polarization state of the FeFET device 100 from the second polarization state 200-2 (as shown in FIGS. 2B and 4B) to the third polarization state 200-3 (FIG. 2C). In some embodiments, the programming method 400-3 includes connecting both the gate electrode 140 (or word line WL) and the drain region 114 (or bit line BL) to a ground voltage GND (e.g., V=0) and applying a first programming voltage +VP1 to the source region 112 (or source line SL) for a sufficient duration (pulse width) to switch the ferroelectric polarization in the first region R1 from the second polarity to the first polarity while leaving the remnant polarization in the second region R2 at the second polarity. According to this process, a source-gate voltage +VP1 causes a switch in ferroelectric polarity in the first region R1, while a drain-gate voltage potential of 0V is insufficient to change the ferroelectric polarity in the second region R2. In this manner, the first region R1 of the ferroelectric layer 130 can be programmed independently from the second region R2 of the ferroelectric layer 130.

[0058] Next, FIG. 4D schematically illustrates an exemplary method 400-4 for programming the FeFET device 100 to have a fourth polarization state 200-4 (FIG. 2D). In particular, for illustrative purposes, FIG. 4D illustrates programming operations that may be performed to change the polarization state of the FeFET device 100 from the second polarization state 200-2 (as shown in FIGS. 2B and 4B) to the fourth polarization state 200-4 (FIG. 2D). In some embodiments, the programming method 400-4 includes connecting both the gate electrode 140 (or word line WL) and the source region 112 (or source line SL) to a ground voltage GND (e.g., V=0) and applying a first programming voltage +VP1 to the drain region 114 (or bit line BL) for a sufficient duration (pulse width) to switch the ferroelectric polarization in the second region R2 from the second polarity to the first polarity while leaving the remnant polarization in the first region R1 at the second polarity. According to this process, a drain-gate voltage +VP1 causes a switch in the ferroelectric polarity in the second region R2, while a source-gate voltage potential of 0V is insufficient to change the ferroelectric polarity in the first region R1. In this manner, the second region R2 of the ferroelectric layer 130 can be programmed independently from the first region R1 of the ferroelectric layer 130.

[0059] In some embodiments, the programming method illustrated in FIGS. 4A-4D is implemented when the different regions R1 and R2 comprise "engineered" ferroelectric domains with distinctly different sizes. In other embodiments, the same or similar programming method of FIGS. 4A-4D can be applied when the ferroelectric layer 130 is natural and has many ferroelectric domains, where programming the polarization state of the ferroelectric layer 130 is implemented using a partial polarization switching technique. According to such a technique, the process for programming the polarization state of the ferroelectric layer 130 would include applying a sequence of one or more programming pulses of +VP1 to the source region 112 or drain region 114 with increasing programming pulse counts to incrementally increase or decrease the net polarity of polarization in a given region (e.g., R1 and R2) adjacent to the source region 112 or drain region 114.

[0060] For example, Figures 4E and 4F schematically illustrate a method for programming multiple different states of a multi-level FeFET device according to another exemplary embodiment of the present disclosure. More specifically, Figures 4E and 4F schematically illustrate an alternative embodiment for achieving additional polarization states of FeFET device 100, encoded by additional threshold voltages Vt5 and Vt6, respectively. In this embodiment, a programming scheme implementing the programming operations of Figures 4A-4F allows FeFET device 100 to be programmed to one of six different states.

[0061] In particular, FIG. 4E schematically illustrates programming process 400-5, a modification of process 400-3 of FIG. 4C, for increasing the net polarization in the first region R1′ to obtain an additional polarization state encoded by Vt5. Programming process 400-5 can be performed by applying two or more consecutive programming pulses +VP1 to source region 112, where an increasing number of programming pulses +VP1 serve to increase the partial polarization switching in the region of ferroelectric layer 130 adjacent to source region 112, thereby incrementally increasing the amount of polarization adjacent source region 112 to achieve a different polarization region R1′ that is larger than the first polarization region R1 as shown in FIG. 4C. Additionally, programming process 400-5 results in a different-sized polarization region R2′ adjacent drain region 114 that is smaller than the second polarization region R2 as shown in FIG. 4C. In some embodiments, the amplitude and / or duration of the programming pulse +VP1 applied to the source region 112 can be modulated to cause increased partial polarization switching of the ferroelectric domains in the ferroelectric layer 130 adjacent to the source region 112.

[0062] Similarly, FIG. 4F schematically illustrates programming process 400-6, a modification of process 400-4 of FIG. 4D , for increasing the net polarization in second region R2′ to obtain an additional polarization state encoded by Vt6. Programming process 400-6 can be performed by applying two or more consecutive programming pulses +VP1 to drain region 114, where an increasing number of programming pulses +VP1 serve to increase the partial polarization switching in the region of ferroelectric layer 130 adjacent to drain region 114, thereby incrementally increasing the amount of polarization in the region adjacent to drain region 114 to achieve a different polarization region R1′ that is larger than second polarization region R2 as shown in FIG. 4D . Additionally, programming process 400-6 results in a different-sized polarization region R1′ adjacent source region 112 that is smaller than first polarization region R2 as shown in FIG. 4D . In some embodiments, the amplitude and / or duration of the programming pulse +VP1 applied to the drain region 114 can be modulated to cause increased partial polarization switching of the ferroelectric domains of the ferroelectric layer 130 adjacent to the drain region 114.

[0063] In another embodiment, Figures 4E and 4F illustrate a programming method that can be used to program the partial polarization states of FeFET device 100 in a multi-level FeFET device 100 having four different states. In particular, the programming method illustrated in Figures 4E and 4F can be used to program the effective threshold voltages V of the four exemplary states of FeFET device 100 described above in conjunction with Figures 2A-2D. T 3 and V T 4 can be further differentiated to program the (0,1) and (1,0) logic states of FeFET device 100. In this case, the "sizes" of different regions R1 and R2 can be used to, for example, generate different drain currents I D 1, I D 2. I D 3, and I DThe four read currents can be adjusted to be more distinguishable from each other and more evenly spaced.

[0064] 5A and 5B schematically illustrate a method for programming different states of a multi-level FeFET device according to another exemplary embodiment of the present disclosure. More specifically, FIGS. 5A and 5B schematically illustrate methods 500-1 and 500-2 for programming different polarization states 200-3 and 200-4 (as shown in FIGS. 2C and 2D ) of FeFET device 100 using a first programming voltage VP1 and a second programming voltage VP2, where VP2 > VP1 (e.g., VP2 = 2 × VP1). The programming method of FIGS. 5A and 5B allows first and second regions R1 and R2 of ferroelectric layer 130 to be programmed simultaneously (i.e., in the same programming cycle) while having opposite polarization polarities.

[0065] For example, FIG. 5A schematically illustrates an exemplary method 500-1 for programming FeFET device 100 to have third polarization state 200-3 (FIG. 2C). In particular, for illustrative purposes, FIG. 5A illustrates programming operations that can be performed to change the polarization state of FeFET device 100 from fourth polarization state 200-4 (FIG. 2D) to third polarization state 200-3 (FIG. 2C). In some embodiments, programming method 500-1 includes connecting drain region 114 (or bit line BL) to ground voltage GND (e.g., V=0), applying a first programming voltage +VP1 to gate electrode 140 (or word line WL), and applying a second programming voltage +VP2 to source region 112 (or source line SL), where +VP1 and +VP2 are applied for a duration (pulse width) sufficient to switch the ferroelectric polarization in both regions R1 and R2. In particular, the programming method 500-1 causes the ferroelectric polarization in the first region R1 to switch from the second polarity to the first polarity and the ferroelectric polarization in the second region R2 to switch from the first polarity to the second polarity, resulting in the FeFET device 100 having a third polarization state 200-3.

[0066] 5A, a gate-drain voltage potential of +VP1 is sufficient to switch the ferroelectric polarity in the second region R2 from a first polarity to a second polarity, while a source-gate voltage [(+VP2)-(+VP1)] is sufficient to switch the ferroelectric polarity in the first region R1 from the second polarity to the first polarity. Assuming that the ferroelectric domains in both regions R1 and R2 have coercive voltages less than or equal to VP1, the second programming voltage VP2 should have a magnitude of at least 2×VP1 such that the voltage difference is VP2-VP1≧VP1.

[0067] Next, FIG. 5B schematically illustrates an exemplary method 500-2 for programming FeFET device 100 to have a fourth polarization state 200-4 (FIG. 2D). In particular, for illustrative purposes, FIG. 5B illustrates programming operations that can be performed to change the polarization state of FeFET device 100 from third polarization state 200-3 (FIG. 2C) to fourth polarization state 200-4 (FIG. 2D). In some embodiments, programming method 500-2 includes connecting source region 112 (or source line SL) to ground voltage GND (e.g., V=0), applying a first programming voltage +VP1 to gate electrode 140 (or word line WL), and applying a second programming voltage +VP2 to drain region 114 (or bit line BL), where +VP1 and +VP2 are applied for a duration (pulse width) sufficient to switch the ferroelectric polarization in both regions R1 and R2. In particular, the programming method 500-2 causes the ferroelectric polarization in the first region R1 to switch from a first polarity to a second polarity and the ferroelectric polarization in the second region R2 to switch from the second polarity to the first polarity, resulting in the FeFET device 100 having a fourth polarization state 200-4.

[0068] According to programming method 500-2 of FIG. 5B, a gate-source voltage +VP1 is sufficient to switch the ferroelectric polarity in the first region R1 from a first polarity to a second polarity, while a drain-gate voltage [(+VP2)-(+VP1)] is sufficient to switch the ferroelectric polarity in the second region R2 from the second polarity to the first polarity. Again, assuming that the ferroelectric domains in both regions R1 and R2 have the same (or substantially the same) coercive voltage (less than or equal to VP1), the second programming voltage VP2 should have a magnitude of at least 2×VP1 so that the voltage difference is VP2-VP1≧VP1. Programming methods 500-1 and 500-2 provide exemplary embodiments for enabling simultaneous switching of the polarity of the ferroelectric polarization in both regions R1 and R2 to opposite polarities when both regions R1 and R2 require polarity switching to program FeFET device 100 to have one of target polarization states 200-3 or 200-4. In other embodiments, as described above, the programming method of FIGS. 4A-4D can be used to independently program different regions R1 and R2 in two separate programming operations.

[0069] FIG. 6 schematically illustrates a memory device including nonvolatile memory cells implemented using multi-level FeFET devices, according to an exemplary embodiment of the present disclosure. More specifically, FIG. 6 schematically illustrates a memory device 600 including a memory cell array 610, row control circuitry 620, column control circuitry 630, a control signal block 640, and an address decoder 650. The memory cell array 610 includes a plurality of nonvolatile memory cells 612 arranged in an n x m array of n rows and m columns. In some embodiments, each memory cell 612 includes a one-transistor (1-T) architecture in which the FeFET device operates as both an access (select) transistor and a storage element. In some embodiments, each memory cell 612 includes a multi-level FeFET device the same as or similar to the FeFET device 100 described above, thereby enabling each memory cell 612 to store at least four different binary logic states.

[0070] The memory cell array 610 includes a plurality (n) of word lines WL1, WL2, ..., WLn (or more generally, word lines WL) extending in the row direction. Each word line WL is connected to the gate terminals of m FeFET devices of the memory cells 610 in a given row. The memory cell array 610 includes a plurality (m) of source lines SL1, SL2, ..., SLm (or more generally, source lines SL) and a plurality (m) of bit lines BL1, BL2, ..., BLm (or more generally, bit lines BL). Each column in the memory cell array 610 includes at least one source line SL and at least one bit line BL. In a given column, each source line SL is connected to the source terminals of the n FeFET devices of the memory cells 610 in the given column, and each bit line BL is connected to the drain terminals of the n FeFET devices of the memory cells 610 in the given column. 6, in some embodiments, each column has a separate control line connected to the body or well terminals of the FeFET devices in the memory cells 612 in the column, allowing the body substrates or wells of the FeFET devices in the memory cells 612 to be biased as needed during programming and read operations or during idle periods.

[0071] The row control circuit 620 includes a word line decoder circuit 622 and a word line voltage driver circuit 624. The column control circuit 630 includes a column decoder circuit 632, a bit line and source line voltage driver circuit 634, and a bit line sense amplifier circuit 636. The control block 640 includes circuitry configured to generate control signals for controlling the row control circuit 620 and the column control circuit 630. The address decoder 650 is configured to receive an external address from the host and decode the address into a physical address, which is provided to the row control circuit 620 and the column control circuit 630 to select one or more memory cells 612 for performing data access operations (e.g., read and write operations).

[0072] The row control circuit 620 is configured to control the activation / deactivation of word lines WL for performing read and write operations. More specifically, the word line decoder circuit 622 is configured to decode addresses received from the address decoder 650 and determine which word lines WL should be activated based on the decoded addresses. The word line voltage driver circuit 624 is configured to generate voltage signals (e.g., voltage pulses) for driving the word lines WL during read and write operations. For example, in some embodiments, the word line voltage driver circuit 624 is configured to (i) generate a first voltage VG_Read when performing read operations (e.g., FIGS. 3A-3E), (ii) generate programming voltages such as VP1, VP2, and GND when performing write operations (e.g., FIGS. 4A-4F, 5A, and 5B), and (iii) generate other voltages applied to unselected word lines during given data access operations and during idle times when the memory 600 is not being utilized. The row control circuit 620 receives a number of control signals from a control signal block 640, including but not limited to clock signals, write enable signals, read enable signals, address decode enable signals, etc., for controlling the operation of the word line decoder circuit 622 and the word line voltage driver circuit 624.

[0073] The column control circuit 630 is configured to control activation / deactivation of the source lines SL and bit lines BL (and substrate body / well control lines) to perform read and write operations. More specifically, the column decoder circuit 632 is configured to decode addresses received from the address decoder 650 and determine which columns (e.g., source lines SL and bit lines BL) to activate based on the decoded addresses. The bit line / source line voltage driver circuit 634 is configured to generate voltage signals (e.g., voltage pulses) to drive the source lines SL and bit lines BL during read and write operations. For example, in some embodiments, the bit line-source line voltage driver circuit 634 is configured to (i) generate a second voltage VD_Read to drive the bit line BL and the source line SL (e.g., the first source / drain terminal 112 and the second source / drain terminal 114) when performing a read operation to operate a given FeFET device of a selected memory cell 612 in saturation mode (e.g., FIGS. 3A-3E), (ii) generate programming voltages, such as VP1, VP2, and GND, to drive the source line SL and the bit line BL when performing a write (programming) operation (e.g., FIGS. 4A-4D, 5A, and 5B), and (iii) generate other voltages that are applied to the source line SL and the bit line BL of unselected columns during a given data access operation and during idle times when the memory device 600 is not being utilized.

[0074] Additionally, the bit line sense amplifier circuit 636 senses the drain current I output from a given memory cell 612 on a given bit line BL during a read operation to determine the state of the given memory cell 612. D For example, in some embodiments, the bit line sense amplifier circuit 636 is configured to read or otherwise sense the sensed current I D multiple reference currents I D 1, I D 2. I D 3, and I D4, the sensed current I D (See, e.g., FIG. 3C ). The column control circuit 630 receives a number of control signals from a control signal block 640, including, but not limited to, clock signals, write / read enable signals, address decode enable signals, etc., for controlling the operation of the column control circuit 630.

[0075] While the exemplary embodiment of FIG. 6 is described in the context of a memory cell 612 having a 1T FeFET (or 1F) configuration, it should be understood that the exemplary multi-level FeFET devices described herein can be implemented in other suitable types of memory cell configurations. Moreover, memory device 600 can be implemented in a variety of configurations and applications. For example, in some embodiments, memory device 600 comprises an integrated circuit (IC) memory device implemented as non-volatile system memory of a computing system or device (e.g., a server machine, computer, mobile device, etc.). In other embodiments, memory device 600 is implemented as a storage resource of a computing system or device (e.g., direct-attached storage (DAS), network-attached storage (NAS), etc.).

[0076] Moreover, while circuit blocks 620, 630, 640, and 650 are generally illustrated in FIG. 6 , it should be understood that circuit blocks 620, 630, 640, and 650 can be implemented using known circuit configurations and techniques for managing and controlling nonvolatile memory systems suitable for a given application. Furthermore, circuit blocks 620, 630, 640, and 650, along with other circuitry for controlling the memory array, can be implemented as an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc. Additionally, the various row and column configurations and control operations can vary depending on how programming and read operations are performed, such as applying voltages to word lines, bit lines, and source lines to perform read / write operations on target memory cells to ensure nondestructive reading of the FeFET states of selected memory cells and to prevent disturbance of the memory states of the FeFET devices of unselected memory cells.

[0077] It will be appreciated that the various circuit blocks 620, 630, 640, and 650 and associated functionality collectively comprise a control system operatively coupled to non-volatile memory cell array 610 and configured to perform various operations, including, but not limited to, programming the FeFET devices of non-volatile memory cells 612 and reading the stored logic states of the FeFET devices of non-volatile memory cells 612 using the programming and reading techniques described above and illustrated generally in Figures 3A-3E, 4A-4F, 5A, and 5B. Moreover, the control system comprises additional components (e.g., circuits, processors, etc.) for implementing memory management functions and performing data access operations, where such additional components include, but are not limited to, an integrated memory controller, memory / storage interface circuitry, etc.

[0078] More specifically, in some embodiments, the control system of memory device 600 includes an integrated memory controller (including hardware, software, and / or firmware) configured to communicate with a host processor and manage memory operations, including, but not limited to, garbage collection, error correction code (ECC), bad block management, and other types of memory management functions typically implemented using integrated memory controllers. Additionally, the control system includes memory / storage interface circuitry to enable the host system and processor to interface and communicate with memory device 600 using, for example, one or more known communication protocols and / or storage control protocols. Such protocols include, but are not limited to, Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (eSATA), Parallel ATA (PATA), Non-Volatile Memory Express (NVMe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect Express (PCIe), Fibre Channel, etc.

[0079] It should be understood that the FeFET devices described herein can be utilized in a variety of applications, hardware, or electronic systems, or combinations thereof. Hardware and systems suitable for practicing the exemplary embodiments described herein may include, but are not limited to, personal computers, communications networks, electronic commerce systems, portable communications devices (e.g., mobile phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the exemplary embodiments provided herein, those skilled in the art will be able to contemplate other implementations and applications of the techniques and devices described herein.

[0080] The description of various embodiments of the present disclosure is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. An apparatus comprising:

1. A non-volatile memory comprising an array of non-volatile memory cells, at least one non-volatile memory cell comprising a ferroelectric field effect transistor (FeFET) device, said FeFET device comprising: a first source / drain region and a second source / drain region disposed in an upper surface of the substrate; a gate structure comprising a ferroelectric layer disposed over the substrate and a gate electrode disposed over the ferroelectric layer; the nonvolatile memory, wherein the ferroelectric layer comprises a first region adjacent to the first source / drain region and a second region adjacent to the second source / drain region; a control system operatively coupled to the nonvolatile memory to program the FeFET device of the at least one nonvolatile memory cell to have one of a plurality of different logic states by performing a programming operation to simultaneously program the first region and the second region of the ferroelectric layer; and wherein the one logic state corresponds to a polarization state of the FeFET device in which the first region of the ferroelectric layer has a remanent polarization with a first polarity and the second region has a remanent polarization with a second polarity opposite to the first polarity, and the programming operation comprises: applying a reference voltage to the second source / drain region; applying a first programming voltage to the gate electrode; applying a second programming voltage to the first source / drain region; wherein a magnitude of the second programming voltage is greater than a magnitude of the first programming voltage. the magnitude of the first programming voltage produces a potential difference between the gate electrode and the second source / drain region sufficient to switch the polarity of the remanent polarization in the second region to the second polarity; 2. The device of claim 1, wherein a difference between the magnitude of the second programming voltage and the magnitude of the first programming voltage creates a potential difference between the first source / drain region and the gate electrode sufficient to switch the polarity of the remanent polarization in the first region to the first polarity.

3. The device described in claim 2, wherein the programming operation is performed in a polarization state of the FeFET device in which the first region of the ferroelectric layer has a residual polarization having the second polarity and the second region has a residual polarization having the first polarity.

4. the ferroelectric layer has a polycrystalline microstructure including a plurality of crystal grains having an average grain size; The device of any one of claims 1 to 3, wherein the gate length of the gate structure is at least twice the average grain size of the ferroelectric layer.

5. the first region of the ferroelectric layer overlaps a portion of the first source / drain region, and the second region of the ferroelectric layer overlaps a portion of the second source / drain region; an amount of overlap between the first source / drain region and the first region of the ferroelectric layer is on the order of at least one average grain size of the ferroelectric layer; 5. The device of claim 4, wherein an amount of overlap between the second source / drain regions and the second region of the ferroelectric layer is on the order of at least one average grain size of the ferroelectric layer.

6. the first region of the ferroelectric layer includes a first ferroelectric domain; the second region of the ferroelectric layer comprises a second ferroelectric domain; The device of any one of claims 1 to 5, wherein the first ferroelectric domain and the second ferroelectric domain have the same or substantially similar coercive field properties.

7. The nonvolatile memory is further comprising control lines connected to the at least one non-volatile memory cell, the control lines comprising: a word line connected to the gate electrode of the FeFET device; a source line connected to the first source / drain region of the FeFET device; and a bit line connected to the second source / drain region of the FeFET device; the control system is operably coupled to the control line; the control system generating a programming control voltage on the control line to program the FeFET device of the at least one non-volatile memory cell to store the one logic state of the plurality of different logic states represented by at least two bits; the plurality of different logic states being: a first logic state corresponding to a first polarization state of the FeFET device, wherein the first region and the second region each include a remanent polarization having the first polarity; a second logic state corresponding to a second polarization state of the FeFET device, wherein the first region and the second region each include a remanent polarization having the second polarity; a third logic state corresponding to a third polarization state of the FeFET device, wherein the first region includes a remnant polarization having the first polarity and the second region includes a remnant polarization having the second polarity; and a fourth logic state corresponding to a fourth polarization state of the FeFET device, wherein the first region contains a remnant polarization having the second polarity and the second region contains a remnant polarization having the first polarity; and wherein the one logic state corresponds to the third polarization state.

8. 8. The device of claim 7, wherein the control system generates read control voltages on the plurality of control lines to perform a read operation, wherein in the read operation, the read control voltages cause the FeFET device to operate in a saturation mode and generate a current that is sensed by the control system, and wherein a logic state of the at least one non-volatile memory cell is determined based on the sensed current.

9. the control system comparing the sensed current to a plurality of reference currents to determine the logic state of the at least one non-volatile memory cell; 9. The apparatus of claim 8, wherein the plurality of reference currents comprises a first reference current corresponding to the first logic state, a second reference current corresponding to the second logic state, a third reference current corresponding to the third logic state, and a fourth reference current corresponding to the fourth logic state.

10. the read operation includes a first read operation and a second read operation; the control system performs the first read operation by applying a read voltage having a first read polarity to the first source / drain region and the second source / drain region of the FeFET device, causing the FeFET device to operate in a saturation mode and generate a first current sensed by the control system; performing the second read operation by the control system applying the read voltage having a second read polarity opposite to the first read polarity to the first source / drain region and the second source / drain region of the FeFET device to cause the FeFET device to operate in a saturation mode and generate a second current sensed by the control system; the control system comparing the first current and the second current; the control system determining that the FeFET device has the third polarization state in response to determining that the first current is less than the second current; 9. The apparatus of claim 8, wherein the control system determines that the FeFET device has the fourth polarization state in response to determining that the first current is greater than the second current.

11. 1. A method comprising: programming a ferroelectric field effect transistor (FeFET) device to store one of a plurality of different logic states, the FeFET device comprising: a first source / drain region and a second source / drain region; a gate structure comprising a ferroelectric layer and a gate electrode disposed over the ferroelectric layer; the ferroelectric layer comprising a first region adjacent to the first source / drain region and a second region adjacent to the second source / drain region; Programming the FeFET device to store the one logic state includes performing a programming operation to simultaneously program the first region and the second region of the ferroelectric layer to program the FeFET device such that the first region of the ferroelectric layer has a polarization state having a first polarity and the second region has a polarization state having a remanent polarization having a second polarity opposite the first polarity, the programming operation comprising: applying a reference voltage to the second source / drain region; applying a first programming voltage to the gate electrode; applying a second programming voltage to the first source / drain region; wherein the magnitude of the second programming voltage is greater than the magnitude of the first programming voltage.

12. The method of claim 11, wherein the magnitude of the first programming voltage creates a potential difference between the gate electrode and the second source / drain region sufficient to switch the polarity of the remanent polarization in the second region to the second polarity; 12. The method of claim 11 , wherein a difference between the magnitude of the second programming voltage and the magnitude of the first programming voltage creates a potential difference between the first source / drain region and the gate electrode sufficient to switch the polarity of the remanent polarization in the first region to the first polarity.

13. The method described in claim 12, wherein the programming operation is performed in a polarization state of the FeFET device in which the first region of the ferroelectric layer has a residual polarization having the second polarity and the second region has a residual polarization having the first polarity.

14. the plurality of different logic states being: a first logic state corresponding to a first polarization state of the FeFET device, wherein the first region and the second region each include a remanent polarization having the first polarity; a second logic state corresponding to a second polarization state of the FeFET device, wherein the first region and the second region each include a remanent polarization having the second polarity; a third logic state corresponding to a third polarization state of the FeFET device, wherein the first region includes a remnant polarization having the first polarity and the second region includes a remnant polarization having the second polarity; and a fourth logic state corresponding to a fourth polarization state of the FeFET device, wherein the first region contains a remnant polarization having the second polarity and the second region contains a remnant polarization having the first polarity; wherein the one logic state corresponds to the third polarization state.

15. The method comprising: programming the FeFET device to have the first polarization state; programming the FeFET device to have the second polarization state; and programming the FeFET device to have the fourth polarization state, wherein programming the FeFET device to have the first polarization state comprises: applying a ground voltage to the gate electrode; applying the first programming voltage to the first source / drain region and the second source / drain region; a magnitude of the first programming voltage creating a potential difference between the gate electrode and each of the first source / drain region and the second source / drain region, the potential difference being sufficient to switch the polarity of the remanent polarization in each of the first region and the second region to the first polarity; programming the FeFET device to have the second polarization state; applying the ground voltage to the first source / drain region and the second source / drain region; applying the first programming voltage to the gate electrode; the magnitude of the first programming voltage creates a potential difference between the gate electrode and each of the first source / drain region and the second source / drain region, the potential difference being sufficient to switch the polarity of the remanent polarization in each of the first region and the second region to the second polarity; programming the FeFET device to have the fourth polarization state; applying the ground voltage to the gate electrode and the first source / drain region; applying the first programming voltage to the second source / drain region; 15. The method of claim 14, wherein a magnitude of the first programming voltage creates a potential difference between the second source / drain region and the gate electrode, the potential difference being sufficient to switch the polarity of the remanent polarization in the second region to the first polarity, while a potential difference between the gate electrode and the first source / drain region is insufficient to switch the polarity of the remanent polarization in the first region, such that the first region maintains the remanent polarization having the second polarity.

16. The method, comprising programming the FeFET device to have the fourth polarization state, wherein programming the FeFET device to have the fourth polarization state comprises: applying a ground voltage to the first source / drain region; applying the first programming voltage to the gate electrode; applying the second programming voltage to the second source / drain region; Including, a magnitude of the first programming voltage creating a potential difference between the gate electrode and the first source / drain region, the potential difference being sufficient to switch the polarity of the remanent polarization in the first region to the second polarity; 15. The method of claim 14, wherein the difference between the magnitude of the second programming voltage and the magnitude of the first programming voltage creates a potential difference between the second source / drain region and the gate electrode, the potential difference being sufficient to switch the polarity of the remanent polarization in the second region to the first polarity.

17. the first polarization state corresponds to a first threshold voltage of the FeFET device, the second polarization state corresponds to a second threshold voltage of the FeFET device, the third polarization state corresponds to an effective third threshold voltage of the FeFET device, and the fourth polarization state corresponds to an effective fourth threshold voltage of the FeFET device; The method further includes performing a read operation to determine a logic state of the FeFET device, wherein performing the read operation comprises: applying a ground voltage to the first source / drain region of the FeFET device; applying a first voltage to the gate electrode of the FeFET device, the first voltage having a magnitude greater than the first threshold voltage, the second threshold voltage, and the effective third and fourth threshold voltages of the FeFET device; applying a second voltage to the second source / drain region of the FeFET device, the second voltage having a magnitude that provides a drain-source voltage sufficient to operate the FeFET device in a saturation mode; sensing a current generated by the FeFET device operating in the saturation mode; and comparing the sensed current to a plurality of reference currents to determine the logic state of the FeFET device.

18. 18. The method of claim 17, wherein the plurality of reference currents comprises a first reference current corresponding to the first logic state, a second reference current corresponding to the second logic state, a third reference current corresponding to the third logic state, and a fourth reference current corresponding to the fourth logic state.

19. the first polarization state corresponds to a first threshold voltage of the FeFET device, the second polarization state corresponds to a second threshold voltage of the FeFET device, the third polarization state corresponds to an effective third threshold voltage of the FeFET device, and the fourth polarization state corresponds to an effective fourth threshold voltage of the FeFET device; The method further includes performing a read operation to determine a logic state of the FeFET device, wherein performing the read operation comprises: performing a first read operation, applying a ground voltage to the first source / drain region of the FeFET device; applying a first voltage to the gate electrode of the FeFET device, the first voltage having a magnitude greater than the first threshold voltage, the second threshold voltage, and the effective third and fourth threshold voltages of the FeFET device; applying a second voltage to the second source / drain region of the FeFET device, the second voltage comprising a magnitude sufficient to operate the FeFET device in a saturation mode; performing the first read operation, the first read operation including sensing a first current generated by the FeFET device operating in the saturation mode; performing a second read operation, applying the ground voltage to the second source / drain region of the FeFET device; applying the first voltage to the gate electrode of the FeFET device; applying the second voltage to the first source / drain region of the FeFET device to operate the FeFET device in a saturation mode; performing the second read operation, the second read operation including sensing a second current generated by the FeFET device operating in the saturation mode; comparing the first current and the second current; determining that the FeFET device has the third polarization state in response to determining that the first current is less than the second current; and and determining that the FeFET device has the fourth polarization state in response to determining that the first current is greater than the second current.

20. A computer program comprising program code adapted to perform the method according to any of claims 11 to 19, when the program is running on a computer.

Images