Semiconductor device and manufacturing method thereof

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device comprises a cell region in which a plurality of MISFET are formed, and an outer peripheral region enclosing the cell region in a planar view. In the cell region and the outer peripheral region, an n-type impurity region DNW is formed in a semiconductor substrate SUB. An element separation portion STI, a p-type impurity region HPW and an n-type impurity region HNW are formed in the semiconductor substrate SUB in the outer peripheral region in such a way as to enclose the cell region in the planar view. A p-type impurity region PLD and an n-type impurity region NLD are formed in the semiconductor substrate SUB in the cell region in such a way as to be in contact with the impurity region HPW. The element separation portion STI is positioned in the impurity region HPW and separated from a junction interface between the impurity region HPW and the impurity region NLD.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an impurity region surrounding a cell region and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device includes a semiconductor substrate on which multiple semiconductor elements such as MISFETs (Metal Insulator Semiconductor Field Effect Transistors) are formed. An n-type impurity region is formed deep in the semiconductor substrate, and this n-type impurity region electrically isolates the multiple semiconductor elements from the semiconductor substrate, thereby improving noise resistance.

[0003] For example, as shown in Figure 32 of Patent Document 1, a cell region including multiple MISFETs is surrounded by a peripheral region in a plan view. In the peripheral region, a p-type impurity region for supplying a voltage to a well region that serves as a channel region of the MISFET, and an n-type impurity region for supplying a voltage to an isolation impurity region are formed. The cell region is electrically isolated from other semiconductor elements by this peripheral region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5487304 Summary of the Invention [Problem to be solved by the invention]

[0005] In a structure such as that of Patent Document 1, in which each impurity region is used to supply power to the channel region and isolate elements, if the structure of the cell region is changed, the existing structure of the peripheral region may not be able to accommodate the change. That is, if the structure of the cell region is changed, it may become difficult to join the p-type impurity region to the channel region, and the breakdown voltage may decrease near the peripheral region. This may result in a decrease in the reliability of the semiconductor device.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] A semiconductor device according to one embodiment includes a cell region in which a plurality of MISFETs are formed, and a peripheral region that surrounds the cell region in a plan view. the semiconductor device includes: a first impurity region of a first conductivity type formed in a semiconductor substrate in the cell region and the peripheral region; an element isolation portion formed in the semiconductor substrate from a surface of the semiconductor substrate to a predetermined depth in the peripheral region so as to surround the cell region in a planar view; a second impurity region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate from the surface of the semiconductor substrate to a position deeper than the element isolation portion in the peripheral region so as to surround the cell region in a planar view; a third impurity region of the first conductivity type formed in the semiconductor substrate from the surface of the semiconductor substrate to the first impurity region in the peripheral region so as to surround the second impurity region in a planar view; a fourth impurity region of the second conductivity type formed in the semiconductor substrate in the cell region so as to be located on the first impurity region and in contact with the second impurity region; and a fifth impurity region of the first conductivity type formed in the semiconductor substrate in the cell region so as to be in contact with the second impurity region from the surface of the semiconductor substrate to the fourth impurity region. Here, the element isolation portion includes a trench formed in the semiconductor substrate and an insulating film buried in the trench, and the element isolation portion is located in the second impurity region and is spaced apart from the junction interface between the second impurity region and the fifth impurity region.

[0009] A method for manufacturing a semiconductor device according to one embodiment is a method for manufacturing a semiconductor device including a cell region in which a plurality of MISFETs are formed and a peripheral region surrounding the cell region in a plan view, the method comprising the steps of: (a) forming a first impurity region of a first conductivity type in a semiconductor substrate in the cell region and the peripheral region; (b) forming an element isolation portion in the semiconductor substrate in the peripheral region from a surface of the semiconductor substrate to a predetermined depth so as to surround the cell region in a plan view; (c) forming a second impurity region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate in the peripheral region from a surface of the semiconductor substrate to a position deeper than the element isolation portion so as to surround the cell region in a plan view; and (d) forming a second impurity region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate from a surface of the semiconductor substrate to a position deeper than the element isolation portion so as to surround the cell region in a plan view. (e) forming a third impurity region of the first conductivity type in the semiconductor substrate in the peripheral region, extending from a surface of the semiconductor substrate to the first impurity region so as to surround the cell region, (f) forming a fifth impurity region of the first conductivity type in the semiconductor substrate in the cell region, extending from a surface of the semiconductor substrate to the fourth impurity region so as to be in contact with the second impurity region, wherein the element isolation portion includes a trench formed in the semiconductor substrate and an insulating film buried in the trench, and the element isolation portion is located in the second impurity region and is spaced apart from a junction interface between the second impurity region and the fifth impurity region. [Effects of the Invention]

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a part of a semiconductor device in a first embodiment. [Figure 2] 1 is an enlarged plan view of a main part of a semiconductor device according to a first embodiment. [Figure 3]1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a manufacturing process following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing a manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 1 is a graph showing experimental data obtained by the inventors of the present application. [Figure 13] 1 is a graph showing experimental data obtained by the inventors of the present application. [Figure 14] 10 is an enlarged plan view of a main part of a semiconductor device according to a second embodiment. FIG. [Figure 15] 11 is an enlarged plan view of a main part of a semiconductor device according to a third embodiment. FIG. [Figure 16] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 17] 1 is a graph showing experimental data obtained by the inventors of the present application. [Figure 18] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing process following FIG. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device in Study Example 1. [Figure 22] FIG. 10 is a cross-sectional view showing a semiconductor device in Study Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Structure of semiconductor device> The structure of the semiconductor device according to the first embodiment will be described below with reference to FIGS. 1 to 4. FIG. 1 is a plan view showing a part of the semiconductor device (semiconductor chip) according to the first embodiment. FIG. 2 is a plan view of a main part showing an enlarged region 1A shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line AA shown in FIG. 2. FIG. 4 is a cross-sectional view taken along line BB shown in FIG. 2.

[0015] As shown in FIG. 1, the semiconductor device includes various semiconductor elements such as multiple MISFETs, Zener diodes ZD, resistors, and capacitors. Here, the region where the multiple MISFETs are formed is shown as a cell region CR. Each semiconductor element is surrounded by an n-type impurity region HNW in plan view. Furthermore, each semiconductor element is electrically isolated from each other by the impurity region HNW and an n-type impurity region DNW (described later) in cross-sectional view.

[0016] 2, the semiconductor device includes a cell region CR and an outer peripheral region OR that surrounds the cell region CR in a plan view. The multiple MISFETs in the cell region CR constitute part of the circuitry of, for example, a DC / DC converter or a power supply IC. Each of the multiple MISFETs has a gate electrode GE extending in the Y direction.

[0017] In the outer periphery region OR, a p-type impurity region HPW is formed which surrounds the cell region CR in plan view and extends in the X and Y directions. In addition, in the outer periphery region OR, an n-type impurity region HNW is formed which surrounds the impurity region HPW in plan view and extends in the X and Y directions.

[0018] 3 and 4, the semiconductor substrate SUB is a laminate of a support substrate SS made of a p-type silicon substrate and a p-type semiconductor layer (epitaxial layer) EP formed on the support substrate SS by epitaxial growth. Various impurity regions are formed in the semiconductor layer EP, but for the sake of simplicity, the following description will be given assuming that the various impurity regions are formed in the semiconductor substrate SUB.

[0019] In the cell region CR and the peripheral region OR, an n-type impurity region DNW is formed in the semiconductor substrate SUB. The impurity region DNW separates the plurality of MISFETs in the cell region CR from the support substrate SS, thereby improving noise resistance.

[0020] First, the structure of the outer peripheral region OR will be described.

[0021] In the peripheral region OR, an element isolation portion STI is formed in the semiconductor substrate SUB from the surface of the semiconductor substrate SUB to a predetermined depth. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB and an insulating film such as a silicon oxide film embedded in the trench.

[0022] In the peripheral region OR, a p-type impurity region HPW and an n-type impurity region HNW are formed in the semiconductor substrate SUB from the surface of the semiconductor substrate SUB to a position deeper than the element isolation parts STI. The impurity region HNW is formed in the semiconductor substrate SUB from the surface of the semiconductor substrate SUB to the impurity region DNW. A high-concentration diffusion region PR is formed in the impurity region HPW surrounded by the element isolation parts STI, and a high-concentration diffusion region NR is formed in the impurity region HNW surrounded by the element isolation parts STI.

[0023] Next, the structure of the cell region CR will be described.

[0024] A p-type impurity region PLD is formed in the semiconductor substrate SUB in the cell region CR so as to be located on the impurity region DNW and in contact with the impurity region HPW. Also, an n-type impurity region NLD and a p-type impurity region PW are formed in the semiconductor substrate SUB in the cell region CR from the surface of the semiconductor substrate SUB to the impurity region PLD so as to be in contact with the impurity region HPW.

[0025] 3 and 4, an n-type source region NS and a p-type heavily doped diffusion region PR are formed in the impurity region PW. As shown in Fig. 2, an opening is provided near the center of the gate electrode GE, and the source region NS and the heavily doped diffusion region PR are formed inside the opening.

[0026] An n-type drain region ND is formed in the impurity region NLD. The impurity region PW is surrounded by the impurity region NLD in plan view. A gate electrode GE is formed on the impurity region PW and the impurity region NLD via a gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film. The gate electrode GE is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0027] The source region NS forms the source region of the MISFET. The drain region ND, together with the impurity region NLD, forms part of the drain region of the MISFET. The impurity region PW located directly below the gate electrode GE forms the channel region of the MISFET.

[0028] Sidewall spacers SW are formed on each side of the gate electrode GE. The sidewall spacers SW are, for example, a laminated film of a silicon oxide film and a silicon nitride film formed on the silicon oxide film. An insulating film IF1 having a pattern that exposes part of the surface of the semiconductor substrate SUB and part of the gate electrode GE is formed on the surface of the semiconductor substrate SUB so as to cover part of the gate electrode GE and the sidewall spacers SW. The insulating film IF1 is, for example, a silicon oxide film.

[0029] A silicide film SI is formed in the region exposed from the insulating film IF1. That is, the silicide film SI is formed on the surface of each of a part of the gate electrode GE, the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR. The source region NS and the heavily doped diffusion region PR of the cell region CR are electrically connected by the same silicide film SI. The silicide film SI is, for example, a cobalt silicide (CoSi2) film, a nickel silicide (NiSi) film, or a nickel platinum silicide (NiPtSi) film.

[0030] In the cell region CR and the peripheral region OR, an interlayer insulating film IL is formed on the surface of the semiconductor substrate SUB. The interlayer insulating film IL is, for example, a silicon oxide film. The interlayer insulating film IL may be a stacked film of a silicon nitride film and a silicon oxide film formed on the silicon nitride film.

[0031] A plurality of contact holes CH1 are formed in the interlayer insulating film IL. A plurality of plugs PG are formed inside each of the contact holes CH1. The plugs PG are made of, for example, a laminated film of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film, and the conductive film is, for example, a tungsten film.

[0032] A plurality of contact holes CH1 are located on the surfaces of the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR. Although not shown here, a plurality of wirings connected to the plurality of plugs PG are formed on the interlayer insulating film IL. A predetermined voltage is supplied to the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR from the plurality of wirings.

[0033] The heavily doped diffusion region NR, the impurity region HNW, and the impurity region DNW are each conductive as n-type impurity regions, and are therefore fixed at the same potential. The heavily doped diffusion region PR, the impurity region HPW, the impurity region PLD, and the impurity region PW are each conductive as p-type impurity regions, and are therefore fixed at the same potential. The drain region ND and the impurity region NLD are each conductive as n-type impurity regions, and are therefore fixed at the same potential.

[0034] Although not shown here, a contact hole CH1 and a plug PG are also formed on the surface of the gate electrode GE on which the silicide film SI is formed. A gate voltage is supplied to the gate electrode GE through this plug PG.

[0035] Furthermore, a slit-shaped contact hole CH2 is formed in the interlayer insulating film IL. A dummy plug DPG is formed inside the contact hole CH2. The dummy plug DPG is made of a barrier metal film and a conductive film similar to those of the plug PG. The contact hole CH2 and the dummy plug DPG are formed on the surfaces of the impurity region HPW and the impurity region NLD so as to straddle the junction interface between the impurity region HPW and the impurity region NLD.

[0036] A recombination promotion layer RCL is formed on the surface of the semiconductor substrate SUB located at the bottom of the contact hole CH2. The recombination promotion layer RCL in the first embodiment is a crystal defect layer formed by the plasma etching process performed when forming the contact hole CH2. As shown in FIG. 2, the contact hole CH2 and the recombination promotion layer RCL extend at least in the Y direction and also in the X direction along the junction interface.

[0037] The impurity concentration of the n-type impurity region DNW is, for example, 1×10 16 ~1×10 17 cm -3 The impurity concentration of the p-type impurity region HPW is, for example, 5×10 16 ~5×10 17 cm -3 The impurity concentration of the n-type impurity region HNW is, for example, 1×10 16 ~1×10 17 cm -3 The impurity concentration of the p-type impurity region PLD is, for example, 1×10 16 ~8×10 16 cm -3 The impurity concentration of the n-type impurity region NLD is, for example, 1×10 16 ~5×10 16 cm -3 The impurity concentration of the p-type impurity region PW is, for example, 5×10 17 ~5×10 18 cm -3 The impurity concentration of each of the n-type high concentration diffusion region NR, the n-type source region NS, and the n-type drain region ND is, for example, 1×1019 ~1×10 21 cm -3 The impurity concentration of the p-type high concentration diffusion region PR is, for example, 1×10 19 ~1×10 21 cm -3 is.

[0038] The diameter (width in the X direction and width in the Y direction) of the contact hole CH1 is, for example, 0.16 μm to 0.20 μm inclusive. The width of the contact hole CH2 in the direction perpendicular to the extending direction of the contact hole CH2 is, for example, 0.16 μm to 0.20 μm inclusive.

[0039] The main features of the first embodiment are that the element isolation part STI is located in the impurity region HPW and is spaced apart from the junction interface between the impurity region HPW and the impurity region NLD, and that the recombination promotion layer RCL is formed so as to straddle the junction interface. However, such features will be explained using an example after explaining the manufacturing method of the semiconductor device.

[0040] <Method of manufacturing a semiconductor device> The method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to the manufacturing steps shown in Figures 5 to 11. The following description will be given based on the cross section AA of Figure 3.

[0041] As shown in Figure 5, first, a p-type support substrate SS is prepared. The support substrate SS is made of silicon. Next, a p-type semiconductor layer EP is formed on the support substrate SS by epitaxial growth. This forms a semiconductor substrate SUB, which is a stack of the support substrate SS and the semiconductor layer EP.

[0042] As shown in FIG. 6, in the cell region CR and the peripheral region OR, an n-type impurity region DNW is formed in the semiconductor substrate SUB (in the semiconductor layer EP) by photolithography and ion implantation.

[0043] Furthermore, in the peripheral region OR, an element isolation portion STI is formed in the semiconductor substrate SUB from the surface of the semiconductor substrate SUB to a predetermined depth so as to surround the cell region CR in a plan view. First, a trench is formed in the semiconductor substrate SUB using photolithography and etching. Next, an insulating film such as a silicon oxide film is formed on the semiconductor substrate SUB so as to fill the trench. Next, the insulating film on the semiconductor substrate SUB is removed by polishing using a CMP method, leaving the insulating film in the trench. In this way, an element isolation portion STI composed of the trench and the insulating film is formed.

[0044] 7, a p-type impurity region HPW is formed in the semiconductor substrate SUB in the peripheral region OR from the surface of the semiconductor substrate SUB to a position deeper than the element isolation part STI by photolithography and ion implantation. Next, an n-type impurity region HNW is formed in the semiconductor substrate SUB in the peripheral region OR from the surface of the semiconductor substrate SUB to the impurity region DNW by photolithography and ion implantation.

[0045] Next, a p-type impurity region PLD is formed in the semiconductor substrate SUB in the cell region CR by photolithography and ion implantation so as to be located on the impurity region DNW and in contact with the impurity region HPW. Next, an n-type impurity region NLD is formed in the semiconductor substrate SUB in the cell region CR by photolithography and ion implantation so as to be in contact with the impurity region HPW. Next, a p-type impurity region PW is formed in the semiconductor substrate SUB in the cell region CR by photolithography and ion implantation so as to be in contact with the impurity region HPW.

[0046] The impurity region HPW, the impurity region HNW, the impurity region PLD, the impurity region NLD, and the impurity region PW may be formed in any order.

[0047] 8, a gate insulating film GI made of, for example, silicon oxide is formed on the impurity region PW and the impurity region NLD, for example, by thermal oxidation or CVD. Next, a polycrystalline silicon film into which, for example, n-type impurities are introduced is formed on the impurity region PW and the impurity region NLD via the gate insulating film GI, for example, by CVD. Thereafter, the polycrystalline silicon film is patterned to form a gate electrode GE on the gate insulating film GI.

[0048] Next, an insulating film such as a silicon nitride film is formed on the semiconductor substrate SUB by, for example, a CVD method so as to cover the gate electrode GE. Next, the insulating film is subjected to an anisotropic etching process to form sidewall spacers SW on each side surface of the gate electrode GE.

[0049] As shown in FIG. 9, in the cell region CR, a source region NS is formed in the impurity region PW and a drain region ND is formed in the impurity region NLD by photolithography and ion implantation. At this time, in the outer periphery region OR, a high-concentration diffusion region NR is formed in the impurity region HNW. Next, by photolithography and ion implantation, a high-concentration diffusion region PR is formed in the impurity region HPW of the outer periphery region OR. At this time, the high-concentration diffusion region PR shown in FIG. 4 is also formed in the impurity region PW of the cell region CR. Note that the high-concentration diffusion region PR may be formed before the source region NS, the drain region ND, and the high-concentration diffusion region NR.

[0050] 10, an insulating film IF1 such as a silicon oxide film is formed on the surface of the semiconductor substrate SUB by, for example, CVD so as to cover the gate electrode GE. Next, the insulating film IF1 is patterned by photolithography and etching. As a result, a pattern is formed in the insulating film IF1 that opens part of the surface of the semiconductor substrate SUB and part of the surface of the gate electrode.

[0051] Next, a silicide film SI is formed by salicide technology on a portion of the surface of the semiconductor substrate SUB exposed from the insulating film IF1 and on a portion of the surface of the gate electrode. First, a metal film is formed on the insulating film IF1, the surface of the semiconductor substrate SUB, and the surface of the gate electrode by, for example, sputtering. This metal film is made of, for example, cobalt, nickel, or a nickel-platinum alloy. Next, the semiconductor substrate SUB is subjected to a first heat treatment at about 300°C to 400°C, and then to a second heat treatment at about 600°C to 700°C, thereby reacting the materials contained in the semiconductor substrate SUB and the gate electrode GE with the metal film. As a result, a silicide film SI is formed on the surface of the semiconductor substrate SUB exposed from the insulating film IF1 and on the surface of the gate electrode GE. Then, the unreacted metal film is removed.

[0052] 11, in the cell region CR and the peripheral region OR, an interlayer insulating film IL is formed on the surface of the semiconductor substrate SUB by, for example, a CVD method. The interlayer insulating film IL may be a single layer of silicon oxide film, or may be a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0053] Next, a plurality of contact holes CH1 and CH2 are formed in the interlayer insulating film IL by plasma etching. The plurality of contact holes CH1 are located on the surfaces of the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR, and reach the respective silicide films SI. The contact hole CH2 is formed on the surfaces of the impurity region HPW and the impurity region NLD so as to straddle the junction interface between the impurity region HPW and the impurity region NLD.

[0054] By the above-described plasma etching process, a crystal defect layer is formed on the surface of the semiconductor substrate SUB located at the bottom of the contact hole CH2. This crystal defect layer becomes the recombination promotion layer RCL.

[0055] Next, plugs PG are formed inside the plurality of contact holes CH1, and dummy plugs DPG are formed inside the contact holes CH2, thereby manufacturing the semiconductor device shown in FIG.

[0056] To form the plugs PG and the dummy plugs DPG, first, a barrier metal film is formed by, for example, sputtering on the interlayer insulating film IL including the insides of the plurality of contact holes CH1 and CH2. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film.

[0057] Next, a conductive film such as a tungsten film is formed on the barrier metal film by, for example, a CVD method, and then the conductive film and the barrier metal film formed outside the plurality of contact holes CH1 and outside the contact hole CH2 are removed by a polishing process using a plasma etching process or a CMP process.

[0058] <Main features of Study Example 1 and Embodiment 1> A semiconductor device in Study Example 1 studied by the present inventors will be described below with reference to Fig. 21. In the semiconductor device in Study Example 1, the element isolation part STI is formed so as to straddle the junction interface between the impurity region HPW and the impurity region NLD.

[0059] FIG. 21 shows a manufacturing process corresponding to FIG. 7. Ion implantation is performed to form the p-type impurity region PLD, but ions tend to have difficulty reaching the area directly below the element isolation portion STI. This can cause problems such as the impurity region PLD not being formed near the contact point with the impurity region HPW or the impurity concentration of the impurity region PLD being significantly reduced. That is, the impurity region PLD may not be electrically conductive to the impurity region HPW. This can cause a problem in that the potential supplied to the high-concentration diffusion region PR and the impurity region HPW is not transmitted to the impurity region PLD and the impurity region PW.

[0060] To address this problem, in the first embodiment, the element isolation part STI is positioned in the impurity region HPW so as to be away from the junction interface between the impurity region HPW and the impurity region NLD, as shown in Fig. 3. This allows the impurity region PLD to be in reliable contact with the impurity region HPW, and a power supply path from the high-concentration diffusion region PR to the impurity region PW is secured, thereby improving the reliability of the semiconductor device.

[0061] <Main features of Study Example 2 and Embodiment 1> A semiconductor device in Study Example 2 studied by the present inventors will be described below with reference to Fig. 22. The semiconductor device in Study Example 2 is almost the same as the semiconductor device in Embodiment 1, except that a recombination promotion layer RCL is not formed.

[0062] One of the tests for reliability of semiconductor devices is a test for measuring the parasitic breakdown voltage BVceo. If the parasitic breakdown voltage BVceo starts to decrease, there is a risk that element breakdown will occur during transient operation of the semiconductor device, when the protection circuit operates, or when latch-up occurs. Therefore, there is a need for technology that can suppress the decrease in the parasitic breakdown voltage BVceo.

[0063] 22, in this measurement test, the source region NS and the heavily doped diffusion region PR are in an open state (no voltage is supplied). Therefore, no voltage is supplied to the p-type impurity regions PW, PLD, and HPW. A reference voltage (GND) is supplied to the impurity region NLD via the drain region ND. A positive voltage (V+) is supplied to the n-type impurity region DNW via the heavily doped diffusion region NR and the impurity region HNW.

[0064] The inventors of the present application have discovered a phenomenon in which the parasitic breakdown voltage BVceo begins to decrease when the total value of the gate widths of the plurality of MISFETs formed in the cell region CR reaches a certain length.

[0065] The following discussion is a mechanism discovered by the inventors of this application through investigations using TCAD. When a positive voltage is applied to the impurity region DNW, electron-hole pairs are generated at the interface between the impurity region DNW and the impurity region PLD. Since the source region NS and the heavily doped diffusion region PR are "OPEN," holes are gradually accumulated in the impurity region PLD. The accumulated holes increase the potential of the impurity region PLD. Eventually, the impurity region PLD and the drain region ND connected to "GND" are semi-biased, and the parasitic bipolar transistor is activated. This parasitic bipolar transistor causes a decrease in the parasitic breakdown voltage BVceo.

[0066] The relationship between the total value [μm] of the gate width W of the gate electrodes GE and the reduction in the parasitic breakdown voltage BVceo will be explained below with reference to Fig. 12. Here, the inventors of the present application have found through experiments that recombination centers are active in the outer peripheral region OR.

[0067] 12, when the total value of the gate widths W is small, for example, when the total value of the gate widths W is smaller than 1000 μm, most of the holes accumulated in the impurity region PLD are consumed by recombination in the outer peripheral region OR. As a result, the impurity region PLD and the drain region ND are short-circuited due to the junction breakdown voltage before they are quasi-biased, and the parasitic breakdown voltage BVceo is fixed at approximately 18 V.

[0068] On the other hand, when the total value of the gate widths W is large, for example, when the total value of the gate widths W is 1000 μm or more, the number of electron-hole pairs generated at the interface between the impurity region DNW and the impurity region PLD becomes greater than the number of holes that recombine in the peripheral region OR. For this reason, in Study Example 2, as the total value of the gate widths W increases, the parasitic breakdown voltage BVceo decreases.

[0069] Based on the above considerations, the inventors of the present invention have devised a structure that can suppress a decrease in the parasitic breakdown voltage BVceo by promoting recombination near the boundary between the cell region CR and the outer periphery region OR.

[0070] Note that recombination here means that holes and electrons combine and disappear. Recombination mainly occurs in the depletion layer IVL formed at the interface between the hole-rich p-type region and the electron-rich n-type region. Therefore, in order to promote recombination, it is effective to form a recombination promotion layer RCL on the surface of the semiconductor substrate SUB where the depletion layer IVL is formed. Furthermore, the larger the area where the recombination promotion layer RCL overlaps with the depletion layer IVL, the greater the effect of suppressing a decrease in the parasitic breakdown voltage BVceo.

[0071] 3, in the first embodiment, a recombination promotion layer RCL for recombining electrons and holes is formed on the surface of each of the impurity region HPW and the impurity region NLD so as to straddle the junction interface between the impurity region HPW and the impurity region NLD. As described above, the recombination promotion layer RCL in the first embodiment is a crystal defect layer formed by plasma etching. This crystal defect layer acts as a mid-gap level and promotes the recombination of holes.

[0072] 12, in the study example, the parasitic breakdown voltage BVceo starts to decrease when the total value of the gate widths W reaches approximately 1000 μm, and when the total value of the gate widths W reaches 5000 μm or more, the parasitic breakdown voltage BVceo decreases to approximately 12 V. However, in the first embodiment, even when the total value of the gate widths W is 5000 μm or more, the decrease in the parasitic breakdown voltage BVceo is suppressed. Therefore, according to the first embodiment, the reliability of the semiconductor device can be improved.

[0073] However, by providing the recombination promotion layer RCL, the decrease in the parasitic breakdown voltage BVceo is suppressed, but there is a concern that a recombination current may flow between the drain region ND and the source region NS as an off-leak current. Figure 13 shows the results of an experiment conducted by the inventors on the off-leak current. As shown in Figure 13, there is almost no increase in the off-leak current between Study Example 2 and Embodiment 1, and it was found that the increase is at the level of measurement error.

[0074] Incidentally, it is most preferable that the contact hole CH2 and the recombination promotion layer RCL are formed so as to straddle the junction interface between the impurity region HPW and the impurity region NLD. However, even if the contact hole CH2 and the recombination promotion layer RCL are formed only in a region slightly away from the junction interface, a decrease in the parasitic breakdown voltage BVceo can be suppressed to some extent.

[0075] That is, the contact hole CH2 and the recombination promotion layer RCL may be formed on the surface of the impurity region HPW at a position closer to the junction interface than the impurity region HNW. For the same purpose, the contact hole CH2 and the recombination promotion layer RCL may be formed on the surface of the impurity region NLD at a position closer to the junction interface than the drain region ND. In these cases, the distance between the contact hole CH2 and the recombination promotion layer RCL and the junction interface is preferably within 40 nm.

[0076] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Fig. 14. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0077] In the first embodiment, the contact hole CH2 is formed in a slit shape, but in the second embodiment, it is divided into a plurality of dot-shaped contact holes CH2. Therefore, the recombination promotion layer RCL in the second embodiment is a plurality of crystal defect layers formed at the bottom of the plurality of contact holes CH2. That is, the plurality of contact holes CH2 and the plurality of crystal defect layers are arranged at a distance from each other at least in the Y direction along the junction interface between the impurity region HPW and the impurity region NLD, and are also arranged at a distance from each other in the X direction.

[0078] The contact hole CH2 in the second embodiment has the same shape as the contact hole CH1, and the diameter (width in the X direction and width in the Y direction) of the contact hole CH2 is, for example, 0.16 μm or more and 0.20 μm or less. Furthermore, each contact hole CH2 is formed by the same manufacturing process as each contact hole CH1.

[0079] In the second embodiment, the contact area between the semiconductor substrate SUB and the entire contact hole CH2 is smaller than in the first embodiment. That is, the formation area of ​​the recombination promotion layer RCL is smaller. Therefore, as shown in FIG. 12, the first embodiment is superior to the second embodiment in terms of suppressing a decrease in the parasitic breakdown voltage BVceo. However, the second embodiment can also sufficiently suppress a decrease in the parasitic breakdown voltage BVceo compared to the second study example.

[0080] However, since the contact hole CH2 in the second embodiment has the same shape as the contact hole CH1, problems such as defective shapes of the contact hole CH2 are less likely to occur in the second embodiment than in the first embodiment, and semiconductor devices can be manufactured more stably.

[0081] (Embodiment 3) 15 and 16, a semiconductor device according to the third embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0082] In the first embodiment, the recombination promotion layer RCL is formed in the process of forming the contact hole CH2, and the dummy plug DPG is formed inside the contact hole CH2. However, in the third embodiment, the contact hole CH2 and the dummy plug DPG are not formed.

[0083] 15 and 16, in the third embodiment, a dummy silicide film DSI is formed on each surface of the impurity region HPW and the impurity region NLD so as to straddle the junction interface between the impurity region HPW and the impurity region NLD. The dummy silicide film DSI itself acts as a mid-gap level and functions as a recombination promotion layer RCL. The recombination promotion layer RCL (silicide film SI) extends at least in the Y direction and also in the X direction along the junction interface, as in the first embodiment.

[0084] In order to form the dummy silicide film DSI, a pattern that opens around the junction interface is provided in the insulating film IF1 in the manufacturing process of Figure 10. Thereafter, the dummy silicide film DSI is formed as the recombination promotion layer RCL by the same process as the process for forming the other silicide films SI. Therefore, the recombination promotion layer RCL in the third embodiment is made of the same material as the other silicide films SI.

[0085] Furthermore, the third embodiment has the advantage that the width of the recombination promotion layer RCL can be more freely designed than the first embodiment. In the first embodiment, the width of the recombination promotion layer RCL depends on the width of the contact hole CH2 and is approximately the same as the width of the contact hole CH1, for example, 0.16 μm or more and 0.20 μm or less. In the third embodiment, the width of the recombination promotion layer RCL (the width of the dummy silicide film DSI) can be easily made larger than the width of the contact hole CH1. Therefore, it is easier to suppress a decrease in the parasitic breakdown voltage BVceo. Note that the width of the recombination promotion layer RCL mentioned above is the width in the direction perpendicular to the extending direction of the recombination promotion layer RCL (dummy silicide film DSI).

[0086] 17 shows the results of measuring how much the parasitic breakdown voltage BVceo changes depending on the width L1 of the recombination promotion layer RCL. Note that the width L1 indicates the width of the recombination promotion layer RCL formed from the end of the element isolation part STI toward the impurity region NLD.

[0087] 17, it can be seen that the decrease in the parasitic breakdown voltage BVceo is suppressed when the width L1 is approximately 2.3 μm or more. That is, it can be seen that the decrease in the parasitic breakdown voltage BVceo is suppressed when the recombination promotion layer RCL approaches the junction interface and the area where the recombination promotion layer RCL and the depletion layer IVL overlap increases. In the experiment of FIG. 17, the width of the dummy silicide film DSI is gradually increased from the edge of the element isolation part STI, but the dummy silicide film DSI does not need to be in contact with the edge of the element isolation part STI, as long as it is formed around the periphery of the junction interface (around the depletion layer IVL).

[0088] In the third embodiment, too, the provision of the recombination promotion layer RCL makes it easier for the recombination current to flow as off-leakage current. As described above, in the third embodiment, the width of the recombination promotion layer RCL can be easily made larger than the width of the contact hole CH2 in the first embodiment. However, since there is a concern that the off-leakage current may increase accordingly, it is preferable to appropriately set the width of the recombination promotion layer RCL.

[0089] In the third embodiment, the recombination promotion layer RCL may be composed of a plurality of dummy silicide films DSI, as in the second embodiment. In this case, by providing a plurality of opening patterns in the insulating film IF1 along the junction interface, a plurality of dummy silicide films DSI can be formed in the opening patterns. That is, the plurality of dummy silicide films DSI may be arranged along the junction interface while being spaced apart from each other at least in the Y direction, and may also be arranged while being spaced apart from each other in the X direction.

[0090] (Fourth embodiment) The semiconductor device according to the fourth embodiment will be described below with reference to Figures 18 to 20. In the following description, differences from the first embodiment will be mainly described, and explanation of points that overlap with the first embodiment will be omitted. Figures 18 to 20 show the manufacturing steps corresponding to Figures 5 to 7.

[0091] In the first embodiment, the n-type impurity region DNW is used as a structure for electrically isolating each semiconductor element. In the fourth embodiment, the n-type impurity region NBL is used as a structure equivalent to the n-type impurity region DNW.

[0092] As shown in Figure 18, first, a p-type support substrate SS is prepared. Next, in the cell region CR and the peripheral region OR, n-type impurity regions NBL are formed in the support substrate SS using photolithography and ion implantation. Next, a p-type semiconductor layer EP is formed on the support substrate SS using epitaxial growth. This forms a semiconductor substrate SUB, which is a stack of the support substrate SS and the semiconductor layer EP.

[0093] In the first embodiment, the semiconductor layer EP is formed first, and then the impurity region DNW is formed in the semiconductor layer EP by ion implantation. Since the impurity region DNW needs to be formed within the range of the ion implantation, there is a problem in that it is difficult to increase the thickness of the semiconductor layer EP. As in the fourth embodiment, the impurity region NBL is first formed in the support substrate SS by ion implantation, and then the semiconductor layer EP is formed, thereby increasing the thickness of the semiconductor layer EP. Therefore, the fourth embodiment has higher manufacturing costs than the first embodiment, but offers advantages such as improved breakdown voltage and noise resistance.

[0094] The impurity region DNW in the first embodiment is located at a depth of about 2.0 to 3.0 μm from the upper surface of the semiconductor substrate SUB, whereas the impurity region NBL in the fourth embodiment is located at a depth of about 6.0 to 12.0 μm from the upper surface of the semiconductor substrate SUB. The impurity concentration of the impurity region DNW in the first embodiment is, for example, 1×10 16 ~1×10 17 cm -3 However, the impurity concentration of the impurity region NBL in the fourth embodiment is, for example, 1×10 17 ~1×10 18 cm -3 is.

[0095] Next, as shown in FIG. 19, an element isolation portion STI is formed in the peripheral region OR, and an n-type impurity region DHNW is formed in the semiconductor substrate SUB by photolithography and ion implantation. The impurity region DHNW is formed as a part of the impurity region HNW described later, and serves to achieve electrical conduction between the impurity region NBL and the impurity region HNW. The impurity concentration of the impurity region DHNW is, for example, 1×10 16 ~1×10 17 cm -3 is.

[0096] 20, impurity regions HPW, HNW, PLD, NLD, and PW are formed by the same method as in Embodiment 1. The subsequent manufacturing steps are the same as those in FIG.

[0097] The technology described in the fourth embodiment is also applicable to the second and third embodiments.

[0098] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0099] 1A Expansion Area CH1~CH3 contact holes CR Cell Area DHNW n-type impurity region DNW n-type impurity region DPG dummy plug DSI dummy silicide film EP Semiconductor layer (epitaxial layer) GE gate electrode GI gate insulating film HPW p-type impurity region HNW n-type impurity region IF1 insulating film IL Interlayer insulating film IVL depletion layer NBL n-type impurity region ND n-type drain region NLD n-type impurity region NR n-type heavily doped diffusion region NS n-type source region OR outer area PG plug PLD p-type impurity region PR p-type high concentration diffusion region RCL recombination promotion layer SI silicide film SS support board STI element isolation section SUB Semiconductor substrate SW Sidewall Spacer ZD Zener diode

Claims

1. A semiconductor device including a cell region in which a plurality of MISFETs are formed, and a peripheral region surrounding the cell region in a plan view, a first impurity region of a first conductivity type formed in a semiconductor substrate in the cell region and the peripheral region; an isolation portion formed in the semiconductor substrate from a surface of the semiconductor substrate to a predetermined depth in the peripheral region so as to surround the cell region in a plan view; a second impurity region that is formed in the semiconductor substrate from the surface of the semiconductor substrate to a position deeper than the element isolation part in the peripheral region so as to surround the cell region in a plan view, and that is of a second conductivity type opposite to the first conductivity type; a third impurity region of the first conductivity type formed in the semiconductor substrate from the surface of the semiconductor substrate to the first impurity region in the peripheral region so as to surround the second impurity region in a plan view; a fourth impurity region of the second conductivity type formed in the semiconductor substrate in the cell region, the fourth impurity region being located on the first impurity region and in contact with the second impurity region; a fifth impurity region of the first conductivity type formed in the semiconductor substrate from the surface of the semiconductor substrate to the fourth impurity region in the cell region so as to be in contact with the second impurity region; Equipped with the element isolation portion includes a trench formed in the semiconductor substrate and an insulating film buried in the trench, the element isolation portion is located in the second impurity region and is spaced apart from a junction interface between the second impurity region and the fifth impurity region.

2. 2. The semiconductor device according to claim 1, a recombination promotion layer for recombining electrons and holes is formed on the surface of each of the second impurity region and the fifth impurity region so as to straddle the junction interface.

3. 3. The semiconductor device according to claim 2, Each of the plurality of MISFETs is a sixth impurity region of the second conductivity type formed in the semiconductor substrate in the cell region, the sixth impurity region extending from the surface of the semiconductor substrate to the fourth impurity region; a source region of the first conductivity type formed in the sixth impurity region; a drain region of the first conductivity type formed in the fifth impurity region; a gate electrode formed on the sixth impurity region and the fifth impurity region via a gate insulating film; and a total value of gate widths of the gate electrodes of the plurality of MISFETs in a first direction in a plan view is 1000 μm or more.

4. 4. The semiconductor device according to claim 3, an interlayer insulating film formed on a surface of the semiconductor substrate in the cell region and the peripheral region; a contact hole formed in the interlayer insulating film and reaching the semiconductor substrate; a plug formed inside the contact hole; Further provided with the recombination promotion layer is a crystal defect layer formed on the surface of the semiconductor substrate located at the bottom of the contact hole, The contact hole and the crystal defect layer extend at least in the first direction along the junction interface.

5. 4. The semiconductor device according to claim 3, an interlayer insulating film formed on a surface of the semiconductor substrate in the cell region and the peripheral region; a plurality of contact holes formed in the interlayer insulating film and reaching the semiconductor substrate; a plurality of plugs formed in the plurality of contact holes, respectively; Further provided with the recombination promotion layer is a plurality of crystal defect layers formed at the bottoms of the plurality of contact holes, The semiconductor device, wherein the plurality of contact holes and the plurality of crystal defect layers are arranged along the junction interface while being spaced apart from each other at least in the first direction.

6. 4. The semiconductor device according to claim 3, the recombination promotion layer is made of a silicide film, The silicide film extends along the junction interface in at least the first direction.

7. 7. The semiconductor device according to claim 6, The semiconductor device, wherein the silicide film is a cobalt silicide film, a nickel silicide film, or a nickel platinum silicide film.

8. 7. The semiconductor device according to claim 6, an interlayer insulating film formed on a surface of the semiconductor substrate in the cell region and the peripheral region; a first contact hole formed in the interlayer insulating film and positioned on the source region or the drain region; a first plug formed inside the first contact hole and electrically connected to the source region or the drain region; Further provided with In a second direction intersecting the first direction in a plan view, the width of the silicide film is larger than the width of the first contact hole.

9. A method for manufacturing a semiconductor device including a cell region in which a plurality of MISFETs are formed and a peripheral region surrounding the cell region in a plan view, the method comprising: (a) forming a first impurity region of a first conductivity type in the semiconductor substrate in the cell region and the peripheral region; (b) forming an isolation portion in the semiconductor substrate in the peripheral region so as to surround the cell region in a plan view, the isolation portion extending from a surface of the semiconductor substrate to a predetermined depth; (c) forming a second impurity region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate from a surface of the semiconductor substrate to a position deeper than the element isolation portion in the peripheral region so as to surround the cell region in a plan view; (d) forming a third impurity region of the first conductivity type in the semiconductor substrate, in the peripheral region, from the surface of the semiconductor substrate to the first impurity region, so as to surround the second impurity region in a plan view; (e) forming a fourth impurity region of the second conductivity type in the semiconductor substrate in the cell region, the fourth impurity region being located on the first impurity region and in contact with the second impurity region; (f) forming a fifth impurity region of the first conductivity type in the cell region, from the surface of the semiconductor substrate to the fourth impurity region, so as to be in contact with the second impurity region; Equipped with the element isolation portion includes a trench formed in the semiconductor substrate and an insulating film buried in the trench, the element isolation portion is located in the second impurity region and is spaced apart from a junction interface between the second impurity region and the fifth impurity region.

10. 10. The method for manufacturing a semiconductor device according to claim 9, a recombination promotion layer for recombining electrons and holes is formed on the surface of each of the second impurity region and the fifth impurity region so as to straddle the junction interface.

11. 11. The method for manufacturing a semiconductor device according to claim 10, (g) forming a sixth impurity region of the second conductivity type in the semiconductor substrate in the cell region, the sixth impurity region extending from the surface of the semiconductor substrate to the fourth impurity region; (h) forming a gate insulating film on the sixth impurity region and the fifth impurity region; (i) forming a gate electrode on the sixth impurity region and the fifth impurity region via the gate insulating film; (j) forming a source region of the first conductivity type in the sixth impurity region; (k) forming a drain region of the first conductivity type in the fifth impurity region; and a total value of gate widths of the gate electrodes of the plurality of MISFETs in a first direction in a plan view is 1000 μm or more.

12. 12. The method for manufacturing a semiconductor device according to claim 11, (m) forming an interlayer insulating film on the surface of the semiconductor substrate in the cell region and the peripheral region; (n) forming a contact hole in the interlayer insulating film by plasma etching, the contact hole reaching the semiconductor substrate; (o) forming a plug inside the contact hole; Further provided with the recombination promotion layer is a crystal defect layer formed on the surface of the semiconductor substrate located at the bottom of the contact hole by the plasma etching process, The method for manufacturing a semiconductor device, wherein the contact hole and the crystal defect layer extend at least in the first direction along the junction interface.

13. 12. The method for manufacturing a semiconductor device according to claim 11, (m) forming an interlayer insulating film on the surface of the semiconductor substrate in the cell region and the peripheral region; (n) forming a plurality of contact holes in the interlayer insulating film by plasma etching, the contact holes reaching the semiconductor substrate; (o) forming a plurality of plugs in the plurality of contact holes; Further provided with the recombination promotion layer is a plurality of crystal defect layers formed by the plasma etching process on the surface of the semiconductor substrate located at the bottoms of the plurality of contact holes, The method for manufacturing a semiconductor device, wherein the plurality of contact holes and the plurality of crystal defect layers are arranged along the junction interface while being spaced apart from each other at least in the first direction.

14. 12. The method for manufacturing a semiconductor device according to claim 11, (p) forming a first insulating film on the surface of the semiconductor substrate, the first insulating film having a pattern that opens a portion of the surface of the semiconductor substrate; (q) forming a silicide film on the surface of the semiconductor substrate exposed from the first insulating film; Further provided with the recombination promotion layer is made of a silicide film, The silicide film extends along the junction interface in at least the first direction.

15. 15. The method for manufacturing a semiconductor device according to claim 14, The method for manufacturing a semiconductor device, wherein the silicide film is a cobalt silicide film, a nickel silicide film, or a nickel platinum silicide film.

16. 15. The method for manufacturing a semiconductor device according to claim 14, (m) forming an interlayer insulating film on the surface of the semiconductor substrate in the cell region and the peripheral region; (n) forming a first contact hole in the interlayer insulating film by plasma etching so as to be located on the source region or the drain region; (o) forming a first plug inside the first contact hole so as to be electrically connected to the source region or the drain region; Further provided with a width of the silicide film in a second direction intersecting the first direction in a plan view, the width of the silicide film being larger than a width of the first contact hole;

17. 10. The method for manufacturing a semiconductor device according to claim 9, The step (a) comprises: (a1) providing a support substrate; (a2) forming a semiconductor layer on the support substrate by an epitaxial growth method to form the semiconductor substrate, which is a laminate of the support substrate and the semiconductor layer; (a3) forming the first impurity region in the semiconductor layer; The method for manufacturing a semiconductor device comprising the steps of:

18. 10. The method for manufacturing a semiconductor device according to claim 9, The step (a) comprises: (a4) providing a support substrate; (a5) forming the first impurity region in the support substrate; (a6) forming a semiconductor layer on the support substrate by an epitaxial growth method to form the semiconductor substrate, which is a laminate of the support substrate and the semiconductor layer; The method for manufacturing a semiconductor device comprising the steps of:

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