Semiconductor memory device and control method thereof

Abstract

To provide a semiconductor storage device capable of reducing leakage current generated in a sense amplifier in a data retained state, and a control method thereof.SOLUTION: A semiconductor storage device includes: a sense amplifier 10 connected to a pair of bit lines BLT and BLB, which is a sense amplifier 10 including at least one of transistors 10a, 10b, 10c, and 10d connected to the bit line BLB on a low-voltage power side among the pair of bit lines BLT and BLB; and a control unit 20 that sets a voltage of the bit line BLB on the low-voltage power side to a predetermined voltage VBLL higher than a voltage VSS of the low voltage power in a state where a predetermined operation is not being performed and the sense amplifier 10 retains data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] For example, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is configured to generate a weak potential difference between a pair of bit lines based on data stored in a memory cell, and amplify this potential difference using a sense amplifier to read data. A typical sense amplifier is known to include a pair of N-channel field effect transistors (nMOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)) and a pair of P-channel field effect transistors (pMOSFETs) (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 08-139290 Summary of the Invention [Problem to be solved by the invention]

[0004] The operating voltage of semiconductor memory devices is decreasing in response to the trend toward lower power consumption. This decrease in operating voltage also leads to a decrease in the threshold voltage of transistors in sense amplifiers. Furthermore, when the voltage of the bit line on the low-voltage power supply side of a pair of bit lines is set to 0V while the sense amplifier is retaining data (after sensing data), at least one transistor connected to the bit line on the low-voltage power supply side will have a gate-source voltage of 0V. However, a decrease in the threshold voltage of a transistor may increase leakage current generated by the transistor whose gate-source voltage is 0V while the sense amplifier is retaining data.

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a semiconductor memory device capable of reducing the leakage current generated in a sense amplifier in a data holding state, and a control method thereof. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a semiconductor memory device comprising: a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to the bit line on the low-voltage power supply side of the pair of bit lines; and a control unit that sets the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply when a predetermined operation is not being performed and the sense amplifier is retaining data.

[0007] According to this invention, when a predetermined operation is not being performed and the sense amplifier is holding data, the voltage of the bit line on the low-voltage power supply side is set to a predetermined voltage higher than the voltage of the low-voltage power supply. For example, when the voltage of the low-voltage power supply is 0 V, the back gate-source voltage of a transistor whose gate-source voltage is 0 V becomes a negative voltage, and the threshold voltage of the transistor increases due to the back bias effect, thereby making it possible to reduce the leakage current generated in the transistor. This makes it possible to reduce the leakage current generated in the sense amplifier in the data holding state.

[0008] The present invention also provides a method for controlling a semiconductor memory device, wherein the semiconductor memory device includes a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to the bit line on the low-voltage power supply side of the pair of bit lines, and a control unit of the semiconductor memory device executes a step of setting the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply when a predetermined operation is not being performed and the sense amplifier is retaining data. [Effects of the Invention]

[0009] According to the semiconductor memory device and the control method thereof of the present invention, it is possible to reduce the leakage current generated in the sense amplifier in the data holding state. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a control unit. [Figure 3] 10A and 10B are diagrams illustrating an example of voltage changes of each control signal and a bit line on a low-voltage power supply side. [Figure 4] FIG. 10 is a diagram illustrating another example of the configuration of the control unit. DETAILED DESCRIPTION OF THE INVENTION

[0011] 1 and 2 are diagrams showing an example of the configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in Fig. 1 and 2, the semiconductor memory device includes at least one sense amplifier 10 connected to a pair of complementary bit lines BLT and BLB, and a control unit 20. In this embodiment, to simplify the explanation, detailed explanations of other components well known in semiconductor memory devices (e.g., a power supply circuit, a command decoder, an address decoder, a clock generator, etc.) will be omitted.

[0012] Furthermore, in this embodiment, the semiconductor memory device is described as a DRAM by way of example, but the semiconductor memory device may be another type of semiconductor memory device (for example, a static random access memory (SRAM), a flash memory, etc.).

[0013] The sense amplifier 10 is a cross-coupled latch type sense amplifier, and includes a pair of P-channel field effect transistors (pMOSFETs) 10a and 10b and a pair of N-channel field effect transistors (nMOSFETs) 10c and 10d, as shown in Fig. 1. Here, the pMOSFETs 10a and 10b are an example of a "pair of first transistors" in the present invention, and the nMOSFETs 10c and 10d are an example of a "pair of second transistors" in the present invention.

[0014] Of the pair of pMOSFETs 10a, 10b, one pMOSFET 10a has a source terminal connected to a node CSP on the high-voltage power supply side, a drain terminal connected to a bit line BLT on the high-voltage power supply side, and a gate terminal connected to a bit line BLB on the low-voltage power supply side. The other pMOSFET 10b of the pair of pMOSFETs 10a, 10b has a source terminal connected to a node CSP on the high-voltage power supply side, a drain terminal connected to a bit line BLB on the low-voltage power supply side, and a gate terminal connected to a bit line BLT on the high-voltage power supply side. In this embodiment, a case where the voltage of the high-voltage power supply is 1 V and the voltage VSS of the low-voltage power supply is 0 V will be described as an example.

[0015] Furthermore, the drain terminal of one nMOSFET 10c of the pair of nMOSFETs 10c, 10d is connected to the bit line BLT on the high-voltage power supply side, the source terminal is connected to the node CSN on the low-voltage power supply side, and the gate terminal is connected to the bit line BLB on the low-voltage power supply side.Furthermore, the drain terminal of the other nMOSFET 10d of the pair of nMOSFETs 10c, 10d is connected to the bit line BLB on the low-voltage power supply side, the source terminal is connected to the node CSN on the low-voltage power supply side, and the gate terminal is connected to the bit line BLT on the high-voltage power supply side.

[0016] The bit line BLT on the high-voltage power supply side is connected to one local data line LDQT of a pair of complementary local data lines LDQT, LDQB via an nMOSFET 10e, the gate terminal of which receives a column select signal CSL corresponding to an externally input column address. The bit line BLB on the low-voltage power supply side is connected to the other local data line LDQB of the pair of complementary local data lines LDQT, LDQB via an nMOSFET 10f, the gate terminal of which receives the column select signal CSL. A memory cell 11 is connected to the bit line BLB on the low-voltage power supply side. The memory cell 11 may have a well-known configuration, for example, including an nMOSFET 11a, the gate terminal of which receives a row select signal WL, and a capacitor 11b.

[0017] The configuration of the sense amplifier 10 shown in FIG. 1 is an example, and the sense amplifier 10 may include other circuits (for example, an equalizer circuit) not shown in FIG.

[0018] Here, when the voltage of the bit line BLB on the low-voltage power supply side of the pair of bit lines BLT and BLB is set to 0 V while the sense amplifier 10 is retaining data (after sensing data), the gate-source voltages of the pMOSFET 10b, nMOSFET 10c, and nMOSFET 10f are 0 V. In this case, if the operating voltage of the semiconductor memory device decreases in response to a reduction in power consumption of the semiconductor memory device, the threshold voltages of the pMOSFET 10b, nMOSFET 10c, and nMOSFET 10f also decrease, which may increase the leakage current generated in each of the pMOSFET 10b, nMOSFET 10c, and nMOSFET 10f while the sense amplifier is retaining data. Therefore, in this embodiment, while the sense amplifier is retaining data, the voltage of the bit line BLB on the low-voltage power supply side is set to a predetermined voltage VBLL higher than the voltage VSS of the low-voltage power supply (e.g., 0 V).

[0019] 2, a configuration example of the control unit 20 will be described. The control unit 20 is configured to set the voltage of the bit line BLB on the low-voltage power supply side to a predetermined voltage VBLL higher than the voltage VSS of the low-voltage power supply when a predetermined operation is not being performed and the sense amplifier 10 is holding data.

[0020] Furthermore, when a predetermined operation is performed in a state in which the voltage of the bit line BLB on the low-voltage power supply side is set to a predetermined voltage VBLL, the control unit 20 may set the voltage of the bit line BLB on the low-voltage power supply side to the voltage VSS of the low-voltage power supply. This sets the voltage of the bit line BLB on the low-voltage power supply side to the voltage VSS when the predetermined operation is performed, making it possible to perform the predetermined operation normally.

[0021] Here, the predetermined operation may include at least one of reading and writing data stored in the memory cell 11 connected to the sense amplifier 10, and precharging the pair of bit lines BLT and BLB. This makes it possible to set the voltage of the bit line BLB on the low-voltage power supply side to a predetermined voltage VBLL when at least one of reading and writing data stored in the memory cell 11 and precharging the pair of bit lines BLT and BLB is not performed.

[0022] The predetermined voltage VBLL may be lower than the voltage (1 V in this embodiment) of the bit line BLT, which is the bit line BLT on the higher voltage power supply side of the pair of bit lines BLT and BLB. This makes it possible to generate a potential difference between the pair of bit lines BLT and BLB when the sense amplifier 10 is holding data.

[0023] As shown in FIG. 2, the control unit 20 includes a first supply unit 21 that supplies the voltage VSS of the low-voltage power supply to the bit line BLB on the low-voltage power supply side, and a second supply unit 22 that supplies a predetermined voltage VBLL to the bit line BLB on the low-voltage power supply side when a predetermined operation is not being performed.

[0024] The first supply unit 21 includes a first switch unit 21a that supplies a predetermined voltage VBLL supplied from the second supply unit 22 to the bit line BLB on the low-voltage power supply side when a first control signal PD indicating that a predetermined operation is not to be performed is input, and a second switch unit 21b that supplies a voltage VSS of the low-voltage power supply to the bit line BLB on the low-voltage power supply side when a second control signal NSE indicating that a predetermined operation is to be performed is input.

[0025] In this embodiment, the first switch section 21a is configured with an nMOSFET. The drain terminal of this nMOSFET is connected to a node CSN on the low-voltage power supply side of each sense amplifier 10, and the source terminal is connected to the second supply section 22. A first control signal PD is input to the gate terminal. When a high-level first control signal PD indicating that a predetermined operation is not to be performed is input to the gate terminal of the first switch section 21a, the first switch section 21a supplies a predetermined voltage VBLL supplied from the second supply section 22 to the node CSN on the low-voltage power supply side of each sense amplifier 10. The predetermined voltage VBLL is then supplied to the bit line BLB on the low-voltage power supply side.

[0026] In this embodiment, the second switch section 21b is configured with an nMOSFET. The drain terminal of this nMOSFET is connected to a node CSN on the low-voltage power supply side of each sense amplifier 10, and the source terminal is connected to a voltage VSS of the low-voltage power supply. A second control signal NSE is input to the gate terminal. When a high-level second control signal NSE indicating that a predetermined operation is to be performed is input to the gate terminal, the second switch section 21b supplies the voltage VSS of the low-voltage power supply to the node CSN on the low-voltage power supply side of each sense amplifier 10. The voltage VSS of the low-voltage power supply is then supplied to the bit line BLB on the low-voltage power supply side.

[0027] The first control signal PD and the second control signal NSE may be complementary to each other. The first control signal PD and the second control signal NSE may be generated in the control unit 20 or by another circuit provided in the semiconductor memory device.

[0028] The second supply unit 22 includes a comparator 22a and a switch unit 22b. The comparator 22a has a first terminal (+ terminal) to which the voltage of the bit line BLB on the low-voltage power supply side is input (connected to a node CSN on the low-voltage power supply side of each sense amplifier 10), and a second terminal (- terminal) to which a reference voltage VREF (=predetermined voltage VBLL) is input. The output terminal of the comparator 22a is connected to the switch unit 22b. In this embodiment, the switch unit 22b is configured by an nMOSFET. The drain terminal of this nMOSFET is connected to a node CSN on the low-voltage power supply side of each sense amplifier 10 via the first switch unit 21a of the first supply unit 21, and the source terminal is connected to the voltage VSS of the low-voltage power supply. The gate terminal receives a signal output from the comparator 22a. With this configuration, the second supply unit 22 outputs the predetermined voltage VBLL.

[0029] An example of the operation of the control unit 20 will be described with reference to FIG. 3. First, assume that a predetermined operation (either reading or writing data stored in the memory cell 11, or precharging the pair of bit lines BLT and BLB) is being performed in the semiconductor memory device. In this case, the first control signal PD is at a low level, and the second control signal NSE is at a high level. At this time, the control unit 20 supplies the voltage VSS of the low-voltage power supply to the node CSN on the low-voltage power supply side of each sense amplifier 10. As a result, the voltage VSS of the low-voltage power supply is supplied to the bit line BLB on the low-voltage power supply side.

[0030] Next, when the predetermined operation is completed (when the predetermined operation is not performed) and the sense amplifiers 10 are holding data, at time t0, the first control signal PD goes high and the second control signal NSE goes low. At this time, the control unit 20 supplies a predetermined voltage VBLL to the node CSN on the low-voltage power supply side of each sense amplifier 10. As a result, the predetermined voltage VBLL is supplied to the bit line BLB on the low-voltage power supply side.

[0031] Here, when a predetermined operation is not being performed and the sense amplifier 10 is holding data, the voltage of the bit line BLB on the low-voltage power supply side is set to a predetermined voltage VBLL that is higher than the voltage VSS of the low-voltage power supply. As a result, for example, the back gate-source voltage of a transistor (nMOSFET 10c, nMOSFET 10f in the example shown in FIG. 1) whose gate-source voltage is 0V when the voltage VSS of the low-voltage power supply is 0V becomes negative, and the threshold voltage of the transistors 10c and 10f increases due to the back bias effect, thereby reducing the leakage current generated in the transistors 10c and 10f.

[0032] Next, at time t1, when a predetermined operation (either reading or writing data stored in the memory cell 11, or precharging the pair of bit lines BLT and BLB) is performed, the first control signal PD goes low and the second control signal NSE goes high. At this time, the control unit 20 supplies the voltage VSS of the low-voltage power supply to the node CSN on the low-voltage power supply side of each sense amplifier 10. In this way, when the predetermined operation is performed, the voltage of the bit line BLB on the low-voltage power supply side is set to the voltage VSS, making it possible to perform the predetermined operation normally.

[0033] As described above, according to the semiconductor memory device and control method thereof of this embodiment, when a predetermined operation is not being performed and the sense amplifier 10 is retaining data, the voltage of the bit line BLB on the low-voltage power supply side is set to a predetermined voltage VBLL higher than the voltage VSS of the low-voltage power supply. This causes, for example, the back gate-source voltage of transistors (nMOSFET 10c and nMOSFET 10f in the example shown in FIG. 1 ) whose gate-source voltage is 0V when the voltage of the low-voltage power supply is 0V to become negative. This increases the threshold voltage of the transistors 10c and 10f due to the back bias effect, thereby reducing the leakage current generated in the transistors 10c and 10f. Furthermore, since the gate-source voltage of the nMOSFET 10f becomes negative, the leakage current generated in the nMOSFET 10f can be reduced. This reduces the leakage current generated in the sense amplifier 10 in the data retention state.

[0034] The above-described embodiments have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, each element disclosed in the above embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0035] For example, in the above-described embodiment, the control unit 20 has been described as having the configuration shown in FIG. 2 as an example, but the present invention is not limited to this. For example, the control unit 20 may have another configuration as shown in FIG. 4. Referring to FIG. 4, the first supply unit 21 of the control unit 20 includes a first switch unit 21a, a second switch unit 21b, a third switch unit 21c, and a fourth switch unit 21d. Here, the configurations of the first switch unit 21a and the second switch unit 21b are the same as those in the above-described embodiment.

[0036] The third switch section 21c is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to node CSN on the low-voltage power supply side of each sense amplifier 10, and the source terminal is connected to the drain terminal of the nMOSFET constituting the fourth switch section 21d. The signal output from comparator 22a of second supply section 22 is input to the gate terminal of this nMOSFET.

[0037] The fourth switch section 21d is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the source terminal of the third switch section 21c, the source terminal is connected to the voltage VSS of the low-voltage power supply, and the first control signal PD is input to the gate terminal.

[0038] 4 includes a comparator 22a, a NOT circuit 22c, and a switch unit 22d. The comparator 22a has the same configuration as in the above-described embodiment. A first control signal PD is input to the NOT circuit 22c. The switch unit 22d is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to a node CSN on the low-voltage power supply side of each sense amplifier 10 via the first switch unit 21a of the first supply unit 21, and the source terminal is connected to the voltage VSS of the low-voltage power supply. The signal output from the NOT circuit 22c is input to the gate terminal.

[0039] The control unit 20 configured as shown in FIG. 4 can also operate in the same manner as in the embodiment when the control signals PD and NSE are input as shown in FIG.

[0040] 2 and 4, the case where each of the switch sections 21a, 21b, 21c, 21d, 22b, and 22d is configured with a MOSFET has been described as an example, but the present invention is not limited to this. For example, each of the switch sections 21a, 21b, 21c, 21d, 22b, and 22d may be configured with a transistor other than a MOSFET, or may be configured with an element or circuit other than a transistor.

[0041] 2 and 4, the control unit 20 includes one first supply unit 21 and one second supply unit 22. However, the present invention is not limited to this. For example, the control unit 20 may include multiple first supply units 21 and one second supply unit 22. In this case, similar to the example shown in FIGS. 2 and 4, each of the multiple first supply units 21 may be connected to a node CSN on the low-voltage power supply side of each of the multiple sense amplifiers 10, and one second supply unit 22 may be connected to each of the multiple first supply units 21. This allows the single second supply unit 22 to supply a predetermined voltage VBLL to the bit line BLB on the low-voltage power supply side via each of the multiple first supply units 21.

[0042] Furthermore, the configurations of the sense amplifier 10 and the control unit 20 in the above-described embodiment are merely examples, and may be changed as appropriate, or various other configurations may be adopted. [Explanation of symbols]

[0043] 10...Sense amplifier (SA) 10a, 10b...A pair of P-channel field effect transistors (pMOSFETs) 10c, 10d...A pair of N-channel field-effect transistors (nMOSFETs) 11...Memory cell 20...Control unit 21...1st supply section 21a...First switch section 21b...Second switch section 22...Second supply section 22a...Comparator BLT, BLB...a pair of bit lines NSE: Second control signal PD...First control signal VBLL: Predetermined voltage VSS: Low voltage power supply voltage

Claims

1. a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to a bit line of the pair of bit lines on the low voltage power supply side; a control unit that sets the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply when a predetermined operation is not being performed and the sense amplifier is holding data; the control unit sets the voltage of the bit line on the low-voltage power supply side to the voltage of the low-voltage power supply when the predetermined operation is performed in a state in which the voltage of the bit line on the low-voltage power supply side is set to the predetermined voltage; the predetermined operation includes precharging the pair of bit lines; Semiconductor memory device.

2. the predetermined operation further includes, in addition to the precharge, at least one of reading and writing data stored in a memory cell connected to the sense amplifier; 2. The semiconductor memory device according to claim 1.

3. The control unit one or more first supply units that supply the voltage of the low voltage power supply to bit lines on the low voltage power supply side; a second supply unit that supplies the predetermined voltage to the bit line on the low-voltage power supply side when the predetermined operation is not being performed; 2. The semiconductor memory device according to claim 1.

4. The first supply unit is a first switch unit that supplies the predetermined voltage supplied from the second supply unit to the bit line on the low voltage power supply side when a first control signal indicating that the predetermined operation is not to be performed is input; a second switch unit that supplies the voltage of the low-voltage power supply to the bit line on the low-voltage power supply side when a second control signal indicating that the predetermined operation is to be performed is input.

4. The semiconductor memory device according to claim 3.

5. The second supply unit is a comparator having a first terminal to which the voltage of the bit line on the low voltage power supply side is input, and a second terminal to which the predetermined voltage is input; 5. The semiconductor memory device according to claim 3.

6. the predetermined voltage is lower than the voltage of the bit line of the pair of bit lines on the high-voltage power supply side; 2. The semiconductor memory device according to claim 1.

7. The sense amplifier a pair of first transistors, one of which is connected to a bit line on a high-voltage power supply side and the other of which is connected to a bit line on a low-voltage power supply side; a pair of second transistors, one of which is connected to a bit line on a high-voltage power supply side and the other of which is connected to a bit line on a low-voltage power supply side; 2. The semiconductor memory device according to claim 1.

8. one of the pair of first transistors and the pair of second transistors is an N-channel field effect transistor, and the other of the pair of first transistors and the pair of second transistors is a P-channel field effect transistor; 8. The semiconductor memory device according to claim 7.

9. The voltage of the low voltage power supply is 0 V.

2. The semiconductor memory device according to claim 1.

10. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device comprises: a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to a bit line of the pair of bit lines on the low voltage power supply side; a control unit of the semiconductor memory device, setting a voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply when a predetermined operation is not being performed and the sense amplifier is holding data; when the predetermined operation is performed in a state in which the voltage of the bit line on the low-voltage power supply side is set to the predetermined voltage, the voltage of the bit line on the low-voltage power supply side is set to the voltage of the low-voltage power supply; the predetermined operation includes precharging the pair of bit lines; A method for controlling a semiconductor memory device.

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