Analog-Digital Hybrid Integrator

Abstract

To provide an analog-digital hybrid integrator simultaneously performing integration and digital conversion of an input signal.SOLUTION: An analog-digital hybrid integrator includes: an operational amplifier 110 coupled to an input terminal; a first capacitor 120 coupled to an input terminal in parallel with the operational amplifier; a plurality of second capacitors 130 coupled in parallel with the first capacitor 120; and a plurality of buffers 140 coupled in series with each other and coupled in parallel with the plurality of second capacitors 130, respectively.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an analog-digital hybrid integrator. [Background technology]

[0002] Integrators are a key mixed-signal circuit building block, primarily used in analog-to-digital converters and delta-sigma modulators. A switched-capacitor integrator periodically charges an input capacitor and integrates the charge on an integrating capacitor.

[0003] Conventional active integrators are used in various ADCs to shape noise and achieve high gain at the expense of high power consumption for high performance.

[0004] Active integrators are classified into analog integrators, digital integrators, and analog-digital hybrid integrators.

[0005] FIG. 1 is a circuit diagram showing a conventional analog integrator.

[0006] Referring to Figure 1, an analog operational amplifier 1 integrates an analog input signal (Vin) and stores it in a capacitor 2. An analog output signal (Vout) is generated by the charge stored in the capacitor 2. In this case, the analog operational amplifier 1 consumes high static power.

[0007] FIG. 2 is a circuit diagram showing a conventional digital integrator.

[0008] Referring to FIG. 2, the digital operational amplifier 3 integrates a digital input signal (Vin) and then outputs a unit cycle delay (unit cycle delay z -1 ) 4. In this case, the digital integrator integrates the quantized signal, resulting in an output signal with quantization errors.

[0009] Digital integrators have a limit to the precision they can store. For example, when storing the number X = 0.3218231..., if a digital integrator with a precision of 0.01 is used, the number will be stored as 0.322, and the error (0.322 - 0.3218231... = 0.000177...) will remain as an error, and the digital integrator will generate an amplified error as the number of integrations increases.

[0010] FIG. 3 is a circuit diagram showing a conventional analog-digital hybrid integrator.

[0011] 3, an analog operational amplifier 1 receives an analog input signal (Vin) that is converted into a digital signal by a quantizer 5, fed back, and integrated by a capacitor 2, and then generates an analog output signal. The analog-digital hybrid integrator stores the digitalized version of the analog input signal and also stores the analog output signal. Conventional analog-digital hybrid integrators cannot perform continuous integration, and can only perform integration after quantization of the analog input signal, resulting in a time delay.

[0012] FIG. 4 is a circuit diagram showing another conventional analog-digital hybrid integrator.

[0013] Referring to Figure 4, an analog operational amplifier (op-amp) 1 integrates an analog input signal (Vin) using a capacitor 2, converts it to a digital signal using a quantizer 5, and feeds it back. The analog-digital hybrid integrator stores the digital version of the analog input signal and also stores the analog output signal. Conventional analog-digital hybrid integrators exhibit increased nonlinearity due to mismatch between the quantizer and the feedback capacitor, and a one-clock time delay occurs because integration is performed after quantization of the analog input signal. Summary of the Invention [Problem to be solved by the invention]

[0014] The present invention has been devised to solve the above-mentioned problems, and an object of the present invention is to provide an analog-digital hybrid integrator that simultaneously performs integration and digital conversion of an input signal.

[0015] It is also an object of the present invention to provide an analog-digital hybrid integrator that can store both a digitally quantized signal and an analog residual signal and perform continuous integration.

[0016] It is a further object of the present invention to provide an analog-digital hybrid integrator that eliminates mismatch between the digitally quantized signal and the feedback capacitor, minimizing the time delay between the quantization of the input signal and the integration action.

[0017] The object of the present invention is not limited to the above-mentioned object, and other unmentioned objects will be easily understood from the following description. The technical problem of the present invention is not limited to the above-mentioned technical problem, and other unmentioned technical problems will be easily understood by a person skilled in the art from the following description. [Means for solving the problem]

[0018] An analog-digital hybrid integrator according to one embodiment of the present invention includes an operational amplifier connected to an input terminal, a first capacitor connected to the input terminal in parallel with the operational amplifier, a plurality of second capacitors connected in parallel with the first capacitor, and a plurality of buffers connected in series with each other and in parallel with the plurality of second capacitors, respectively.

[0019] The operational amplifier provides output voltages to the plurality of buffers, respectively.

[0020] The plurality of buffers are connected in series to form a delay chain.

[0021] The plurality of buffers include a first buffer that receives an input of “1” and outputs “1”, a second buffer that receives an input of “0” and outputs “0”, a third buffer that receives an input of “0” state and outputs “1” state, forming a rising edge, and a fourth buffer that receives an input of “1” state and outputs “0” state, forming a falling edge.

[0022] In an initial state, the number of the first buffers is equal to the number of the second buffers.

[0023] If the output voltage fed back from the operational amplifier to the buffer is greater than the existing voltage, the fourth buffer outputs "1" and changes to the first buffer, increasing the number of the first buffers, and the fourth buffer forming the falling edge propagates and moves in the direction of the second buffer.

[0024] If the output voltage fed back from the operational amplifier to the buffer is smaller than the existing voltage, the third buffer outputs "0" and changes to the second buffer, increasing the number of the second buffers, and the third buffer forming the rising edge propagates and moves in the direction of the first buffer.

[0025] An analog-digital hybrid integrator according to another embodiment of the present invention includes an operational amplifier that receives and integrates a subtraction signal obtained by subtracting a quantized output signal from an input signal; a first capacitor that stores a residual signal; a plurality of buffers that quantize the output signal of the operational amplifier and are connected in series; a plurality of second capacitors that store the input signal and the quantized output signals of the plurality of buffers; a first switch that is connected between an input terminal and the plurality of second capacitors and between the plurality of second capacitors and a ground terminal, and that switches the input signal of the input terminal and outputs it to the plurality of second capacitors; and a second switch that is connected between output terminals of the plurality of buffers and the plurality of second capacitors and between the plurality of second capacitors and the operational amplifier, and that switches the subtraction signal and outputs it to the operational amplifier.

[0026] An analog-digital hybrid integrator according to another embodiment of the present invention further includes a first reset switch connected in parallel with the first capacitor and the operational amplifier, for resetting a residual signal of the first capacitor.

[0027] An analog-digital hybrid integrator according to another embodiment of the present invention further includes a second reset switch connected to the output terminals of the plurality of buffers, receiving a reference voltage (Vref) when on, and resetting the plurality of buffers and the plurality of second capacitors to their initial states.

[0028] When the first switch is in an on state and the second switch is in an off state, the input signal at the input terminal is stored in the plurality of second capacitors.

[0029] When the first switch is in an off state and the second switch is in an on state, the plurality of buffers output the quantized output signals to the plurality of second capacitors, and the plurality of second capacitors output subtracted signals obtained by subtracting the stored analog input signals from the quantized output signals of the plurality of buffers to the operational amplifier. [Effects of the Invention]

[0030] According to the analog-digital hybrid integrator of the embodiment of the present invention, it is driven almost entirely as a capacitor in the digital domain, which allows the capacitor size in the analog domain to be reduced, and the power consumption of the operational amplifier to be significantly reduced.

[0031] Furthermore, the analog-digital hybrid integrator according to the embodiment of the present invention does not require an additional quantizer, ensuring energy efficiency and compact structure.

[0032] According to the analog-digital hybrid integrator of the embodiment of the present invention, the circularly connected buffer chains can achieve high speed since separate integration and quantization are performed simultaneously.

[0033] According to an analog-digital hybrid integrator according to an embodiment of the present invention, edges are continuously propagated through continuous operation in a circular delay chain structure, thereby achieving high linearity and a capacitor mismatch shaping effect without the need for a separate circuit.

[0034] The effects of the present invention are not limited to those described above, and other effects not mentioned will be easily understood by those skilled in the art from the following description. [Brief explanation of the drawings]

[0035] [Figure 1] FIG. 1 is a circuit diagram showing a conventional analog integrator. [Figure 2] FIG. 1 is a circuit diagram showing a conventional digital integrator. [Figure 3] FIG. 1 is a circuit diagram illustrating a conventional analog-digital hybrid integrator. [Figure 4] FIG. 1 is a circuit diagram showing another conventional analog-digital hybrid integrator. [Figure 5] FIG. 1 is a circuit diagram illustrating an analog-digital hybrid integrator according to an embodiment of the present invention. [Figure 6] FIG. 2 is a circuit diagram illustrating a delay chain of an analog-digital hybrid integrator according to one embodiment of the present invention. [Figure 7] FIG. 2 is a circuit diagram illustrating the feedback operation of an analog-digital hybrid integrator according to an embodiment of the present invention. [Figure 8] FIG. 10 is a circuit diagram illustrating an analog-digital hybrid integrator according to another embodiment of the present invention. [Figure 9] FIG. 10 is a diagram illustrating the operation state of an analog-digital hybrid integrator according to another embodiment of the present invention for a Φ1 signal. [Figure 10] FIG. 10 is a diagram illustrating the operation state of an analog-digital hybrid integrator according to another embodiment of the present invention for a Φ2 signal. [Figure 11] 1A is a timing diagram showing a reset clock that resets a first capacitor; FIG. 1B is a timing diagram showing a clock signal that controls the on / off operation of a first switch and a second switch; FIG. 1C is a timing diagram showing an output signal that is fed back from an operational amplifier; FIG. 1D is a timing diagram showing a quantized output signal from a buffer; and FIG. 1E is a timing diagram showing an input signal and a final output that has undergone digital signal processing of an analog-digital hybrid integrator according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] The present invention can be modified in various ways and can have various embodiments, and a specific embodiment will be described in detail with reference to the drawings. However, this does not limit the present invention to the specific embodiment, and it should be understood that the present invention includes all modifications, equivalents, and alternatives within the spirit and technical scope of the present invention. In each drawing, similar components are designated by the same reference numerals.

[0037] Although terms such as "first," "second," "A," and "B" are used to describe various components, the components are not limited by these terms. These terms are used merely to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component, without departing from the scope of the present invention. The term "and / or" means the inclusion of a combination of two or more related listed items or any of two or more related listed items.

[0038] When a component is "connected" or "coupled" to another component, it should be understood that the component may be directly connected or coupled to the other component, but that there may be other components between them. In contrast, when a component is "directly connected" or "directly coupled" to another component, it should be understood that there is no other component between them.

[0039] The terms used in this specification are merely for the purpose of describing particular embodiments and are not intended to limit the present invention. The singular expressions include the plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprise" or "have" are intended to specify the presence of a feature, numeral, step, operation, component, part, or combination thereof described in the specification, but do not exclude the presence or possibility of addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof.

[0040] It should also be noted that terms such as "first," "second," etc. are used herein for distinction purposes only and are not meant to indicate or predict priority or precedence.

[0041] Unless otherwise specified, all terms, including technical or scientific terms, used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0042] Throughout the specification and claims, an expression that a part includes a certain element does not mean that it can further include other elements, but does not mean that it excludes other elements, unless otherwise specified.

[0043] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0044] Figure 5 is a circuit diagram illustrating an analog-digital hybrid integrator according to an embodiment of the present invention, and Figure 6 is a circuit diagram illustrating a delay chain of an analog-digital hybrid integrator according to an embodiment of the present invention.

[0045] Referring to FIG. 5, an analog-digital hybrid integrator according to one embodiment of the present invention includes an operational amplifier 110 connected to an input terminal, a first capacitor 120 connected in parallel with the operational amplifier 110 at the input terminal, a plurality of second capacitors 130 connected in parallel with the first capacitor 120, and a plurality of buffers 140 connected in series with each other and connected in parallel with the plurality of second capacitors 130, respectively.

[0046] The operational amplifier 110 integrates the analog input signal in the analog domain and generates an output voltage that controls the second capacitor 130 and the buffer 140 that make up the delay chain.

[0047] The first capacitor 120 forms an analog domain together with the operational amplifier 110 and stores the analog signal integrated by the operational amplifier 110 .

[0048] 5 and 6, the second capacitor 130 is connected in parallel with the first capacitor 120, and together with the buffer 140 constitutes a digital domain, and operates by receiving the output of the operational amplifier 110 as a control signal. The number of second capacitors 130 may be the same as the number of buffers 140.

[0049] 5 and 6, the buffer 140 may be an even number of buffers, and operates as an n-bit quantizer, so that 2 n For example, the buffer 140 may consist of 2 5 = 32 pieces.

[0050] Alternatively, the buffer 140 may be an odd number of bits and operates as an n-bit quantizer, so that 2 n For example, the buffer 140 operates as a 5-bit quantizer, so 5 It may consist of -1=31 pieces.

[0051] The buffers 140 are connected in series to each other and driven as a circular delay chain. The buffers 140 are connected to the output terminals of the operational amplifiers 110, and receive the output voltages of the operational amplifiers 110 as inputs.

[0052] The buffers 140 are arranged between the output terminals of the second capacitors 130 and are connected in series with each other, so that the buffers 140 are connected in parallel with the second capacitors 130 and the first capacitors 120.

[0053] The operation of the analog-digital hybrid integrator according to one embodiment of the present invention will now be described: Figure 7 is a circuit diagram showing the feedback operation of the analog-digital hybrid integrator according to one embodiment of the present invention.

[0054] 7, in an analog-digital hybrid integrator, an analog input signal varies the voltage output from an operational amplifier 110. The varied output voltage is input to a buffer 140, which operates as a circular delay chain, forming a feedback loop.

[0055] In the initial state, the buffer 140 includes a first buffer 141 that receives an input of "1" and outputs "1", and a second buffer 142 that receives an input of "0" and outputs "0". In the initial state, the number of first buffers 141 may be the same as the number of second buffers 142.

[0056] The buffer 140 also includes a third buffer 143 that receives an input of a "0" state, outputs a "1" state, and forms a rising edge, and a fourth buffer 144 that receives an input of a "1" state, outputs a "0" state, and forms a falling edge.

[0057] For example, if buffer 140 consists of 32 buffers to represent 5 bits, there are 15 first buffers 141, 15 second buffers 142, one third buffer 143 is placed between first buffer 141 and second buffer 142, and one fourth buffer 144 is placed between first buffer 141 and second buffer 142.

[0058] If the output voltage fed back from operational amplifier 110 to buffer 140 is greater than the existing voltage, fourth buffer 144 changes to first buffer 141, which receives an input of "1" state and outputs "1", and second buffer 142 connected to fourth buffer 144 changes to first buffer 141 via fourth buffer 144 up to the magnitude of the fed back output voltage.

[0059] In other words, if the fed back output voltage is greater than the existing voltage, the fourth buffer 144 of the falling edge outputs "1" and changes to the first buffer 141, thereby increasing the number of first buffers 141, and the fourth buffer 144 forming the falling edge propagates and moves in the direction of the second buffer 142.

[0060] On the other hand, if the output voltage fed back from the operational amplifier 110 to the buffer 140 is smaller than the existing voltage, the third buffer 143 changes to the second buffer 142 that receives an input of the "0" state and outputs "0", and the first buffer 141 connected to the third buffer 143 changes to the second buffer 142 via the third buffer 143 up to the magnitude of the feedback output voltage.

[0061] In other words, when the fed back output voltage is smaller than the existing voltage, the third buffer 143 of the rising edge outputs "0" and changes to the second buffer 142, thereby increasing the number of second buffers 142, and the third buffer 143 forming the rising edge propagates and moves in the direction of the first buffer 141.

[0062] A second capacitor 130 samples and stores the output of buffer 140 in its changed state.

[0063] Once this operation is complete, the second capacitor 130 outputs a portion of the input voltage as a quantized digital signal, and the analog operational amplifier 110 outputs the remainder of the input voltage as an analog residue signal.

[0064] For example, we will describe a case where buffer 140 consists of 32 buffers to represent 5 bits, and in the initial state, there are 15 first buffers 141, 15 second buffers 142, one third buffer 143 is placed between first buffer 141 and second buffer 142, and one fourth buffer 144 is placed between first buffer 141 and second buffer 142.

[0065] When the input voltage is +10.4, the number of first buffers 141 that output "1" among the buffers 140 increases by 10 to 25, and the second capacitors 130 connected to the increased number of first buffers 141 sample 10, storing "1" respectively. After that, the second capacitors 130 output a quantized digital signal of "10," and when the operational amplifier 110 outputs 0.4, which is the remainder of the input voltage, the first capacitor 120 stores 0.4, which is the analog output signal.

[0066] In this state, if an additional input signal of +3.92 is input, the analog-digital hybrid integrator of the present invention represents a total of +14.32, so four of the buffers 140 in the "0" state are further changed to first buffers 141, and propagation to the fourth buffer 144 is carried out until a total of 19 first buffers 141 are present. As a result, the second capacitors 130 connected to the increased first buffers 141 sample the increased number of first buffers 141, which is 4, and store "1" in each. After that, the second capacitors 130 output a quantized digital signal of "14," and when the operational amplifier 110 outputs 0.32, which is the remainder of the input voltage, the first capacitor 120 stores 0.32, which is the analog output signal.

[0067] This allows an analog-digital hybrid integrator according to one embodiment of the present invention to continuously integrate an input signal without resetting.

[0068] An analog-digital hybrid integrator according to another embodiment of the present invention will now be described. Figure 8 is a circuit diagram showing an analog-digital hybrid integrator according to another embodiment of the present invention.

[0069] 8, an analog-digital hybrid integrator according to another embodiment of the present invention includes an operational amplifier 110 that receives and integrates a subtraction signal obtained by subtracting a quantized output signal from an input signal; a first capacitor 120 that stores a residual signal; a plurality of buffers 140 that quantize the output signal of the operational amplifier 110 and are connected in series; a plurality of second capacitors 130 that store the input signal and the quantized output signals of the plurality of buffers; a first switch 150 that is connected between an input terminal and the plurality of second capacitors 130 and between the plurality of second capacitors 130 and a ground terminal and switches an input signal at the input terminal to output the input signal to the plurality of second capacitors 130; and a second switch 160 that is connected between an output terminal of the plurality of buffers 140 and the plurality of second capacitors 130 and between the plurality of second capacitors 130 and the operational amplifier 110 and switches the subtraction signal to output the input signal to the operational amplifier 110.

[0070] Referring to FIG. 8 , an analog-digital hybrid integrator according to another embodiment of the present invention may further include a first reset switch 170 connected in parallel with the first capacitor 120 and the operational amplifier 110 to reset the residual signal of the first capacitor 110.

[0071] In addition, an analog-digital hybrid integrator according to another embodiment of the present invention may further include a second reset switch (not shown) connected to the output terminals of the plurality of buffers 140, receiving a reference voltage (Vref) when turned on, and resetting the plurality of buffers 140 and the plurality of second capacitors 130 to their initial states.

[0072] The operational amplifier 110 integrates the analog input signal in the analog domain and provides an output signal to each buffer 140 that controls a second capacitor 130 and a buffer 140 that form a delay chain.

[0073] The first capacitor 120 forms an analog domain together with the operational amplifier 110 and stores the analog signal integrated by the operational amplifier 110 .

[0074] The buffer 140 may be an even number, for example, 2 to operate as a 5-bit quantizer. 5 = 32. The buffers 140 are connected in series with each other and driven as a circular delay chain.

[0075] Alternatively, the buffer 140 may be an odd number of bits and operates as an n-bit quantizer, so that 2 n For example, the buffer 140 operates as a 5-bit quantizer, so 5 It may consist of -1=31 pieces.

[0076] The buffers 140 are arranged between the output terminals of the second capacitors 130 and are connected in series with each other. The buffers 140 are connected in parallel with the second capacitors 130.

[0077] The buffers 140 are connected in series to each other and driven as a circular delay chain. The buffers 140 are connected to the output terminals of the operational amplifiers 110, respectively, and receive the output voltages of the operational amplifiers 110 as inputs.

[0078] The second capacitor 130 is connected in parallel with the first capacitor 120, and operates together with the buffer 140 by receiving the output of the operational amplifier 110 as a control signal. The number of second capacitors 130 may be the same as the number of buffers 140.

[0079] When the first switch 150 is turned on, the second capacitor 130 stores the input signal at the input terminal, and when the second switch 160 is turned on, the second capacitor 130 outputs a signal obtained by subtracting the quantized output signal of the buffer from the input signal to the operational amplifier 110.

[0080] The first switch 150 is connected between the input terminal and the second capacitor 130, and between the second capacitor 130 and the ground terminal, and performs an on / off operation at a constant cycle. When the first switch 150 is in an on operation, it outputs an input signal to the second capacitor 130.

[0081] The second switch 160 is connected between the output terminal of the buffer 140 and the second capacitor 130, and between the second capacitor 130 and the operational amplifier 110, and alternately performs on / off operation together with the first switch 150. The second switch 160 outputs the quantized output signal of the buffer 140 to the second capacitor 130.

[0082] The operation of the analog-digital hybrid integrator according to another embodiment of the present invention will now be described.

[0083] FIG. 9 is a diagram showing the operation state of an analog-digital hybrid integrator according to another embodiment of the present invention for a Φ1 signal. FIG. 10 is a diagram showing the operation state of an analog-digital hybrid integrator according to another embodiment of the present invention for a Φ2 signal. FIG. 11(a) is a timing diagram showing a reset clock that resets a first capacitor. FIG. 11(b) is a timing diagram showing a clock signal that controls the on / off operation of a first switch and a second switch. FIG. 11(c) is a timing diagram showing an output signal that is fed back from an operational amplifier. FIG. 11(d) is a timing diagram showing a quantized output signal of a buffer. FIG. 11(e) is a timing diagram showing an input signal and a processed digital output of an analog-digital hybrid integrator according to another embodiment of the present invention.

[0084] Referring to FIG. 11(a), when the second reset switch receives a reset signal, the buffer 140 receives a reference voltage (Vref) and is set to an initial state, and when the first reset switch 170 receives a reset signal, the first capacitor 120 erases the residual signal.

[0085] 8 and 11(b), in the initial state, the buffer 140 includes a first buffer 141 that receives an input of "1" and outputs "1", and a second buffer 142 that receives an input of "0" and outputs "0". In the initial state, the number of first buffers 141 may be the same as the number of second buffers 142.

[0086] The buffer 140 also includes a third buffer 143 that receives an input of a "0" state, outputs a "1" state, and forms a rising edge, and a fourth buffer 144 that receives an input of a "1" state, outputs a "0" state, and forms a falling edge.

[0087] For example, if the buffer 140 consists of 32 buffers to represent 5 bits, there are 15 first buffers 141, 15 second buffers 142, one third buffer 143 placed between the first buffer 141 and the second buffer 142, and one fourth buffer 143 placed between the first buffer 141 and the second buffer 142.

[0088] 9 and 11(b), the Φ1 signal turns on the first switch 150 and turns off the second switch 160. At this time, the input signal at the input terminal is stored in the second capacitor 130.

[0089] 10 and 11(b), the Φ2 signal turns the first switch 150 off and the second switch 130 on. Referring to Fig. 10, the buffer 140 outputs a quantized output signal to the second capacitor 130, and the second capacitor 130 outputs a subtracted signal obtained by subtracting the stored analog input signal from the quantized output signal of the buffer 140 to the operational amplifier 110.

[0090] Referring to FIG. 10, an operational amplifier 110 integrates the subtracted signal and feeds it back to a buffer 140, and a first capacitor 120 stores the analog residue signal.

[0091] Also, referring to FIG. 6, if the output voltage fed back from the operational amplifier 110 to the buffer 140 is greater than the existing voltage, the fourth buffer 144 changes to the first buffer 141 which receives an input of the “1” state and outputs “1”, and the second buffer 142 connected to the fourth buffer 144 changes to the first buffer 141 via the fourth buffer 144 up to the magnitude of the feedback output voltage.

[0092] In other words, if the fed back output voltage is greater than the existing voltage, the buffer of the falling edge outputs "1" to increase the number of the first buffer 141, and the fourth buffer 144 forming the falling edge propagates and moves in the direction of the second buffer 142.

[0093] Also, referring to FIG. 6, if the output voltage fed back from the operational amplifier 110 to the buffer 140 is smaller than the existing voltage, the third buffer 143 changes to the second buffer 142 that receives an input of a “0” state and outputs “0”, and the first buffer 141 connected to the third buffer 143 changes to the second buffer 142 via the third buffer 143 up to the magnitude of the feedback output voltage.

[0094] In other words, if the fed back output voltage is smaller than the existing voltage, the rising edge buffer outputs "0" to increase the number of second buffers 142, and the third buffer 143 forming the rising edge propagates and moves in the direction of the first buffer 141.

[0095] Upon completion of this operation, the buffer 140 outputs the quantized digital signal to the second capacitor 130 .

[0096] For example, when the input voltage is +10.4, the number of first buffers 141 that output "1" among the buffers 140 increases by 10 to 25, and the second capacitors 130 connected to the increased number of first buffers 141 sample 10, storing "1" respectively. After that, the second capacitors 130 output a quantized digital signal of "10," and when the operational amplifier 110 outputs 0.4, which is the remainder of the input voltage, the first capacitor 120 stores 0.4, which is the analog output signal.

[0097] In this state, when an additional input signal of +3.92 is input, four of the buffers 140 in the "0" state are further changed to first buffers 141 so that the analog-digital hybrid integrator of the present invention expresses a total of +14.32, and propagation to the fourth buffer 144 is performed until the total number of first buffers 141 reaches 19. As a result, the second capacitors 130 connected to the increased first buffers 141 sample the increased number of first buffers 141, 4, and store "1" respectively. After that, the second capacitors 130 output a quantized digital signal of "14," and when the operational amplifier 110 outputs 0.32, which is the remainder of the input voltage, the first capacitors 120 store 0.32, which is the analog output signal.

[0098] Referring to FIG. 11(e), it can be seen that in the analog-digital hybrid integrator according to another embodiment of the present invention, the digital output (Dout) converges to the input voltage (Vin) from 20 ns.

[0099] The digital output (Dout) is the final output calculated by averaging the output signals (D[1] to D

[32] ) obtained by the continuous operation of the analog-digital hybrid integrator according to the present invention.

[0100] The above description is merely an example illustrating the technical concept of the present invention, and a person skilled in the art to which the present invention pertains can make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are for illustrative purposes only and do not limit the technical concept of the present invention. The scope of the technical concept of the present invention should be interpreted by the appended claims, and all technical concepts within the scope of the claims should be interpreted as being within the scope of the present invention. [Explanation of symbols]

[0101] 110: operational amplifier, 120: first capacitor, 130: second capacitor, 140: buffer, 141: first buffer, 142: second buffer, 143: third buffer, 144: fourth buffer, 150: first switch, 160: second switch, 170: reset switch.

Claims

1. An operational amplifier connected to the input terminal; a first capacitor connected between the input and output terminals of the operational amplifier; a plurality of buffers connected in series to each other to form a circular chain and controlled by the output signal of the operational amplifier; a plurality of second capacitors connected between the input terminal of the operational amplifier and the plurality of output terminals of the plurality of buffers; Including, an analog-digital hybrid integrator, wherein each of the plurality of second capacitors is connected to a corresponding output terminal of the plurality of buffers;

2. 2. The analog-digital hybrid integrator of claim 1, wherein the operational amplifier provides an output voltage to each of the plurality of buffers.

3. 2. The analog-digital hybrid integrator of claim 1, wherein the plurality of buffers include: a first buffer that receives an input of “1” and outputs “1”; a second buffer that receives an input of “0” and outputs “0”; a third buffer that receives an input of a “0” state and outputs a “1” state, forming a rising edge; and a fourth buffer that receives an input of a “1” state and outputs a “0” state, forming a falling edge.

4. 4. The analog-digital hybrid integrator according to claim 3, wherein the number of the first buffers is equal to the number of the second buffers in an initial state.

5. 4. The analog-digital hybrid integrator according to claim 3, wherein when the output voltage fed back from the operational amplifier to the buffer is greater than the existing voltage, the fourth buffer outputs "1" and changes to the first buffer, thereby increasing the number of the first buffers, and the fourth buffer forming a falling edge propagates and moves in the direction of the second buffer.

6. 4. The analog-digital hybrid integrator according to claim 3, wherein when the output voltage fed back from the operational amplifier to the buffer is smaller than the existing voltage, the third buffer outputs "0" and changes to the second buffer, thereby increasing the number of the second buffers, and the third buffer forming a rising edge propagates and moves in the direction of the first buffer.

7. An operational amplifier connected to an input terminal, which receives and integrates a subtraction signal obtained by subtracting a quantized output signal from an input signal at said input terminal; a first capacitor for storing a residual signal and connected between the input and output of the operational amplifier; a plurality of buffers that quantize the output signal of the operational amplifier and are connected in series to form a circular chain; a plurality of second capacitors connected between the input terminal of the operational amplifier and a plurality of output terminals of the plurality of buffers, for storing the input signal and the quantized output signals of the plurality of buffers; and each of the plurality of second capacitors connected to a corresponding output terminal of the plurality of buffers. a first switch connected between the input terminal and the plurality of second capacitors and between the plurality of second capacitors and a ground terminal, respectively, for switching an input signal at the input terminal to sample and store the input signal in the plurality of second capacitors; second switches connected between the output terminals of the plurality of buffers and the plurality of second capacitors, and between the plurality of second capacitors and the input terminal of the operational amplifier, respectively, for switching the subtraction signal and outputting it to the operational amplifier; An analog-digital hybrid integrator, comprising:

8. 8. The analog-digital hybrid integrator of claim 7, further comprising: a first reset switch connected in parallel with the first capacitor and the operational amplifier, for resetting a residual signal on the first capacitor.

9. 8. The analog-digital hybrid integrator of claim 7, further comprising: a second reset switch connected to the output terminals of the plurality of buffers, receiving a reference voltage (Vref) when turned on, and resetting the plurality of buffers and the plurality of second capacitors to their initial states.

10. 8. The analog-digital hybrid integrator of claim 7, wherein the operational amplifier provides an output voltage to each of the plurality of buffers.

11. 8. The analog-digital hybrid integrator of claim 7, wherein the plurality of buffers include: a first buffer that receives an input of “1” and outputs “1”; a second buffer that receives an input of “0” and outputs “0”; a third buffer that receives an input of a “0” state and outputs a “1” state, forming a rising edge; and a fourth buffer that receives an input of a “1” state and outputs a “0” state, forming a falling edge.

12. 12. The analog-digital hybrid integrator of claim 11, wherein the number of the first buffers is initially the same as the number of the second buffers.

13. 12. The analog-digital hybrid integrator of claim 11, wherein when the output voltage fed back from the operational amplifier to the plurality of buffers is greater than an existing voltage, the fourth buffer outputs "1" and changes to the first buffer, thereby increasing the number of the first buffers, and the fourth buffer forming a falling edge propagates and moves in the direction of the second buffer.

14. 12. The analog-digital hybrid integrator of claim 11, wherein when the output voltage fed back from the operational amplifier to the plurality of buffers is smaller than the existing voltage, the third buffer outputs "0" and changes to the second buffer, thereby increasing the number of the second buffers, and the third buffer forming a rising edge propagates and moves in the direction of the first buffer.

15. 8. The analog-digital hybrid integrator according to claim 7, wherein when the first switch is in an on state and the second switch is in an off state, an input signal at the input terminal is stored in the plurality of second capacitors.

16. 8. The analog-digital hybrid integrator of claim 7, wherein when the first switch is in an off state and the second switch is in an on state, the plurality of buffers output the quantized output signals to the plurality of second capacitors, and the plurality of second capacitors output, to the operational amplifier, subtracted signals obtained by subtracting the stored analog input signals from the quantized output signals of the plurality of buffers.

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