Semiconductor device and manufacturing method thereof

Abstract

To improve performance of a semiconductor device including a trench gate type MOSFET in which a p-type impurity is introduced into a bottom of a groove buried with a gate electrode.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a plurality of grooves D1 on a principal surface of an n-type semiconductor substrate SB; forming a p-type semiconductor region R1 in the semiconductor substrate SB by introducing a p-type impurity and carbon into a bottom surface or a side surface of each groove D1; forming a gate electrode via an insulation film inside each of the plurality of grooves D1; and forming a p-type second semiconductor region in the semiconductor substrate SB in contact with a side surface of the groove D1 between adjacent grooves D1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique that is effective when applied to a method for manufacturing a semiconductor device including a trench gate MOSFET. [Background technology]

[0002] A well-known power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, which requires a high breakdown voltage, is a trench-gate MOSFET having a gate electrode in a trench provided in the main surface of a substrate. Patent Document 1 (JP 2012-33951 A) describes a power MOSFET with a double-gate structure in which a gate electrode and a field plate electrode are embedded in a trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-33951 Summary of the Invention [Problem to be solved by the invention]

[0004] In trench-gate MOSFETs, the electric field tends to concentrate at the bottom of the trench, making it difficult for the depletion layer to expand sufficiently, making it difficult to achieve high breakdown voltages. In contrast, in n-channel MOSFETs, one method of alleviating the electric field is to implant impurities such as boron (B) into the bottom of the trench. However, when the boron diffuses due to heat treatment after this implantation process, the width of the n-type layer between adjacent trenches narrows, causing problems such as an increase in on-resistance (Ron) due to the blockage of the current path and complicated alternating current (AC) characteristics. These problems become more pronounced as the cell pitch becomes smaller. One possible solution is to increase the cell pitch, but this makes it difficult to integrate cells.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A brief summary of a representative embodiment of the present invention will be given below.

[0007] The semiconductor device manufacturing method according to one embodiment is a method for manufacturing a trench-gate MOSFET, in which p-type impurities and carbon (C) are introduced into the bottom surface of a trench provided for burying a gate electrode.

[0008] The semiconductor device according to one embodiment is a trench gate MOSFET in which p-type impurities and carbon are introduced into the bottom of a trench in which a gate electrode is buried. [Effects of the Invention]

[0009] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 2] 2 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 1. [Figure 3] 3 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 2. [Figure 4] 4 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 3. [Figure 5] 5 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 4. [Figure 6] 6 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 6. [Figure 8]8 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 1 is a schematic planar layout illustrating a semiconductor device according to an embodiment; [Figure 15] 1 is an enlarged cross-sectional view showing a semiconductor device according to an embodiment of the present invention; [Figure 16] 10A and 10B are cross-sectional views of a semiconductor device according to a first modification of the embodiment during a manufacturing process. [Figure 17] 10A and 10B are cross-sectional views of a semiconductor device according to a first modification of the embodiment during a manufacturing process. [Figure 18] 10A and 10B are cross-sectional views of a semiconductor device according to a first modification of the embodiment during a manufacturing process. [Figure 19] 10A and 10B are cross-sectional views of a semiconductor device according to a first modification of the embodiment during a manufacturing process. [Figure 20] 10A and 10B are cross-sectional views of a semiconductor device according to a first modification of the embodiment during a manufacturing process. [Figure 21] 10 is a schematic planar layout showing a semiconductor device according to a second modification of the embodiment; [Figure 22] 10A and 10B are cross-sectional views of a semiconductor device during a manufacturing process as a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0012] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] Also," - " and " + " is a symbol that indicates the relative impurity concentration of n-type or p-type conductivity. For example, in the case of n-type, "n - "," "n," "n + The concentration of n-type impurities increases in this order.

[0015] Here, a power MOSFET will be described as an example of the semiconductor device of the present application. A power MOSFET is a semiconductor device capable of handling power of several watts or more. The semiconductor device of the present application includes a trench-gate power MOSFET, which is a trench-gate type MOSFET among power MOSFETs. A trench-gate power MOSFET has a gate electrode made of polysilicon or the like in a relatively long and narrow trench formed in the main surface (top surface, first main surface) of a semiconductor substrate, and a channel is formed in the thickness direction of the semiconductor substrate. In this case, the top surface side of the semiconductor substrate typically serves as the source, and the back surface side (bottom surface, second main surface side) serves as the drain. The following description will be given using a MOSFET (MOS field-effect transistor) as an example. However, the following embodiments are not limited to MOSFETs and can be applied to MISFETs (Metal Insulator Semiconductor Field Effect Transistors).

[0016] The semiconductor device of the present application also includes a trench-gate double-gate power MOSFET, which is a type of trench-gate power MOSFET. The trench-gate double-gate power MOSFET has a field plate electrode (dummy gate electrode) below a gate electrode (intrinsic gate electrode) in a trench. The field plate electrode functions to disperse a steep potential gradient concentrated near the drain-side end of the gate electrode, and is electrically connected to the source electrode.

[0017] <Details of areas for improvement> The details of this room for improvement will be described below with reference to the drawings. Figure 22 is a cross-sectional view of a semiconductor device during a manufacturing process as a comparative example. In this comparative example, a manufacturing process of a trench gate power MOSFET will be described.

[0018] As shown in FIG. 22, in the manufacturing process of the comparative example MOSFET, an n-type semiconductor substrate SB is prepared, and then multiple trenches D1 are formed in the main surface of the substrate. Then, to prevent electric field concentration at the bottom of the trenches D1 in the completed MOSFET, boron (B), a p-type impurity, is implanted into the bottom of the trenches D1 by ion implantation. This forms a p-type semiconductor region RP, a region into which the p-type impurity has been implanted, in the semiconductor substrate SB near the bottom of the trenches D1. Next, a field plate electrode FP and a gate electrode GE are formed in the trenches D1 via insulating films IF1 and IF2. Next, p-type impurities (e.g., boron (B)) are implanted into the upper surface of the semiconductor substrate SB. Subsequently, a thermal diffusion process (heat treatment) is performed to diffuse the p-type impurities implanted into the semiconductor substrate SB by this implantation process. This thermal diffusion process (heat treatment) is performed at 1100°C for 10 minutes or more. This forms a p-type semiconductor region CR, a channel formation region, in the region into which the p-type impurity has been implanted. This results in the structure shown in FIG. 22. Thereafter, although not shown, a source region is formed on the upper surface of the semiconductor substrate SB, and wiring is formed on the semiconductor substrate SB, thereby almost completing the semiconductor device of the comparative example.

[0019] As described in the problem to be solved by the invention, trench-gate MOSFETs have a problem in that the electric field tends to concentrate at the bottom of the trench, making it difficult for the depletion layer to sufficiently expand. As a result, the drain-source breakdown voltage BVDSS of the MOSFET is low, making it difficult to increase the breakdown voltage of the MOSFET.

[0020] In the semiconductor device of the comparative example, p-type impurities are introduced into the bottom of the trenches D1, thereby enabling the MOSFET to withstand a high voltage. However, during the thermal diffusion process to form the semiconductor region CR, which serves as the channel formation region, the p-type impurities (e.g., boron (B)) introduced into the bottom of the trenches D1 may diffuse as indicated by the black arrows in Figure 22. This narrows the width of the n-type layer (drift layer) between adjacent trenches D1, blocking the current path indicated by the white arrows in Figure 22 and increasing the on-resistance Ron. Furthermore, an increase in the on-resistance Ron can lead to problems such as a higher on-resistance during AC operation of the MOSFET compared to DC (direct current) operation, and more complex AC characteristics, i.e., fluctuations in switching characteristics. These problems become more pronounced as the cell pitch of the MOSFET decreases. In other words, the smaller the distance between the trenches D1, the greater the on-resistance. Therefore, increasing the cell pitch to ensure a current path is considered a countermeasure, but this makes cell integration difficult and hinders the miniaturization of semiconductor devices.

[0021] As described above, there is room for improvement in MOSFETs in which impurities for reducing the electric field are introduced into the bottom of the trench for burying the gate.

[0022] Therefore, in the following embodiment, a device is devised to solve the above-mentioned room for improvement. The technical concept of the device-devised embodiment will be described below.

[0023] (Embodiment) <Method of manufacturing a semiconductor device> The method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS.

[0024] First, as shown in Figure 1, +A semiconductor substrate SB (at this stage, a planar circular semiconductor wafer) is prepared by growing an epitaxial layer (semiconductor layer) EP made of high-resistivity n-type silicon (Si) single crystal on a substrate 1S made of n-type silicon (Si) single crystal. The semiconductor substrate SB has a main surface (first main surface) and a back surface (second main surface) opposite the main surface. Next, an insulating film HM made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate SB (the upper surface of the epitaxial layer EP). Here, a silicon oxide film is used as the insulating film HM, but other materials such as silicon nitride (Si3N4) may also be used.

[0025] Next, as shown in Fig. 2, a resist pattern is formed on the insulating film HM through a series of photolithography processes, such as coating a photoresist (hereinafter simply referred to as resist) film, exposing it to light, and developing it. Thereafter, the insulating film HM is etched using the resist pattern as an etching mask, and the resist pattern is then removed, thereby forming a pattern of the insulating film HM for forming trenches on the main surface of the semiconductor substrate SB. This pattern of the insulating film HM functions as a hard mask film for forming the trenches.

[0026] Next, using the pattern of the insulating film HM as an etching mask, the semiconductor substrate SB is etched by anisotropic dry etching to form a plurality of trenches D1. Each of the plurality of trenches D1 does not reach the substrate 1S, but reaches partway to a depth of the epitaxial layer EP.

[0027] 3, using the insulating film HM as an ion implantation blocking mask, carbon (C) and p-type impurity boron (B) are implanted into the bottom of each trench D1 by ion implantation. This forms a p-type semiconductor region R1 into which boron and carbon have been introduced in the epitaxial layer EP (in the semiconductor substrate SB) near the bottom of the trench D1. Here, the semiconductor region R1 is formed by implanting boron and carbon into the same region.

[0028] In this implantation step, boron and carbon are implanted in separate steps. Either boron or carbon may be implanted first. The boron implantation energy here is 10 keV, and the dose is 1.0×10 13 cm -2 The carbon implantation energy is 12 keV, and the dose is 5.0 × 10 15 ~5.0×10 16 cm -2 These values ​​vary depending on the target breakdown voltage of the device, the impurity concentration of the epitaxial layer, the through film thickness, etc. The semiconductor region R1 has crystal defects due to the introduction of carbon.

[0029] 4, the insulating film HM is removed to expose the main surface of the semiconductor substrate SB (i.e., the semiconductor wafer). Then, the semiconductor substrate SB is subjected to a thermal oxidation process to form an insulating film IF1 made of, for example, silicon oxide on the main surface of the semiconductor substrate SB, including the inner surfaces of the trenches D1. The thickness of the insulating film IF1 is, for example, about 200 nm.

[0030] 5, a conductive film SF1 made of, for example, low-resistance polycrystalline silicon is deposited by CVD (Chemical Vapor Deposition) on the insulating film IF1 on the main surface of the semiconductor substrate SB. This fills the trenches D1 with the conductive film SF1. Impurities (e.g., phosphorus (P), boron (B), arsenic (As), or antimony (Sb)) that act as dopants for silicon are introduced into the conductive film SF1 to reduce its resistance.

[0031] 6, a part of the conductive film SF1 is etched to expose the insulating film IF1 on the main surface of the semiconductor substrate SB, and the upper surface of the conductive film SF1 in the trench D1 is recessed to a depth halfway through the trench D1, thereby forming a field plate electrode (dummy gate electrode) FP made of the conductive film SF1 remaining in the trench D1.

[0032] 7, the insulating film IF1 exposed from the field plate electrode FP is removed by etching to expose the main surface of the semiconductor substrate SB and part of the side surface of the trench D1. As a result, the insulating film IF1 remaining between the trench D1 and the field plate electrode FP functions as a gate insulating film for the field plate electrode FP.

[0033] Next, as shown in FIG. 8, the semiconductor substrate SB is subjected to a thermal oxidation process to form an insulating film IF2, which is a gate insulating film made of a silicon oxide film, on the main surface of the semiconductor substrate SB, including the side surfaces of the trench D1. The insulating film IF2 is formed not only on the surface of the epitaxial layer EP but also on the surface of the exposed field plate electrode FP. Here, the insulating film IF2 is formed to a thickness thinner than the insulating film IF1. This is to improve the current driving capability of the MOSFET and reduce the on-resistance. The thickness of the insulating film IF2 is, for example, about 50 nm.

[0034] Next, a conductive film SF2 made of, for example, low-resistance polycrystalline silicon is deposited by CVD on the insulating films IF1 and IF2 on the main surface of the semiconductor substrate SB, including inside the trench D1. This fills the upper part of the trench D1 with the conductive film SF2. The conductive film SF2 is doped with the same impurities as the conductive film SF1, thereby reducing its resistance.

[0035] 9, the conductive film SF2 and the insulating film IF2 are etched back by anisotropic dry etching to expose the main surface of the semiconductor substrate SB. This forms a gate electrode GE made of the conductive film SF2 remaining in the trench D1. The gate electrode GE has a recessed structure in which its upper surface is recessed below the main surface of the semiconductor substrate SB.

[0036] 10, p-type impurities such as boron (B) are introduced into the main surface of the semiconductor substrate SB by ion implantation. Then, a thermal diffusion process is performed on the semiconductor substrate SB to form a p-type semiconductor region CR for channel formation. That is, the semiconductor region CR is formed in the semiconductor substrate SB between adjacent trenches D1 and in contact with the side surface of the trench D1. This thermal diffusion process (heat treatment) is performed at 1100°C for 10 minutes or more. Specifically, the thermal diffusion process is performed at 1100°C for 30 minutes.

[0037] By forming the semiconductor region CR after the gate oxidation process, it is possible to avoid the influence of surface segregation during the gate oxidation process (silicon oxidation). In particular, in the case of an n-channel MOSFET (using boron (B) as the channel impurity), the impurity concentration is likely to fluctuate due to surface segregation, so it is preferable to form the semiconductor region CR for channel formation after the gate oxidation process. The depth of the semiconductor region CR is shallower than the depth of the trench D1, for example, equal to the depth of the gate electrode GE.

[0038] 11, p-type impurities such as phosphorus (P) or arsenic (As) are introduced into the main surface of the semiconductor substrate SB by ion implantation. After that, a thermal diffusion process is performed on the semiconductor substrate SB to form n + A source region SR, which is a type semiconductor region, is formed. The semiconductor region CR and the source region SR are each formed in the semiconductor substrate SB, in contact with the side surface of the trench D1, and extending from the main surface of the semiconductor substrate SB to a depth of the semiconductor substrate SB. The depth of the source region SR is shallower than the depth of the semiconductor region CR.

[0039] Next, as shown in FIG. 12, an interlayer insulating film IL made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate SB, and then a resist pattern exposing a contact hole formation region is formed on the interlayer insulating film IL by the photolithography process described above. Subsequently, the interlayer insulating film IL is etched using the resist pattern exposing the contact hole formation region as an etching mask, and the resist pattern is then removed to form a contact hole CH in the interlayer insulating film IL. Then, using the interlayer insulating film IL as an etching mask, a portion of the semiconductor substrate SB (the upper surface of the epitaxial layer EP) exposed therethrough is etched to form a trench D2. The trench D2 penetrates the source region SR and terminates midway through the semiconductor region CR for channel formation. A p-type impurity such as boron is then introduced into the semiconductor substrate SB at the bottom of the trench D2 by ion implantation or the like to form a p-type semiconductor region BC.

[0040] Next, as shown in FIG. 13, a conductive film M1 is formed on the main surface of the semiconductor substrate SB by, for example, sputtering. The conductive film M1 covers the upper surface of the interlayer insulating film IL and fills the contact holes CH. The conductive film M1 filled in the contact holes CH forms a conductive connection portion. Furthermore, the conductive film M1 on the interlayer insulating film IL forms, for example, a source pad. That is, the source pad is electrically connected to the source region SR via the conductive connection portion in the contact holes CH.

[0041] The source pad is electrically connected to the semiconductor region CR via the conductive connection in the contact hole CH and the semiconductor region BC. In a region not shown, the source pad is electrically connected to the field plate electrode FP via the conductive connection in the contact hole CH. In a region not shown, a gate pad made of a conductive film M1 separated from the source pad is formed, and the gate pad is electrically connected to the gate electrode GE via the conductive connection in the contact hole CH.

[0042] where n+ The bottom of the n-type substrate 1S, i.e., the semiconductor substrate SB, forms a drain region. The source region SR, the gate electrode GE, the semiconductor region CR which is a channel formation region, and the drain region (substrate 1S) form an n-channel MOSFET. The MOSFET of this embodiment is a trench double-gate power MOSFET having a field plate electrode FP and a gate electrode GE in the trench D1.

[0043] Thereafter, a drain electrode made of a metal film covering the bottom surface of the substrate 1S is formed, and then the semiconductor wafer is cut by a dicing process to obtain a plurality of individual semiconductor chips. Through the above steps, the semiconductor device of this embodiment is almost completed.

[0044] <Structure of semiconductor device> The semiconductor device of this embodiment is + The semiconductor substrate SB includes a p-type substrate 1S and an epitaxial layer EP, which is an n-type semiconductor layer, on the substrate 1S. A plurality of trenches D1 are arranged side by side on the main surface of the semiconductor substrate SB. A p-type semiconductor region CR, which is a channel formation region, is formed in the semiconductor substrate SB between adjacent trenches D1, and an n-type semiconductor region CR is formed from the main surface of the semiconductor substrate SB to the upper surface of the semiconductor region CR. + A source region SR is formed.

[0045] A trench D2 shallower than the trench D1 is formed in the main surface of the semiconductor substrate SB between adjacent trenches D1 at a position spaced apart from the trench D1. +A type semiconductor region BC is formed in the trench D1. A field plate electrode FP is formed in the trench D1 with an insulating film IF1 interposed therebetween, and a gate electrode GE is formed in the trench D1 above the field plate electrode with an insulating film IF2 interposed therebetween. The gate electrode GE is insulated from the semiconductor substrate SB and the field plate electrode FP by the insulating film IF2. An interlayer insulating film IL is formed on the semiconductor substrate SB. A contact hole CH, which is a through hole, is formed in the interlayer insulating film IL directly above the trench D2. A conductive film M1 is formed on the interlayer insulating film IL, in the contact hole CH, and in the trench D2.

[0046] n + The substrate 1S forms a drain region. The source region SR, the gate electrode GE, the semiconductor region CR which is a channel formation region, and the drain region (substrate 1S) form an n-channel MOSFET. The epitaxial layer EP forms a drift layer.

[0047] At the bottom of the trench D1, interstitial defects exist in the epitaxial layer EP at the locations where carbon has been implanted. These defects can prevent the diffusion of p-type impurities in the epitaxial layer EP.

[0048] FIG. 14 shows a planar layout of a semiconductor chip, which is a semiconductor device according to this embodiment. FIG. 14 shows a trench D1 in the semiconductor chip, a trench D3 formed on the periphery of the cell region, and a trench D4 along the periphery of the semiconductor chip. As shown in FIG. 14, in the cell region, the trench D1 extends in the Y direction along the upper surface of the substrate. A plurality of trenches D1 are also arranged in the X direction along the upper surface of the substrate. The X and Y directions are perpendicular to each other in a planar view. The trench D1 is a cell trench, and the trenches D3 and D4 are peripheral trenches. The trench D2 (see FIG. 13), which is a cell trench, extends in the Y direction between the trenches D1 adjacent to each other in the X direction. A gate electrode GE and a field plate electrode are formed in each trench D1 along the shape of the trench D1. That is, the gate electrodes GE are arranged in a striped pattern in a planar view.

[0049] Groove D3 constitutes a termination ring, and a conductive film is formed in groove D3 with, for example, an insulating film interposed therebetween. Groove D4, which surrounds groove D3 in plan view, constitutes a seal ring and has the same structure as the termination ring.

[0050] Although an n-channel MOSFET has been described here, the effects of the semiconductor device of this embodiment, which will be described later, can also be obtained with a p-channel MOSFET in which the conductivity type of each semiconductor region is inverted. In the case of a p-channel MOSFET, the impurity introduced into the bottom of the groove D1 described with reference to FIG. 3 is, for example, p (phosphorus), which is an n-type impurity.

[0051] <Effects of the embodiment> One of the main features of this embodiment is that after the formation of the trench D1 and before the heat treatment for forming the semiconductor region CR, p-type impurities and carbon are implanted into the bottom of the trench D1 to form the semiconductor region R1. By introducing p-type impurities (here, boron (B)) into the bottom of the trench D1, it is possible to realize electric field relaxation at the bottom of the trench D1 in the completed MOSFET, thereby ensuring the breakdown voltage of the semiconductor device.

[0052] Here, by introducing carbon into the bottom of the trench D1 in addition to the p-type impurity, thermal diffusion of the p-type impurity (p-type ions) contained in the semiconductor region R1 can be prevented during the heat treatment performed after the formation of the semiconductor region R1. This is thought to be because the introduction of carbon creates interstitial defects in the semiconductor substrate SB, which hinder the migration of the p-type impurity. The heat treatment referred to here is, for example, the heat treatment for forming the semiconductor region CR or the heat treatment for forming the source region SR.

[0053] Preventing the diffusion of p-type impurities prevents the width of the n-type layer (drift layer) between adjacent trenches D1 from narrowing. This prevents the current path of the MOSFET from being blocked, preventing an increase in on-resistance Ron. This prevents the problem of on-resistance during AC operation being higher than during DC operation and the problem of AC characteristics becoming more complex, which are caused by an increase in on-resistance Ron.

[0054] Therefore, since there is no need to increase the cell pitch to ensure a current path, the cells can be integrated and the semiconductor device can be miniaturized, thereby eliminating the room for improvement described above and improving the performance of the semiconductor device.

[0055] FIG. 15 shows an enlarged cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 15, the groove D1 is tapered with respect to the main surface of the semiconductor substrate SB, and its width increases from the bottom to the top (opening). The cell pitch in this application refers to one period of a plurality of cell structures repeatedly arranged in a cell region of a semiconductor chip. Specifically, the cell pitch CP shown in FIG. 15 is the sum of the width X1, which is the shortest distance between adjacent grooves D1 (mesa portions) in the X direction (the short-side direction of the groove D1), and the opening width X2 of the groove D1 in the X direction. In other words, the cell pitch CP refers to the shortest distance in the X direction from one end of the opening of the groove D1 to another groove D1 adjacent to the groove D1 at the end opposite to the end.

[0056] Here, the implantation of p-type impurities and carbon into the bottom of trench D1 in the cell region has been described, but p-type impurities and carbon may also be implanted not only into the cell region but also into trenches D3 and D4, which are peripheral trenches shown in Fig. 14. Alternatively, p-type impurities and carbon may be implanted only into the bottom of trench D3 or D4, without implanting p-type impurities and carbon into the bottom of trench D1 in the cell region, thereby increasing the breakdown voltage of the periphery of the cell region and designing it to be lower than the periphery.

[0057] <Variation 1> In the above embodiment, carbon is implanted into a region where p-type impurities are implanted at the bottom of a trench where a gate electrode is to be buried. The carbon implantation region preferably overlaps with the p-type impurity implantation region. The following FIGS. 16 and 17 show enlarged cross-sectional views of a semiconductor device according to this modification during the manufacturing process. In these figures, cross marks (x) are indicated at locations where defects have occurred due to carbon implantation. Here, the location where defects are generated by carbon implantation is also the region where p-type impurities are implanted to form semiconductor region R1 (see FIG. 13).

[0058] The position where carbon is implanted can be changed as appropriate by changing the carbon implantation energy, as shown in Figures 16 and 17. For the ion implantation process with an implantation angle of 0 degrees, Figure 16 shows the case where the implantation energy is small, and Figure 17 shows the case where the implantation energy is large.

[0059] Furthermore, even when oblique ion implantation is performed to implant p-type impurities and carbon into the side surfaces of trench D1, the position where carbon is introduced can be changed by adjusting the angle and energy of ion implantation. Regarding the oblique ion implantation process, FIG. 18 shows a case where the implantation energy is low, and FIG. 19 shows a case where the implantation energy is high. Furthermore, as shown in FIG. 20, both ion implantation with an implantation angle of 0 degrees and oblique ion implantation may be performed.

[0060] <Variation 2> In the first embodiment, the gate electrodes are arranged in a stripe pattern, but this is not limiting. For example, the gate electrodes may be arranged in a lattice or net pattern, i.e., a so-called mesh pattern. Figure 21 shows a planar layout of a semiconductor chip, which is a semiconductor device of this modification. In Figure 21, the gate electrodes and field plate electrodes are formed along the shape of the trench D1.

[0061] 21, the grooves D1 are arranged in a mesh pattern in plan view. That is, an end of a plurality of grooves D1 extending in the Y direction and lined up in the X direction is connected to each of the grooves D1 extending in the X direction and lined up in the Y direction. The grooves D1 extending in the Y direction and lined up in the X direction are arranged in a plurality of rows in the Y direction, and the positions of the grooves D1 in adjacent rows in the Y direction are shifted by a half period. Grooves D1 extending in the Y direction and adjacent to each other in the X direction are connected by grooves D1 extending in the Y direction and lined up in the X direction, so that the plurality of grooves D1 in groove D3 are integrated to form a single mesh-like layout.

[0062] By forming the gate electrode in a mesh shape, the gate density can be improved, which further reduces the on-resistance. In addition, the gate resistance can be reduced, which reduces switching loss.

[0063] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0064] For example, in this example, a trench double-gate power MOSFET having a field plate electrode and a gate electrode in the trench has been described. In contrast, even in a trench-gate power MOSFET having only a gate electrode without a field plate electrode in the trench, the same effect as in the first embodiment can be obtained by introducing p-type impurities and carbon into the bottom of the trench. [Explanation of symbols]

[0065] 1S board BC, CR, R1, RP semiconductor area D1, D2, D3, D4 grooves EP epitaxial layer FP field plate electrode GE gate electrode HM insulating film IF1, IF2 insulating film SB semiconductor substrate SR Source Region

Claims

1. (a) providing a semiconductor substrate of a first conductivity type; (b) forming a plurality of aligned trenches on the main surface of the semiconductor substrate; (c) forming a first semiconductor region of the second conductivity type in the semiconductor substrate by introducing an impurity of a second conductivity type different from the first conductivity type and carbon into each of a bottom surface and a side surface of the trench; (d) after the step (c), forming a first electrode on the inside of each of the plurality of grooves via a second insulating film; (e) after the step (d), forming a gate electrode on the inside of each of the plurality of trenches via a first insulating film; (f) after the step (e), forming a second semiconductor region of the second conductivity type in the semiconductor substrate between adjacent ones of the trenches and in contact with the side surfaces of the trenches; (g) forming a source region of the first conductivity type in the semiconductor substrate from the main surface of the semiconductor substrate to the second semiconductor region; and In the step (d), the gate electrode is formed on the first electrode via the first insulating film inside each of the plurality of trenches; a bottom portion of the semiconductor substrate that constitutes a drain region of the first conductivity type; The source region, the drain region, the gate electrode, and the first semiconductor region constitute a field effect transistor.

2. 2. The method of manufacturing a semiconductor device according to claim 1, The step (e) is (e1) introducing the impurity of the second conductivity type into the semiconductor substrate in contact with the side surface of the trench; (e2) after the step (e1), performing a heat treatment to diffuse the impurity of the second conductivity type, thereby forming the second semiconductor region; The method for manufacturing a semiconductor device comprising the steps of:

3. 2. The method of manufacturing a semiconductor device according to claim 1, In the step (c), the first semiconductor region is formed by implanting the second conductivity type impurity and carbon into the same region by ion implantation.

4. In the method for manufacturing a semiconductor device according to claim 1, The step (c) (c1) forming the first semiconductor region in the semiconductor substrate by introducing the second conductivity type impurity and carbon into the bottom surface of the trench; (c2) forming the first semiconductor region in the semiconductor substrate by introducing the second conductivity type impurity and carbon into the side surface of the trench; The method for manufacturing a semiconductor device comprising the steps of:

5. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the dose of carbon in the step (c) is 5.0×10 15 to 5.0×10 16 cm −2 .

6. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the plurality of grooves are arranged in a mesh pattern in a plan view.

7. a semiconductor substrate of a first conductivity type; a plurality of trenches formed in a main surface of the semiconductor substrate and aligned along the main surface; a gate electrode formed inside each of the plurality of trenches with a first insulating film interposed therebetween; a first electrode formed on the inside of each of the plurality of grooves via a second insulating film; a first semiconductor region of a second conductivity type different from the first conductivity type formed in the semiconductor substrate near the bottom and side surfaces of the plurality of trenches; a second semiconductor region of the second conductivity type formed in the semiconductor substrate between adjacent trenches and in contact with the side surface of the trench; a source region of the first conductivity type formed in the semiconductor substrate from the main surface of the semiconductor substrate to the second semiconductor region; a drain region of the first conductivity type formed at a bottom of the semiconductor substrate; and the gate electrode is formed on the first electrode with the first insulating film interposed therebetween inside each of the plurality of trenches; the source region, the drain region, the gate electrode, and the first semiconductor region constitute a field effect transistor, The first semiconductor region contains the second conductivity type impurity and carbon.

8. The semiconductor device according to claim 7, The semiconductor device, wherein the plurality of grooves are arranged in a mesh pattern in a plan view.

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