Semiconductor Devices

Abstract

To provide a semiconductor device that has a transistor with good electrical characteristics.SOLUTION: Provided is a semiconductor device in which a storage circuit and a circuit are produced on the same substrate. The storage circuit has a capacitive element, a first transistor and a second transistor. The capacitive element and any one of a source and a drain of the second transistor are electrically connected with a gate of the first transistor. The circuit has a third transistor and a fourth transistor. Each of the first transistor and the third transistor has an active layer containing silicon. Each of the second transistor and the fourth transistor has an active layer containing an oxide semiconductor.SELECTED DRAWING: Figure 23

Description

[Technical Field]

[0001] One aspect of the present invention relates to a circuit system using a semiconductor and other semiconductor devices. Another embodiment of the present invention relates to a driving method or a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical fields. The technical field of the present invention relates to a product, a method, or a manufacturing method. Process, Machine, Manufacture, or Composition of Matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a display ... light-emitting device, a power storage device, a memory device, a display device, a light-emitting device, a storage device, a memory device, a storage device, a storage device, a storage device, a storage device, a storage device, a storage device, a storage device, a storage device, a The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices are all and semiconductor devices. devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are semiconductors. They may have equipment.

[0004] In this specification, the term "circuit system" refers to a circuit including a capacitor, a transistor, a resistor, a memory element, It refers to a circuit in general that has semiconductor devices such as electrodes and wiring. A driving circuit for driving the semiconductor device, a power supply circuit, etc. may be included. The system includes inverter circuits, NAND circuits, AND circuits, NOR circuits, OR circuits, buffers, , level shifter, XOR circuit, XNOR circuit, AND-NOR circuit, OR-NAND circuit , AND-OR-INV circuit, OR-AND-INV circuit, analog switch, flip Flops, settable flip-flops, resettable flip-flops, set and and resettable flip-flops, adders, half adders, multiplexers, demultiplexers lexers, registers, scan registers, retention registers, isolators, and detectors It may include one or more of the coders, etc. [Background technology]

[0005] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials for transistors. However, oxide semiconductors are attracting attention as other materials.

[0006] For example, zinc oxide or In-Ga-Zn oxide can be used as the oxide semiconductor. Techniques for producing a transistor have been disclosed (see Patent Documents 1 and 2).

[0007] In recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, Demand is increasing for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0009] One aspect of the present invention provides a circuit system having transistors with good electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor having good electrical characteristics. The object of the present invention is to provide a circuit system having a transistor and a capacitive element with a small capacitance. Alternatively, one embodiment of the present invention is a circuit system including a transistor suitable for miniaturization. Another object of one embodiment of the present invention is to provide a system having a high switching speed. One of the objectives is to provide a circuit system that improves the operating speed. An object of one embodiment of the present invention is to provide a circuit system with improved writing speed. Another embodiment of the present invention provides a circuit system with improved read speed. Another object of one embodiment of the present invention is to provide a circuit system with low power consumption. Another object of one embodiment of the present invention is to provide a memory element having good retention characteristics. One of the objectives is to provide a circuit system having a plurality of elements. Another object of the present invention is to provide a novel semiconductor device. It shall be one of the following.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a capacitor and a transistor electrically connected to the capacitor. In the semiconductor device, the capacitance of the capacitive element is equal to or greater than 0.1 fF and less than 10 fF; The transistor includes an oxide semiconductor film, and the semiconductor device operates at room temperature during writing. The semiconductor device has a delay time of 0.1 ns or more and less than 5 ns.

[0012] One embodiment of the present invention is a semiconductor device in which a memory circuit and a circuit are formed over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. The gate of the first transistor is connected to a capacitance element and the source or drain of the second transistor. The third transistor and the fourth transistor are electrically connected to each other. a third transistor and a fourth transistor connected in series to each other; The first transistor and the third transistor have active layers containing silicon. The second transistor and the fourth transistor have an active layer formed of an oxide semiconductor film. The semiconductor device has the following.

[0013] One embodiment of the present invention is a semiconductor device in which a memory circuit and a circuit are formed over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. The gate of the first transistor is connected to a capacitance element, and the source or The drains of the third transistor and the fourth transistor are electrically connected to each other. a third transistor and a fourth transistor are connected in series with each other. The first to fourth transistors have active layers formed using an oxide semiconductor film. It is a semiconductor device.

[0014] In each of the above aspects, the transistor having the active layer formed of the oxide semiconductor film is It is preferable that the channel length is 1 nm or more and less than 100 nm. In the above, the oxide semiconductor film is composed of oxygen, In, Zn, and M (M is Ti, Ga, Y, Z). In addition, in each of the above embodiments, it is preferable that the alloy contains at least one of the following elements: In each of the above embodiments, the oxide semiconductor film preferably has a crystal part. The film preferably has a crystal portion oriented along the c-axis. [Effects of the Invention]

[0015] According to one aspect of the present invention, a circuit system having a transistor with good electrical characteristics is provided. Alternatively, according to one embodiment of the present invention, a transformer having good electrical properties can be provided. It is possible to provide a circuit system having a resistor and a capacitive element with a small capacitance. According to one embodiment of the present invention, a circuit system including a transistor suitable for miniaturization is provided. Alternatively, according to one aspect of the present invention, the switching speed (also known as the operating speed) can be improved. Alternatively, according to one embodiment of the present invention, a circuit system can be provided in which the following characteristics are improved: In this way, it is possible to provide a circuit system with improved writing speed. By this method, it is possible to provide a circuit system with improved read speed. According to one embodiment of the present invention, a circuit system with low power consumption can be provided. According to one aspect of the present invention, it is possible to provide a circuit system having a memory element with good retention characteristics. Alternatively, a novel circuit system can be provided. Alternatively, a novel semiconductor device can be provided. Placement can be provided.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram illustrating an example of a circuit system. [Figure 2] (A)-(C): Circuit diagrams showing an example of a memory device. (D): Cross-sectional view of the same. [Figure 3] (A) is a schematic diagram showing an example of a memory cell array, and (B) is a circuit diagram showing an example of a memory cell. [Figure 4] FIG. 2 is a circuit diagram showing an example of a memory cell array. [Figure 5] 10A and 10B are timing charts showing an example of the operation of a memory cell array. [Figure 6] FIG. 2 is a circuit diagram showing an example of a memory cell array. [Figure 7] FIG. 2 is a circuit diagram showing an example of a memory cell array. [Figure 8] FIG. 1 is a cross-sectional view showing an example of a memory cell array. [Figure 9] FIG. 1 is a cross-sectional view showing an example of a memory cell array. [Figure 10] A partial enlarged view of Figure 9. [Figure 11] FIG. 1 is a cross-sectional view showing an example of a memory cell array. [Figure 12] (B): A top view showing an example of a transistor. (A) and (C): Cross-sectional views of the same. [Figure 13] (B): A top view showing an example of a transistor. (A) and (C): Cross-sectional views of the same. [Figure 14] 1A to 1D are cross-sectional views showing an example of a transistor. [Figure 15] 1A to 1D are cross-sectional views showing an example of a method for manufacturing a memory cell array. [Figure 16] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a memory cell array. [Figure 17] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a memory cell array. [Figure 18] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a memory cell array. [Figure 19] 19A is a circuit diagram showing an example of a semiconductor device, and (B) and (C) are cross-sectional views showing an example of the configuration of the semiconductor device of FIG. [Figure 20] 20A is a circuit diagram showing an example of a semiconductor device, and (B) and (C) are cross-sectional views showing an example of the configuration of the semiconductor device of FIG. [Figure 21] 21A is a circuit diagram showing an example of a semiconductor device, and FIG. 21B is a cross-sectional view showing an example of the configuration of the semiconductor device of FIG. [Figure 22] 1A to 1I are circuit diagrams showing examples of semiconductor devices. [Figure 23] 1A is a cross-sectional view showing a configuration example of a semiconductor device, and FIGS. 1B and 1C are circuit diagrams showing an example of a semiconductor device. [Figure 24] 1A is a cross-sectional view showing a configuration example of a semiconductor device, and FIGS. 1B and 1C are circuit diagrams showing an example of a semiconductor device. [Figure 25] FIG. 1 illustrates an example of an RF device. [Figure 26] (A)-(F): Diagrams showing examples of RF device usage. [Figure 27] FIG. 2 is a diagram showing an example of a CPU. [Figure 28] FIG. 1 is a circuit diagram illustrating an example of a memory circuit. [Figure 29] (A)-(F): Diagrams showing examples of electronic devices. [Figure 30] 10A and 10B are diagrams illustrating band structures in a stacked structure of an insulating film and an oxide semiconductor film. [Figure 31] FIG. 10 shows measurement results of cutoff frequencies of OS transistors. [Figure 32] FIG. 10 shows the Vg-Id characteristics of the fabricated transistors. [Figure 33] (A): Circuit diagram of the fabricated circuit system. (B): Layout diagram of the same. (C): Optical microscope photograph of the same. [Figure 34] FIG. 10 is a schematic diagram showing operating waveforms during a write operation of the fabricated circuit system. [Figure 35] FIG. 10 is a graph showing the relationship between the voltage of the floating node and the write time of the fabricated circuit system. [Figure 36] FIG. 10 is a graph showing the relationship between the writing time and the capacitance of the fabricated circuit system. [Figure 37] DC characteristics of a transistor (CAAC-OS FET) using CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) film. (A): Measurement results of drain current-gate voltage (Id-Vg) characteristics. (B): Measurement results of drain current-drain voltage (Id-Vd) characteristics. [Figure 38] FIG. 10 shows the measurement results of the transconductance gm characteristics of a CAAC-OS FET. [Figure 39] FIG. 10 is a graph showing measurement results of high-frequency gain versus frequency of a CAAC-OS FET. [Figure 40] This figure shows the relationship between Vd and the cutoff frequency and maximum oscillation frequency of a CAAC-OS FET. [Figure 41] Circuit diagram of the fabricated memory circuit. [Figure 42] FIG. 42 is a diagram showing the relationship between the load capacitance Cload and the write time of the memory circuit in FIG. [Figure 43] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 44] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 45] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 46] Electron diffraction pattern of CAAC-OS. [Figure 47] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 48] 1A to 1C illustrate a method for forming a CAAC-OS film. [Figure 49] A diagram explaining the InMZnO4 crystal. [Figure 50] 1A to 1C illustrate a method for forming a CAAC-OS film. [Figure 51] 1A to 1C illustrate a method for forming a CAAC-OS film. [Figure 52] A diagram explaining the nc-OS film formation method. DETAILED DESCRIPTION OF THE INVENTION

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are designated by the same Reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a component, the hatch pattern may be the same and no particular symbol may be attached.

[0020] In each figure described in this specification, the size of each component, layer thickness, or area is shown for clarity. The figures may be exaggerated for illustrative purposes and are not necessarily limited to that scale.

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It is not a numerical limitation.

[0022] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. " refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This includes angles between 85° and 95°.

[0023] A transistor is a type of semiconductor device that controls the amplification of current and voltage, and conduction or non-conduction. The transistor in this specification can realize a switching operation that controls the is an IGFET (Insulated Gate Field Effect Tran) transistors and thin film transistors (TFTs) r), and a transistor has three elements called the gate, source, and drain. In this specification and the like, the two terminals other than the gate of a transistor are These are sometimes called the first and second terminals of the transistor.

[0024] For example, in this specification, when it is explicitly stated that X and Y are connected, , when X and Y are electrically connected, and when X and Y are functionally connected, , and the case where X and Y are directly connected. For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0025] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0026] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state) and allows current to flow. The switch has the function of controlling whether or not current flows. It has the function to switch between them.

[0027] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (synthesis circuit, memory circuit, control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if the signal is transmitted to Y.

[0028] When it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (i.e., there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected across the , when X and Y are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. The same applies if it is explicitly stated that the

[0029] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z2 When the transistor is electrically connected to Y through (or without) or the first terminal) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to part of Z2. If another part of Z2 is directly connected to Y, it can be expressed as follows: This can be done.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" terminals) are electrically connected to each other, and X, the source (or first terminal, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order. It can also be expressed as "the source (or first terminal) of the transistor." ) is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Y. The transistor is electrically connected to the X terminal (or the first terminal, etc.) of the transistor. The first terminal (or second terminal, etc.), Y are electrically connected in this order. Alternatively, "X is the distance between the source (or first terminal, etc.) and drain ( or the second terminal, etc.) and is electrically connected to Y, and X, the source (or is the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), Y is the connection order Using the same expression as these examples, By specifying the order of connections in the circuit configuration, the source (or Distinguish between the first terminal (or first terminal, etc.) and the drain (or second terminal, etc.) to determine the technical scope. These expression methods are merely examples, and the present invention is not limited to these expression methods. Here, X, Y, Z1, and Z2 are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.

[0031] (Embodiment 1) In this embodiment, a circuit system of one embodiment of the present invention will be described with reference to FIGS. 1 to 18. Here, a memory device will be described as an example of a circuit system.

[0032] <Example of circuit system configuration> FIG. 1 is a block diagram showing an example of a circuit system.

[0033] The circuit system 10 shown in FIG. 1 includes a memory cell array 12 and a peripheral circuit 14. The peripheral circuit 14 is electrically connected to the memory cell array 12. The peripheral circuit 14 includes: Row Driver, Column Driver r), and A / D converter, etc. are provided. The edge circuit 14 may include a logic circuit or the like.

[0034] The memory cell array 12 and the peripheral circuit 1 electrically connected to the memory cell array 12 4 (here, a row selection driver, a column selection driver, and an A / D converter) , may also be referred to as a storage device.

[0035] Here, a memory circuit that can be used in the circuit system of one embodiment of the present invention will be described with reference to FIG. An example of this will be described.

[0036] 2A is a circuit diagram showing an example of a memory device. The memory circuit 25 shown in FIG. , a transistor 21, a transistor 22, and a capacitor 23. The memory circuit 25 It is possible to retain data even when power is not supplied, and there is no limit to the number of times it can be written. In addition, the memory circuit 25 does not have, for example, the memory cells of the memory cell array 12 shown in FIG. It is possible to apply

[0037] Specifically, the transistor 21 and the transistor 22 are semiconductors including an oxide semiconductor. A transistor in which a channel is formed in a layer (hereinafter referred to as an "OS transistor") .) As shown in Figure 2(A), the OS (Oxide Semiconductor) The transistors with the notation "tor" indicate that they have an oxide semiconductor layer. The same applies to the other drawings. Also, in FIG. 2(A), the transistor 21 and the transistor In the example shown, both of the transistors 22 are OS transistors, but the present invention is not limited to this. At least one of the transistors 21 and 22 may be an OS transistor. It is highly preferred that transistor 22 be an OS transistor. By applying OS transistors to the memory circuit 25, it is possible to reduce the power consumption of the memory circuit 25. Specifically, since the off-state current of the transistor 22 can be reduced, It is possible to retain the stored contents. In other words, no refresh operation is required. This allows the frequency of refresh operations to be reduced significantly, resulting in sufficient power consumption. Therefore, it is possible to provide a memory circuit 25 with a reduced size.

[0038] Furthermore, the memory circuit 25 shown in FIG. 2A does not require a high voltage for writing data. For example, unlike conventional flash memory, Since electrons are not injected into the floating gate or extracted from the floating gate, Therefore, the problem of deterioration of the insulator does not occur. There is no limit to the number of times it can be rewritten, which is a problem with conventional flash memory, and it is highly reliable. This is a dramatically improved semiconductor device. Therefore, data is written, enabling high-speed operation.

[0039] The capacitance of the capacitance element 23 of the memory circuit 25 is equal to or greater than 0.1 fF and less than 10 fF. By setting the capacitance of the capacitance element 23 within the above range, the writing speed can be improved. In other words, the writing time can be shortened. In principle, the write time should be between 0.1 nsec and 5 nsec when operating at room temperature. Or, when operating at room temperature, the write speed frequency can be set to 0.2 GHz. The write speed can be set to 10 GHz or less at room temperature. This is converted to a bit rate of 400Mbps (bit pe r second) or more and 20 Gbps or less.

[0040] Here, the write time is the time required to charge the capacitor 23 of the memory circuit 25 and store data. In other words, it is the time required to charge the capacitance element 23 to 90% when writing The potential of the node FN is changed from a low level potential to a low level potential of the bit line (wiring WB This refers to the time required for the potential to rise to 90% of the reference potential (L).

[0041] The write speed is the time it takes for the write transistor of the memory circuit to change from a non-conductive state to a conductive state. Alternatively, the write speed can be expressed as a function of the current gain of the write transistor being 1 or more. In the memory circuit 25, the maximum frequency (cutoff frequency) of the transistor may be used. The transistor 22 serves as a write transistor.

[0042] Either one or both of the transistors 21 and 22 has a channel length of It is preferable that the region is 1 nm or more and less than 100 nm, and the channel length is 5 nm or more and less than 60 nm. It is more preferable that the channel length of the transistor is in the range of 100 nm or less. By doing so, it is possible to realize a miniaturized memory device or a circuit having the memory device and having a small circuit area. It is possible to provide a low-power-consumption circuit system having the memory device. do.

[0043] The memory circuit 25 shown in FIG. 2A includes a wiring WBL (also called a write bit wiring), a wiring RBL (also called read bit wiring), wiring WWL (also called write word wiring), The wiring RWL (also called read word wiring) and wiring SL (also called source line) are connected to the power supply. The wiring RBL is electrically connected to the first terminal of the transistor 21. The wiring SL is electrically connected to the second terminal of the transistor 21. The wiring WWL is electrically connected to the first terminal of the transistor 22. The gate electrode of the transistor 21 is electrically connected to the The second terminal of the capacitor 22 and the first terminal (first electrode) of the capacitor element 23 are electrically connected to each other. The line RWL is electrically connected to the second terminal (second electrode) of the capacitance element 23.

[0044] In addition, in FIG. 2A, the electrode of the capacitor 23 and the gate electrode of the transistor 21 are The electrically connected node is called node FN. The symbol "FN" indicates that the node is in an electrically floating state. In this specification, the term "node" refers to a node that can become a node. refers to a location on a wiring provided to electrically connect elements.

[0045] In the memory circuit 25 shown in FIG. 2A, the gate electrode (node ​​FN) of the transistor 21 The memory circuit 25 can hold the potential for a long period of time. I will explain the output.

[0046] To write data, first, the potential of the wiring WWL is set to a potential that turns on the transistor 22. This turns on the transistor 22, and the gate of the transistor 21 The potential of the wiring WBL is applied to the electrode and the first terminal of the capacitance element 23. A predetermined charge is applied to the electrode 23. Here, the wiring WBL is set to a low level or a high level. The capacitance element 23 is connected to the wiring WB Next, the potential of the wiring WWL is applied to the transistor 2 By turning off the transistor 22, the node FN is in an electrically floating state, and the charge given to the capacitance element 23 is held. Then, the data is written into the memory circuit 25 shown in FIG.

[0047] Since the off-state current of the transistor 22 is extremely small, the charge given to the capacitor 23 is retained for a long time. Therefore, data can be retained even when power is not supplied. It becomes Noh.

[0048] The following explains how to read data. A state in which a predetermined potential (constant potential) is applied to the wiring RBL. When an appropriate potential (read potential) is applied to the wiring RWL, the potential held in the capacitor element 23 The wiring SL has different potentials depending on the amount of charge. , the apparent threshold when a high level potential is applied to the gate electrode of the transistor 21. The value V th_H Generally, a low level potential is applied to the gate electrode of the transistor 21. The apparent threshold V th_L Here, the apparent threshold voltage The voltage refers to the potential of the wiring RWL required to turn the transistor 21 on. Therefore, the potential of the wiring RWL is V th_H and V th_L Let V0 be the potential between By doing so, the potential applied to the gate electrode of the transistor 21 can be determined. For example, In the write operation, if a high level potential is applied to the gate electrode of the transistor 21, In this case, the potential of the wiring RWL is V0 (> V th_H ), the transistor 21 is "on" When a low-level potential is applied, the potential of the wiring RWL becomes V0 (< V th_L), the transistor 21 remains in the "off state." By determining the potential of the line RBL, the stored data can be read out.

[0049] When the memory circuits 25 are arranged in an array, the data of the desired memory circuit 25 is In this way, if data is not read out, the capacitance element The potential at which transistor 21 is in the "off state" regardless of the amount of charge held in 23 , that is, V th_H Alternatively, a smaller potential may be applied to the wiring RWL. When the charge amount stored in the capacitor 23 exceeds the threshold voltage, the transistor 21 is turned on. The potential at which the th_L If a larger potential is applied to the wiring RWL, good.

[0050] Figure 2(A) shows an example of a two-transistor gain cell structure. The memory cell structure is as follows: 2A. For example, the memory circuit 26 shown in FIG. 2B or the memory circuit 26 shown in FIG. The storage circuit 27 can be applied to a memory cell.

[0051] The memory circuit 26 shown in FIG. 2B is an example of a three-transistor gain cell structure. In the memory circuit 26, the transistor 24 functions as a read transistor, and the wiring R The gate of the capacitor 23 is electrically connected to the node FN. The second terminal is electrically connected to the wiring CNL. 25. When reading data, the wiring CNL The potential of the node FN may be increased by controlling the potential of the node FN.

[0052] The memory circuit 27 shown in FIG. 2C is different from the memory circuit 25 in that the transistor 21 is not provided. The memory circuit 27 can be driven in the same manner as the memory circuit 25. The data read operation of 27 will be described. When the transistor 22 is turned on, the floating state The wiring WBL in this state is electrically connected to the capacitance element 23, and the wiring capacitance associated with the wiring WBL and the capacitance element The charge is redistributed between the electrodes 23. As a result, the potential of the wiring WBL changes. The amount of change in the potential is determined by the amount of charge stored in the capacitance element 23 (or the amount of charge stored in the first terminal of the capacitance element 23). It takes different values ​​depending on the potential.

[0053] For example, the potential of the first terminal (node ​​FN) of the capacitance element 23 is V, and the capacitance of the capacitance element 23 is C , the wiring capacitance associated with the wiring WBL is CB, and the potential of the wiring WBL before the charge redistribution is V B0, the potential of the wiring RWL is 0 [V], and the other electrode of the wiring capacitance associated with the wiring WBL is If the potential is 0 [V], the potential of the wiring WBL after the charge is redistributed is (CB × VB0 +C×V) / (CB+C). Therefore, the state of the storage circuit 27 is If the potential V of the first terminal has two states, V1 and V0 (V1>V0), the potential V1 is maintained. When the potential of the wiring WBL is The potential of the wiring WBL when the potential V0 is maintained is (=(CB×VB0+C×V0) / (C Therefore, when the potential of the wiring WBL is compared with a predetermined potential, This allows the data to be read out.

[0054] An example of the device structure of the memory circuit 25 shown in FIG. 2(A) is shown in FIG. 2(D). 1 shows a cross section of the transistors 21 and 22 of the memory circuit 25 in the channel length direction. In the actual memory circuit 25, the channels of the transistors 21 and 22 The longitudinal directions do not have to coincide with each other. This also applies to other drawings.

[0055] The memory circuit 25 shown in FIG. 2D includes a transistor 21 and a transistor 22 on a substrate 31. 1, the capacitor element 23 above the transistor 21 and the transistor 22 above the capacitor element 23. The transistor 21 has a conductive film 32 on a substrate 31 and an insulating film 3 3, a semiconductor film 34a on the insulating film 33, a semiconductor film 34b on the semiconductor film 34a, and a semiconductor a conductive film 35 electrically connected to the semiconductor film 34b; The conductive film 36, the conductive film 35, the semiconductor film 34b, the semiconductor film 34c on the conductive film 36, and the semiconductor The insulating film 37 is formed on the film 34c, and the conductive film 38 is formed on the insulating film 37.

[0056] In the transistor 21, the conductive film 32 functions as a back gate electrode. The insulating film 33 functions as an underlayer for the semiconductor film 34 and as a gate insulating film. The conductive films 35 and 36 also function as a source electrode and a drain electrode. The insulating film 37 also functions as a gate insulating film. It functions as a gate electrode.

[0057] The transistor 22 is made up of a conductive film 42, an insulating film 43 on the conductive film 42, and a semiconductor layer on the insulating film 43. The conductor film 44a, the semiconductor film 44b on the semiconductor film 44a, and the semiconductor film 44b are electrically connected to each other. a conductive film 45 electrically connected to the semiconductor film 44b; a conductive film 46 electrically connected to the semiconductor film 44b; The semiconductor film 44b and the semiconductor film 44c on the conductive film 46, and the insulating film 47 on the semiconductor film 44c and a conductive film 48 on the insulating film 47.

[0058] In the transistor 22, the conductive film 42 functions as a backgate electrode. The insulating film 43 also functions as a base film for the semiconductor film 44 and as a gate insulating film. The conductive films 45 and 46 also function as a source electrode and a drain electrode. The insulating film 47 also functions as a gate insulating film. The transistor 21 and the transistor 22 function as a gate electrode. Although the structure in which 22 has a back gate electrode is shown, the present invention is not limited to this structure, and the back gate A configuration without a gate electrode may also be used.

[0059] As shown in FIG. 2D, the transistor 21, the capacitor 23, and the transistor 22 By arranging at least some of the components in an overlapping manner, a circuit system with a small circuit area can be achieved. It is possible.

[0060] Next, an example of a semiconductor device including a plurality of memory circuits 25 shown in FIG. 2D will be described with reference to FIGS. This will be explained using FIG.

[0061] <Configuration example of memory cell array> 3A is a schematic diagram showing an example of a memory cell array. The cell array 300 has a number of sub-arrays SCA arranged horizontally by a number of vertically (a and b are the same) in a plane. Each sub-array SCA is arranged in an array of c stacked layers (c is a natural number). In this way, the memory cell array 300 is made up of memory cells MC. It has a structure in which MCs are arranged three-dimensionally.

[0062] In the specification and drawings, to distinguish between the same elements (signals, wiring, elements, circuits, etc.), In some cases, identifiers such as "1" and "[L1]" are added to terms to indicate row numbers, column numbers, order, etc. For example, "MC_j" is the jth (j is a natural number from 1 to c) of the subarray SCA. ) memory cell MC.

[0063] The memory cells MC can have a circuit configuration similar to that of the memory circuits 25-27 (FIG. 2). FIG. 3B shows an example of a circuit diagram of the memory cell MC_j. MC_j includes a transistor Ta_j, a transistor Tb_j, and a capacitance element Ca_j. The memory cell MC_j shown in FIG. 3B is a modification of the memory circuit 25 shown in FIG. Here, the symbol "Ta_j" indicates that the transistor Ta is a constituent element of the memory cell MC_j. These symbols may also be used in other drawings.

[0064] The first terminal of the transistor Ta_j is electrically connected to the wiring BL, and the second terminal of the transistor Ta_j is electrically connected to the wiring BL. The gate electrode of the transistor Ta_j is electrically connected to the gate electrode of the transistor Tb_j. The first terminal of the transistor Tb_j is electrically connected to the wiring WWL_j. The first terminal is electrically connected to the line SL. a first terminal (first electrode) of the transistor Tb_j is electrically connected to the gate electrode of the transistor Tb_j, The second terminal (second electrode) is electrically connected to the wiring RWL_j.

[0065] The transistor Ta_j has a back gate electrode (BG). The electrode can be applied with a potential lower or higher than the source electrode, The threshold voltage of Ta_j can be shifted in the positive or negative direction. By shifting the threshold voltage of the n-channel transistor in the positive direction, the gate voltage Normally-off is realized, where the transistor is in a non-conducting state (off state) even when the potential is 0V. The potential applied to the back gate electrode may be variable. When the potential applied to the back gate electrode is made variable, the potential can be controlled. A circuit for controlling the back gate electrode may be connected to the back gate electrode. The back gate electrode and the gate electrode of the transistor Ta_j may be connected to each other. By applying the same potential, the on-current increases, the initial characteristic variations are reduced, and the -GBT( -Gate Bias-Temperature) Stress test degradation suppression and different This makes it possible to suppress fluctuations in the on-state current rise voltage at the drain voltage. By increasing the on-current of the transistor Ta_j, for example, the write operation of the memory cell array 300 can be performed. The loading time can be reduced.

[0066] Although not shown in FIG. 3B, the transistor Tb_j also has a back gate electrode. By providing a back gate electrode, the on-current of the transistor Tb_j can be increased. The increase in the on-current can reduce the read time of the memory cell array 300, for example. The ejection speed can be increased.

[0067] Here, the voltage of the node FN is controlled by controlling the word signal given to the wiring WWL_j. The potential of the memory cell MC_j is set to a potential corresponding to the potential of the wiring BL. , by controlling the read signal given to the wiring RWL_j, The potential of the node FN is set to a potential corresponding to the potential of the node FN. It means to read it out.

[0068] A potential corresponding to binary or multi-valued data is applied to the wiring BL. is k-bit data (k is a natural number greater than or equal to 2). Specifically, it is 2-bit data. If there is a signal, it is four-valued data, and the signal input to the wiring BL has four types of potential levels. A read signal is applied to the wiring RWL_j. In order to selectively read data from the memory cell MC_j, a signal is generated to control the potential of the node FN. A word signal is applied to the wire WWL_j. This is a signal that turns on the transistor Ta_j in order to provide the potential of L to the node FN. do.

[0069] The node FN is connected to the first electrode of the capacitor Ca_j, the second terminal of the transistor Ta_j, and This corresponds to one of the nodes on the wiring that connects the gate electrode of the transistor Tb_j. For example, For example, the node FN may contain liquid crystal elements or organic EL (Electroluminescence) elements. When the display element is provided, the memory cell M A part of C_j can be made to function as a pixel of a display device.

[0070] The potential of the node FN is based on the data applied to the wiring BL. , the transistor Ta_j is turned off to be in an electrically floating state, and the capacitance The element Ca_j capacitively couples the wiring RWL_j and the transistor Tb_j. Therefore, the potential of the node FN can be changed by changing the potential of the wiring RWL_j. When the potential of the read signal applied to the wiring RWL_j is changed, the potential of the node FN The potential is the original potential plus the change in the potential of the read signal.

[0071] The transistor Ta_j switches between a conductive state and a non-conductive state to write data. The transistor Ta_j has a function as a switch that controls the input. By maintaining the state, the potential based on the written data is maintained. The transistor Ta_j is an n-channel transistor.

[0072] In addition, when the transistor Ta_j is in a non-conducting state, a potential difference between the source electrode and the drain electrode is It is preferable to use a transistor with a low off-state current. The low off-state current is obtained when the voltage between the source and drain electrodes is 10 V at room temperature. The normalized off-state current per 1 μm of channel width is 10 zA or less. As a transistor with such a low off-state current, Examples include transistors.

[0073] By using a transistor with a small off-state current as the transistor Ta_j, Therefore, the potential of the node FN, which is in a floating state, can be maintained for a long period of time. Therefore, the refresh frequency of the memory cell MC_j can be reduced, and the power consumption Therefore, a semiconductor device with less noise can be realized.

[0074] For example, if the potential held at node FN is 3.15 x 10 for 10 years at 85°C, 8 seconds ) in order to maintain the normalized off-state current per 1 fF of capacitance, the transistor Ta_j The current value is 4.3 yA (yoctoampere: 1 yA is 1 x 10 -24 A) It is preferable that it is less than In this case, it is preferable that the allowable fluctuation in the potential of the node FN is within 0.5 V. Alternatively, it is preferable that the normalized off-state current at 95°C is less than 1.5 yA. It's nice.

[0075] In the configuration of the memory cell MC_j shown in FIG. 3B, when the transistor Ta_j is in a non-conductive state, Therefore, the potential of the node FN is maintained. The transistor Ta_j is a switch that can suppress the fluctuation of the potential caused by the movement of A transistor with a small off-state current is particularly preferable.

[0076] Therefore, by using a transistor Ta_j with a low off-state current, The cell array 300 can be a nonvolatile memory. The data written to C_j remains in the node until transistor Ta_j is again turned on. You can keep it in the FN.

[0077] The transistor Tb_j has a potential between the source electrode and the drain electrode in accordance with the potential of the node FN. In the configuration of the memory cell MC_j shown in FIG. The current Id flowing between the source electrode and the drain electrode of the transistor Tb_j is The current flowing between the transistor Tb_j and the wiring SL is a The transistor used in the above (hereinafter referred to as a Si transistor) may be used. An OS transistor using a conductor as an active layer may also be used. j is an OS transistor and an n-channel transistor.

[0078] The transistors Ta_j and Tb_j have, for example, a switching speed of Fast n-channel transistors can be used. For example, the transistor switch The switching speed is 0.1 ns or more and less than 5 ns. By using an OS transistor containing an oxide (preferably an oxide containing In, Ga, and Zn), The above switching speed can be achieved by using the The switching speed represents the time it takes for one transistor to go from a non-conducting state to a conducting state. The switching speed of a transistor is the current that flows when the transistor is used as an amplifier. It may also be expressed as the speed corresponding to the maximum frequency (cutoff frequency) at which the flow gain is 1 or more.

[0079] <Memory cell array circuit configuration example 1> Here, the memory cells MC_j shown in FIG. 3B are arranged three-dimensionally to form a memory cell array An example of the memory cell array 300 is shown in FIG. As shown in Figure 4, the subarray SCA is The array SCA has c memory cells MC, and each memory cell MC is connected to a wiring BL and The wiring SL is shared.

[0080] <Example of memory cell array operation> Next, the operation of the memory cell array 300 shown in FIG. 5 is a timing chart illustrating an example of the operation of the rechargeable battery array 300. The diagram shows the wiring WWL_c, wiring RWL_c, node FN, wiring BL, and wiring SL. This shows the changes in each signal given to

[0081] First, the write operation will be explained using FIG. 5(A). Here, we will explain the write operation of binary data. However, the memory cell array 300 is not limited to writing binary data. In addition, multi-value data can be written. , a write period T1, a pause period T2, and a non-selection period T3 are shown.

[0082] In the write period T1, first, a potential V2 is applied to the wiring WWL_c. L has a potential corresponding to the binary data, that is, a high (H) level potential or a low (L) level potential. The wiring SL is supplied with a potential of the same level as that of the wiring BL. When BL is at H level, the line SL is also given a H level potential. At this time, the line SL is also supplied with an L-level potential.

[0083] In the idle period T2, the wiring BL and the wiring SL are applied with a low-level potential, and the wiring RWL_ A potential V0 is applied to the wiring WWL_c and the wiring WWL_c. The potential V2 should be a positive potential. The absolute value of the potential V2 is greater than the potential at the H level. It is preferable that the potential be large, for example, the potential of the H level plus the threshold voltage of the transistor Ta_c. and less than the H-level potential plus three times the threshold voltage of the transistor Ta_c. Just do that.

[0084] In the non-selection period T3, a potential V1 is applied to the wiring RWL_c and the wiring WWL_c. The potential V1 may be set to, for example, a negative potential. The absolute value of the potential V1 is greater than the potential of the H level. For example, it is preferable that the potential be higher than the H level potential plus the threshold voltage of the transistor Tb_c. If it is large and less than three times the H level potential plus the threshold voltage of transistor Tb_c, In addition, an L-level potential is applied to the wirings BL and SL.

[0085] Next, the read operation will be described with reference to FIG. 5(B). The timing chart shows a period T4 in which the potential of the wiring BL is precharged, a period T5 in which the potential of the wiring BL is precharged, and a period T6 in which the potential of the wiring BL is precharged. 10 shows a period T5 during which the wiring BL is discharged for this purpose, and a non-selection period T6.

[0086] In the period T4 shown in FIG. 5B, the wiring BL is precharged. A potential V1 is applied to the wiring RWL_c. , V1 is a potential lower than V0. For example, V0 is the ground potential and V1 is a negative potential. In addition, a potential corresponding to the data is held at the node FN. The line BL is supplied with an H-level potential (VH), and the line SL is supplied with an L-level potential (VH). Here, the absolute value of the potential V1 is preferably greater than the potential of the H level, For example, the potential of the H level plus the threshold voltage of the transistor Tb_c is greater than the potential of the H level. The potential should be less than three times the bell potential plus the threshold voltage of transistor Tb_c.

[0087] In the period T4, the wiring BL is supplied with an H-level potential VH and then placed in an electrically floating state. That is, the wiring BL is in a state where a potential fluctuation occurs due to charging or discharging of electric charges. This floating state can be achieved by turning off the switch that applies a potential to the wiring BL.

[0088] Next, in a period T5 shown in FIG. 5B, the potential of the node FN is set to At this time, the line WWL_c is discharged at the potential V 1 is applied to the wiring SL. The wiring SL is applied with a potential of L level as in the previous period. Since the potential V0 is applied to RWL_c, the potential of the node FN rises. The conduction state of the transistor Tb_c changes depending on the potential of FN. When the potential of the wiring BL When a low-level potential is written to the node FN, the potential of the node FN drops to the potential VL. Since the transistor Tb_c is in a non-conductive state, the potential of the wiring BL is maintained at the H level. It will be held.

[0089] Next, in a period T6 shown in FIG. 5B, the potential of the wiring RWL_c is set to V1. This puts memory cell MC_c into a non-selected state, enabling the operation of reading data from memory cell MC_c. The work is completed.

[0090] <Memory cell array circuit configuration examples 2 and 3> Other examples of the circuit configuration of the memory cell array 300 are shown in FIGS. 6 and 7. 1 is a circuit diagram showing an example of a memory cell array 300, and is a circuit diagram of a sub-array SCA.

[0091] The circuit configuration example in FIG. 6 is a modification of FIG. 4. The difference from the example in FIG. 4 is that odd-numbered memory cells The even-numbered memory cells MC and the even-numbered memory cells MC are electrically connected to different wirings SL. The odd-numbered memory cells MC and the even-numbered memory cells MC are alternately connected to the line BL. Therefore, the integration density of the sub-array SCA can be increased. In the sub-array SCA shown in Fig. 7, c Each memory cell MC shares one wiring SL. It can be made easier.

[0092] <Memory cell stack structure example 1> 8 is a cross-sectional view showing an example of a memory cell array. The example of FIG. 8 has the circuit configuration of FIG. This corresponds to an example in which a memory cell array is configured with sub-arrays SCA each having a plurality of sub-arrays.

[0093] Figure 8 shows three adjacent subarrays (SCA[α-1], SCA[α], and SCA[α +1]) are shown in the figure. The sub-arrays SCA are adjacent to each other when the x In the y-plane, one of the x-coordinate and y-coordinate is different by 1, while the other is the same. For example, , the y-coordinates of the three subarrays (SCA[α-1], SCA[α], SCA[α+1]) are If they are equal, then if the x-coordinate of the subarray SCA[α] is k (k is an integer between 2 and a), , the x-coordinate of the subarray SCA[α-1] is k-1, and the x-coordinate of the subarray SCA[α+1] is k-1. The x coordinate is k+1.

[0094] Figure 8 shows the memory of the sub-arrays (SCA[α-1], SCA[α], SCA[α+1]). Although not shown, the memory cells MC_1 and MC_2 of each sub-array are On each of the memory cells MC_2, a memory cell MC_3 is stacked. By increasing the number of stacked memory cells MC, the circuit area is increased. The degree of integration of the memory cell array 300 can be increased without increasing the number of memory cells.

[0095] The device structure of the memory cell array 300 shown in FIG. For clarity of the drawing, only some of the elements (transistors) constituting the memory cell array 300 are shown. The identification symbol "_1" is not attached to the symbols (e.g., Ta). The structure of the memory cell array 300 may be described with or without the addition of a suffix such as "1". The same applies to the other drawings.

[0096] In each memory cell MC, the transistor Ta and the transistor Tb are made of an oxide semiconductor material. A capacitance element Ca is provided on the transistor Tb. An insulating film 216 is provided between the gate Tb and the capacitance element Ca. Preferably, a part of the insulating film 115 overlaps with the transistor Tb. The conductive film 204a is sandwiched between the conductive film 151 and the conductive film 155 to form a capacitor element Ca. The conductive film 204b serves as the source electrode or the drain electrode of the transistor Tb. The conductive film 151 is connected to the gate electrode 20 of the transistor Tb via the plug 141. 3 and electrically connected to each other.

[0097] The transistor Ta is provided on the capacitance element Ca. An insulating film 156 is provided between the transistors Ta. At least a part of the transistor Ta is It is preferable that the conductive film 104a is provided so as to overlap with the capacitor element Ca. b respectively function as the source electrode and the drain electrode of the transistor Ta.

[0098] The conductive films 204a and 204b are electrically connected to the wiring SL (not shown). The conductive film 104a is connected to the conductive film 104a via the plug 142, the conductive film 153, the plug 145, and the like. The conductive film 204a and the conductive film 104a are electrically connected to the wiring BL (not shown). The plug 142, the conductive film 153, the plug 145, etc. are electrically connected to the wiring BL. It may also function as such.

[0099] Two adjacent memory cells MC_j share the plug 142, the conductive film 153, etc. Specifically, the memory cell MC_j of the subarray SCA[α] is ] and the memory cell MC_j share the plug 142, the plug 145, and the conductive film 153. By sharing plugs and conductive layers between two adjacent sub-arrays (SCAs), memory cells The integration density of the array 300 can be increased.

[0100] In addition, the conductive film 104a and the conductive film 204b are shared by the adjacent MC_j. Specifically, the subarrays SCA[α-1] and SCA[α] are The transistor Ta shares the conductive film 104a. Each transistor Tb of CA[α+1] shares the conductive film 204a. By sharing the conductive film, the integration degree of the memory cell array 300 can be increased.

[0101] <Memory cell stack structure example 2> 9 and 10 show modifications of the memory cell array 300 shown in FIG. The memory cell array 300 shown in FIG. , layers 291 to 297. The layer 291 includes a transistor. The layer 92 and the layer 293 include a conductive film. The layer 294 includes a transistor. The layers 295 and 296 include conductive films, and the layer 297 includes a transistor.

[0102] In the sub-array SCA of the memory cell array 300 shown in FIG. The order is element Ca, transistor Ta, transistor Tb, capacitor Ca, and transistor Ta. In contrast, in the sub-array SCA shown in FIG. By arranging the transistor Tb, the capacitance element Ca, the transistor Ta, and the capacitance The element Ca and the transistor Tb are stacked in this order. This simplifies the process. .

[0103] In the memory cell MC, a capacitance element Ca is provided on the transistor Tb. The transistor Ta is provided on the capacitor Ca. The capacitor Ca overlaps with the transistor Tb. It is preferable that the second insulating film has a region overlapping with the transistor Ta. A part of the capacitance element Ca has an area overlapping with the transistor Tb of the adjacent memory cell MC. By using the device structure shown in FIG. The degree of integration can be increased.

[0104] Specifically, in the subarray SCA[α], the memory cell MC_2 and the memory cell MC _3 has a symmetrical structure. Therefore, the capacitance element Ca is connected to the transistor Ta and By using this structure, the sub-array SCA In this case, the memory cells MC can be arranged alternately, and the memory cell MC A capacitance element can be formed on the transistor Ta, which increases the degree of integration. 8, the process can be simplified.

[0105] In the sub-array SCA[α], c memory cells MC are arranged alternately. As a result, in the two memory cells MC adjacent to each other on the top and bottom, the transistors Ta and In this way, the active region of the adjacent memory cells is The transistors constituting the memory cell array 300 are formed in the same layer. Since the number of memory cells is reduced, the memory cell array 300 can be manufactured in fewer steps. By reducing the number of manufacturing steps, the yield can be increased. As the number of layers increases, the film stress of, for example, an insulating film, a conductive film, a semiconductor film, etc. Therefore, it is recommended to reduce the number of films to be laminated. This can reduce failures of the semiconductor device due to film peeling or the like.

[0106] <Memory cell stack structure example 3> An example of a memory cell array is shown in Fig. 11. The memory cell array 300 shown in Fig. 8 and 9. FIG.

[0107] In the memory cell array 300 shown in FIG. 11, the memory cells MC are arranged alternately. 9 in the same way as in FIG. 9. The following points are different: In the memory cell MC, A capacitance element Ca is located, and a transistor Tb is located above the capacitance element Ca. In the several memory cells MC (MC_1, MC_3 in FIG. 11), the transistor Tb The gate electrode 203 of the even-numbered memory cell M is electrically connected to the capacitance element Ca. In C (memory cell MC_2 and memory cell MC_4 in FIG. 11), the conductive film 205 is The conductive film 205 is electrically connected to the capacitor element Ca. It functions as a gate electrode.

[0108] That is, in the example of FIG. 11, the memory cell MC_j where j is an odd number and the memory cell MC_ In the example of FIG. 11, the transistor Ta and the transistor Tb are the same. The semiconductor film of the transistor Ta and the semiconductor film of the transistor Tb do not need to be formed on a single layer. The semiconductor film having the transistor T can be formed from a different semiconductor film. The semiconductor films of the transistors a and Tb are made of oxides with different constituent elements and atomic ratios. It is easy to form the semiconductor film.

[0109] The above is a description of an example of the configuration of the memory cell array 300. The structures of the transistors Ta and Tb included in the circuit 300 will be described.

[0110] <Transistor configuration example 1> FIG. 12B is a top view illustrating an example of the structure of a transistor, and FIG. 12(B) is a cross-sectional view taken along line AB in FIG. 12(B), and FIG. 12(C) is a cross-sectional view taken along line CD in FIG. 12(B). The transistor TR1 shown in FIG. 12 is an OS transistor, and the transistor of the memory cell MC The transistor TR1 is an example of a transistor equivalent to the transistor Ta. It can also be applied to Tb.

[0111] The transistor TR1 includes a semiconductor film 101, a conductive film 104a, a conductive film 104b, a gate insulating film 104b, and a gate insulating film 104c. The insulating film 102 , the gate electrode 103 , the conductive film 105 , and the insulating film 114 are included.

[0112] The semiconductor film 101 includes a semiconductor film 101a in contact with the upper surface of the insulating film 114, a semiconductor film 101a and a semiconductor film 101b in contact with the upper surface of the semiconductor film 101b. In the example of FIG. 12A, the semiconductor film 101 includes a semiconductor film 101a, a semiconductor film 101b, a semiconductor film 101c, and a semiconductor film 101c. The semiconductor film 101 has a laminated structure of the above-mentioned laminated film 101b and the semiconductor film 101c. The gate electrode 103, the gate insulating film 102, and the gate insulating film 103 may be formed as a single layer. The edges of the gate insulating film 102 and the semiconductor film 101c are approximately aligned. In the etching process for forming the film 101c, the gate electrode 103 functions as a mask. Because.

[0113] The conductive film 104a and the conductive film 104b serve as a source electrode and a drain electrode, respectively. The conductive film 104a and the conductive film 104b are in contact with the upper surface of the semiconductor film 101b, and The semiconductor film 101c is separated from the semiconductor film 101b and the conductive film 104. The gate electrode 103 is in contact with the upper surfaces of the gate insulating film 104a and the conductive film 104b. The conductive film 105 faces the semiconductor film 101 via the insulating film 114. The conductive film 105 functions as a back gate electrode of the transistor TR1.

[0114] In other words, the semiconductor film 101a is provided between the insulating film 114 and the semiconductor film 101b. The semiconductor film 101c is provided between the semiconductor film 101b and the gate insulating film 102. The conductive film 104a and the conductive film 104b are in contact with the upper surface of the semiconductor film 101b. The side surface of the semiconductor film 101b is in contact with the bottom surface of the conductive film 104a and the bottom surface of the semiconductor film 101c. and contacts the conductive film 104b.

[0115] Note that the conductive film 105 may not be provided. The conductive film 105 may be electrically connected to the gate electrode 103. When the gate electrode 103 is electrically connected and the same potential is applied, the on-current increases. Addition, reduction of initial characteristic variations, -GBT (-Gate Bias-Temperature e) Suppression of degradation during stress testing and rise of on-current at different drain voltages It is possible to suppress voltage fluctuations by increasing the on-current of transistor TR1. For example, the read speed of the memory cell array 300 can be increased.

[0116] In addition, the semiconductor film 101b is electrically surrounded by the electric field of the gate electrode 103. (The structure of the transistor that electrically surrounds the semiconductor film by the electric field of the conductive film is called s This is called a surrounded channel (s-channel) structure. The transistor TR1 is an s-channel structure device. In the s-channel structure, a channel may be formed in the bulk. A large current can be passed between the source and drain electrodes of the transistor, and the current when it is conducting (ON current) can be increased.

[0117] The s-channel structure described above can obtain a high on-current, making it suitable for miniaturized OS transistors. This structure is suitable for OS transistors. The semiconductor device having the transistor is a highly integrated and highly dense semiconductor device. For example, an OS transistor can be fabricated with a channel length of 1 nm or more and less than 100 nm. More preferably, the channel length is in the range of 5 nm to 60 nm.

[0118] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). The source (source region or source electrode) in the region where the channel is formed. The distance between the transistor and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In this case, the channel length is any one value, maximum value, or maximum value in the region where the channel is formed. The minimum or average value.

[0119] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on state). The area where the gate electrode overlaps with the electrode (the part of the body where current flows) forms a channel. The source (source region or source electrode) and drain (drain region or The length of the part where the gate electrode (gate electrode) faces the drain electrode is called the length of the part where the gate electrode faces the drain electrode. In this case, the channel width does not necessarily have the same value in all regions. The channel width of the data may not be determined to a single value. The channel width is any one value, maximum value, minimum value or average value in the region where the channel is formed. The average value is used.

[0120] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in a transistor with a fine, three-dimensional structure, the upper surface of the semiconductor The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the inside of the semiconductor In this case, the apparent channel width shown in the top view may be The effective channel width where the channel is actually formed is larger than the actual channel width.

[0121] In addition, in a transistor with a three-dimensional structure, the effective channel width is measured For example, it may be difficult to estimate the effective channel width from the design value. Therefore, it is necessary to assume that the shape of the semiconductor is known. If it is not known precisely, it is difficult to accurately measure the effective channel width.

[0122] Therefore, in this specification and the like, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The source (source region or source electrode) and the drain (drain region or The apparent channel width, which is the length of the part where the gate electrode (or drain electrode) faces the gate electrode, is called the " Surrounded Channel Width (SCW) In this specification, when simply referring to the channel width, In this specification, the term "channel width" may refer to the actual channel width or apparent channel width. When simply referred to as channel width, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosed channel width The values ​​are determined by taking cross-sectional TEM images and analyzing the images. It is possible.

[0123] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0124] Hereinafter, each component of the transistor TR1 shown in FIG. 12 will be described in detail.

[0125] <Insulating film that functions as a base film> The insulating film 114 preferably contains an oxide, particularly an oxide that releases oxygen by heating. It is preferable that the semiconductor film 101 contains a material. is preferred.

[0126] As an oxide material that releases oxygen by heating, it is possible to It is preferable to use an oxide containing more oxygen than the stoichiometric composition. Oxygen-containing oxide films were analyzed by thermal desorption spectroscopy (TDS). In the ion spectroscopy analysis, the amount of oxygen released in terms of oxygen atoms was 1 .0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3The oxide film is one of the above. The surface temperature of the film during the TDS analysis was 1 The temperature range is preferably 00°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower.

[0127] Examples of oxide materials that release oxygen when heated include silicon oxide and silicon oxynitride. It is preferable to use a material containing silicon, or a metal oxide can also be used. Metal oxides include aluminum oxide, aluminum oxynitride, gallium oxide, and oxynitride. Gallium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride In this specification, silicon oxynitride refers to a compound thereof. Silicon nitride oxide is a material that has a higher oxygen content than nitrogen as a composition. This refers to a material that contains more nitrogen than oxygen.

[0128] When an oxide semiconductor is used for the semiconductor film 101, oxygen released from the insulating film 114 is converted into oxygen. This allows oxygen vacancies in the oxide semiconductor to be reduced. As a result, fluctuations in the electrical characteristics of the transistor TR1 can be suppressed, and reliability can be improved.

[0129] The upper surface of the insulating film 114 is planarized by, for example, CMP (Chemical Mechanical Polishing). The surface has been flattened by a flattening process using a method such as mechanical polishing. It is preferable.

[0130] <Semiconductor film> The semiconductor film 101 preferably contains a semiconductor having a band gap larger than that of silicon. Preferably, the semiconductor film 101 is made of an oxide semiconductor. By using semiconductor materials with a wide band gap and low carrier density, It is preferable to use such a material for the semiconductor film 101 because it can reduce the current in the OFF state. By using such a material, fluctuations in electrical characteristics can be suppressed, and a highly reliable transistor can be realized.

[0131] More specifically, it is preferable to use an oxide semiconductor film as the semiconductor film 101. For example, the semiconductor film 101b may have a composition of In:Ga:Zn=1:1:1, 2:1:3, 3:1:2 In the case of using an In-Ga-Zn oxide having an atomic ratio of 4:2:3, the semiconductor film 101 a or the semiconductor film 101c is In:Ga:Zn=1:3:2, 1:3:4, 1:3 :6, 1:6:4, 1:6:8, 1:6:10, 1:9:6, or 1:2:3 The semiconductor film 101b can be made of an In-Ga-Zn oxide having a molecular ratio of 0.1 to 0.2. The atomic ratios of the solid film 101a and the semiconductor film 101c are calculated by subtracting the above atomic ratios from the above atomic ratios as an error. The semiconductor film 101a and the semiconductor film 101c have a variation of ±20%. Materials having the same composition may be used, or materials having different compositions may be used.

[0132] When an In-M-Zn oxide is used as the semiconductor film 101b, the semiconductor film 101b The target used to form the semiconductor film is a metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is 1 / 3. z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. It is preferable to use an oxide having an atomic ratio of 1 to 6. This facilitates the formation of a CAAC-OS film, which will be described later. Typical examples of the atomic ratio are In:M:Zn = 1:1:1, 2:1:3, 3:1:2, etc. There are such cases.

[0133] When In-M-Zn oxide is used as the semiconductor film 101a and the semiconductor film 101c, the target used to form the semiconductor films that become the semiconductor film 101a and the semiconductor film 101c <00012...​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​<Conductive film functioning as source electrode and drain electrode> The conductive film 104a and the conductive film 104b are made of aluminum, titanium, chromium, nickel, copper, Gold, such as yttrium, zirconium, molybdenum, silver, tantalum, or tungsten The metal or alloy containing this metal as the main component is used as a single layer structure or a laminated structure. A single-layer structure of aluminum film containing silicon, and a two-layer structure of aluminum film laminated on titanium film Two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, Two-layer structure in which a copper film is laminated on a titanium film or titanium nitride film and the titanium film Alternatively, an aluminum film or copper film is laminated on the titanium nitride film, and then a titanium film is further laminated on top of that. a three-layer structure forming a titanium nitride film or a molybdenum nitride film, a molybdenum film or a molybdenum nitride film, An aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There are also three-layer structures in which a molybdenum film or a molybdenum nitride film is formed on top of the first layer. A transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0137] <Gate insulating film> The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminated layer or a single layer.

[0138] The gate insulating film 102 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y Nz ), nitrogen-doped hafnium Luminate (HfAl x O y N z ), using high-k materials such as yttrium oxide Good too.

[0139] The gate insulating film 102 may be made of aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, silicon oxide oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide insulating film, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide The insulating film can be formed using a nitride insulating film such as the above, or a film made of a mixture of the above materials.

[0140] The gate insulating film 102 is made of an acid having a stoichiometric composition, similar to the insulating film 114. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0141] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. Like the stacked film of hafnium, a part of the gate insulating film is made of hafnium oxide, aluminum oxide, and oxide. By using a material with many electron capture levels, such as tantalum, and by using it at a higher temperature (the operating temperature of the semiconductor device), Or higher than the storage temperature, or 125°C or higher and 450°C or lower, typically 1 Under the temperature range of 50°C to 300°C, the potential of the gate electrode is set to the potential of the source electrode and drain electrode. By maintaining a higher state for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move towards the poles, and some of them are captured by the electron capture levels.

[0142] In this way, a transistor that has captured the necessary number of electrons in the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The process of adding the conductive layer may be performed during the manufacturing process of the transistor.

[0143] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After the wafer processing, or after the wafer dicing process. It is advisable to carry out this at any stage before shipping from the factory, such as after packaging. It is preferred that the subsequent exposure to temperatures above 125°C is not carried out for more than one hour.

[0144] <Gate electrode> The gate electrode 103 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It is made of an alloy of metals. In addition, either manganese or zirconium Alternatively, one or more metals selected from the above may be used. Semiconductors such as polycrystalline silicon and silicides such as nickel silicide are used. The gate electrode 103 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of aluminum film containing silicon, a titanium film stacked on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; Two-layer structure with tantalum nitride or tungsten nitride film laminated on top of tungsten nitride film A two-layer structure in which a titanium film is laminated on top of the titanium film, and an aluminum film is laminated on top of the titanium film. There are also three-layer structures in which a titanium film is formed on top of the aluminum. One or more metals selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film made of a combination of multiple metals or a nitride film may be used.

[0145] The gate electrode 103 is made of indium tin oxide or indium containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide may also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0146] In addition, an In-Ga-Zn oxynitride semiconductor film is formed between the gate electrode 103 and the gate insulating film. , In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Zn oxynitride Semiconductor film, Sn oxynitride semiconductor film, In oxynitride semiconductor film, metal nitride film (InN, These films have a specific energy of 5 eV or more, preferably 5.5 eV or more. The electron affinity of the oxide semiconductor is larger than that of the oxide semiconductor. The threshold voltage of the transistor can be shifted to the positive side, resulting in a so-called normally-off transistor. For example, an In-Ga-Zn oxynitride semiconductor film can be used to realize a switching element with high characteristics. When used, the nitrogen concentration is at least higher than that of the semiconductor film 101, specifically, 7 atomic % or more of I An n-Ga-Zn oxynitride semiconductor film is used.

[0147] <Conductive film functioning as a back gate electrode> The conductive film 105 may be formed using a material similar to that of the gate electrode 103 .

[0148] <Transistor configuration example 2-6> Next, a configuration example different from that of the transistor TR1 shown in FIG. 12 will be described. 14 shows a modified example of the transistor TR1.

[0149] The transistor TR1 shown in FIG. 12 has a gate insulating film 102 and a semiconductor film 101c. The TR2 shown in FIG. 13 is processed so that the end of the semiconductor film 101c is It is processed so as to be positioned inside the gate insulating film 102. 13(A) is a cross-sectional view taken along line AB in FIG. 13(B). 13(C) is a cross-sectional view taken along the line CD.

[0150] The transistors shown in FIG. 14 are the transistor Ta of the memory cell MC and the transistor 14 is a cross-sectional view of the transistor in the channel length direction.

[0151] The transistor TR3 shown in FIG. 14A is a modified example of the transistor TR2. The structure of the conductive film 104a is different from that of the conductive film 104b. For example, the transistor TR3 is The semiconductor film 101a and the semiconductor film 101b can be fabricated through the steps. For this purpose, two semiconductor films are formed, and the conductive film 104a and the conductive film 104b are formed on the stacked film of the semiconductor films. A resist mask is formed on the conductive film, and the conductive film is etched. A mask made of a conductive film is formed by etching the semiconductor film stack using this mask. Then, a mask is processed to form a conductive film. Then, a conductive film 104a and a conductive film 104b are formed.

[0152] The transistor TR4 shown in FIG. 14B is a modified example of the transistor TR2. In the transistor TR4, the semiconductor film 101c is in contact with the lower surfaces of the conductive films 104a and 104b. By adopting such a structure, the semiconductor film 101a and the semiconductor film 101b and exposing the semiconductor film 101c to the atmosphere during the deposition of each film constituting the semiconductor film 101c. Since the films can be formed continuously without any interfacial defects, the number of interfacial defects can be reduced.

[0153] The transistor TR5 shown in FIG. 14C is a modified example of the transistor TR4. In the transistor TR5, an opening is provided in the insulating film 116 to form a plug 118a and a plug 118b. The plugs are used as the source and drain electrodes of the transistor.

[0154] The transistor TR6 shown in FIG. 14(D) is a modified example of the transistor TR5. In the transistor TR6, a low resistance region 171a and a low resistance region 171b are provided in the semiconductor film 101. For example, the low resistance region is formed as follows: Next, a gate insulating film 102 and a gate electrode 103 are formed. Next, using the gate electrode 103 as a mask, the low resistance region 171a and the low resistance region 171b The low resistance regions 171a and 171b are regions with high carrier density.

[0155] Methods for increasing the carrier density include adding impurities and forming oxygen vacancies. For example, to increase the carrier density, elements can be added by ion implantation. Usable elements include, for example, argon, boron, carbon, and magnesium. , aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, Chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium Zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium It is preferable to add one or more selected from the group consisting of zinc, hafnium, tantalum and tungsten. The low resistance region 171a and the low resistance region 171b are doped with the above impurity elements at a concentration of 5×10 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 That's all, and more Preferably 2 x 10 20 atoms / cm 3 More preferably, 5 × 10 20 atom s / cm 3 This is an area that includes the above.

[0156] The low resistance region 171a and the low resistance region 171b can trap unnecessary hydrogen. There is a possibility that unnecessary hydrogen may be trapped in the low resistance region 171a and the low resistance region 171b. This can reduce the hydrogen concentration in the channel region.

[0157] The above is a list of transistors that can be applied to the transistors Ta and Tb. 10 is a diagram illustrating an example of the configuration of the data.

[0158] <Memory cell fabrication method example> 15 to 18, a method for manufacturing the memory cell array 300 shown in FIG. 9 will be described below. Here, an example of the method will be described. The transistor TR2 shown is applied.

[0159] A substrate 100 is prepared. The substrate 100 is, for example, a single crystal silicon substrate (p-type semiconductor semiconductor substrates, including n-type semiconductor substrates, silicon carbide and gallium nitride A compound semiconductor substrate, a glass substrate, or the like can be used. In the following, a case where single crystal silicon is used as the substrate 100 will be described. This article explains:

[0160] Next, a conductive film that will become the conductive film 105 and the like is formed on the substrate 100. The conductive film can be formed by, for example, sputtering, CVD (thermal CVD, MOCVD, etc. The methods used include the MBE method, ALD method, and PLD method. Next, a resist mask is formed, and unnecessary portions of the conductive film that will become the conductive film 105 and the like are etched away. The resist mask is then removed, and the conductive film 105 and the like are formed.

[0161] Next, an insulating film 114 is formed on the substrate 100 and the conductive film 105. For example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), It can be formed by using MBE, ALD, PLD, or the like. When the film is formed by a CVD method, preferably a PECVD method, the coating property can be improved. In order to reduce damage caused by plasma, thermal CVD and MOCV are preferable. The D method or the ALD method is preferred.

[0162] In order to make the insulating film 114 contain excess oxygen, for example, the insulating film 114 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to remove oxygen. Alternatively, a region containing the hydroxyl group may be formed, or both methods may be combined.

[0163] For example, the insulating film 114 after deposition may contain oxygen (at least oxygen radicals, oxygen atoms, and oxygen ions). The oxygen-introducing method includes introducing oxygen into the silicon dioxide gas to form a region containing excess oxygen. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0164] The oxygen introduction treatment can be performed using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, a mixture of carbon dioxide, hydrogen and argon may be used. stomach.

[0165] After the insulating film 114 is formed, the insulating film 114 is polished by a CMP method or the like to improve the flatness of the upper surface. A flattening process may also be performed.

[0166] Next, a connection to the source electrode or drain electrode of the transistor Tb is formed on the insulating film 114. First, an opening is provided in the insulating film 114. Next, the opening is A conductive film 133 that will become a plug is formed so as to fill the gap (FIG. 15(A)).

[0167] Next, the conductive film 133 is subjected to planarization treatment so that the surface of the insulating film 114 is exposed. A groove 134 is formed (FIG. 15(B)).

[0168] Next, a semiconductor film that will become the semiconductor film 101a, etc., and a semiconductor film that will become the semiconductor film 101b, etc. are formed on the insulating film 114. The semiconductor films are successively formed without being exposed to the atmosphere. It is preferable that the semiconductor film that becomes the semiconductor film 101a and the semiconductor film that becomes the semiconductor film 101b are formed by the above-mentioned method. The semiconductor film is formed by sputtering, CVD, MBE, PLD, ALD, etc. The film can be formed by

[0169] The semiconductor film that will become the semiconductor film 101a and the like and the semiconductor film that will become the semiconductor film 101b and the like When forming an In-Ga-Zn oxide film by MOCVD, the source gas is For example, trimethylindium, trimethylgallium, and dimethylzinc may be used. The combination of source gases is not limited to the above, and may be replaced with trimethylindium. Alternatively, triethylgallium may be used in place of trimethylgallium. Dimethyl zinc may be replaced by diethyl zinc.

[0170] After forming the semiconductor films that will become the semiconductor films 101a and 101b, a heat treatment is performed. The heat treatment is preferably carried out at a temperature of 250°C or higher and 650°C or lower, and more preferably at a temperature of 300°C or higher and 500°C or lower. At temperatures below ℃, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or The heat treatment may be carried out under pressure. In order to compensate for the oxygen released, the reaction may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The heat treatment may be performed immediately after the semiconductor film is formed, or after processing the semiconductor film to form island-shaped semiconductor layers. The heat treatment may be performed after the insulating film 101a, the semiconductor film 101b, and the like are formed. Oxygen is supplied to the semiconductor film from 114, and oxygen vacancies in the semiconductor film can be reduced.

[0171] After that, a resist mask is formed and unnecessary portions are removed by etching. By removing the resist mask, the stack of island-shaped semiconductor films 101a, 101b, etc. A layer structure is formed (Figure 15(C)).

[0172] When the semiconductor film is etched, part of the insulating film 114 is etched, and the semiconductor film The insulating film 114 in the region not covered by the semiconductor film 101a, the semiconductor film 101b, etc. is thinned. Therefore, in order to prevent the insulating film 114 from being lost by the etching, the thickness of the insulating film 114 is set to a predetermined value. It is preferable to form it in a shape similar to that shown in FIG.

[0173] Thereafter, conductive films that will become the conductive films 204a and 204b are formed. Electroplating method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE The resist mask can be formed by a method such as an ALD method or a PLD method. and then removing unnecessary portions of the conductive film that will become the conductive films 204a and 204b by etching. After that, the resist mask is removed, and the conductive film 204a, the conductive film 204b, etc. are formed ( Figure 15(D)).

[0174] Here, when the conductive film is etched, the semiconductor film 101b and the upper part of the insulating film 114 are etched. The portions that do not overlap with the conductive film 204a and the conductive film 204b are etched, and the portions that do not overlap with the conductive film 204a and the conductive film 204b are thinned. Therefore, the thickness of the semiconductor film or the like that will become the semiconductor film 101b is reduced by etching. It is preferable to form the hole thick in advance, taking into consideration the depth to be reached.

[0175] Next, the gate insulating film 202 and the semiconductor film 101c are formed. After the semiconductor film 101c is formed, a resist mask is formed and a gate insulating film is formed by etching. Next, a conductive film to be a gate electrode 203 may be formed by etching the conductive film 202 and the semiconductor film 101c. After that, a resist mask is formed, and the conductive film is processed by etching to form a gate. The resist mask is then removed. At this stage, the transistor T b is formed (Figure 16(A)).

[0176] The semiconductor film that becomes the semiconductor film 101c is formed by sputtering, CVD, MBE or P The film may be formed using the LD method, ALD method, or the like.

[0177] As the semiconductor film that becomes the semiconductor film 101c, an In-Ga-Zn oxide film is grown by MOCV. When forming a film by the D method, trimethylindium and trimethylgallium are used as raw material gases. and dimethyl zinc, etc. may be used. The combination of raw material gases is not limited to the above. In place of trimethylindium, triethylindium or the like may be used. Instead of methylgallium, triethylgallium or the like may be used. Alternatively, diethyl zinc or the like may be used.

[0178] Although not shown in FIGS. 8 to 11, the insulating film 212 and the insulating film 213 are formed on the transistor Tb. An insulating film 213 may be formed (FIG. 16(B)).

[0179] The insulating film 212 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using the MBE method, ALD method, PLD method, etc. After the insulating film 212 is formed, heat treatment is preferably performed. Therefore, oxygen is supplied to the semiconductor film 101b from the insulating film 114 and the like, and the The insulating film 212 may have a stacked structure of two or more layers. In that case, for example, the insulating film 212 may have a two-layer laminate structure, with the lower layer being, for example, silicon oxide. silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxynitride Aluminum, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0180] The insulating film 213 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride The material may be a multilayer or single layer.

[0181] Next, an insulating film 216 is formed on the insulating film 213. The insulating film 216 is made of, for example, silicon oxide. silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxynitride Aluminum, aluminum nitride oxide, aluminum nitride, etc. may be used. The insulating film 216 is formed by a method such as sputtering, CVD (thermal CVD, M OCVD, PECVD, etc.), MBE, ALD, or PLD methods In addition, when an organic insulating material such as an organic resin is used as the insulating film 216, In this case, the insulating film 216 may be formed by a coating method such as spin coating. After the formation, it is preferable to perform a flattening process on the upper surface.

[0182] Next, the insulating film 216, the insulating film 213, the insulating film 212, the gate insulating film 202, and the semiconductor film Openings are provided in the base 101, etc., and plugs 141, 142, and 143 are inserted into the openings. A conductive film such as 143 is formed, and a planarization process is performed so that the surface of the insulating film 216 is exposed. , plugs 141, 142, 143, etc. are formed (FIG. 16(C)).

[0183] Next, a conductive film is formed on the insulating film 216 and the plugs 141, etc., and a mask is formed to perform etching. Then, the conductive films 151, 152, 153, etc. are formed. Then, the insulating film 115 is formed. The insulating film 115 can function as an insulating film for the capacitive element Ca. The materials that can be used for the insulating film 115 are the same as those described for the gate insulating film 102, for example. Please refer to the following.

[0184] Next, a conductive film 155 and the like are formed over the insulating film 115. For the materials and the like that can be used, refer to the description of the conductive film 105. A progeny Ca can be formed (Figure 17(B)).

[0185] Next, the insulating film 156 is formed over the conductive film 155 and the insulating film 115. The upper surface may be flattened. For the insulating film 156, see the description of the insulating film 216. Next, the conductive film 105 and the like are formed on the insulating film 156. Next, the insulating film 114 is formed. Next, openings are formed in the insulating film 156 and the insulating film 114, and a conductive film is formed in the openings to fill them. The surface of the conductive film is flattened so that the insulating film 114 is exposed. Lugs 145 and the like are formed (FIG. 17(C)).

[0186] Next, the transistor Ta and the like are formed (see FIG. 18).

[0187] For the formation of the transistor Ta, please refer to the description of the transistor Tb. As shown in FIG. 18, the transistor Ta of the memory cell MC_1 and the memory cell M The transistor Tb of C_2 can be formed in the same process.

[0188] By repeating the above steps, the memory cell array 300 shown in FIG. 9 can be fabricated. possible.

[0189] As described above, the configuration and method shown in this embodiment can be appropriately combined with the configuration and method shown in other embodiments and used. together.

[0190] (Embodiment 2) Referring to FIGS. 19 to 21, in this embodiment, a configuration example of a circuit that can be used in a circuit system according to an aspect of the present invention will be described in detail. together.

[0191] <CMOS Circuit> The circuit 2011 shown in FIG. 19(A) is a so-called CMOS inverter circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. FIG. 19(B) shows an example of the device structure of the circuit 2011. structure. An example of the structure of the circuit 2011 is shown.

[0192] FIG. 19(B) is a cross-sectional view showing a configuration example of the circuit 2011. The circuit 2011 includes a substrate 22 01, a transistor 2200, a transistor 2100, a wiring line 2202, a plug 2 203, a wiring line 2206, a wiring line 2205, an element isolation layer 2204, an insulating film 2207, and an insulating film 2208. The transistor 2200 includes an impurity region 2001 that functions as a source region or a drain region, a gate electrode 2003, a gate insulating film 2004, and a sidewall insulating layer 2005.

[0193] The circuit 2011 shown in FIG. 19(B) has a transistor 2 using a first semiconductor material at the lower part. 200 and has a transistor 2100 made of a second semiconductor material on top. In FIG. 19(B), the transistor 2100 using the second semiconductor material is the transistor according to Embodiment 1. The OS transistor shown in is used. The transistor on the left side of the dashed line is The right side is the transistor 210. The left side is the transistor 210. The right side is the transistor 2200. 22. As shown in the figure, two types of transistors are shown. By stacking transistors, the area occupied by the circuit is reduced, allowing multiple circuits to be placed at higher density. can be placed.

[0194] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (strained silicon) (including), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum the second semiconductor (e.g., gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.); The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can easily operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0195] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors can be used, and the appropriate transistor should be used depending on the circuit. In the circuit 2011 of (A), the transistor 2200 is a p-channel type.

[0196] As shown in FIG. 19C, an impurity region 2002 is provided in a transistor 2200. The impurity region 2002 may be an LDD (Lightly Doped Drain) The impurity concentration of the impurity region 2001 is The gate electrode 2003 and the sidewall insulating layer 2005 are used as a mask. By using this, the impurity region 2001 and the impurity region 2002 can be formed in a self-aligned manner. In particular, when the transistor 2200 is an n-channel type, there is a risk of deterioration due to hot carriers. In order to suppress the degradation, it is preferable to provide an impurity region 2002 .

[0197] The transistor 2200 may be a transistor having silicide (salicide) or Alternatively, a transistor without the sidewall insulating layer 2005 may be used. ) can further reduce the resistance of the source region and the drain region, In addition, since it can operate at low voltage, it reduces the power consumption of semiconductor devices. It is possible to do this.

[0198] FIG. 19B shows a structure in which a back gate electrode is provided in the transistor 2100. However, a configuration without a back gate electrode may also be used.

[0199] The substrate 2201 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a multi-crystal crystalline semiconductor substrates, compound semiconductor substrates made of silicon germanium, and SOI (Sil A semiconductor substrate can be used. The transistor formed by using this material can easily operate at high speed. When a single crystal silicon substrate is used, an impurity element that gives n-type conductivity is added to a part of the substrate 2201. The n-type well is formed by doping, and a p-type transistor is placed in the n-type well region. Impurity elements that give n-type conductivity include phosphorus (P), arsenic (A), and As an impurity element to give p-type conductivity, boron (B) or the like can be used. You can be there.

[0200] The substrate 2201 may be a conductive substrate or an insulating substrate on which a semiconductor film is provided. The conductive substrate may be a metal substrate, a stainless steel substrate, or a stainless steel foil. tungsten substrate, tungsten foil substrate, etc. Examples of the insulating substrate include a glass substrate, a quartz substrate, a plastic substrate, a flexible substrate, Examples include laminated films, paper containing fibrous materials, and base films. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or silicon dioxide. An example of a flexible substrate is polyethylene terephthalate. (PET), polyethylene naphthalate (PEN), polyethersulfone (PES) Examples include plastics such as acrylic, and flexible synthetic resins. Examples of laminated films include polypropylene, polyester, polyvinyl fluoride, and Examples of the base film include polyester and polyamide. , polyimide, aramid, epoxy, inorganic vapor deposition film, or paper.

[0201] Note that a semiconductor element may be formed using a substrate and then transferred to another substrate. Examples of the substrate onto which the semiconductor element is transferred include the above-mentioned substrates as well as paper substrates, Cellophane substrate, aramid film substrate, polyimide film substrate, stone substrate, wood substrate , Fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) ) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc. ), leather substrate, or rubber substrate. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of durable devices, It is possible to provide thermal resistance, reduce weight, or make the product thinner.

[0202] The transistor 2200 is separated from other elements formed on the substrate 2201 by an element isolation layer 2204. The element isolation layer 2204 is made of aluminum oxide, aluminum oxynitride, and Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide an insulator containing one or more selected from the group consisting of neodymium oxide, hafnium oxide, tantalum oxide, etc. It can be used.

[0203] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulating film provided near the semiconductor film of the transistor 2200 is converted into silicon dummy. This has the effect of terminating green bonds and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, Hydrogen in the insulating film provided near the semiconductor film 100 generates carriers in the oxide semiconductor. This may be one of the factors that cause the transistor 2100 to become less reliable. Therefore, an oxide film is formed on the upper layer of the transistor 2200 using a silicon-based semiconductor material. When the transistor 2100 using a nitride semiconductor is stacked, hydrogen diffusion occurs between the transistors. It is particularly effective to provide an insulating film 2207 that has the function of preventing diffusion. 07, the reliability of the transistor 2200 is improved by confining hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, the reliability of the system can be improved.

[0204] The insulating film 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0205] In addition, a transistor 2100 including an oxide semiconductor film is formed on the transistor 2100 so as to cover the transistor 2100. An insulating film 2208 having a function of preventing hydrogen diffusion can be formed on the resistor 2100. The insulating film 2208 can be made of a material similar to that of the insulating film 2207. In particular, it is preferable to use aluminum oxide. The aluminum oxide film is resistant to hydrogen, moisture, etc. High blocking effect that prevents both impurities and oxygen from passing through the membrane Therefore, an aluminum oxide film is used as the insulating film 2208 covering the transistor 2100. By using the above, oxygen can be prevented from being released from the oxide semiconductor film included in the transistor 2100. At the same time, water and hydrogen can be prevented from entering the oxide semiconductor film.

[0206] The plug 2203 is made of copper (Cu), tungsten (W), molybdenum (Mo), and gold (Au ), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (C o) Low-resistivity materials, or alloys, or compounds containing these as the main components It is preferable to use a single layer or a multilayer of conductive films containing the same. It is preferable to use a high melting point material such as tin or molybdenum. It is preferable to form the wiring using a low-resistance conductive material such as copper. Furthermore, a Cu-Mn alloy is used. When the material is heated, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide suppresses the diffusion of Cu. It is preferable because it has a function of controlling the

[0207] Wiring 2202 and wiring 2205, copper (Cu), tungsten (W), molybdenum (Mo ), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (Co) as a low-resistivity material, or alloy, or a material with these as its main component. It is preferable to use a single layer or a multilayer of a conductive film containing a compound having the above-mentioned properties. It is preferable to use a compatible high melting point material such as tungsten or molybdenum. It is preferable to form the wiring layer from a low-resistance conductive material such as aluminum or copper. When an alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide forms C This is preferable because it has the function of suppressing the diffusion of u.

[0208] The wiring 2206 is made of the same material as the source electrode or drain electrode of the transistor 2100. It can be formed.

[0209] In addition, in Figures 19(B) and (C), symbols and hatching patterns are not given. The dark regions represent regions made up of insulating materials. These regions include aluminum oxide, Aluminum oxide nitride, magnesium oxide, silicon oxide, silicon oxynitride, nitride oxide Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide selected from zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. The insulating material may contain one or more of the following materials: polyimide resin, Polyamide resin, acrylic resin, siloxane resin, epoxy resin, phenolic resin, etc. A synthetic resin can also be used. This is shown in Figs. 20(B), (C) and 21(C) below. The same is true for B).

[0210] By appropriately connecting the electrodes of the transistor 2100 and the transistor 2200, various Other examples are shown in Figures 20 and 21.

[0211] <Analog switch> The circuit 2012 shown in FIG. 20A includes a transistor 2100 and a transistor 2200. The circuit configuration connects the source and drain of each transistor, and functions as a so-called analog switch. FIG. 20B is a cross-sectional view showing an example of a device structure of the circuit 2012. The transistor 2200 shown in FIG. 19(B) is a planar transistor. However, transistor 2200 can be a variety of types of transistors. For example, 3D structures such as FIN type and TRI-GATE type It can be a transistor, etc. An example of such a transistor is shown in Figure 20(B).

[0212] As shown in FIG. 20(B), an insulating film 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a protrusion (also called a fin) with a thin tip. An insulating film may be provided on the semiconductor layer when the protrusions are formed. It acts as a mask to prevent the substrate 2211 from being etched. The protrusion does not have to have a thin tip, and may be, for example, a protrusion having a substantially rectangular parallelepiped shape. The protrusions may have thick tips. 14 is provided on which a gate electrode 2213 is provided. In the semiconductor substrate 1, an impurity region 2215 that functions as a source region or a drain region is formed. As shown in FIG. 20(C), an impurity region 2216 may be provided. 2216 functions as an LDD region and an extension region.

[0213] <Memory circuit> By using a transistor according to one embodiment of the present invention, it is possible to keep the stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written will be described. do.

[0214] The circuit 2013 shown in FIG. 21A includes a transistor 2100 using a second semiconductor material. and a transistor 2200 using a first semiconductor material, and a capacitor 2300. The circuit 2013 has a circuit configuration similar to that of the memory circuit 25 in FIG. Therefore, the description of the memory circuit 25 is used to describe the configuration of the circuit 2013. In the example of 1(A), the transistor 2200 is an n-channel type.

[0215] The transistor 2100 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 2100 has a small off-state current, so that It is possible to retain the stored contents for a longer period of time, i.e., no refresh operation is required. It is possible to provide a semiconductor device that does not require a refresh operation or that requires an extremely low frequency of refresh operations. This allows for a sufficient reduction in power consumption.

[0216] The transistor 2100 may be any of the transistors described in Embodiment 1. This allows for excellent subthreshold characteristics and makes it possible to fabricate miniaturized transistors. Also, the switching speed is fast, allowing for high-speed operation. The transistor is a transistor using single crystal silicon or the like as a semiconductor material other than an oxide semiconductor. This allows for fine transistors and high-speed operation. This makes it possible to realize a semiconductor device that can perform high-speed write and read operations.

[0217] FIG. 21B shows an example of a device structure of the circuit 2013. The transistor 2200 may be either an n-channel or a p-channel type. In the case of a channel type, the impurity region 2002 may or may not be provided. The transistor 2100 may not have a back gate electrode.

[0218] In the examples of FIGS. 19 to 21, the substrate 2201 and the semiconductor substrate 2211 are made of bulk materials. However, one embodiment of the present invention is not limited to this. For example, an SOI substrate can also be used. Cut.

[0219] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0220] (Embodiment 3) In this embodiment, an example of a circuit that can be applied to a circuit system of one embodiment of the present invention will be described. This will be explained using FIG.

[0221] A transistor that uses an oxide semiconductor in the active layer or a transistor that uses silicon in the active layer Examples of circuits using transistors are shown in Figures 22(a) to 22(i). Transistors using oxide semiconductors are called OS transistors, and silicon is used in the active layer. A p-channel Si transistor is called a Si transistor. An n-channel Si transistor is called an n-Si transistor. Note that the conductivity type of the OS transistor is n-channel unless otherwise specified. For convenience, in FIG. 22, p-channel transistors are designated as PMOS, and n-channel transistors are designated as PMOS. It is described as a transistor NMOS.

[0222] The aim is to develop a metal-oxide semiconductor (OS) transistor with a low short-channel effect, which can be easily fabricated and has a high integration density. To utilize the lithography, the channel length of the OS transistor should be between 1 nm and 100 nm. It is preferable that the thickness is 5 nm or more and 60 nm or less. In order to form the OS transistor on the same substrate, a Si transistor is required. The channel length is preferably 1 nm or more and less than 100 nm. , more preferably 5 nm or more and 60 nm or less, or 5 nm or more and 30 nm or less.

[0223] The circuit shown in FIG. 22(a) and FIG. 22(b) includes a transistor 700, and is used as a switch, for example. The transistor 700 functions as a transistor circuit. The illustrated transistor 700 has a first gate (top gate or front gate) and A dual-gate OS transistor having a second gate (back gate) By separately controlling the first gate and the second gate, the on-state characteristics and the off-state characteristics can be improved. Good is possible.

[0224] The circuit shown in FIG. 22(c) includes a transistor 700, a transistor 701, and a node F By holding a potential at the node FN, the same as the memory circuit 25 (FIG. 2A) In the example of FIG. 22(c), the transistor 70 The transistor 700 is an OS transistor. The transistor 701 may be a p-Si transistor. , an n-Si transistor or an OS transistor may be used.

[0225] The circuit shown in FIG. 22(d) includes a transistor 700, a transistor 701, and a capacitor element 22(d) includes the memory circuit 25 (FIG. 2( The circuit configuration is the same as A) and can function as a memory circuit. The transistor 700 is a dual-gate OS transistor. It may be a p-Si transistor, an n-Si transistor, or an OS transistor. If p-Si transistors are used, the data input sequence will be the same as the timing in Figure 5. This differs from the timing chart.

[0226] In the circuits of FIG. 22(c) and FIG. 22(d), the transistors 700 and 701 are OS transistors. In the case of a photoresist, the substrate does not need to be a silicon substrate, and can be a transparent substrate such as glass or quartz glass. It is possible to use a transparent substrate, a metal substrate, or the like.

[0227] In miniaturization, n-channel transistors require LDD and distortion formation, and p-channel transistors require OS transistors require more complex processes than transistors. Therefore, the circuits in Figure 22(c) and Figure 22(d) do not require the complicated process of The transistor 701 is a p-Si transistor, and the transistor 700 is an OS transistor. This makes it possible to simplify the manufacturing process.

[0228] OS transistors do not require high-temperature processes above 900°C, so they are superior to Si transistors. OS transistors are more suitable for integration than other semiconductor elements. By applying OS transistors to circuits, elements can be integrated three-dimensionally. In other words, the OS transistor can provide a semiconductor device with high integration density. Since it can be formed using a lower temperature process than Si transistors, OS By stacking transistors, it is possible to provide a highly reliable and high-performance semiconductor device. It is Noh.

[0229] The circuit of FIG. 22(e) is a modification of the circuit of FIG. 22(d), in which instead of the transistor 701, , includes a transistor 702 and a transistor 703 electrically connected in series. , the first terminal of transistor 702 is connected to a high power supply potential (V DD ) is given to the wiring or electrode The second terminal of the transistor 703 is electrically connected to the The transistor 700 is electrically connected to a wiring or an electrode. transistor, transistor 702 is a p-Si transistor, and transistor 703 is an n-Si transistor. Transistors 702 and 703 are C The transistor 700 is fabricated using a low-temperature process. This allows for high compatibility with the manufacturing process of general Si transistors, making it suitable for It is easy to form transistor 700 on transistor 702 and transistor 703. .

[0230] FIG. 22(f) shows an example of a CMOS inverter circuit. The transistor 700 is an OS transistor. transistor 701 is a p-Si transistor, and transistor 702 is a p-Si transistor. The fabrication of 0 can be performed using a low-temperature process, which is similar to the manufacturing process for general Si transistors. Since the matching is also high, it is easy to form the transistor 700 on the transistor 702. is.

[0231] The circuit shown in FIG. 22(g) includes a transistor 700, a transistor 701, and a transistor The transistor 701 and the transistor 702 are connected to each other. The gate of transistor 701 is electrically connected to transistor 704. The diode 706 is electrically connected to the input terminal of the diode 706 via the resistor 700. an input terminal of a node 706, a gate of a transistor 700, a first terminal of a transistor 701, and the second terminal of the transistor 704 are connected to different wiring or voltage sources, not shown. The transistor 700, the transistor 701, and the transistor The circuit composed of the resistor 704, the diode 706, and the node FN is similar to that shown in FIG. 22(c) etc. The input terminal of the diode 706 and the The data corresponding to the potential between the diode and the output terminal can be held at the node FN. By using a photodiode as 706, it can function as a sensor element. In this case, the circuit shown in FIG. 22(g) can function as an optical sensor circuit. A potential corresponding to the photocurrent flowing through the photodiode (diode 706) is maintained at the node FN. It can be done.

[0232] The sensor element applied to the circuit shown in FIG. 22(g) is not limited to an optical sensor element. For example, the sensor element can measure force, displacement, position, Speed, acceleration, angular velocity, rotation speed, distance, light (e.g., visible light, infrared), electromagnetic waves (e.g., , EEG), magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, Measure or detect flow rate, humidity, gradient, vibration, or odor, and output the results as a voltage signal. An element that can convert a signal into a current signal is used. For example, a photodiode Instead of (706), a temperature sensor element is used, which is a series connection of two resistor elements with different temperature characteristics. A child may be provided.

[0233] In the circuit diagram of FIG. 22(g), the transistor 700 is an OS transistor. The transistor 701 and the transistor 704 may be p-Si transistors or nS The diode 706 may be an i-transistor or an OS transistor. A photodiode using silicon may also be used. When 04 is a Si transistor, the transistor 700 can be manufactured using a low-temperature process. This is highly compatible with the manufacturing process of general Si transistors, making it suitable for transistors 7 It is easy to form transistor 700 on transistor 701 and transistor 704.

[0234] In the circuit of FIG. 22(g), one of the transistors 701 and 704 When a Si transistor is used on one side and an OS transistor on the other side, the Si transistor It is possible to create circuits that combine the high-speed characteristics of the MOSFET with the low leakage characteristics of the OS transistor. is.

[0235] In the circuit of FIG. 22(g), the transistors 701 and 704 are O In the case of an S transistor, the process can be further simplified. As shown in Example 3, if the technology node is finer, the OS transistor It is possible to obtain frequency characteristics equivalent to those of Si transistors, so even with the above configuration, It is possible to form a circuit that combines high speed operation with low leakage characteristics.

[0236] The circuit shown in FIG. 22(h) is a circuit including a transistor 700 and a transistor The transistor 700 has a first gate electrically connected to a first terminal. The first gate is electrically connected to a wiring or electrode (not shown). The first terminal and the second terminal of the transistor 704 may be electrically connected to each other. The Enhanced It can function as an inverter circuit of the ement / depletion type. The transistor 700 is a dual-gate OS transistor. By making it variable, it is possible to control the characteristics of the circuit (inverter circuit) shown in Figure 22(h). The transistor 704 may be an OS transistor or an n-Si transistor. It is possible.

[0237] The circuit shown in FIG. 22(i) is similar to the circuit shown in FIG. 22(h), in that it is electrically connected in series. The circuit shown in FIG. 22(i) includes a transistor 700 and a transistor 704. The gate of the transistor 700 is electrically connected to a wiring or electrode (not shown). However, it is different from the circuit in Fig. 22(h). The circuit shown in Fig. 22(i) is It can function as an / enhancement type inverter. The gate potential of the transistor 700 may be fixed or variable. The transistor 704 is an OS transistor or an n-Si transistor. The resistor may be a resistor.

[0238] In FIG. 22(h) and FIG. 22(i), the transistor 704 is a Si transistor. In this case, a transistor 704 is provided on the transistor 704 in the same manner as in the circuit shown in FIG. 700 can be made.

[0239] Note that the OS transistors used in the circuit diagrams of FIGS. A second gate electrode may or may not be provided as required.

[0240] All of the circuits (semiconductor devices) shown in Figures 22(a) to 22(i) are fabricated on the same substrate. Therefore, it is possible to mount multiple circuits with different functions and performance on the same board. For example, the circuits shown in Figure 22(d) and Figure 22(f) can be fabricated on the same substrate. The semiconductor device fabricated in this manner is shown in FIG. 23(A), and the semiconductor device fabricated in this manner is shown in FIG. 22(d) and FIG. 22(i). FIG. 24A shows a semiconductor device in which a circuit is manufactured over the same substrate.

[0241] FIG. 23(A) is a cross-sectional view showing an example of the configuration of a semiconductor device. The circuit diagram of Figure 23(B) is shown in Figure 22( The circuit diagram in Figure 23(c) corresponds to the circuit diagram in Figure 22(d). In the semiconductor device shown in FIG. 3(A), a transistor 700 is an OS transistor. In this example, the transistor 701 and the transistor 702 are p-Si transistors. FIG. 23A shows the cross-sectional structure of each transistor in the channel length direction.

[0242] The semiconductor device shown in FIG. 23A includes a transistor 700, a transistor 701, and a transistor The transistor 702, the capacitor element 705, the substrate 730, the element isolation layer 731, and the insulating film 7 32, an insulating film 733, a plug 711, a plug 712, a plug 713, and a plug 7 14, wiring 721, wiring 722, wiring 723, wiring 724, and wiring 74 1. In FIG. 23(A), a plurality of plates formed in the same layer Of the plugs, only one plug is marked with a code, and the other plugs are marked with a code to avoid complication. Therefore, the symbols are omitted.

[0243] For details of the substrate 730, refer to the description of the substrate 2201 in FIG. 19(B). For details of the insulating film 732, refer to the element isolation layer 2204 in FIG. 19(B). 19B, the insulating film 733 is similar to the insulating film 2207 in FIG. For details of the plugs 711 to 714, refer to the description of 2208. For details of the wirings 721 to 723, refer to the wiring 220 in FIG. 19B. Please refer to the description in 2.

[0244] The wiring 741 functions as a second gate electrode of the transistor 700. The wiring 41 may be formed using the material that can be used for the wirings 721 to 723. In some cases, the wiring 741 may be omitted. The source electrode and the drain electrode can be made of the same material.

[0245] In FIG. 23(A), the areas without symbols and hatching patterns are insulators. These regions include aluminum oxide, aluminum oxide nitride, and Sodium, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, nitride Silicon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, acid containing one or more selected from the group consisting of lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Insulators such as polyimide resin and polyamide resin can be used in this region. , acrylic resin, siloxane resin, epoxy resin, phenolic resin, or other organic resin is used. It is also possible.

[0246] By configuring the semiconductor device as shown in FIG. 23(A), a memory circuit (transistor and flash memory) The FETs (including the floating node) and their peripheral circuits can be fabricated on the same substrate. Since OS transistors do not require heat treatment at temperatures above 900°C, circuits can be fabricated using lower temperature processes. Furthermore, miniaturized OS transistors can be fabricated using silicon in the active layer. The frequency characteristics are equivalent to those of n-channel transistors using silicon dioxide. CMOS circuits that combine p-Si transistors are capable of high-speed operation.

[0247] FIG. 24(A) is a cross-sectional view showing an example of the configuration of a semiconductor device, and the circuit shown in FIG. 24(B) is shown on the left side. The circuit diagram of Figure 24(B) is shown in Figure 22(i), and the circuit diagram of Figure 24(C) is shown on the right. The circuit diagram in FIG. 24(C) corresponds to the circuit diagram in FIG. 22(d). The semiconductor device shown in A) includes a transistor 700, a transistor 701, and a transistor 7 24(A) shows an example in which an OS transistor is used. FIG. 1 is a cross-sectional view in the channel length direction.

[0248] The semiconductor device shown in FIG. 24A includes a transistor 700, a transistor 701, and a transistor A transistor 704, a capacitor element 705, a substrate 735, an insulating film 732, and an insulating film 733 , a plug 711, a plug 712, a plug 713, a plug 714, and a wiring 721. , wiring 722, wiring 723, wiring 724, wiring 741, wiring 742, and 24A, multiple wirings formed in the same layer are included. Of the many plugs, only one plug is given a code, and the other plugs are left uncoded to avoid complication. To avoid this, the signs are omitted.

[0249] For details of the substrate 735, refer to the description of the substrate 2201 in FIG. Other devices may be formed in the substrate 735. In that case, the surface of the substrate 735 may be flat. It is preferable to perform a planarization process by CMP or the like so that the surface becomes smooth.

[0250] For details of the insulating film 732, see the description of the insulating film 2207 in FIG. 19B. For details, see the description of the insulating film 2208 in FIG. 19B. For details of 4, refer to the description of the plug 2203 in FIG. 19(B), and for details of the wirings 721 to 723, refer to For details, refer to the description of the wiring 2202 in FIG.

[0251] The wiring 741 functions as a second gate electrode of the transistor 700, and the wiring 742 The wiring 743 serves as a second gate electrode of the transistor 701. The wirings 741 to 743 function as second gate electrodes of the gate electrodes 704. The wirings 721 to 723 can be formed using the same material. In some cases, the wirings 741 to 743 may be omitted.

[0252] The wiring 724 is connected to the source or drain electrodes of the transistor 700 and the transistor 704. The electrode can be made of the same material as the electrode.

[0253] In FIG. 24(A), the areas without symbols and hatching patterns are These regions are made of insulating materials, such as aluminum oxide and nitride oxide. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide , silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide One selected from the group consisting of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Insulators containing the above can be used. Organic resins such as acrylic resin, siloxane resin, epoxy resin, and phenolic resin are used. It can also be used.

[0254] By configuring the semiconductor device as shown in FIG. 24(A), a memory circuit (transistor and flash memory) The FETs (including the floating node) and their peripheral circuits can be fabricated on the same substrate. Since OS transistors do not require heat treatment at temperatures above 900°C, they can be fabricated using lower temperature processes. In addition, OS transistors can be stacked with other semiconductor elements. It is possible to arrange elements three-dimensionally, and to create highly integrated semiconductor devices. Furthermore, miniaturized OS transistors can be fabricated using silicon in the active layer. The frequency characteristics are equivalent to those of the n-channel transistors used in the previous study. The circuit is capable of high-speed operation.

[0255] The channel length dependence of electron mobility in OS transistors is also comparable to that of Si transistors. The effect is not as great as the channel length dependence of electron mobility in OS transistors. Even if the channel length is reduced from 10 μm to 100 nm, there is no clear decrease in the field-effect mobility. I can't see the bottom.

[0256] Therefore, when using OS transistors with a channel length of 10 μm or less, The difference in field-effect mobility between Si transistors and silicon transistors is 10 μm or more when the channel length of the transistor is The OS transistor is a transistor with a channel length of 100 nm or less. When used for a transistor, the thickness is about 1 / 30 of that of a Si transistor, preferably about 1 / 10. More preferably, it is possible to reduce the difference to about one-third of the field-effect mobility.

[0257] In addition, when an OS transistor is used in a transistor with a channel length of approximately 100 nm, S It is believed that it is possible to achieve a field effect mobility comparable to that of an i-transistor. Therefore, microfabricated OS transistors can achieve switching speeds comparable to those of Si transistors. , it is possible to realize frequency characteristics.

[0258] In addition, the OS transistor has a low off-state current. In circuits, a low off-state current reduces the capacitance required to hold charge. Cut.

[0259] The configuration of this embodiment mode can be combined with other embodiments and examples as appropriate. .

[0260] (Fourth embodiment) In this embodiment, a memory device such as the memory cell array 300 exemplified in the above embodiment is Here, the memory device is a row selector connected to a memory cell array. The pixel circuit may include a select driver, a column select driver, an A / D converter, and the like.

[0261] The RF device in this embodiment has a memory circuit therein, and stores necessary information in the memory circuit. The information is stored in the memory and transmitted to and from the outside using a non-contact means, for example, wireless communication. Due to these characteristics, RF devices can identify items by reading their individual information. It can be used for individual authentication systems that distinguish between people. To achieve this, extremely high reliability is required.

[0262] 25 is a block diagram showing an example of the configuration of an RF device. 800 includes an antenna 804, a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation It includes a circuit 808 , a logic circuit 809 , a memory circuit 810 , and a ROM 811 .

[0263] The reverse current of the transistor exhibiting the rectifying action included in the demodulation circuit 807 is sufficiently suppressed. A material that can achieve this, for example, an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged opposite each other and communication is carried out by mutual induction. Electromagnetic coupling method, electromagnetic induction method that communicates using an induced electromagnetic field, radio wave method that communicates using radio waves The RF device 800 shown in this embodiment is compatible with any of these methods. It can also be used for

[0264] Next, the configuration of each circuit will be described. The antenna 804 is connected to the communication device 801 (interrogator, reader). 803 is transmitted and received between the antenna 802 connected to the The rectifier circuit 805 receives a radio signal through the antenna 804. The input AC signal generated by the capacitor is rectified, for example, by half-wave double voltage rectification. This is a circuit that generates an input potential by smoothing the rectified signal using a quantum element. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A rectifier circuit is a circuit that generates a large amount of power when the amplitude of the input AC signal is large and the internally generated voltage is large. This is a circuit that controls the upper power so that it does not enter the subsequent circuit.

[0265] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0266] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0267] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for doing this.

[0268] The above-mentioned circuits can be selected or removed as needed.

[0269] Here, the memory circuit described in the above embodiment can be applied to the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Therefore, the memory circuit of one embodiment of the present invention can be suitably used in an RF device. The power (voltage) required to write data is significantly lower than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance between when reading and writing data. Furthermore, it prevents malfunctions or erroneous writing caused by insufficient power when writing data. It is possible.

[0270] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF device produced, This means that unique numbers can only be assigned to products that have been shipped, and the unique numbers of the products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0271] Next, an example of how to use the RF device will be described with reference to Fig. 26. The applications are wide-ranging, but for example, banknotes, coins, securities, bearer bonds, certificates (driving licenses, etc.) Licenses and resident registration cards, etc., Figure 26(A)), packaging containers (wrapping paper, bottles, etc., Figure 26(C)), Recording media (DVDs, videotapes, etc., Figure 26(B)), vehicles (bicycles, etc., Figure 26(D) )), personal belongings (bags, glasses, etc.), food, plants, animals, the human body, clothing, daily necessities, Medical products including medicines and drugs, or electronic devices (liquid crystal display devices, EL display devices, televisions) equipment, or mobile phones) or tags attached to each item (Figure 26(E), Figure 26(F)) and can be used.

[0272] The RF device 4000 according to one embodiment of the present invention can be attached to a surface or embedded in a device. For example, in the case of a book, the sensor is embedded in the paper and then fixed to the object in a package made of organic resin. If so, it is embedded in the organic resin and fixed to each article. The F Device 4000 is small, thin, and lightweight, so even after being fixed to an item, it remains attached to the item. It does not impair the design of the product itself. It is also suitable for banknotes, coins, securities, bearer bonds, Alternatively, by providing an RF device 4000 according to one aspect of the present invention on a document or the like, authentication can be performed. By utilizing this authentication function, it is possible to prevent counterfeiting. Also, packaging containers, recording media, personal belongings, food, clothing, household goods, or electronic devices By attaching an RF device according to one aspect of the present invention to a system such as an inspection system, In addition, even in the case of vehicles, the R according to one aspect of the present invention can be used. By installing an F device, you can increase security against theft. Cut.

[0273] As described above, the RF device according to one aspect of the present invention can be used for each of the applications listed in this embodiment. This reduces the operating power consumption, including the writing and reading of information, thereby extending the maximum communication distance. It is also possible to transmit information for an extremely long time even when the power is cut off. Since it can be retained for a long period of time, it can be used in applications where writing and reading are not performed frequently. can be done.

[0274] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0275] (Embodiment 5) In this embodiment, at least the memory cell array 300 etc. described in the embodiment are included. A CPU including a memory device will be explained. Here, the memory device is connected to a memory cell array. It may include a row selection driver, a column selection driver, an A / D converter, and the like.

[0276] FIG. 27 shows a configuration of at least one of the memory devices described in the previous embodiments and other semiconductor devices. FIG. 10 is a block diagram showing the configuration of an example of a CPU used in the unit.

[0277] The CPU shown in FIG. 27 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 27 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their use. For example, the CPU or the configuration including the arithmetic circuit shown in FIG. 27 is regarded as one core, and the core is divided into multiple It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a calculation circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0278] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0279] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0280] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generator generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0281] In the CPU shown in FIG. 27, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0282] In the CPU shown in FIG. 27, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0283] FIG. 28 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory circuit 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory circuit 1200 may include a diode, a resistor, an inductor, etc., as needed. The transistor 1209 is an oxide semiconductor. Preferably, the transistor has a channel formed in the semiconductor layer.

[0284] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory circuit 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0285] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first terminal of the switch 1203 is The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 The control signal RD input to the gate of the transistor 1213 controls the first and second terminals. The conduction or non-conduction between the two (i.e., the on-state or off-state of the transistor 1213) is selected. The first terminal of the switch 1204 is connected to one of the source and drain terminals of the transistor 1214. The second terminal of the switch 1204 is connected to the source and drain of the transistor 1214. On the other hand, the switch 1204 receives a control signal input to the gate of the transistor 1214. RD controls whether the first terminal and the second terminal are conductive or non-conductive (i.e., transistor 12 14 on or off state) is selected.

[0286] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The gate of the transistor 1210 is electrically connected to one of the gates of the transistor 1210. The part is designated as node M2. One of the source and drain of the transistor 1210 is connected to the low power supply voltage. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage. The first terminal of the transistor 1203 (either the source or drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) The first terminal of the switch 1204 (either the source or drain of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the drains is electrically connected to a wiring that can supply a power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) a first terminal of the transistor 1204 (either the source or drain of the transistor 1214) and a second terminal of the logic The input terminal of the element 1206 and one of the pair of electrodes of the capacitor element 1207 are electrically connected to each other. Here, the connection point is referred to as node M1. The other of these may be configured to receive a constant potential. A capacitor element may be configured to receive a voltage such as ND or a high power supply voltage such as VDD. The other of the pair of electrodes 1207 is connected to a wiring (e.g. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a fixed For example, a low power supply potential (GND, etc.) or a high A power supply potential (such as VDD) can be input. The other electrode is electrically connected to a wiring (for example, a GND line) that can supply a low power supply potential. are connected to the network.

[0287] The capacitors 1207 and 1208 are formed by using parasitic capacitances of transistors and wirings. It is also possible to omit this by actively using

[0288] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive or non-conductive state between the first and second terminals, and one of the switches When the first and second terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a conductive state. The gap is in a non-conductive state.

[0289] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 28, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0290] In FIG. 28, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the input If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, , from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) The signal to be output can be input to the node.

[0291] In addition, in FIG. 28, among the transistors used in the memory circuit 1200, The transistors other than the transistor 1209 are formed on a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The transistor may be a Si transistor in which a channel is formed in a silicon substrate. All the transistors used in the memory circuit 1200 have channels formed in an oxide semiconductor layer. Alternatively, the memory circuit 1200 may include an OS transistor. In addition to 209, an OS transistor may be included, and the remaining transistors may be oxide semiconductor. A transistor in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than a conductor. It is also possible to do so.

[0292] The circuit 1201 in FIG. 28 can be, for example, a flip-flop circuit. The logic element 1206 may be an inverter or a clocked inverter. can.

[0293] In the semiconductor device of one embodiment of the present invention, while power supply voltage is not supplied to the memory circuit 1200, The data stored in the circuit 1201 is transferred to a capacitor 1208 provided in the circuit 1202. Therefore, it can be retained.

[0294] In addition, the off-state current of an OS transistor is extremely small. The current is higher than the off-state current of a transistor whose channel is formed in crystalline silicon. Therefore, by using an OS transistor as the transistor 1209, Even while the power supply voltage is not supplied to the memory circuit 1200, the signal held in the capacitor 1208 In this way, the memory circuit 1200 can maintain its data even when the supply of power supply voltage is stopped. It is possible to retain memory contents (data).

[0295] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the operation, after the power supply voltage is supplied again, the circuit 1201 This can shorten the time it takes to restore the original data.

[0296] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory circuit 1200 is restarted. After the capacitor 1208 is opened, the signal held by the capacitor 1208 is transferred to the transistor 1210 (ON state or OFF state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0297] Such a memory circuit 1200 may be used as a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0298] In this embodiment, the memory circuit 1200 is used in a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSIs such as LSIs and PLDs (Programmable Logic Devices), It can also be applied to RF devices (Radio Frequency Devices).

[0299] For example, in this specification and the like, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, metal substrates, stainless steel substrates, stainless steel foils Substrate with tungsten foil, tungsten substrate, substrate with tungsten foil, flexible substrate, adhesive Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples include polyethylene terephthalate (PET), polyethylene terephthalate (PE ... Plastics such as polyethylene naphthalate (PEN) and polyethersulfone (PES) For example, synthetic resin such as acrylic resin is used. Examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy, and inorganic vapor deposition. Films or papers, etc. In particular, semiconductor substrates, single crystal substrates, or SOI substrates, etc. By manufacturing transistors using this method, variations in characteristics, size, shape, etc. can be reduced. This allows the manufacture of transistors with low resistance, high current capability, and small size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated. This can be achieved.

[0300] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0301] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0302] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0303] (Embodiment 6) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) navigation systems, audio playback devices (car audio, digital audio players) Layers, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 29. .

[0304] The portable game machine shown in FIG. 29A includes a housing 901, a housing 902, a display portion 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 29(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0305] The portable data terminal shown in FIG. 29(B) comprises a first housing 911, a second housing 912, a first display unit The first display unit 91 has a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 913 and the second display unit 912. and a display having a function as a position input device added to at least one of the first display unit 914 and the second display unit 915. The function as a position input device can be achieved by touching the display device. Alternatively, the function as a position input device can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0306] The notebook personal computer shown in FIG. 29C includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0307] The electric refrigerator-freezer shown in FIG. 29(D) includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a He has 33 etc.

[0308] The video camera shown in FIG. 29(E) comprises a first housing 941, a second housing 942, a display unit 943, and a , operation keys 944, a lens 945, a connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0309] The standard car shown in FIG. 29(F) includes a body 951, wheels 952, a dashboard 953, It has Light 954 etc.

[0310] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0311] (Embodiment 7) In this embodiment, an oxide semiconductor film included in a semiconductor device will be described in detail.

[0312] The oxide semiconductor film is an oxide semiconductor containing indium. When indium is contained, the carrier mobility (electron mobility) increases. The circuit system of the embodiment includes oxygen, In, Zn, and M (wherein M is Ti, Ga, Y, Zr, It is preferable to use an oxide semiconductor film containing La, Ce, Nd, or Hf. M is, for example, an element having a high bond energy with oxygen. Alternatively, the element M may be, for example, an element having an energy higher than that of indium. The semiconductor film contains zinc. When an oxide semiconductor contains zinc, it may be easily crystallized.

[0313] In addition, it is preferable to use an oxide having a wide energy gap for the oxide semiconductor film. The energy gap of the oxide semiconductor film is, for example, 2.5 eV to 4.2 eV. , preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. Below.

[0314] In addition, when the oxide semiconductor film has a stacked structure, for example, as shown in FIG. Alternatively, the semiconductor film 44a, the semiconductor film 44b, and the semiconductor film 44c may be stacked.

[0315] The semiconductor films 44a and 44c contain oxygen other than the oxygen constituting the semiconductor film 44b. The semiconductor film 44b is an oxide semiconductor composed of one or more elements. The semiconductor film 44a and the semiconductor film 44b are made of one or more elements other than oxygen. c is formed, the interface between the semiconductor film 44a and the semiconductor film 44b, and the semiconductor film 44b An interface state is unlikely to be formed at the interface between the semiconductor film 44c and the silicon dioxide film 44b.

[0316] The semiconductor film 44a, the semiconductor film 44b, and the semiconductor film 44c are made of at least indium. When the semiconductor film 44a is an In-M-Zn oxide, In and When the sum of M is 100 atomic %, In is preferably less than 50 atomic %. M is higher than 50 atomic %, and more preferably In is less than 25 atomic %; The content of the semiconductor film 44b is set to be higher than 75 atomic %. When the sum of In and M is 100 atomic %, it is preferable that In is 25 atomic %. mic%, M is less than 75 atomic %, and more preferably In is 34 atomic % % or more and M is less than 66 atomic %. In the case of Zn oxide, when the sum of In and M is 100 atomic %, preferably In is less than 50 atomic %, M is higher than 50 atomic %, and more preferably I n is set to be less than 25 atomic % and M is set to be higher than 75 atomic %. The film 4c may be made of the same oxide as the semiconductor film 44a.

[0317] The semiconductor film 44b has an acid having a larger electron affinity than the semiconductor films 44a and 44c. For example, the semiconductor film 44b is made of a material selected from the group consisting of the semiconductor films 44a and 44c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. 5 or less, more preferably, an oxide having a larger energy level than the above by 0.15 eV or more and 0.4 eV or less. , electron affinity is the difference in energy between the vacuum level and the bottom of the conduction band.

[0318] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor film 44c contains indium gallium oxide. The atomic ratio [In / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and More preferably, it is 90% or more.

[0319] Furthermore, the semiconductor film 44c more preferably contains gallium oxide. The semiconductor film 44c can function as a blocking film to prevent indium diffusion. By forming the gallium oxide film on the lower semiconductor film 44b, the insulating film from the semiconductor film 44a can be easily formed. This can eliminate or suppress the diffusion of zinc.

[0320] When an electric field is applied to the gate electrode of the transistor, the semiconductor film 44a, the semiconductor film 44b, and the semiconductor A channel is formed in the semiconductor film 44b of the conductive film 44c, which has a large electron affinity.

[0321] Here, the band structure of the stacked structure of the insulating film and the oxide semiconductor film is shown in FIG. FIG. 30 shows the vacuum level (denoted as vacuum level), the thickness of each film (insulating film 43 , the semiconductor film 44a, the semiconductor film 44b, the semiconductor film 44c, and the insulating film 47) The energy (denoted as Ec) and the energy at the top of the valence band (denoted as Ev) are shown.

[0322] Between the semiconductor film 44a and the semiconductor film 44b, In addition, between the semiconductor film 44b and the semiconductor film 44c, The semiconductor film 44b may have a mixed region of the semiconductor film 44c. Therefore, the level density of the semiconductor film 44a, the semiconductor film 44b, and the semiconductor film 44c is reduced. In this laminate, the energy changes continuously near each interface (continuous junction). (also called a band structure).

[0323] In FIG. 30, the semiconductor film 44a and the semiconductor film 44c have the same Ec. However, they may be different. For example, the semiconductor film 44 is thicker than the semiconductor film 44a. The Ec of c may have high energy.

[0324] At this time, the electrons are not in the semiconductor film 44a and the semiconductor film 44c, but in the semiconductor film 44 bMoves mainly inside.

[0325] As described above, the interface state density at the interface between the semiconductor film 44a and the semiconductor film 44b, By lowering the interface state density at the interface between the semiconductor film 44b and the semiconductor film 44c, Therefore, the movement of electrons in the semiconductor film 44b is not hindered, and the on-current of the transistor is reduced. It can be made higher.

[0326] When the transistor has the s-channel structure described above, the semiconductor film 44b Therefore, the thicker the semiconductor film 44b, the larger the channel region. That is, the thicker the semiconductor film 44b, the higher the on-current of the transistor. For example, it is possible to obtain a thickness of 20 nm or more, preferably 40 nm or more, and more preferably 60 nm or more. More preferably, the semiconductor film 44b may have a region with a thickness of 100 nm or more. However, since the productivity of semiconductor devices may decrease, for example, 300 nm or less, A semiconductor having a region with a thickness of preferably 200 nm or less, more preferably 150 nm or less This may be called film 44b.

[0327] In order to increase the on-state current of the transistor, the thickness of the semiconductor film 44c is as small as possible. For example, it is preferably less than 10 nm, more preferably 5 nm or less, and even more preferably 3 nm or less. On the other hand, the semiconductor film 44c has a channel shape. The semiconductor film 44b is formed by adding elements other than oxygen (hydrogen, silicon) that make up the adjacent insulator. Therefore, the semiconductor film 44c has a function of blocking the intrusion of For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the semiconductor film 44c has a region with a thickness of 2 nm or more. The semiconductor film 44c is formed by: It is preferable that the material has oxygen blocking properties.

[0328] In order to increase reliability, the semiconductor film 44a is thick and the semiconductor film 44c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor film 44a may have a region with a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor film 44a, the interface between the adjacent insulating film and the semiconductor film 44a The distance from the semiconductor film 44b where the channel is formed can be increased. Therefore, for example, the thickness is set to 200 nm or less, preferably 120 If the semiconductor film 44a has a region with a thickness of 80 nm or less, more preferably 80 nm or less, good.

[0329] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors, generating electrons as carriers. Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove impurities to achieve high purity so that the impurities are not included as much as possible.

[0330] Note that the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film reduces the amount of oxygen in the oxide semiconductor film. Therefore, dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film may increase the number of electron vacancies. a process of adding oxygen to the oxide semiconductor film to compensate for oxygen vacancies increased by the In this specification and the like, the treatment of adding oxygen to an oxide semiconductor film is referred to as oxygen-adding treatment. Alternatively, the amount of oxygen contained in the oxide semiconductor film may be higher than the stoichiometric composition. This treatment is sometimes referred to as peroxygen treatment.

[0331] In this way, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies through oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is very close to i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that there are very few carriers derived from donors in the oxide semiconductor film. (close to zero), and the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 This means that the above is the case.

[0332] Furthermore, a transistor including an i-type or substantially i-type oxide semiconductor film is extremely advantageous. For example, when a transistor using an oxide semiconductor film is The drain current in the MOSFET state is 1×10 at room temperature (approximately 25°C). -18 A or less, preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1x at 85°C 10 -15 A or less, preferably 1×10 -18 A or less, more preferably 1×10 -21 A or less. Note that the transistor being in the off state means that the transistor is an n-channel transistor. In the case of a transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. If the gate voltage is more than 1V, 2V, or 3V less than the threshold voltage, the transistor The starter is turned off.

[0333] Next, the structure of the oxide semiconductor will be described.

[0334] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0335] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0336] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. This can also be described as a structure that has a high degree of order but no long-range order.

[0337] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor (isotropic amorphous). The oxide semiconductor is then oxidized to form a completely amorphous structure. However, a-like OS is a semiconductor that can be used in a microscopic area. Although it has a periodic structure, it has voids and is an unstable structure. It can be said that the physical properties are similar to those of an amorphous oxide semiconductor.

[0338] <caac-os> First, let me explain about CAAC-OS.

[0339] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0340] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries. Therefore, the CAAC-OS is not clearly characterized by the grain boundaries. It can be said that the resulting decrease in electron mobility is unlikely to occur.

[0341] Below, we will explain the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration correction function was used to obtain high-resolution TEM images. , specifically referred to as a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images can be obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0342] An enlarged Cs-corrected high-resolution TEM image of area (1) in Figure 43(A) is shown in Figure 43(B). From Figure 43(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0343] As shown in Figure 43(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The pellets can also be called nanocrystals (nc). AAC-OS, CANC(C-Axis Aligned nanocrystals) ) can also be referred to as an oxide semiconductor.

[0344] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See Figure 43(D)). The tilt between the pellets observed in Figure 43(C) The location where the crack occurs corresponds to the area 5161 shown in FIG.

[0345] FIG. 44(A) shows the C of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. The s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 44(A). ) are enlarged Cs-corrected high-resolution TEM images shown in Figure 44(B), Figure 44(C), and Figure 44(D), respectively. As shown in Figure 44(D), Figure 44(B), Figure 44(C) and Figure 44(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0346] Next, C analyzed by X-ray diffraction (XRD) For example, CAAC-O with InGaZnO4 crystals When S is subjected to structural analysis using the out-of-plane method, the result is as shown in Figure 45(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal is c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0347] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31 In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is a structure produced by the out-of-plane method. The analysis shows a peak at 2θ around 31°, but no peak at 2θ around 36°.

[0348] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction almost perpendicular to the c-axis. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 5 The sample is fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a (φ scan) is performed, no clear peak appears as shown in Figure 45(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane as shown in Figure 45(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0349] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the probe diameter is 300 nm parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in Figure 46(A) is generated. This diffraction pattern may appear due to the presence of InGaZnO4 This includes spots due to the (009) plane of the crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied to the same sample perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 46(B). 6(B), a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 46(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface.

[0350] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the incorporation of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0351] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0352] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0353] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 Such an oxide semiconductor can be a highly pure intrinsic or substantially highly pure oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect states. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0354] <nc-os> Next, we will explain nc-OS.

[0355] In the high-resolution TEM image, nc-OS has two distinct regions: one where crystals can be confirmed and the other where clear crystals can be confirmed. The crystalline part contained in nc-OS is The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0356] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, in contrast to nc-OS, there are cases where it is difficult to distinguish the particles from the pellets. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction is performed on nc-OS, high brightness regions are observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. This may be the case.

[0357] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) The semiconductor may also be referred to as an oxide semiconductor having a structure (s).

[0358] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0359] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0360] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystalline parts can be clearly seen, and areas where crystalline parts can be seen. and areas where it is not possible to

[0361] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0362] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as Sample B) and CAAC-OS (hereinafter referred to as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0363] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0364] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are considered to be InGaZnO4 crystal parts. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0365] Figure 47 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of ke OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown in Figure 47 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystal part within the range of As shown in (2) and (3) in Figure 47, regardless of the cumulative electron dose, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that...

[0366] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC- It is clear that it has an unstable structure compared to the OS.

[0367] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0368] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of a single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 becomes. Thus in, for example, an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 becomes. Also in, for example, an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 becomes.

[0369] Note that there may be cases where single crystals of the same composition do not exist. In that case, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures and each has various characteristics. Note that the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS,

[0370] CAAC-OS. Note that the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS.

[0371] <Film Formation Methods for CAAC-OS and nc-OS> Next, an example of a film formation method for CAAC-OS will be described.

[0372] FIG. 48(A) is a schematic diagram of the film formation chamber. CAAC-OS can be formed by a sputtering method. ​

[0373] As shown in FIG. 48(A), the substrate 5220 and the target 5230 are arranged facing each other. Between the substrate 5220 and the target 5230 there is a plasma 5240. A heating mechanism 5260 is provided below the substrate 5220. The get 5230 is glued to the backing plate. A plurality of magnets are arranged in positions facing the target 5230. The sputtering method that uses a magnetic field to increase the film deposition rate is called magnetron sputtering. It is called.

[0374] The distance d between the substrate 5220 and the target 5230 (target-substrate distance (TS distance) The distance is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or oxygen in a volume of 5). % or more), and the pressure is 0.01 Pa or more and 100 Pa or less, preferably is controlled to be 0.1 Pa or more and 10 Pa or less. By applying a voltage, a discharge starts and plasma 5240 is observed. A high density plasma region is formed near the nozzle 5230 by the magnetic field. In the region, the deposition gas is ionized to generate ions 5201. , for example, oxygen cations (O + ) and argon cations (Ar + ) etc.

[0375] The target 5230 has a polycrystalline structure having a plurality of crystal grains, and As an example, in FIG. 49, the InMZn The crystal structure of O4 (element M is, for example, Ga or Sn) is shown in FIG. 49. This is the crystal structure of InMZnO4 when observed from the vertical direction. The negative charge of the oxygen atoms creates a repulsive force between two adjacent M-Zn-O layers. Therefore, the InMZnO4 crystals are formed between two adjacent M-Zn-O layers. It has a cleavage plane at

[0376] Ions 5201 generated in the high-density plasma region are attracted to the target 5230 by the electric field. The particles are accelerated and eventually collide with the target 5230. At this time, flat or planar particles are formed from the cleavage plane. Pellets 5200, which are pellet-shaped sputtered particles, are peeled off (see FIG. 48(A)).

[0377] The pellet 5200 is the part sandwiched between the two cleavage planes shown in FIG. When only the mat 5200 is extracted, its cross section is as shown in Figure 48(B), and the top surface is as shown in Figure 48(C). ) It can be seen that the pellet 5200 is formed by the impact of the collision of the ion 5201. This may cause distortion in the structure. Particle 5203 is also ejected from get 5230. Particle 5203 can be one atom or Therefore, the particle 5203 is an atomic particle. It can also be called icles.

[0378] The pellet 5200 is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. Alternatively, the pellet 5200 may have a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of plates or pellets. However, the shape of the pellets 5200 is not limited to triangles or hexagons, for example, when it is a shape made up of multiple triangles For example, a quadrilateral (e.g., a rhombus) is formed by joining two triangles (e.g., an equilateral triangle). ) may also be used.

[0379] The thickness of the pellet 5200 is determined depending on the type of deposition gas. 5200 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5200 has a width of 1 nm or more and 3 nm or less, preferably The thickness is 1.2 nm to 2.5 nm. For example, a target having an In-M-Zn oxide Ions 5201 are bombarded onto the substrate 5230. As a result, the M-Zn-O layer, the In-O layer, and The pellet 5200 having three layers, the M-Zn-O layer and the M-Zn-O layer, is peeled off. As the target 5230 peels off, the particle 5203 is also ejected from the target 5230.

[0380] As the pellet 5200 passes through the plasma 5240, its surface becomes negatively or positively charged. For example, when the pellet 5200 is in the plasma 5240, 2- negative charge from As a result, the oxygen atoms on the surface of the pellet 5200 may become negatively charged. In addition, when the pellet 5200 passes through the plasma 5240, It may grow by combining with indium, element M, zinc, or oxygen in 40. .

[0381] The pellets 5200 and particles 5203 that have passed through the plasma 5240 are Some of the particles 5203 are small in mass and can be removed by a vacuum pump or other device. It may be discharged to the outside.

[0382] Next, the deposition of pellets 5200 and particles 5203 on the surface of the substrate 5220 is described. This will be explained using FIG.

[0383] First, the first pellet 5200 is deposited on the substrate 5220. The pellet 5200 is a flat plate. Since the film has a shape like a film, it is deposited with the flat side facing the surface of the substrate 5220 (see FIG. 50(A)). At this time, the charge on the surface of the pellet 5200 facing the substrate 5220 is released through the substrate 5220. do.

[0384] Next, the second pellet 5200 reaches the substrate 5220. The surface of the first pellet 5200 and the surface of the second pellet 5200 are electrically charged. A repulsive force is generated (see Figure 50(B)).

[0385] As a result, the second pellet 5200 avoids the first pellet 5200 and falls on the substrate 5 The particles are deposited at a location slightly away from the surface of 220 (see Figure 50(C)). By repeating this process, Countless pellets 5200 are deposited on the surface of the substrate 5220 to a thickness equivalent to one layer. Between the pellets 5200, there is a pile of pellets 5200. There will be areas where there is no

[0386] Next, the particle 5203 reaches the surface of the substrate 5220 (see FIG. 50(D)).

[0387] The particles 5203 cannot accumulate in active areas such as the surface of the pellet 5200. Therefore, the pellets 5200 are deposited so as to fill in the areas where the pellets 5200 are not deposited. The particles 5203 grow laterally between the pellets 5200 (also called lateral growth). In this way, the pellets 5200 are connected to each other. Particles 5203 are deposited until they fill the gap. This mechanism is the same as the deposition mechanism in the ALD method. Similar to a rhythm.

[0388] There are several possible mechanisms for the lateral growth of particles 5203 between pellets 5200. For example, as shown in FIG. 50(E), the first M-Zn-O layer is connected to the side surface. In this case, after the first M-Zn-O layer is formed, the In-O The first M-Zn-O layer is then joined to the second M-Zn-O layer (first mechanism).

[0389] Alternatively, for example, as shown in FIG. 51(A), first, a layer of M-Zn-O is formed on one side of the first layer. Next, as shown in FIG. 51(B), one of the In-O layer is bonded to the other side of the In-O layer. One particle 5203 is bonded to each surface. Next, as shown in Figure 51(C), the second layer M- In some cases, one particle 5203 is bonded to one side of the Zn-O layer to form a connection (see the 2 mechanism).

[0390] In addition, Figure 51(A), Figure 51(B) and Figure 51(C) occur simultaneously and are connected. In some cases (third mechanism).

[0391] As described above, the mechanism of lateral growth of the particles 5203 between the pellets 5200 However, there are other mechanisms that may cause Pellet There is also a possibility that particles 5203 may grow laterally between the particles 5200.

[0392] Therefore, even if multiple pellets 5200 are facing in different directions, multiple The particles 5203 grow laterally and fill the gaps between the pellets 5200, forming a crystal. The formation of grain boundaries is suppressed. In addition, the particles 5203 smoothly connect the pellets 5200. In other words, the microstructure is different from that of single crystals and polycrystals. A crystalline structure with distortion between small crystalline regions (pellets 5200) is formed. The regions filling the gaps between the crystalline regions are distorted crystalline regions, and therefore these regions are referred to as amorphous structures. It doesn't seem appropriate to call it that.

[0393] When the particles 5203 have filled the gaps between the pellets 5200, the gap becomes as thick as the pellets 5200. A first layer having a thickness of 5200 is formed. A new first pellet 5200 is placed on the first layer. Then, a second layer is formed. This process is repeated to form a stack. A thin film structure having the following structure is formed (see FIG. 48(D)).

[0394] The deposition pattern of the pellets 5200 also changes depending on the surface temperature of the substrate 5220. For example, if the surface temperature of the substrate 5220 is high, the pellet 5200 may be heated to the surface of the substrate 5220. As a result, pellet 5200 and another pellet 5200 However, the proportion of connections not via particle 5203 increases, resulting in highly oriented CAAC-OS. The surface temperature of the substrate 5220 during the CAAC-OS film formation is 100° C. or higher and 500° C. or lower. ° C. or less, preferably 140° C. or more and less than 450° C., and more preferably 170° C. or more and 400° C. Therefore, when a large-area substrate of the 8th generation or later is used as the substrate 5220, It can be seen that almost no warping occurs.

[0395] On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 moves to the surface of the substrate 5220. As a result, pellets 5200 do not pile up. In the case of nc-OS, the pellet 520 Because 0 is negatively charged, pellets 5200 may accumulate at regular intervals. Therefore, although the orientation is low, the amorphous acid has a slight regularity. It has a denser structure than nitride semiconductors.

[0396] In addition, in CAAC-OS, the gaps between pellets are extremely small, Large pellets of different sizes may be formed. The inside of one large pellet has a single crystal structure. For example, the size of the pellet is 10 nm or more and 200 nm or less when viewed from the top. It may be between 100 nm and 100 nm, or between 20 nm and 50 nm.

[0397] According to the above model, when the pellet 5200 is deposited on the surface of the substrate 5220, It is possible to form a CAAC-OS film even if the surface on which the film is to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. CAAC-OS and nc-OS can be deposited uniformly even on large glass substrates. For example, if the structure of the surface (surface to be formed) of the substrate 5220 is an amorphous structure (for example, amorphous It is possible to form a CAAC-OS film even on a silicon dioxide (silicon dioxide).

[0398] In addition, even if the surface of the substrate 5220 on which the film is to be formed is uneven, the film is formed along the shape of the uneven surface. It can be seen that let 5200 is arranged.

[0399] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination. [Example]

[0400] In this example, an OS transistor was fabricated and its cutoff frequency was measured. The cutoff frequency was measured as a function of the channel length of the transistor, and the measurement results are shown in Figure 31.

[0401] The fabricated OS transistor has the same device structure as the transistor TR1 shown in Figure 12. The gate insulating film 102 was formed using a silicon oxynitride film with a thickness of 10 nm. The gate electrode 104a and the conductive film 104b were formed of a 10 nm tungsten film. was formed by a laminated film of a titanium nitride film with a thickness of 10 nm and a tungsten film with a thickness of 10 nm. The back gate electrode (conductive film 105) is not provided. The semiconductor film is made up of three layers of In-Ga-Zn oxide films. The n-oxide film was formed by heating the substrate while sputtering in order to have a crystal part oriented along the c-axis. The film was formed as follows: A silicon wafer was used as the substrate.

[0402] OS transistors with channel lengths L of 60 nm, 100 nm, 180 nm, and 350 nm The frequency characteristics of each OS transistor were measured using a network analyzer. The cutoff frequency of each transistor was calculated. The number of measurements for each channel length L was 1. It is 0.

[0403] From the measurement results in Figure 31, the cutoff frequency is estimated to be approximately 2 GHz when the channel length L is 60 nm. It has been shown that miniaturized OS transistors have excellent frequency characteristics. [Example]

[0404] A circuit system according to one embodiment of the present invention was manufactured and various evaluations were performed. This article explains:

[0405] An OS transistor corresponding to the transistor TR1 shown in FIG. 12 was fabricated, and its electrical characteristics were was evaluated.

[0406] The fabricated OS transistor has a channel length L / channel width W=60 / 60 nm. The back gate electrode was formed of a tungsten film with a thickness of 50 nm. The insulating film is a 100 nm thick silicon oxynitride film and a 50 nm thick aluminum oxide film. The oxide semiconductor film had a stacked structure of a 50-nm-thick silicon oxide film and a 50-nm-thick silicon oxide film. In-Ga-Zn oxide (In:Ga:Zn=1:3:4 [atomic %]) with a thickness of 20 nm, 15 nm thick In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic %]) , 5 nm thick In-Ga-Zn oxide (In:Ga:Zn=1:3:2 [atomic %]) The source and drain electrodes were made of tungsten films with a thickness of 20 nm. The gate insulating film was a silicon oxynitride film with a thickness of 10 nm. The structure is a laminate of a 10 nm thick titanium nitride film and a 10 nm thick tungsten film. .

[0407] FIG. 32 shows the Id-Vg (drain current-gate) curve of the OS transistor fabricated in this example. In FIG. 32, the vertical axis represents Id (drain current) and the horizontal axis represents Vg ( The gate voltage is 0.1V and the drain voltage is 1.8V. No potential was applied to the back gate electrode, i.e., the measurement was performed in a floating state. Figure 2 shows the data for 13 transistors on the same substrate, and also the data for Vd = 0.1V. The data for Vd = 1.8V is shown overlapping the data for Vd = 1.8V. It was confirmed that the OS transistor of this example had good transistor characteristics. .

[0408] Next, a circuit having an OS transistor with the same device structure as the measurement target in Figure 32 was fabricated. The circuit diagram of the circuit that was fabricated is shown in Figure 33(A). The configuration is the same as that of the memory circuit 25 shown in FIG. 2(A) in the first embodiment, and includes a transistor M1, a transistor The transistor M2 and the capacitance element Cs are included.

[0409] Figure 33(B) shows the layout of the fabricated circuit, and Figure 33(C) shows the optical FIG. 33(C) shows an optical microscope photograph of the area corresponding to area 3000 in FIG. 33(B). The optical microscope photograph shown in Figure 33(C) shows that the desired circuit was fabricated. It was confirmed that this was the case.

[0410] In the fabricated circuit, the transistor M1 is an OS transistor with W / L=60 / 60nm. The transistor M1 is an OS transistor with W / L=60 / 60 nm. Here, two types of circuits were fabricated, one with a capacitance of 1 fF and the other with a capacitance of 3 fF. The former will be referred to as a memory circuit Mem1, and the latter will be referred to as a memory circuit Mem2.

[0411] The write operation of the fabricated memory circuits Mem1 and Mem2 was evaluated. 34 is a timing chart of a write operation. This corresponds to the operation of charging the capacitor Cs (node ​​FN). A voltage of 1.1 V was applied to the wiring WBL as a timing signal. A pulse of 3 V was also applied to the wiring WWL. A signal was applied to turn on the transistor M1. The potential of the wiring SL was set to 0 V. Time T write is the voltage at node FN when it is increased to 90% of the voltage at wiring WBL. In the example of operation shown in FIG. write The potential of node FN is 0V. This is the time it takes for the potential of the wiring WBL to reach 1V (a potential that is about 90% of the potential of 1.1V of the wiring WBL).

[0412] FIG. 35 shows the measurement results of the voltage of the node FN versus the write time. FIG. 35(B) shows the measurement results of the memory circuit Mem1, and FIG. 35(B) shows the measurement results of the memory circuit Mem2. The number of measurements was 5 for each. The voltage at node FN flows to the wiring RBL during the write operation. The current flowing through the wiring RBL was measured by measuring the drain current of the transistor M2. The voltage at node FN corresponds to the gate voltage of transistor M2. Therefore, from the measured current value and the Id-Vg characteristics of the transistor M2 obtained in advance, The horizontal axis of Figure 35 shows the write time when the wire WWL is 3V. is the time during which the voltage is applied.

[0413] The measurement results in Figure 35(A)(B) show that the capacitance element Cs can be charged to 90% in an extremely short time. This means that data can be written in an extremely short time. (A) shows that when the capacitance of the capacitor Cs is 1 fF, the potential of the node FN is It is possible to increase the voltage from 0V to 1V. If the capacitance of the capacitance element Cs is 3fF, the potential of the node FN is changed from 0V to 1V within 5nsec. This shows that it is possible to increase

[0414] Next, the write time of the memory circuits (Mem1, Mem2) and the write transistor The relationship with mobility will be explained.

[0415] FIG. 36 shows the capacitance of the capacitance element Cs of the memory circuit (Mem1, Mem2) and the write time. The measured values ​​in Figure 36 are values ​​obtained from the measurement results in Figure 35. 6 shows the average value of the write time of the five memory circuits Mem1 and the average value of the write time of the five memory circuits Mem2. The average values ​​of the write times are shown in Table 1. The write times of the memory circuits Mem1 and Mem2 are also shown in Table 1. The three curves in Figure 36 are the calculation results, and the solid line indicates the time when the operating environment is room temperature. (Calculation result 1) shows the calculation result of the writing time at (27°C). This is the result of increasing the mobility of the transistor M1 by 1 at room temperature (27°C). The dashed line shows the calculation results when the mobility of transistor M1 is doubled at room temperature (27°C). (Calculation result 2), and the dotted line is the calculation result when the mobility is tripled (Calculation result 3). be.

[0416] From the calculation results shown in FIG. 36, it is possible to increase the mobility of the transistor M1 by 1, 2, or 3 times. It was estimated that the write time would decrease. The calculated result almost coincides with the result when the mobility is tripled. When the capacitance element Cs is 1 fF, the actual measurement The value was less than 5 nsec.

[0417] As described above, it has been shown that the circuit fabricated in this embodiment can be applied to high-speed, low-power LSIs.

Example

[0418] In this example, an OS transistor (hereinafter sometimes referred to as "CAAC-OS FET") in which a semiconductor region is formed of a CAAC-OS film was fabricated, and the DC characteristics and RF characteristics of the CAAC-OS FET were measured. Also, a memory circuit was prototyped using the CAAC-OS FET, and its operation was verified. Details are described below.

[0419] <Fabrication of CAAC-OS FET> The prototyped CAAC-OS FET has a channel length L of 60 nm and a channel width W of 60 nm. The CAAC-OS FET has the same device structure as the transistor prototyped in Example 1 and was fabricated in the same process. An underlying insulating film was formed on the silicon wafer surface, and the CAAC-OS FET was formed on the underlying insulating film. The equivalent film thickness of the underlying insulating film in terms of silicon oxide film is 390 nm. Also, the equivalent film thickness of the gate insulating film is 11 nm. The semiconductor film of the prototyped CAAC-OS FET was formed of a three-layer In-Ga-Zn oxide film. The second layer of the In-Ga-Zn oxide film was formed by a sputtering apparatus while heating the silicon wafer so as to have a crystal part oriented in the c-axis direction.

[0420] The electrical characteristics of the fabricated CAAC-OS FET were measured. The measurement results are shown in FIGS. 37 to 39. The measurement data in FIGS. 37 to 39 are those of 5000 CAAC-OS FET groups electrically connected in parallel. Each CAAC-OS FET has L = 60 nm, ​​​​​​​​​​​​​W = 60 nm. That is, FIGS. 37 to 39 show the electrical characteristics of a C AAC-OS FET with W / L = 300 μm / 60 nm.

[0421] <DC Characteristics> FIG. 37(A) shows the drain current-gate voltage (Id-Vg) characteristics of a CAAC-OS FET with W / L = 300 μm / 60 nm, and FIG. 37(B) shows the drain current-drain voltage (Id-Vd) characteristics. The on-current Io at Vg = 2.2 V and Vd = 1.0 V is 2.87 mA, and the S value (subthreshold swing value) is 0.09 V / dec . The off-current is below the measurement lower limit of 1×10 A, which indicates the characteristic of extremely low leakage current of the CAAC-OS -13 FET.

[0422] FIG. 38 shows the transconductance g characteristics of a CAAC-OS FET with W / L = 300 μm / 60 nm. m [[ID=2८]]The drain voltage Vd is 0.1 V, 1.0 V, 2.0 V, 3.0 V, 4 .0 V. The maximum values of g m are 0.4 mS, 3.9 mS, 6.5 mS, 8.0 m S, 9.3 mS respectively. The gate voltages Vg when gm is maximum are 1.90 V , 2.20 V, 2.35 V, 2.65 V, 2.85 V respectively.

[0423] <RF Characteristics> The S parameter measurement of a CAAC-OS FET with W / L = 300 μm / 60 nm (5000 CAAC-OS FETs with W / L = 60 nm / 60 n m) was performed to obtain the RF gain ( current gain |H21| and maximum unidirectional power gain Ug), and the parameter cutoff frequency ( f T ) and the maximum oscillation frequency (f max ) were derived.

[0424] Figure 39 shows the RF gain (|H21|, Ug) with respect to frequency. Vd = 1.0V, V g = 2.2V. Figure 39 shows that f T and f max are both 1.9 GHz. These values are after de-embedding using open and short calibration. edding.

[0425] Figure 40 shows the dependence of f T and f max on the drain voltage Vd. f and f T are plotted under the voltage conditions where gm shown in Figure 38 is at its maximum max value. At drain voltages Vd of 0 .1V, 1.0V, 2.0V, 3.0V, 4.0V, f T is 0.2 GH z, 1.9 GHz, 3.4 GHz, 4.7 GHz, 5.6 GHz respectively, and f max is respectively 0.2 GHz, 1.9 GHz, 3.3 GHz, 4.2 GHz, 4.8 GHz. Figure 40 shows that both f T and f max increase as Vd increases.

[0426] <CAA-OS FET's potential application to LSI> A circuit was prototyped using a CAAC-OS FET and passive elements to verify the application of the CAAC-OS FET to an LS I. Here, as an example, the verification results of the memory circuit shown in Figure 41 are shown. The memory circuit shown in Figure 41 has the same circuit configuration as the memory circuit 25 in Figure 2(A) and has a write transistor MW, a read transistor MR, and a capacitive element Cs. The write transistor MW and the read transistor MR each have W / L = 60 nm / 60 ​The load capacitance C of node FN is load is 1.0fF, As shown in Figure 41, two types of memory circuits were fabricated, with load capacitances C lo ad is the sum of the capacitance element Cs and the parasitic capacitance.

[0427] The write time of the memory circuit shown in Figure 41 was measured. The measurement results are shown in Figure 42. The relationship between the load capacitance of the memory circuit and the write time is shown below. The measurement method is as follows.

[0428] In the initial state, the potential of node IN is set to 0.0V, and the potential of node OSG is set to 3.0V. By doing so, the potential of node FN is set to 0.0V, the potential of node OSG is set to -1.0V, Apply 1.1V to node IN. Apply a pulse (-1.0V to 3.0V) to node OSG. The drain current of the read transistor MR (the current flowing between the node S and the node D) The Id-Vg characteristics of the readout transistor MR, which had been measured in advance, were used to measure the noise. The potential of node FN was estimated. This measurement was carried out by changing the pulse width applied to node OSG. The pulse width is the time during which a potential of 3.0 V is applied to the node OSG. The write time is the pulse width at which the potential of FN becomes 1.0V (90% of the potential of node IN, 1.1V). The solid line in Figure 42 shows the calculation results. load When the value is 3.0fF, the write time is 4.0nsec, and when it is 1.0fF , indicating that the write time is 2.0 nsec.

[0429] <Summary> In this example, a CAAC-OS FET with W / L=60 nm / 60 nm was fabricated. The characteristics and RF characteristics were measured. -13 A) Below 1. 9GHz f T , 1.9GHz f max The write speed of the memory circuit is , 4.0nsec when the floating node load capacitance is 3.0fF, 2.0 when it is 1.0fF It was nsec.

[0430] CAAC-OS FET with L=60nm is expected to be applied to LSIs such as low-power memory devices. Furthermore, miniaturization will improve the RF characteristics of transistors. This is well known for CAAC-O technology nodes smaller than 60nm. S FET can achieve higher frequency f T , f max This means that the present embodiment By miniaturizing CAAC-OS FETs, microwave integrated circuits in the GHz frequency band can be realized. It was shown that application to MIC is possible. [Explanation of symbols]

[0431] 10 Circuit System 12 Memory Cell Array 14 Peripheral circuits 21 Transistor 22 transistor 23 Capacitor element 24 transistors 25 Memory circuit 26 Memory circuit 27 Memory circuit 31 PCB 32 Conductive film 33 Insulating film 34 Semiconductor film 34a Semiconductor film 34b Semiconductor film 34c Semiconductor film 35 Conductive film 36 Conductive film 37 Insulating film 38 Conductive Film 42 Conductive film 43 Insulating film 44 Semiconductor Film 44a Semiconductor film 44b Semiconductor film 44c Semiconductor film 45 Conductive film 46 Conductive Film 47 Insulating Film 48 Conductive Film 100 boards 101 Semiconductor film 101a Semiconductor film 101b Semiconductor film 101c Semiconductor film 102 Gate insulating film 103 gate electrode 104a Conductive film 104b Conductive film 105 Conductive film 114 insulating film 115 insulating film 116 Insulating film 118a plug 118b plug 133 Conductive Film 134 Plug 141 Plug 142 Plug 143 Plug 144 Plug 145 plug 151 Conductive film 152 Conductive film 153 Conductive film 155 Conductive film 156 Insulating film 171a Low resistance region 171b Low resistance region 202 Gate insulating film 203 Gate electrode 204a Conductive film 204b Conductive film 205 Conductive Film 212 insulating film 213 Insulating film 216 Insulating film 291 layers 292 layers 293 layers 294 layers 295 layers 296 layers 297 layers 300 memory cell array 700 transistors 701 Transistor 702 transistors 703 Transistor 704 Transistor 705 Capacitor 706 Diode 711 Plug 712 Plug 713 Plug 714 Plug 721 Wiring 722 Wiring 723 Wiring 724 Wiring 730 board 731 Element isolation layer 732 insulating film 733 Insulating Film 735 PCB 741 Wiring 742 Wiring 743 Wiring 800 RF Devices 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 Memory circuit 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2001 Impurity region 2002 Impurity region 2003 Gate electrode 2004 Gate insulating film 2005 Sidewall insulating layer 2011 Circuit 2012 Circuit 2013 Circuit 2100 transistors 2200 transistors 2201 PCB 2202 Wiring 2203 Plug 2204 Element isolation layer 2205 Wiring 2206 Wiring 2207 Insulating film 2208 Insulating film 2211 Semiconductor substrate 2212 insulating film 2213 Gate electrode 2214 Gate insulating film 2215 Impurity region 2216 Impurity region 2300 Capacitor 3000 area 4000 RF Devices 5100 pellets 5120 board 5161 area 5200 pellets 5201 AEON 5203 particles 5220 board 5230 Target 5240 Plasma 5260 Heating mechanism

Claims

1. a first circuit and a second circuit; each of the first circuit and the second circuit includes a first transistor, a second transistor, and a capacitance element; one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; a semiconductor device in which one electrode of the capacitance element is electrically connected to a gate of the first transistor, a first semiconductor film having a channel region of the first transistor; a first conductive film having a region in contact with an upper surface of the first semiconductor film; a second conductive film having a region in contact with an upper surface of the first semiconductor film; a third conductive film having a region located above the first semiconductor film and functioning as one electrode of the capacitor; a fourth conductive film having a region located above the third conductive film and functioning as the other electrode of the capacitor; a first insulating film having a region located above the fourth conductive film; a second semiconductor film having a region located above the first insulating film and having a channel region of the second transistor; a fifth conductive film having a region in contact with an upper surface of the second semiconductor film and electrically connected to the third conductive film; a sixth conductive film having a region located above the second semiconductor film and functioning as a gate of the second transistor; and each of the third conductive film and the fourth conductive film overlaps with the first semiconductor film; the first circuit and the second circuit share one of the second conductive films; the first transistor has a function of causing a current to flow between the first conductive film and the second conductive film in accordance with an amount of charge held in the capacitor element when the first conductive film and the second conductive film are electrically connected at least through a channel formation region of the first transistor; Semiconductor device.

2. a first circuit and a second circuit; each of the first circuit and the second circuit includes a first transistor, a second transistor, and a capacitance element; one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; a semiconductor device in which one electrode of the capacitance element is electrically connected to a gate of the first transistor, a first semiconductor film having a channel region of the first transistor; a first conductive film having a region in contact with an upper surface of the first semiconductor film; a second conductive film having a region in contact with an upper surface of the first semiconductor film; a third conductive film having a region located above the first semiconductor film and functioning as one electrode of the capacitor; a fourth conductive film having a region located above the third conductive film and functioning as the other electrode of the capacitor; a first insulating film having a region located above the fourth conductive film; a second semiconductor film having a region located above the first insulating film and having a channel region of the second transistor; a fifth conductive film having a region in contact with an upper surface of the second semiconductor film and electrically connected to the third conductive film; a sixth conductive film having a region located above the second semiconductor film and functioning as a gate of the second transistor; a second insulating film having a region located above the sixth conductive film; a seventh conductive film having a region located above the second insulating film and electrically connected to the first conductive film; and each of the third conductive film and the fourth conductive film overlaps with the first semiconductor film; the first circuit and the second circuit share one of the second conductive films; the first transistor has a function of causing a current to flow between the first conductive film and the second conductive film in accordance with an amount of charge held in the capacitor element when the first conductive film and the second conductive film are electrically connected at least through a channel formation region of the first transistor; Semiconductor device.

3. a first circuit and a second circuit; each of the first circuit and the second circuit includes a first transistor, a second transistor, and a capacitance element; one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; a semiconductor device in which one electrode of the capacitance element is electrically connected to a gate of the first transistor, a first semiconductor film having a channel region of the first transistor; a first conductive film having a region in contact with an upper surface of the first semiconductor film; a second conductive film having a region in contact with an upper surface of the first semiconductor film; a third conductive film having a region located above the first semiconductor film and functioning as one electrode of the capacitor; a fourth conductive film having a region located above the third conductive film and functioning as the other electrode of the capacitor; a first insulating film having a region located above the fourth conductive film; a second semiconductor film having a region located above the first insulating film and having a channel region of the second transistor; a fifth conductive film having a region in contact with an upper surface of the second semiconductor film and electrically connected to the third conductive film; a sixth conductive film having a region located above the second semiconductor film and functioning as a gate of the second transistor; a second insulating film having a region located above the sixth conductive film; a seventh conductive film having a region located above the second insulating film and electrically connected to the first conductive film; an eighth conductive film electrically connected to the second conductive film; and each of the seventh conductive film and the eighth conductive film has a region in contact with an upper surface of the second insulating film; each of the third conductive film and the fourth conductive film overlaps with the first semiconductor film; the first circuit and the second circuit share one of the second conductive films; the first transistor has a function of causing a current to flow between the first conductive film and the second conductive film in accordance with an amount of charge held in the capacitor element when the first conductive film and the second conductive film are electrically connected at least through a channel formation region of the first transistor; Semiconductor device.

4. In any one of claims 1 to 3, the second semiconductor film includes an oxide semiconductor; Semiconductor device.

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