Integrated circuits with configurable neuromorphic neurons for artificial neural networks

Abstract

The present disclosure relates to an integrated circuit including a first neuromorphic neuron device. The first neuromorphic neuron device includes an input and an accumulation block including a state variable for performing an inference task based on input data including a time series. The first neuromorphic neuron device may be switchable between a first mode and a second mode. The accumulation block may be configured to perform adjustment of the state variable using a current input signal of the first neuromorphic neuron device and a decay function indicating the decay behavior of the device. The state variable may depend on one or more input signals previously received by the first neuromorphic neuron device.

Description

[Technical Field]

[0001] The present invention relates generally to the field of neural network systems, and more particularly to integrated circuits comprising neuromorphic neuron apparatus. [Background technology]

[0002] A neural network is a computational model used in artificial intelligence systems. A neural network is based on multiple artificial neurons. Each artificial neuron is connected to one or more other neurons, and the links can reinforce or suppress the activation state of adjacent neurons. However, there is a need for improved hardware systems for implementing such neural networks. To improve the performance of neural network hardware systems, such hardware is sometimes designed as neuromorphic hardware. Summary of the Invention

[0003] Various embodiments provide integrated circuits, multi-core chip architectures, and methods as described by the subject matter of the independent claims. Advantageous embodiments are described in the dependent claims. The embodiments of the invention may be freely combined with one another if they are not mutually exclusive.

[0004] In one aspect, the present invention relates to an integrated circuit including a first neuromorphic neuronal device, the first neuromorphic neuronal device including an input and an accumulation block including state variables for performing an inference task based on input data including a time series. The first neuromorphic neuronal device may be switchable between a first mode and a second mode. The accumulation block may be configured to perform adjustment of the state variables using a decay function indicating the current input signals of the first neuromorphic neuronal device and decay behavior of the devices. The state variables may depend on one or more input signals received prior to the first neuromorphic neuronal device. The first neuromorphic neuronal device may be configured to receive the current input signals via the input. Furthermore, when the first neuromorphic neuronal device is switched in the first mode, the first neuromorphic neuronal device may be configured to generate an intermediate value as a function of the state variables. Furthermore, when the first neuromorphic neuronal device is switched in the second mode, the first neuromorphic neuronal device may be configured to generate an intermediate value as a function of the current input signals, independent of the state variables. Additionally, the first neuromorphic neuron device may be configured to generate an output value as a function of the intermediate value.

[0005] In another aspect, the present invention relates to a multi-core chip architecture, the architecture comprising integrated circuits as cores, each integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an input and an accumulation block including state variables for performing an inference task based on input data including a time series, the first neuromorphic neuron device being switchable between a first mode and a second mode.

[0006] The accumulation block may be configured to perform adjustment of the state variables using current input signals of the first neuromorphic neuronal device and a decay function indicative of the decay behavior of the device. The state variables may depend on one or more input signals previously received by the first neuromorphic neuronal device. The first neuromorphic neuronal device may be configured to receive the current input signals via the input. Furthermore, when the first neuromorphic neuronal device is switched in a first mode, the first neuromorphic neuronal device may be configured to generate an intermediate value as a function of the state variables. Furthermore, when the first neuromorphic neuronal device is switched in a second mode, the first neuromorphic neuronal device may be configured to generate an intermediate value as a function of the current input signals, independent of the state variables. Furthermore, the first neuromorphic neuronal device may be configured to generate an output value as a function of the intermediate value.

[0007] In another aspect, the present invention relates to a method for generating an output value of an integrated circuit, the integrated circuit comprising a first neuromorphic neuronal device, the first neuromorphic neuronal device comprising an input and an accumulation block including state variables for performing an inference task based on input data including a time series, the first neuromorphic neuronal device being switchable between a first mode and a second mode, the method including: performing adjustment of the state variables using current input signals of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more input signals previously received by the first neuromorphic neuronal device; receiving the current input signals via the input; generating an intermediate value as a function of the state variables when the first neuromorphic neuronal device is switched in the first mode, or generating the intermediate value as a function of the current input signals, independent of the state variables, when the first neuromorphic neuronal device is switched in the second mode; and generating an output value of the integrated circuit as a function of the intermediate value.

[0008] In another aspect, the present invention relates to a computer program product comprising a computer readable storage medium having computer readable program code embodied therein, the computer readable program code being configured to perform all of the steps of the method.

[0009] Embodiments of the invention will now be described in more detail, by way of example only, with reference to the following drawings in which: [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 illustrates an integrated circuit including a neuromorphic neuron device, in accordance with a preferred embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the flow of input data in an integrated circuit. [Figure 3] FIG. 1 illustrates a neural network simulated using an integrated circuit in accordance with a preferred embodiment of the present invention. [Figure 4] FIG. 1 illustrates an attenuation function block of an integrated circuit. [Figure 5] FIG. 1 illustrates the accumulation and output generation blocks of a neuromorphic neuron device. [Figure 6] FIG. 10 illustrates a further integrated circuit including a neuromorphic neuron device in accordance with a preferred embodiment of the present invention. [Figure 7] FIG. 1 is a diagram showing a crossbar arrangement of memristors. [Figure 8] FIG. 7 shows the integrated circuit of FIG. 6 coupled to a bus system. [Figure 9] FIG. 10 illustrates a further integrated circuit including a neuromorphic neuron device in accordance with a preferred embodiment of the present invention. [Figure 10] 1 illustrates a multi-core chip architecture in accordance with a preferred embodiment of the present invention. [Figure 11] 7 is a flowchart of a method for generating an output value of the integrated circuit of FIG. 6. [Figure 12]FIG. 8 shows a chart containing initialization functions for setting up the memory elements of the crossbar array shown in FIG. 7. [Figure 13] FIG. 10 illustrates a time-dependent initialization function. DETAILED DESCRIPTION OF THE INVENTION

[0011] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0012] A first neuromorphic neuron apparatus (NNA) may be used to simulate one or more neurons of an artificial neural network. The first NNA may also be considered as one neuron of the artificial neural network. When the first NNA is switched in a first mode, the first NNA may be used to perform an inference task based on input data containing time series. The inference task may be realized by repeatedly calculating adjustments to state variables using a decay function with an accumulation block. When the first NNA is switched in a second mode, the first NNA may be used to perform a further inference task based on further input data that does not contain time series. The further inference task may be realized by calculating intermediate values ​​independently of the state variables. In this case, the first NNA may be considered as a non-stateful neuron of the artificial neural network. The non-stateful neuron may be a neuron used in a general multi-layer perceptron (MLP) that does not contain recursive connections. A non-stateful neuron may be a neuron used in a general recurrent neural network (RNN) to process inputs containing time series, where some of the neuron's inputs may constitute inputs from external recurrent connections (i.e., operations from outside the first NNN).

[0013] The input data including the time series may refer to an audio recording and the inference task may refer to audio recognition. The further input data may be in the form of a photograph and the further inference task may be to perform object recognition.

[0014] The first NNA may be switched between the first mode and the second mode during an initialization procedure of an integrated circuit (IC). After the initialization procedure, the IC may be used, for example, for neural network training or for inference or further inference tasks, or both, without switching the mode of the first NNA again. In another example, the first NNA may be switched from the first mode to the second mode or from the second mode to the first mode after the IC initialization procedure. This switching may be useful for applications involving adjustments to the neural network architecture. These adjustments may include changing the type of neurons in one or more layers of the neural network, referring to the layer containing the first NNA. Thus, the presented IC can ease the rapid design of neural networks, particularly the rapid design changes of neural networks, and advantageously, the automated design changes of neural networks.

[0015] The switching of the first NNA from the first mode to the second mode or from the second mode to the first mode may be performed as a function of the value of a parameter indicative of the neural network's performance. This parameter may indicate energy consumption or the neural network's training performance. Thus, the presented IC can facilitate faster learning of the neural network or energy savings when training the neural network or using the neural network for inference tasks.

[0016] The state variables may be maintained, for example, by exchanging state variables through a cyclic connection internal to the first NNA, or by other means, such as a memory, such as a memristor device, e.g., a phase-change memory or other memory technology. In the case of a memristor device, the value of the state variable may be represented by the conductance of the device. The first NNA switched in the first mode may enable accurate and efficient processing of input data containing time series. For example, this input data stream may be directly fed to the first NNA, preferably processed independently by the first NNA. This may enable the first NNA to be applicable to tasks such as unsegmented, connected handwriting recognition or speech recognition when switched in the first mode.

[0017] According to one embodiment, the integrated circuit further comprises a first assembly of memory elements. The first assembly of memory elements comprises input connections for applying corresponding voltages to each input connection to generate a single current in each memory element. In one example, the voltage may be applied in the form of voltage pulses having a constant voltage but varying in pulse length or number of pulses within a time interval to perform pulse width modulation. In a further example, a voltage including at least two different voltage values ​​from a plurality of voltages may be applied. The voltage may be applied using a voltage source or a current source. The first assembly further comprises at least one output connection for outputting an output current. The memory elements are connected to each other such that the output current is a sum of a single current. The output connection of the first assembly may be coupled to an input of the first neuromorphic neuron device. The integrated circuit may be configured to generate a current input signal based on the output current.

[0018] According to another embodiment, the memory elements may be resistive memory elements, also known as memristors. The resistive memory elements may be phase change memory (PCM), metal oxide resistive RAM, conductive bridge RAM, or magnetic RAM elements. The resistive memory elements may each have a conductance G, which may be alterable by applying a programming voltage or current to each resistive memory element (RME). A single weight of the network may be represented by the conductance G of one or more RMEs. The single weight of the network may indicate the strength of a connection between the first NNA and additional neurons disposed in additional layers of the network. Additional layers may be disposed between the layer containing the first NNA and the input layer of the network. In one example, a larger value of the weight may indicate a stronger connection between the first NNA and additional neurons.

[0019] According to another embodiment, the memory elements may be charge-based memory devices such as static random-access memory (SRAM) elements.

[0020] The memory elements may be connected to one another such that at least each of the memory elements may have an electrical link with another one of the memory elements. The electrical link may be direct or indirect. An indirect link may include a resistor. In this case, at least two of the memory elements may be connected to one another through a resistor.

[0021] Because the memory elements are connected together such that the output current is a single current sum, the output current may be considered the result of the scalar product of the first and second vectors. Herein, the first vector may include entries each representing a corresponding voltage value. The second vector may include entries, each of which may be a value stored in one or more of the memory elements, e.g., in the form of a conductance value of one or more RMEs. Thus, the first assembly allows for the calculation of the scalar product at the hardware level by adding a single current to the sum. This embodiment represents a very fast method for obtaining the scalar product result, e.g., faster than scalar product calculations performed on a conventional CPU.

[0022] Faster calculation of scalar products may be beneficial when running the first NNA in the first mode. This may be due to the following reasons: Compared to a first NNA running in a second mode and clocked at a second time step size, the first NNA running in the first mode may need to be clocked at a first time step size, which may be larger than the first time step size. Therefore, the first NNA running in the first mode may require a higher frequency of scalar product calculations. This may be sufficient to resolve time effects in input data containing time series. Faster calculation of scalar products using the first assembly may reduce latency and thus enable the first NNA switched in the first mode to be used in certain real-world applications. As a result, the first assembly may ease practical applications of ICs including a first NNA switchable between the first and second modes, particularly considering ICs applied to real-world applications.

[0023] According to another embodiment, the IC may further include a comparison circuit. The comparison circuit may be configured to compare the intermediate value with a threshold value when the first NNA is switched in the first mode. According to this embodiment, the first NNA may be configured to set an output value equal to 1 when the intermediate value is greater than the threshold value and to set an output value equal to 0 when the intermediate value is less than or equal to the threshold value. The threshold value may represent a threshold voltage for the first NNA, which may be considered a spiking neuron in this case. The comparison circuit may contribute to the spiking characteristics of the first NNA when the first NNA is switched in the first mode. In this case, the first NNA may be considered a spiking neuron of the network.

[0024] The integrated circuit (IC) including the comparison circuit may be configured to simulate or represent a neuron or layer of neurons of a neural network, and when the first NNN is switched in the first mode, the network may be a spiking neural network (SNN) or a layer of the network may be a spiking layer. The spiking layer may be a layer of neurons, and all neurons in the layer may be spiking neurons.

[0025] The use of SNNs or spiking layers can be advantageous as it can allow for sparse communication in the time domain within the network, which can reduce heat generation and energy consumption of ICs.

[0026] The use of spiking neural networks can be advantageous compared to other types of networks, such as MLPs or RNNs, because they have relaxed requirements regarding the required memory and communication of neuron outputs in a multi-layer architecture. For example, the contents of memory can be represented with lower precision, or even binary values ​​can be sufficient. The first spike of an NNN can be represented as a binary value of 1, for example. This can allow for area-efficient and flexible implementation of memory. It can also allow for the utilization of new storage technologies (e.g., RME).

[0027] According to another embodiment, the integrated circuit may further include an analog-to-digital converter (ADC). The output connection of the first assembly of memory elements may be coupled to the input of the first neuromorphic neuron device via the ADC. The output connection of the first assembly may be coupled to the input connection of the ADC, and the output connection of the ADC may be coupled to the input of the first neuromorphic neuron device. The ADC may be configured to convert an output current into a current input signal, the current input signal being a digital signal. The digital current input signal may have the advantage that the logic for implementing the first NNA may be digital, which may reduce the cost of producing the IC. Typically, the first NNA may be implemented by analog elements.

[0028] According to another embodiment, the integrated circuit may further comprise additional assemblies of memory elements. In one embodiment, the memory elements of the additional assemblies may be RMEs. The additional assemblies of memory elements may each be connected to the input connection of the first assembly to apply a corresponding voltage to each memory element of the additional assemblies to generate a respective additional single current in each memory element of each additional assembly. Each of the additional assemblies may comprise a respective output connection to output a respective additional output current. The memory elements of each of the additional assemblies may be connected to each other such that each additional output current is a respective sum of each additional single current in the memory elements of each assembly. The integrated circuit may be configured to generate a corresponding additional current input signal based on each additional output current. The IC may be further configured to generate additional output values ​​based on each additional current input signal using the first NNA or additional neuromorphic neuron devices of the IC.

[0029] The conductance G of one or more RMEs of the further assembly may represent a single weight of the network, which may indicate the strength of the connection between a further NNA and a second further neuron located in a further layer of the network.

[0030] Because the memory elements of each of the additional assemblies are connected to each other so that each additional output current is a respective sum of each additional single current, each additional output current can be considered a respective result of a respective scalar product of the first vector and each additional second vector. Each second additional vector can include entries, each entry being a value stored in one or more of the memory elements of each additional assembly, for example, in the form of a value of the conductance of one or more RMEs of each additional assembly. Thus, each additional assembly can enable the calculation of each scalar product at the hardware level by adding each additional single current to each respective sum. Furthermore, each additional output current can be considered together as a result vector. The result vector can include entries, each entry representing the value of each additional output current.

[0031] This embodiment therefore represents a very fast way to obtain the result of a matrix-vector multiplication, where the matrix contains a vector that is each further second vector, and the second vector as a column, and the first vector.

[0032] If the conductance G of the RME of the further assembly can represent each single weight of the network, each entry of the result vector can represent the current input signal or each further current input signal of the neuron of the layer containing the first NNA. Each entry of the first vector can represent the current output signal of a neuron of the further layer located between this layer and the input layer. Therefore, matrix-vector multiplication can be viewed as the propagation of an output signal of a neuron of the further layer to each input of a neuron of the layer containing the first NNA. Because the matrix-vector multiplication can be performed at the hardware level using the RME, this multiplication can be performed faster than conventional execution on a CPU. This can make it possible to use a first NNA switched in a first mode and clocked at a first time step size to better handle the temporal information of input data containing time series in relation to inter-layer propagation within the network. This can make it possible to create and use deep neuron networks containing hundreds of hidden layers and to perform inference tasks using input data sets containing many time series.

[0033] According to another embodiment, the integrated circuit may further comprise an analog-to-digital converter (ADC), a first memory, and a sequential circuit, wherein the analog-to-digital converter is configured to convert the output current into a current input signal and to convert the further output current into each further current input signal, the first memory is configured to store the current input signal and the further current input signal, and the sequential circuit is configured to continuously transmit the current input signal and the further current input signal to an input of the first neuromorphic neuron device.

[0034] According to another embodiment, the integrated circuit may be configured to generate additional output values ​​using the first NNA, each based on a respective additional current input signal. This may be achieved by the first NNA continuously generating additional output values ​​based on each additional current input signal. Transmission of the current input signal may be achieved in the following manner: a sequential circuit may continuously read the current input signal and the additional current input signals from the first memory and continuously transfer these values ​​to the inputs of the first NNA. This embodiment may enable layer-to-layer propagation using only a single artificial neuron circuit, such as the first NNA. This is advantageous because the number of neurons in a layer does not need to be known a priori to simulate the network at the hardware level.

[0035] According to another embodiment, the integrated circuit may further include additional neuromorphic neuron devices. Each additional neuromorphic neuron device may include an input and an accumulation block including state variables for performing an inference task based on input data including a time series. Each additional neuromorphic neuron device may be switchable between a first mode and a second mode. Each additional output connection of the additional assembly may be coupled, i.e., electronically coupled, to one of the inputs of the additional neuromorphic neuron device. The accumulation block of each additional neuromorphic neuron device may be configured to adjust the state variable of each accumulation block using a decay function indicating the additional current input signal and the decay behavior of each additional neuromorphic neuron device. The state variable of each accumulation block may depend on one or more input signals received prior to each additional neuromorphic neuron device.

[0036] Each further neuromorphic neuronal device may be configured to receive, via an input of each further neuromorphic neuronal device, a further current input signal of each further neuromorphic neuronal device.

[0037] Furthermore, when each further neuromorphic neuronal device is switched in the first mode, each further neuromorphic neuronal device may be configured to generate an intermediate value of each further neuromorphic neuronal device as a function of the state variables of each accumulation block.

[0038] Furthermore, when each further neuromorphic neuronal device is switched in the second mode, each further neuromorphic neuronal device may be configured to generate an intermediate value of each further neuromorphic neuronal device as a function of a further current input signal of each further neuromorphic neuronal device, independent of the state variables of each accumulation block.

[0039] Furthermore, each additional neuromorphic neuron device may be configured to generate each additional output value as a function of the intermediate value of each neuromorphic neuron device. This embodiment may enable significantly faster inter-layer propagation, allowing the first NNA and the additional NNA to generate output values ​​and additional output values ​​in parallel. Furthermore, according to this embodiment, the ADC may directly transfer the current input signal and the additional current input signal to the inputs of the first NNA and the additional NNA, respectively, without storing these signals in the first memory. In this embodiment, a sequential circuit may not be required.

[0040] According to another embodiment, the memory elements of the first assembly and the memory elements of the further assembly may be arranged in rows and columns. Each memory element may represent one of the entries of a matrix. The entries of the matrix may represent each weight of a connection between two neurons of the artificial neural network. A layer of the artificial neural network may be simulated using a first neural network element (NNA). In one example, the layer may include the first neural network element (NNA) and a further neural network element (NNA). The arrangement of the RMEs in rows and columns may simplify the design and manufacturing of the first assembly and the further assembly.

[0041] According to another embodiment, the integrated circuit may further include a first switchable circuit. The first switchable circuit may be configured to operate in a first mode or a second mode. When the first switchable circuit is switched in the first mode, the first switchable circuit may be configured to generate an intermediate value as a function of the state variable. Furthermore, when the first switchable circuit is switched in the second mode, the first switchable circuit may be configured to generate the intermediate value as a function of the current input signal, independent of the state variable. According to this embodiment, only one circuit may be required to generate the intermediate value. This may reduce the number of circuits in the IC. When the first switchable circuit is switched in the first mode and the second mode, generally, only a portion of the first switchable circuit may be used. Such a portion of the first switchable circuit may be logic implementing fused multiplication and addition.

[0042] According to another embodiment, when the first switchable circuit is switched in the second mode, the first switchable circuit may be configured to generate intermediate values ​​as a function of a current input signal and a parameter value derived from a batch normalization algorithm of a training data set for training the first neuromorphic neuron device. According to this embodiment, the parameter value derived from the batch normalization algorithm may be an input value of logic implementing fused multiplication and addition. Batch normalization may facilitate faster training of the network. Performing an inference task using a network trained using batch normalization may require transforming current input values ​​and further current input values ​​by multiplying them by the parameter value derived from the batch normalization algorithm. Thus, this embodiment may enable the use of batch normalization in network training and inference tasks.

[0043] According to another embodiment, the integrated circuit may further include a second switchable circuit and a configuration circuit. The second switchable circuit may be configured to execute in a first mode or a second mode and generate an output value according to a first activation function based on the intermediate value when the second switchable circuit is switched in the first mode. Furthermore, when the second switchable circuit is switched in the second mode, the second switchable circuit may be configured to generate an output value according to a second activation function based on the intermediate value when the second switchable circuit is switched. The configuration circuit may be configured to switch the first switchable circuit and the second switchable circuit between the first mode and the second mode. In one example, the configuration circuit may be configured to simultaneously switch the first switchable circuit and the second switchable circuit between the first mode and the second mode. The first activation function is different from the second activation function. This may increase the flexibility of the IC for various real-world applications. The first activation function may be a rectified linear function, a sigmoid function, or a hyperbolic tangent. Similarly, the second activation function may be a rectified linear function, a sigmoid function, or a hyperbolic tangent.

[0044] According to another embodiment, the integrated circuit may further comprise additional configuration circuitry. The additional or aforementioned configuration circuitry may be configured to simultaneously switch the first neuromorphic neuronal device and each additional neuromorphic neuronal device to the first mode or the second mode. This embodiment may enable fast synchronous switching of all NNAs from the first mode to the second mode and from the second mode to the first mode.

[0045] According to another embodiment, the integrated circuit may further comprise a rectified linear unit. Regardless of whether the first neuromorphic neuron device is switched in the first mode or whether the first neuromorphic neuron device is switched in the second mode, the rectified linear unit may be configured to generate a further intermediate value as a function of the intermediate value. The first neuromorphic neuron device may be configured to generate an output value based on the further intermediate value. The rectified linear unit (ReLU) may be part of the first NNA. The ReLU may enable fast learning in training the network.

[0046] According to another embodiment, the comparison circuit may be configured to compare the further intermediate value with a threshold value when the first neuromorphic neuron device is switched in the first mode. According to this embodiment, the first neuromorphic neuron device may be configured to set an output value equal to the further intermediate value if the further intermediate value is greater than the threshold value, and to set an output value equal to 0 if the further intermediate value is less than or equal to 0. This embodiment may combine the advantages of the ReLU and the first NNA, which is a spiking neuron.

[0047] According to another embodiment, the integrated circuit may further include an input conversion circuit. The input conversion circuit may be configured to change the magnitude of a current input signal using scaling. This scaling may depend on the range of output values ​​of the analog-to-digital converter and may be independent of the mode of the first neuromorphic neuron device. This means that the scaling may be the same regardless of whether the first NNA is switched in the first mode or the second mode. Thus, the input conversion circuit may be used in both modes of the first NNA, thereby reducing the amount of circuitry required within the IC.

[0048] According to another embodiment, the first neuromorphic neuron device may be configured to generate output values ​​whose allowable range of output values ​​is independent of the mode of the first neuromorphic neuron device, meaning that the allowable range of output values ​​is the same when the first neuromorphic neuron device is switched in the first mode or the second mode. This embodiment may enhance the compatibility between different layers of the network.

[0049] According to another embodiment, each memory element may comprise a respective variable conductance, and each conductance may be in a respective shifted state. Each memory element may be configured to set each conductance to a respective initial state. Additionally, each memory element may include a respective shift of each conductance from the respective initial state to the respective shifted state. The respective initial states of each conductance may be calculable using a respective initialization function. The respective initialization function may depend on a respective target state of each conductance, and the respective target state of each conductance may be approximately equal to the respective shifted state of each conductance.

[0050] The term "shift" as used herein refers to a change in the value of conductance over time, such as a decay in conductance over time. The term "shifted state" as used herein refers to a state of conductance that is altered compared to an initial state. Time has passed between a point in time when the conductance is in the initial state and a further point in time when the conductance is in the shifted state. Furthermore, in the shifted state of the conductance of a resistive memory element, the change in conductance over time may be smaller than the change in conductance over time in the initial state of the conductance. Thus, in the shifted state of conductance, the information that may be represented by the actual value of the conductance of a resistive memory element may be retained with greater accuracy over time. In one example, the change in conductance over time in the shifted state of conductance may be less than 10 percent compared to the change in conductance over time in the initial state of the conductance. In another example, the change in conductance over time in the conductance-shifted state may be less than 5 percent, or by further example, less than 1 percent, compared to the change in conductance over time in the conductance-initial state.

[0051] Thus, after setting the conductance to an initial value, the change in conductance over time decreases over time. This effect was observed experimentally to depend on the initial value of the conductance. This embodiment provides a storage device using resistive memory elements with greater precision compared to a standard use case. A standard use case may include programming the conductance of the resistive memory elements to an initial state, after which the resistive memory elements may be used directly. This advantage may be used to generate the single current described above. An output current that may be generated as a sum of the single currents may be generated with greater precision. Thus, resistive memory elements with their respective conductances in the offset states may be used to perform more precise summation at the hardware level.

[0052] The initial state or value of the conductance may be calculated using an initialization function in a computer, e.g., using a look-up table. In another example, the conductance may be calculated using the initialization function in a manual manner.

[0053] According to another embodiment, the accumulation block may comprise a memory element, hereinafter also referred to as an accumulation block memory element (ABME), which may comprise a modifiable physical quantity for storing a state variable, which may be in a displaced state, and the ABME is configured to set the physical quantity to an initial state, the ABME comprising a displacement of the physical quantity from the initial state to the displaced state, the initial state of the physical quantity being computable using a further initialization function, which further initialization function is dependent on a target state of the physical quantity, which target state of the physical quantity is approximately equal to the displaced state of the physical quantity and dependent on the state variable.

[0054] The term "shifted state," as used herein, refers to a change in the value of a physical quantity over time, such as the decay of a physical quantity over time. The term "shifted state," as used herein, refers to a state of a physical quantity that is altered compared to its initial state. Time has passed between a time when the physical quantity is in its initial state and a further time when the physical quantity is in its shifted state. Furthermore, in the shifted state of the physical quantity of the ABME, the change in the physical quantity over time may be smaller than the change in the physical quantity over time at the physical quantity's initial state. Thus, when the physical quantity is in the shifted state, information that may be represented by the actual value of the physical quantity of the ABME may be retained with greater accuracy over time. In one example, the change in the physical quantity over time at the shifted state of the physical quantity may be less than 10 percent compared to the change in the physical quantity over time at the physical quantity's initial state. In another example, the change in the physical quantity over time at the shifted state of the physical quantity may be less than 5 percent, or by further example, less than 1 percent compared to the change in the physical quantity over time at the physical quantity's initial state. The physical quantity may be the conductance of the ABME.

[0055] The ABME may be a resistive memory element. Thus, the ABME may be a phase change memory (PCM), a metal oxide resistive RAM, a conductive bridge RAM, or a magnetic RAM element. The ABME may have a conductance G, which may be alterable by applying a programming voltage or current to the ABME. The value of a state variable may be represented by the conductance G of the ABME.

[0056] The initial states or values ​​of the physical quantities of the ABME may be calculated using a further initialization function, for example, by a computer, using a further look-up table. In another example, the conductance may be calculated using a further initialization function in a manual manner.

[0057] According to another embodiment of the multi-core chip architecture, each integrated circuit may further include a respective first assembly of memory elements. The memory elements of each integrated circuit's first assembly may be RMEs. Each first assembly of memory elements of each IC may include an input connection for applying a corresponding voltage to each input connection to generate a single current in each RME of each first assembly of ICs. Furthermore, each first assembly of RMEs of each IC may include at least one output connection for outputting a corresponding output current of each first assembly of ICs. The RMEs of each first assembly of ICs may be connected to each other such that each output current is a sum of a single current. The output connection of each first assembly may be coupled to an input of a first neuromorphic neuronal device of each integrated circuit. Each integrated circuit may be configured to generate a current input signal for the first neuromorphic neuronal device of each integrated circuit based on each output current. According to this embodiment, at least two of the integrated circuits may be connected to each other to simulate a neural network comprising at least two hidden layers. This embodiment may allow for fast calculation of scalar products to be performed as described above on different cores, i.e., different ICs of a multi-core chip architecture. Similarly, each IC of a multi-core chip architecture may comprise an additional assembly of RMEs, such as those comprised in the presented IC, to achieve fast vector-matrix multiplication on each core of the multi-core chip architecture.

[0058] One of the ICs of the multi-core chip architecture, hereinafter referred to as the first IC, may simulate a first hidden layer of the network, and another of the ICs of the multi-core chip architecture, hereinafter referred to as the second IC, may simulate a second hidden layer of the network.

[0059] According to another embodiment of the multi-core chip architecture, at least one of the integrated circuits, e.g., a first neuromorphic neuron device of a first IC, may be switched in a first mode, and at least one of the other integrated circuits, e.g., a first neuromorphic neuron device of a second IC, may be switched in a second mode. For example, a first neuron network element (NNA) of a first IC may be switched in a first mode, and a first neuron network element (NNA) of a second IC may be switched in a second mode. In this case, a first hidden layer may be disposed between the second hidden layer and the input layer of the network. For example, the first layer may be used to perform speech recognition, and the second layer may perform a classification task based on the speech recognition performed by the first layer. In this example, input data may be advanced in time by spiking neurons in the first layer, and the classification task may be performed using simple neurons in the second layer. The simple neurons may be neurons known from MLPs and may not take into account time effects.

[0060] According to another embodiment of the multi-core chip architecture, the integrated circuits of the multi-core chip architecture may be controlled by a control circuit. The control circuit may include a timer for synchronizing the integrated circuits. This may allow signals to propagate from a first IC to a second IC without creating a bottleneck. A bottleneck may occur if an NNA in the second tier waits for an input signal while another NNA in the second tier is already receiving the input signal.

[0061] According to another embodiment of the multi-core chip architecture, a first integrated circuit may be clocked at a first time step size, and a first neuromorphic neuronal device of the first integrated circuit may be switched in a first mode. Further, in this embodiment, a second integrated circuit may be clocked at a second time step size, and a first neuromorphic neuronal device of the second integrated circuit may be switched in a second mode, and the second time step size may be an integer multiple of the first time step size. The second time step size being an integer multiple of the first time step size may allow the first IC to be synchronized with the second IC, and therefore may allow signals to propagate from the first IC to the second IC without creating a bottleneck.

[0062] According to another embodiment of a method for calculating an output value of an integrated circuit, the method may further include generating a current input signal using an output current of a first assembly of memory elements, the first assembly of memory elements having input connections. The method may further include applying a corresponding voltage to each input connection to generate a single current in each memory element. The method may further include generating the output current as a sum of the single currents. This embodiment may enable fast calculation of the scalar product of a first vector and a second vector. The memory elements of the first assembly may be RMEs.

[0063] FIG. 1 illustrates an integrated circuit 1 according to an example of the present subject matter. The integrated circuit 1 may be implemented in the form of an analog or digital CMOS circuit. The integrated circuit 1 may include a first neuromorphic neuron device 2. The first neuromorphic neuron device 2 (NNA2) may include an input 3 and an accumulation block 101 including a state variable 5 for performing an inference task based on input data including a time series. The first NNA2 may be switchable between a first mode and a second mode. The accumulation block 101 may be configured to adjust the state variable 5 using a current input signal of the first NNA2 and a decay function indicating the decay behavior of the device. The state variable 5 may depend on one or more input signals previously received by the first NNA2. The first NNA2 may be configured to receive a current input signal via an input 3.

[0064] Furthermore, when the first NNA2 is switched in the first mode, the first NNA2 may be configured to generate the intermediate value 6 as a function of the state variable 5. Furthermore, when the first NNA2 is switched in the second mode, the first NNA2 may be configured to generate the intermediate value 6 as a function of the current input signal, independent of the state variable 5. Furthermore, the first NNA2 may be configured to generate an output value as a function of the intermediate value 6. In one simple example, the first NNA2 may set the output value equal to the intermediate value 6. According to another even simpler example, when the first NNA2 is switched in the first mode, the first NNA2 may set the intermediate value 6 equal to the state variable 5.

[0065] FIG. 6 illustrates a further integrated circuit 10 (IC10) according to an example of the present subject matter. The integrated circuit 10 may be implemented in the form of a CMOS circuit. The CMOS circuit may include digital and / or analog circuits. The integrated circuit 10 may include a first neuromorphic neuron device 12. The first neuromorphic neuron device 12 (NNA 12) may include an input 13 and an accumulation block 401 including a state variable 15 for performing an inference task based on input data including a time series. The first NNA 12 may be switchable between a first mode and a second mode. The accumulation block 401 may be configured to adjust the state variable 15 using a current input signal of the first NNA 12 and a decay function indicating the decay behavior of the device. The state variable 15 may depend on one or more input signals previously received by the first NNA 12. The first NNA 12 may be configured to receive a current input signal via the input 13.

[0066] Furthermore, when the first NNA 12 is switched in the first mode, the first NNA 12 may be configured to generate the intermediate value 16 as a function of the state variable 15. Furthermore, when the first NNA 12 is switched in the second mode, the first NNA 12 may be configured to generate the intermediate value 16 as a function of the current input signal, independent of the state variable 15. Furthermore, the first NNA 12 may be configured to generate an output value 18 of the first NNA 12 as a function of the intermediate value 16. In one simple example, the first NNA 12 may set the output value 18 equal to the intermediate value 16. According to another even simpler example, when the first NNA 12 is switched in the first mode, the first NNA 12 may set the intermediate value 16 equal to the state variable 15.

[0067] The first NNA 2, 12 may be configured to receive a stream of input signals x(tn)...x(t-3), x(t-2), x(t-1), x(t), as shown in FIG. 2. These input signals may constitute a time series. The current input signal may be signal x(t). One or more previously received input signals may be signals x(tn)...x(t-3), x(t-2), x(t-1). Each of the input signals may correspond to a value, for example, a floating-point number. If the first NNA 2, 12 is implemented as an analog circuit, the input signal may be a current. If the first NNA 2, 12 is implemented in the form of a digital circuit, the input signal may be a binary-coded number.

[0068] FIG. 3 illustrates a neural network 30. The neural network 30 may include an input layer 31 including k inputs, e.g., inputs in1, in2, ..., ink. Additionally, the neural network 30 may include a first hidden layer 32 including p neurons, e.g., neurons n11, n12, n13, ..., n1p. Additionally, the neural network 30 may include a second hidden layer 33 including m neurons, e.g., neurons n21, n22, n23, ..., n2m. The first NNA 2, 12 may simulate one of the neurons in the actual layer of the network, and the first NNA 2, 12 may receive the output value of a neuron in a previous layer of the network 30. The previous layer may be the first hidden layer 32. The actual layer may be the second hidden layer 33.

[0069] Neural network 30 may be configured to process input signals of neural network 30, such as input signals in1(t), in2(t), ..., ink(t). For example, each of signals in1(tn)..., in1(t-1), in1(t), in2(tn)..., in2(t-1), in2(t), ink(tn)..., ink(t-1), ink(t) may represent a respective pixel of an image that may be input at each time step tn, ..., t-1, t at a corresponding input in1, in2, ..., ink of neural network 30. Hereinafter, the input signals of neural network 30 will be referred to as input signals of neural network 30, and the input signals of first NNAs 2, 12 will be referred to as input signals.

[0070] The input signals x(tn)...x(t-3), x(t-2), x(t-1), x(t) may be generated by IC1, 10 such that each of these input signals may be equal to the scalar product of a first vector and a second vector, respectively. The entries of the first vector may represent the output value of one of the neurons in a previous layer of the neural network 30, e.g., the first hidden layer 32, e.g., neurons n11, n12, n13...n1p, at each time step tn,..., t-3, t-2, t-1, t. These output values ​​may be floating-point numbers, and at each time step tn, ..., t-3, t-2, t-1, t, the output values ​​of the first neuron n11 in the previous layer are out11(tn)...out11(t-3), out11(t-2), out11(t-1), out11(t), and the output values ​​of the second neuron n12 in the previous layer are out12(tn)...out12(t-3), out12(t-2). ), out12(t-1), out12(t), out13(tn)...out13(t-3), out13(t-2), out13(t-1), out13(t) as the output values ​​of the third neuron n13 in the previous layer, and out1p(tn)...out1p(t-3), out1p(t-2), out1p(t-1), out1p(t) as the output values ​​of the pth neuron n1p in the previous layer.

[0071] The entries of the second vector may represent values ​​of weights, e.g., w11, w12, w13, ..., w1p, respectively, that indicate the strength of the connection between the neuron that the first NNA 2, 12 may simulate and the corresponding neuron of the previous layer, e.g., neuron n11, n12, n13, ..., n1p. Similarly, if the first NNA 2, 12 may simulate neuron n2i of the actual layer, the entries of the second vector may be values ​​of weights wi1, wi2, wi3, ..., wip, respectively.

[0072] In one example, a first NNA2, 12 may simulate a first neuron in an actual layer, e.g., neuron n21, and then may simulate a second neuron in the actual layer, e.g., neuron n22, and so on, simulating an mth neuron in the actual layer, e.g., neuron n2m.

[0073] If the first NNA 2, 12 can simulate the first neuron n21 of the second hidden layer 33, the current input signal may be x(t) = w11 * out11(t) + w12 * out12(t) + w13 * out13(t) + ... + w1p * out1p(t). Thus, one of the previously received input signals x(tn) may be x(tn) = w11 * out11(tn) + w12 * out12(tn) + w13 * out13(tn) + ... + w1p * out1p(tn). Naturally, one of the output values ​​of the previous layer neuron may be equal to 0. This can frequently occur if the previous layer neuron is a spiking neuron.

[0074] According to another example, the first NNA 2, 12 may simulate one of the neurons of the first hidden layer 32, for example, neuron n11. In this case, the current input signal may be x(t) = w011 * in1(t) + w012 * in2(t) + w013 * in3(t) + ... + w01k * ink(t). Thus, one of the previously received input signals x(tn) may be x(tn) = w011 * in1(tn) + w012 * in2(tn) + w013 * in3(tn) + ... + w01k * ink(tn).

[0075] In one example, the first NNA 2 may further comprise an output generation block 103. To generate an output value of the first NNA 2 in accordance with the present subject matter, the first NNA 2 includes state variables 5, hereinafter also referred to as time-dependent state variables s(t), s(t-1), ..., s(tn). The state variable s(t) may represent the membrane potential at time step (t) and may be used to define the output value at that time step. The state variable s(t) may indicate the current activation level of the first NNA 2. An incoming spike in the form of a single product w11 * out11(t), w12 * out12(t), w13 * out13(t), ..., or w1p * out1p(t) may increase this activation level and then decay over time or cause a spike. This may occur regardless of whether the first NNA 2 is switched in the first mode or the second mode. The single product may be generated by the received current or digital value at input 3 .

[0076] For example, for each received input signal x(tn)...x(t-3), x(t-2), x(t-1), x(t), the accumulation block 101 may calculate respective state variables s(tn)...s(t-3), s(t-2), s(t-1), s(t). The output generation block 103 may include an activation function 102 to calculate the output value of the first NNA2 at time step (t), hereinafter also referred to as y(t). When the first NNA2 is switched in the first mode, the calculated s(t) may be provided or output by the accumulation block 101 to the output generation block 103 as an intermediate value 6. According to one embodiment, when the first NNA2 is switched in the second mode, the current input signal x(t) may be passed to the output generation block 103.

[0077] In one embodiment, the first NNA 2 may include a first switchable circuit 106. The first switchable circuit 106 may be configured to run in a first mode or a second mode. When the first switchable circuit is switched in the first mode, the first switchable circuit 106 may be configured to generate the intermediate value 6 as a function of the state variable s(t). Furthermore, when the first switchable circuit is switched in the second mode, the first switchable circuit 106 may be configured to generate the intermediate value 6 as a function of the current input signal x(t), independent of the state variable.

[0078] In one example, when the first switchable circuit 106 is switched in the second mode, the first switchable circuit 106 may be configured to generate an intermediate value 6 as a function of a current input signal x(t) and a parameter value 7 derived from a batch normalization algorithm of a training data set for training the first neuromorphic neuron device.

[0079] When the first NNA2 is switched in the first mode, the output generation block 103 may generate an output value y(t) according to the value of the state variable s(t). When the first NNA2 is switched in the first mode, the output generation block 103 may use an activation function 102 to generate the output value y(t) according to the value of the state variable s(t). The activation function 102 may be a step function, a sigmoid function, or a rectified linear activation function. In one example, the first NNA2 may include an additional input including a constant value b, and thus may be biased, and the constant value b (bias value) may be taken into account. For example, when the first NNA2 is switched in the first mode, the bias value b may be used to determine the output value y(t) as y(t) = h(s(t) + b), where h may be the activation function 102. This may enable improvement of the performance of the first NNA2.

[0080] Thus, when the first NNA2 is switched in the first mode, the first NNA2 may be configured, in accordance with the present subject matter, to provide a state variable s(t) using the accumulation block 101 and to provide an output value y(t) using the output generation block 103 for each received signal x(t) of the streams x(tn)...x(t-3), x(t-2), x(t-1), x(t). The state variable s(t) may be considered as an intermediate value 6 in this example. The intermediate value 6, in this example, the state variable s(t), may be calculated as a function of the current input signal x(t) and the state variable s(t-1). If the value b is equal to 0, the output value y(t) may be equal to the state variable s(t) when the first NNA2 is switched in the first mode.

[0081] In order to calculate the state variable s(t) by the accumulation block 101, an initialization of the first NNA 2 may be performed. This initialization may be performed such that the state variable s(0) and the output variable y(0) may be initialized to respective predefined values ​​before receiving any input signal at the input 3 of the first NNA 2. This may enable an implementation based on feedback from a previous state of the first NNA 2, as follows:

[0082] The accumulation block 101 may be configured to calculate the state variable s(t) by taking into account a previous value of the state variable, e.g., s(t-1), and a previous output value, e.g., y(t-1). The previous value of the state variable and the output value s(t-1) and y(t-1) may be values ​​determined by the first NNA2 for a previously received signal x(t-1), as described herein. For example, the accumulation block 101 may

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[0083] The received signal x(t) may induce a current in the first NNA 2. Depending on the current level, the state variable 5 may decay or decrease depending on the time constant τ of the first NNA 2. This decay may be taken into account by the accumulation block 101, for example, to calculate the adjustment of the state variable 5. To that end, the adjustment of s(t-1) may be

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[0084] According to one embodiment, the accumulation block 101 may include a first decay function block (DFB) 235 to perform the adjustment of the state variable 5, as shown in FIG. 4 . The first DFB 235 may implement a decay function. The first DFB 235 may receive an input signal via input 3 and process the input signal. For example, for each received input signal, the first DFB 235 may sum a corresponding value of the received input signal to the state variable 5. The state variable 5 may be considered as a membrane state variable of the first DFB 235, e.g., a membrane potential variable. In one example, the first DFB 235 may calculate a new value of the state variable s(t) at each new time step as a function of a current input signal x(t) and one or more previously received input signals, such as x(t−1), ..., x(tn).

[0085] The first DFB 235 includes a selection unit 305, an adder 302, a synapse unit 309, an output 310, and a memory 303. The memory 303 may store a certain number n+1 of input signals. For example, the memory 303 may store the last n+1 of input signals. The input signals may be stored in the memory 303 according to the FIFO (first in first out) principle. Therefore, when the current input signal x(t) can be received by the first DFB 235, the first input signal received compared to all input signals, for example, x(tn-1), may be deleted in the memory 303.

[0086] The input signal may pass through the synapse unit 309. The selection unit 305 is denoted as x in the following. iFor each received input signal x(tn)...x(t-3), x(t-2), x(t-1), x(t), called i The selection unit 305 may select a weight value (or modulation term) αi corresponding to the arrival time of each input signal x such that more recently received input signals are assigned weight values ​​having higher values. i may be selected, whereby a decay function may be realized.

[0087] The selection unit selects each input signal x i and the corresponding selected weight value α i The selection unit 305 may perform n+1 multiplications at each time step. The selection unit 305 may output the result of each multiplication. For each new time step, a weight value may be newly assigned to each of the stored input values, and the selection unit 305 may perform n+1 multiplications at each time step.

[0088] Adder 302 adds each multiplication x i *α i may be configured to add the single results of these multiplications to generate a sum of these multiplications. This sum may be equal to the current value of the state variable, which may be s(t).

[0089] The first DFB 235 may further include a comparator 313. The comparator 313 may be configured to determine whether the current value of the state variable 5 is greater than or equal to a threshold value. The threshold value may be received, for example, from a unit (not shown) of the first DFB 235 or may be stored in the comparator 313. The first DFB 235 may be configured to spike if the current value of the state variable 5 is greater than or equal to the threshold value. The first DFB 235 may generate the spike by outputting an output signal at the output 310. If IC1 is implemented in the form of an analog circuit, the output signal may be an electrical impulse. If IC1 is implemented in the form of a digital circuit, the output signal may be a binary value, for example, a "1" or a digital number.

[0090] The first DFB 235 may further include a reset unit 311. The reset unit 311 may be configured to set the current value of the state variable 5 to a reset value when the first DFB 235 spikes. The reset value may be stored in the first DFB 235. For example, the reset value may be equal to 0.

[0091] The first DFB 235 has a weight value α i to the selection unit 305. The weight unit 307 may, for example, provide a weight value α i In one example, the weighting unit 307 may include a look-up table including: i The selection unit 305 may be configured to calculate each time difference for each received input signal. The selection unit 305 may comprise a timer for calculating each time difference.

[0092] The output signal of the first DFB 235 may be an intermediate value 6. In this example, the intermediate value 6 may be generated as a function of the current value of the state variable 5 and passed to the output generation block 103.

[0093] Figure 5 illustrates another exemplary implementation of accumulation block 201 of first NNA 2 in accordance with the present subject matter. Figure 5 illustrates the state of accumulation block 201 after receiving signal x(t).

[0094] The accumulation block 201 includes an adder circuit 204, a multiplication circuit 211, and an activation circuit 212. The multiplication circuit 211 may be, for example, a reset gate. The accumulation block 201 may be configured to output the calculated state variable 5 in parallel to the output generation block 103 and the multiplication logic 211 at a branch point 214. The connection 209 between the branch point 214 and the multiplication logic 211 is shown as a dashed line to indicate that the connection 209 involves a time lag. That is, at time step (t), the first NNA 2 processes the received input signal x(t) to generate corresponding s(t) and y(t), and the connection 209 may transmit the value of the previous state of the state variable 5, i.e., the value of s(t-1).

[0095] According to this example, when the first NNA2 is switched in the first mode, the output generation block 103 may generate an output value y(t) as a function of the state variable s(t). The output generation block 103 may provide or output the output value y(t) of the first NNA2 in parallel to the output of the first NNA2 and to a reset module 207 of the first NNA2 at a branch point 217. The reset module 207 may be configured to generate a reset signal from the received output value and provide the reset signal to the multiplication logic 211. For example, for a particular output value y(t-1), the reset module may generate a reset signal indicating a value 1-y(t-1). In this example, the output value may be a binary value, e.g., "0" or "1." The connection 210 is shown as a dashed line to indicate that the connection 210 involves a time lag. That is, at the time when the first NNA 2 processes the received signal x(t) to generate the corresponding s(t) and y(t), the connection 210 may transmit the previous output value y(t-1). The connections 209 and 210 may enable a feedback function to the first NNA 2. In particular, the connection 209 may be a self-loop connection within the accumulation block, and the connection 210 may activate a gate control connection to perform a state reset.

[0096] Upon receiving the state variable value s(t-1) and the output value y(t-1), the multiplication logic 211

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[0097] Referring again to FIG. 6, the accumulation block 401 includes state variables 15, also referred to hereinafter as time-dependent state variables 15s(t), s(t-1), ..., s(tn). The state variable 15s(t) may represent the membrane potential at time step (t) and may be used to define the output value 18 of the first NNA 12 at that time step (t). The state variable 15s(t) may indicate the current activation level of the first NNA 12. An incoming spike in the form of a single product w11 * out11(t), w12 * out12(t), w13 * out13(t), ..., or w1p * out1p(t) may increase this activation level and then decay over time or cause a spike. According to this example, this may only occur if the first NNA 2 is switched in the first mode. The single product may be generated by the received current or digital value at input 13, depending on whether IC 10 is implemented in analog or digital form.

[0098] For example, for each received input signal x(tn)...x(t-3), x(t-2), x(t-1), x(t), the accumulation block 401 may calculate each state variable 15 s(tn)...s(t-3), s(t-2), s(t-1), s(t). According to this example, the IC 10 may include a first switchable circuit 402. When the first neuromorphic neuron device is switched in a first mode, the first switchable circuit 402 may be configured to generate an intermediate value 16 as a function of the state variable 15 s(t-1) of the previous time step and the current input value x(t). Furthermore, when the first neuromorphic neuron device is switched in a second mode, the first switchable circuit 402 may be configured to generate the intermediate value 16 as a function of the current input signal x(t), independent of the state variable 15.

[0099] According to the example shown in FIG. 6 , the first switchable circuit 402 may comprise a fused multiplication and addition circuit (FMAC) 403. Further, the FMAC 403 may comprise a first input 411, a second input 412, and a third input 413. The FMAC 403 may be configured to calculate an output value (output_FMAC) of the FMAC 403 depending on the value applied to the first input 411 (input_1_FMAC), the value applied to the second input 412 (input_2_FMAC), and the value applied to the third input 413 (input_3_FMAC) according to the equation output_FMAC=input_1_FMAC+input_2_FMAC*input_3_FMAC. Using a fused multiplication and addition circuit is advantageous because such types of circuits are standard circuits and may be manufacturable with very little cost and footprint. Such standard circuits can also be optimized for heat generation, fatigue, and overvoltage generation. This applies to both digital and analog implementations of the FMAC403 on IC10.

[0100] The first switchable circuit 402 may comprise a switch 404 , a first input 421 , a second input 422 , a third input 423 , a fourth input 424 , and a fifth input 425 .

[0101] The first NNA 12 may further include an input conversion circuit 405 configured to change the magnitude of the current input signal x(t) using scaling. This scaling may depend on the range of possible output values ​​of the analog-to-digital converter (ADC) 500 and may be independent of the mode of the first NNA 12, i.e., whether the first NNA 12 is switched in a first mode or a second mode. The input conversion circuit 405 may include a fused multiplication and addition circuit 407 to perform scaling of the current input signal x(t) according to a scaling value 408 that defines the range of the ADC 500. The scaling value may be transmitted from the ADC 500 to the first NNA 12 or may be provided as a fixed value in the memory of the IC 10. The NNA 12 may include a further input conversion circuit 409. The further input conversion circuit 409 may be configured to convert integer values ​​of the current input signal x(t) to floating-point values ​​of the current input signal x(t).

[0102] The first NNA 12 may be configured to send the transformed and resized input signal x(t) to the first input 421 of the first switchable circuit 402, regardless of the mode of the first NNA 12. Thus, the transformed and resized input signal x(t) may be applied to the first input 425.

[0103] In one example, first batch normalization parameters 431 may be applied to the second input 422, and second batch normalization parameters 432 may be applied to the third input 423. IC10 may be configured to send the first batch normalization parameters 431 to the second input 422 and send the second batch normalization parameters 432 to the third input 423. The first and second batch normalization parameters 431, 432 may be obtained from a batch normalization technique using a training data set for training the neural network 30.

[0104] In one example, a damping coefficient 433 (dec_fac) may be applied to the fourth input 424. The damping coefficient 433 may be constant in one example. In another example, the damping coefficient 433 may vary over time. The damping coefficient 433 may vary between time steps as a function of the clock frequency to which the IC 10 is clocked. For example, the damping coefficient may be a correction function

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[0105] In one example, the value of the state variable 15s(t-1) for the previous time step may be applied to the fifth input 425. The IC 10 may be configured to transmit the value of the state variable 15s(t-1) for the previous time step from the first memory element 410 of the first NNA 12 to the fifth input 425.

[0106] The IC 10 may further include a configuration circuit 501. The configuration circuit 501 may be configured to switch the first NNA 12 in the first mode or the second mode.

[0107] In one example, the configuration circuit 501 may be configured to switch the switch 404 in a first mode. When the switch 404 is switched in the first mode, the switch 404 may connect the first input 421 of the switchable circuit 402 to the first input 411 of the FMAC 403, the fourth input 424 of the switchable circuit 402 to the second input 412 of the FMAC 403, and the fifth input 425 of the switchable circuit 402 to the third input 413 of the FMAC 403. Thus, in the first mode of the switch 404, the transformed and scaled input signal x(t) may be applied to the first input 411 of the FMAC 403, the damping coefficient 433 may be applied to the second input 412 of the FMAC 403, and the value of the state variable l5s(t-1) from the previous time step may be applied to the third input 413 of the FMAC 403.

[0108] Thus, when the switch 404 is switched in the first mode, the FMAC 403 may generate an output value of the FMAC 403 according to the equation output_FMAC=x(t)+dec_fac*s(t-1).

[0109] Further, configuration circuit 501 may be configured to switch switch 404 in a second mode. When switch 404 is switched in the second mode, switch 404 may connect the second input 432 of switchable circuit 402 to the first input 411 of FMAC 403, the first input 421 of switchable circuit 402 to the second input 412 of FMAC 403, and the third input 433 of switchable circuit 402 to the third input 413 of FMAC 403. Thus, in the second mode of switch 404, the first batch normalization value 431 (batch1) may be applied to the first input 411 of FMAC 403, the transformed and rescaled input signal x(t) may be applied to the second input 412 of FMAC 403, and the second batch normalization value 432 (batch2) may be applied to the third input 413 of FMAC 403.

[0110] Thus, when switch 404 is switched in the second mode, FMAC 403 may generate an output value of FMAC 403 according to the equation output_FMAC=batch1+x(t)*batch2.

[0111] The output value of FMAC 403 may be the intermediate value 16, regardless of the mode of switch 404.

[0112] In addition, the IC 10 may include an activation unit 450. The activation unit 450 may be configured to apply an activation function such as a sigmoid function, a hyperbolic tangent function, a linear function, or a rectified linear function. A particularly useful low-complexity circuit implementation of the activation unit 450 may be a rectified linear unit. Therefore, the activation unit 450 may be referred to hereinafter as a ReLU 450. The ReLU 450 may be configured to generate a further intermediate value 17 as a function of the intermediate value 16. The ReLU 450 may generate the further intermediate value 17 when the first NNA 12 is switched in the first mode. In another example, the ReLU 450 may generate the further intermediate value 17 regardless of the mode of the first NNA 12. ReLU 450 may generate a further intermediate value 17 such that if intermediate value 16 is greater than or equal to 0, further intermediate value 17 is equal to intermediate value 16(int_val), and if intermediate value 16 is less than 0, further intermediate value 17 is equal to 0.

[0113] In one example, the ReLU 450 may include an additional input including a constant value c, and thus may be biased, and the constant value c (bias value) may be taken into consideration. For example, the bias value c may be used to determine the further intermediate value 17 (furth_int_val), such as furth_int_val=ReLU(int_val+c). This may enable improvement of the performance of the first NNA 12. In one example, the bias value c may be used to determine the further intermediate value 17 (furth_int_val), such as furth_int_val=ReLU(int_val+c), only when the first NNA 12 is switched in the first mode.

[0114] The first NNA 12 may be configured to generate an output value 18 based on the further intermediate value 17. In one example, the first NNA 12 may generate the output value 18 as an integer value using an output conversion circuit 451 of the IC 10. When the first NNA 12 is switched to the second mode, the output conversion circuit 451 may be configured to convert a floating-point number to an integer value.

[0115] Additionally, the first NNA 12 may generate an output value 18 in the form of a spike. The spike may be generated using a comparison circuit 452 of the IC 10. The comparison circuit 452 may be configured to compare the further intermediate value 17 with a threshold value. When the first NNA 12 is switched in the first mode, the comparison circuit may compare the further intermediate value 17 with the threshold value. Furthermore, the comparison circuit 452 may be configured to set the output value 18 equal to 1 if the further intermediate value 17 is greater than the threshold value and to set the output value 18 equal to 0 if the further intermediate value 17 is less than or equal to the threshold value. Thus, the comparison circuit 452 may contribute to the spiking characteristics of the first NNA 12. In fact, when the first NNA 12 is switched in the first mode, the first NNA 12 may be configured to simulate a spiking neuron. Thereby, when the first NNA 12 is switched in the first mode, the output value 18 may be a binary value. This may allow for low power spike based communications when using the first NNA 12 to simulate the network 30.

[0116] The first NNA 12 may output the output value 18 via the output 453 of the first NNA 12 regardless of the mode of the first NNA 12. In another example not shown in Figure 6, the first NNA 12 may output the output value 18 via a first output of the first NNA 12 if the output value 18 is generated using the output conversion circuit 451, and may output the output value 18 via a second output of the first NNA 12 if the output value 18 is generated using the comparison circuit 452.

[0117] IC10 may be configured to transmit further intermediate value 17 from activation unit 450 to register 453. Register 453 may be designed as a storage element of IC10. Register 453 may be configured to store further intermediate value 17 in a first register element 453.1 of register 453.

[0118] IC10 may be configured to transmit the stored contents of one of the register elements of register 453 to a multiplexer 454 of IC10. Multiplexer 454 may be configured to pass a further intermediate value 17, which may be stored in a first register element 453.1, transmitted to a first input 455 of multiplexer 454, and transmitted to the first memory element 410 via an output of multiplexer 454 and an input of the first memory element 410.

[0119] When a steering signal that may be applied to the second input 456 of the multiplexer 454 is equal to zero, the multiplexer 454 may be configured to pass the value from the first input 455 of the multiplexer 454 to the first memory element 410. Additionally, in one example, when there is no signal level applied to the second input 456, the multiplexer 454 may pass this value. When a signal level greater than zero is applied to the second input 456, the multiplexer 454 may output a value equal to zero to the first memory element 410. This may occur when the output value 18 calculated using the comparison circuit 452 is greater than zero.

[0120] Thus, the first feedback loop 457 of the IC 10, together with the multiplexer 454, may function as a reset device for the first memory element 410. The second feedback loop 458 may provide a storage mechanism for storing a further intermediate value 17, in this case the current value of the state variable 15s(t), in the register 453, and for providing the current value of the state variable s(t) to the first memory element 410 at the next time step. The first memory element 410 may be configured to store the current value of the state variable 15s(t), here in the form of the further intermediate value 17, for a period that is the same as the time step size of the first NNA 12. The first NNA 12 may be clocked at the first time step size. The second feedback loop 458 may be executed at each time step.

[0121] The first switchable circuit 402, the register 453, and the first memory element 410 together constitute an accumulation block 401, which may adjust the state variable 15 using a decay function given by the current input signal x(t) and the product dec_fac*s(t-1). Since this product may be added to the current input signal x(t) using the first switchable circuit 402, an accumulation may be performed at each time step when the first NNA 12 is running at the first time step size. Since the first switchable circuit 402 may be used to calculate the output value 18 when the first NNA 12 is switched in the second mode, a portion of the accumulation block 401 may be used to calculate the output value 18 when the first NNA 12 is switched in the second mode. Therefore, the number of circuits may be reduced, particularly when the output value 18 is calculated according to the batch normalization parameters batch1 and batch2.

[0122] The accumulation block 401 may include a register 453, e.g., a memory element such as a first register element 453.1, for storing a state variable 15, e.g., a current value of the state variable 15. The first register element 453.1 may store the current value of the state variable 15s(t) at an actual time step (t) in the form of a further intermediate value 17, as described above, to provide this value at the next time step. The first register element 453.1 may contain a physical quantity that is in a displaced state after a time interval has elapsed following programming of the first register element 453.1. The time interval may be the first time step size. For example, the first register element 453.1 may be a resistive memory element containing a changeable conductance.

[0123] The deviated state of the physical quantity of the first resistor element 453.1 may be approximately equal to the target state of the physical quantity of the first resistor element 453.1. In one example, the deviated state of the physical quantity of the first resistor element 453.1 may deviate from the target state of the physical quantity of the first resistor element 453.1 by less than 10 percent, or in another example, by less than 1 percent.

[0124] The physical quantity of the first resistor element 453.1 may be in a displaced state at the next time step. The target state of the physical quantity of the first resistor element 453.1 may be the current value of the state variable 15s(t) at the actual time step (t).

[0125] The first resistor element 453.1 stores the physical quantity in an initial state.

number

number

[0126] Initial state of physical quantities

number

[0127] The initialization function 200 is target_i The target state of the conductance G of the first resistor element 453.1 of FIG. 12, shown as G init_i The conductance of the first resistor element 453.1 of FIG. 12 is shown as

number

[0128] The processor may be an external processor or the control unit 502. The processor may determine an initial state of the physical quantity of the first register element 453.1 based on a target state of the physical quantity of the first register element 453.1.

number

number

[0129] According to one example, the first NNA 12 may be configured to generate output values ​​18 such that the range of acceptable values ​​for the output values ​​18 is independent of the mode of the first NNA 12. This may be achieved by a disconnection operation of the activation unit 450, which may terminate further increase of the output value 18 if the output value 18 is greater than an upper threshold. Thereby, a first range of output values ​​18 that may refer to possible values ​​of the output value 18 when the first NNA 12 is switched in a first mode may be equal to a second range of output values ​​18 that may refer to possible values ​​of the output value 18 when the first NNA 12 is switched in a second mode.

[0130] 7 shows a crossbar array 700 of memory elements 701. The memory elements 701 may be resistive memory elements (or resistive processing units (RPUs) that may comprise multiple resistive memory elements), sometimes referred to below as memristors 701. The memristors 701 store the weights W of the neural network 30. ij For example, local data storage within IC1, 10 may be provided for weights W. ij 7 is a two-dimensional (2D) diagram of a crossbar array 700 that can perform matrix-vector multiplication as a function of n and a set of conductive row wires 702 1~n The set of conductive column wires 7081, 7082...708 m The column wires 708 may be formed from a set of 1~m Wire 702 1~n 7 as intersections and may be referred to hereinafter as intersections. IC 10 may connect column wire 708 1~m and wire 702 1~n For example, the column wires 708 may be designed so that there is no electrical contact between them. 1~m At the intersection, the row wire 702 1~n may be guided above or below.

[0131] Each voltage v1...v n However, the input connections 7031, 7032...703 of the crossbar 700 n , whereby row wire 702 1~n If it is possible to add ij A single current I flows through ij Within the region of the intersection, the column wires 708 1~m and row wire 702 1~n Memristors 701 may be arranged relative to G. Memristors 701 are shown in FIG. 7 as resistive elements each with their own adjustable / updatable resistive conductance, and G ij where i=1..m and j=1..n. Each resistive conductance G ij are the corresponding weights W of the neural network 30. ij may correspond to.

[0132] Each row wire 708 i is the voltage v1...v n The corresponding input connections 7031, 7032...703 n By adding i1 , 701 i2 ...701 in A single current generated in l i1 , l i2 ...l in For example, as shown in FIG. 7, the column wires 708 i The current I generated by i is Equation I i =v1·G i1 +v2·G i2 +v3·G i2 +...+v n G in The first output current I1 generated by column wire 7081 follows the equation I1=v1 G 11 +v2·G 12 +v3·G 13 +...+v n G1n Therefore, the array 700 applies a voltage v 1~n Calculate matrix vector multiplication by multiplying the row wire inputs defined by v. Thus, a single multiplication v i G ij is a memristor 701 ij Each memristor 701 of array 700 can be connected to a corresponding one of the memristors 701 itself, using the associated row or column wires of array 700. ij The current I 2~m may be referred to as the further output current in the following.

[0133] The crossbar arrangement of Figure 7 may, for example, allow for computing the multiplication of a vector x with a matrix W. ij teeth,

number

[0134] FIG. 7 shows a resistive memory element 701 of IC 10. 11 , 701 12 ...701 1n 1 shows an example of a first assembly 704 having corresponding voltages v1...v2. n Each input connects 7031, 7032...703 nIn addition, each resistive memory element 701 11 , 701 12 ...701 1n A single current I 11 , I 12 ...I 1n Input connections 7031, 7032...703 n , and a first output connection 7051 for outputting a first output current I1. 11 , 701 12 ...701 1n means that the first output current I1 is a single current I 11 , I 12 ...I 1n The memory elements 701 may be connected to each other so that the sum of 11 , 701 12 ...701 1n Such connections between row wires 702 1~n and the first column wire 7081. The value of the first output current I1 may represent the value of a first scalar product for calculating the output value of the neural network 30 using value propagation through the layers of the network 30. The first scalar product may be equal to, for example, x(t) = w11 * out11(t) + w12 * out12(t) + w13 * out13(t) + ... + w1p * out1p(t) or x(t) = w011 * in1(t) + w012 * in2(t) + w013 * in3(t) + ... + w01k * ink(t), or a multiple or fraction of this value. The first NNA2,12 may simulate neuron n21 in the former case and neuron n11 in the latter case. Furthermore, in the former case, the number of row wires n may be equal to p, and in the latter case, the number of row wires n may be equal to k.

[0135] The first output connection 7051 of the first assembly 704 may be coupled to the input 13 of the first NNA 12. The IC 10 may be configured to generate a current input signal x(t) based on the first output current I1. In one example, the first NNA 2, 12 may be configured to process the input signal x(t) as an analog signal. In that case, the first output current I1 may be the current input signal x(t).

[0136] In another example, IC10 may be configured to generate a current input signal x(t) based on the first output current I1 using an analog-to-digital converter 706 (ADC 706). In one example, the first NNA 2, 12 may receive the current input signal x(t) only from the first output connection 7051. This example may refer to an application in which the first NNA 2, 12 may simulate an output neuron of the output layer 34 of the neural network 30. In this example, the other column wires 708 2~m may not be required.

[0137] If IC1, 10 is to be used to simulate a layer of network 30 containing more than one neuron, e.g., first hidden layer 32 or second hidden layer 33, then more than one column wire of crossbar 700 is required. 1~m The number of row wires 702 may be equal to the number m of neurons in that layer that the IC1, 10 may simulate. 1~n The number of row wires n may be equal to the number of neurons n in the previous layer of network 30. If the previous layer is the input layer 31, the number of row wires n may be equal to k. If the previous layer is the first hidden layer 32, the number of row wires n may be equal to p.

[0138] In the following, it is described how the IC 10 may use a first NNA 2, 12 to simulate a layer of the network 30 containing two or more neurons, e.g., the second hidden layer 33. In this case, the first NNA 1, 12 may not only be used to calculate an output value 18 for a single current time step (t), but may also be used to calculate a further output value. In the following, the output value 18 is referred to as the first output value out1(t), and the further output value is referred to as out 2~m For this purpose, the column wires 708 are called (t). 1~m The additional output current I generated by 2~m may be used, and IC1, 10 may include the second memory 707.

[0139] Furthermore, the ADC 706 converts the first output current I1 into a first current input signal x(t) and outputs a further output current I 2~m for each further current input signal x of the first NNA2 2~m (t) to convert the further output current I 2~m further output connections 705 of the crossbar 700. 1~m may be output by

[0140] The second memory 707 stores the current input signal x(t), also referred to as x1(t) in the following, and a further current input signal x(t). 2~m The second memory 707 may be configured to store m memory elements 707 1~m and each memory element 707 i , the current input signals x1(t) and x 2~m One of (t) may be stored.

[0141] IC1, 10 uses the first NNA2 to generate each further current input signal x 2~m (t) based on the further output value out 2~m (t) to generate the corresponding applied voltages v1...v nmay correspond to the output values ​​out11(t), out12(t), . . . , out1p(t) of the neurons in the previous layer, where n=p, as described above.

[0142] In one example, the corresponding applied voltages v1...v n may correspond to the output value of an actual layer neuron at a past time step, e.g., the output value of the second neuron n22 of the second hidden layer 33, which may be referred to as out22(t-1), thereby simulating a cyclic connection of the second hidden layer 33.

[0143] Further output values ​​out 2~m To generate (t), IC1, 10 applies a further current input signal x 2~m (t) to the input 13 of the first NNA 2, 12, and controlling the first NNA 2, 12 to generate a first output value out1(t) based on the first current input signal x1(t), as described above. 2~m Based on (t), a further output value out 2~m In so doing, the control unit 502 of IC1,10 may be configured to generate each of the output connections of the second memory element 707. 1~m , the switch of the second memory element 707 may be continuously controlled so that the second memory element 707 is connected to one of the inputs 13 of the first NNA 2, 12. The value transmitted by the second memory element 707, i.e., the first current input signal x1(t) or the further current input signal x 2~m Upon receipt of any one of (t), the first NNA 2, 12 may calculate a further intermediate value 17.

[0144] When the first NNA 2, 12 is switched in the first mode, the control unit 502 may continuously control the register 453 so that further intermediate values ​​17 can be written to the corresponding register element 453.i, i being the current input signal x i (t) corresponds to the index of (t). Similarly, when the first NNA 2, 12 is switched in the first mode, the control unit 502 may control the register 453 so that the corresponding register element 453.i may be connected to the input 455 of the multiplexer 454. 1~m At each generation of (t), the output value out 1~m (t) may be stored in the third memory 504 of IC1,10.

[0145] 8 shows IC10 including a crossbar array 700, an ADC 706, a second memory 707, a first NNA 12, a third memory 504, a configuration circuit 501, and a control unit 502. The configuration circuit 501 and the control unit 502 may be integrated into a configuration and control circuit 503. IC10 may further include a fourth memory 505 for storing received signals, e.g., output values ​​of neurons in a previous layer of network 30, such as out11(t), out12(t), ..., out1p(t). In addition, IC10 may convert the digital received signals into corresponding voltages v1...v n A digital-to-analog converter 506 may be provided to convert the corresponding voltages v1...v n A pulse width modulation scheme may be applied to adapt the duration of the corresponding voltages v...v to each received signal. n may be applied to each received signal, with the corresponding voltage v...v n In one example, IC 10 has an input communication channel 507 for transmitting received signals from bus system 509 to fourth memory 505, and an output value out 1~m An output communication channel 508 may be provided for transmitting (t) to a bus system 509 .

[0146] FIG. 9 illustrates a further integrated circuit 20 (IC20) in accordance with the present subject matter. The integrated circuit 20 may be implemented in the form of a CMOS circuit comprising digital and / or analog circuits. The integrated circuit 20 may comprise a first neuromorphic neuron device 12, hereinafter also referred to as a first NNA 121. Furthermore, the IC20 may comprise additional components similar to those of the IC10, such as a crossbar array 700, an ADC 706, a second memory 707, a third memory 504, a configuration circuit 501, and a control unit 502. The configuration circuit 501 and the control unit 502 may be integrated into a configuration and control circuit 503. The IC20 may further comprise a fourth memory 505 for storing received signals, e.g., output values ​​of neurons in a previous layer of the network 30, such as out11(t), out12(t), ..., out1p(t). In addition, the IC10 converts the digital received signals into corresponding voltages v1...v n In one example, IC 10 may include an input communication channel 507 for transmitting received signals from a bus system 509 to a fourth memory 505, and an output value out 1~m An output communication channel 508 may be provided for transmitting (t) to a bus system 509 .

[0147] In addition to the first NNA12, IC20 is further NNA12 in the following. 2~m Further neuromorphic neuronal apparatus, also called 12 2...i...m Further, NNA12 2~m may each be designed similarly to the first NNA 121.

[0148] Therefore, further NNA12 2~m may each comprise an input and an accumulation block containing state variables for performing inference tasks based on input data containing time series. 2~m may be switchable between a first mode and a second mode.

[0149] Each additional NNA122~m The accumulation block of each further NNA12 2~m Further current input signal x 2~m (t) and each further NNA12 2~m Each further NNA 12 may be configured to perform the adjustment of the state variables of each accumulation block using a decay function that exhibits the decay behavior of 2~m The state variables of each accumulation block are 2~m The input signal may depend on one or more input signals received before

[0150] Each additional NNA12 2~m Each further NNA12 2~m Each further NNA12 2~m Further current input signal x 2~m (t) may be configured to receive

[0151] Additionally, each additional NNA12 2~m is switched in the first mode, each further NNA 12 2~m is a function of the state variables of each accumulation block, 2~m The method may be configured to generate an intermediate value of

[0152] Additionally, each additional NNA12 2~m is switched in the second mode, each further NNA 12 2~m Each further NNA12 2~m Further current input signal x 2~m As a function of (t), each further NNA12 2~m The method may be configured to generate an intermediate value of

[0153] Additionally, each additional NNA12 2~m Each NNA12 2~m Each further output value out as a function of the intermediate value of 2~m (t) may be configured to generate

[0154] Unlike IC10, IC20 has a memory element 707 of a second memory 707. i From each of the first NNA121 or further NNA12 2~m , whereby the current input signals x1(t) and x 2~m (t) is the corresponding output value out 1~m To generate (t), a first NNA121 and a further NNA12 i The output value out may be processed by each of the 2~m Each of the further NNAs 12(t) generates an output value 18 in the same way as the first NNA 121 generates an output value 18 based on the first input signal x1(t). 2~m Thus, IC20 generates the output values ​​out 1~m In one example, the first NNA 121 and the further NNA 12 2~m The combined number of may be less than the number of column wires in crossbar 700, for example, only half or a quarter of the number of column wires. 1~m Parallel computation of part of (t) may be possible, but the size of IC20 may be reduced.

[0155] Each further output connection 705 i Each of these is connected to a further NNA 12 via an ADC 706 and a second memory 707. 2~m 9, the ADC 706 may be coupled, i.e., electronically coupled, to one of the inputs of the current input signals x1(t) and x 2~m (t) are input to the first NNA 121 and the further NNA 12 without storing these signals in the second memory 707. 2~m , each of which may be directly forwarded to a respective input of one of the

[0156] In the example shown in FIG. 9, the configuration circuit 501 comprises a first NNA 121 and each further NNA 12 2~mmay be configured to simultaneously switch between the first mode and the second mode.

[0157] Both IC10 and IC20 may each be considered a type of core in the multi-core chip architecture 1000 shown in FIG. 10. Architecture 1000 may include a communication bus 1001 and multiple cores 1002 to simulate network 30. In one example, network 30 may include multiple hidden layers, e.g., up to 5, 10, 100, or even hundreds of hidden layers, and network 30 is a deep neural network. Each core of cores 1002 may be used to simulate one hidden layer of network 30.

[0158] Each core of cores 1002 may, in one example, be designed as IC 10. In a further example, each core of cores 1002 may be designed as IC 20. Communication bus 1001 may carry output values ​​out generated by one of cores 1002. 1~m A communication channel may be provided for transmitting (t) to another core of the core 1002.

[0159] In the following, the first core 1002 is used to simulate the propagation of a signal from a previous layer to the actual layer of the network 30. 11 and the second core 1002 12 The transmission of signals between each core 1002 can be described. 11 , 1002 12 is the input voltage v1...v n The current input core signal x_core 1~n (t), and the aforementioned output value out 1~m (t) is the current output core signal out_core 1~m (t) may be included as the output value out 1~m (t) is the output voltage v1...v m where the output voltages v...v m For example, the output voltages v1...vm In another example, the analog signal generation may be performed by applying a pulse width modulation scheme to generate the output voltages v1...v m generating a signal from the signal;

[0160] First Core 1002 11 is the first core 1002 11 via the output channel 508 of the first core 1002 11 The output voltage of v1...v m may be transmitted to the bus 1001. 12 bus 1001 and second core 1002 12 via the input channel 507 of the second core 1002 12 Input voltage v1...v n The first core 1002 in the form of 11 The output voltage of v1...v m In this case, the first core 1002 11 The output voltage of v1...v m The number m of the second core 1002 12 Input voltage v1...v n m may be equal to the number n of nodes, i.e., m=n. However, this may not necessarily be the case for all applications of architecture 1000.

[0161] In one example, the first core 1002 11 The output voltage of v1...v m The number m of the second core 1002 12 Input voltage v1...v n In this case, the number of the second core 1002 may be smaller than the number n, i.e., m≦n. 12 Input voltage V m-n ...v n The value of may be 0. For example, in this case, the input channel 507 may represent a value of 0 as the input voltage v m-n ...v n In this case, the row wire 703 m-n ... n The second core 1002 12 Memristor 701 1~m,(m-n)~nTherefore, crossbar 700 allows for the modification of multiple hidden layers of simulated network 30 without modifying the hardware elements of architecture 1000.

[0162] In one example, a first NNA 12 of at least one of the cores 1002, e.g., the first core 1002 11 of the first NNA12 or further NNA12 2~m Or both are switched in the first mode, and the first NNA 12 of at least one other core of the core 1002, for example, the second core 1002 12 of the first NNA12 or further NNA12 2~m Or both are switched in the second mode. For example, the first core 1002 11 NNA12 1~m may be switched in a second mode to simulate the first hidden layer 32, which includes neurons such as neurons of an MLP network. 12 NNA12 1~m may be switched in the first mode to simulate a second hidden layer 33, which includes spiking neurons. The architecture shown in FIG. 10 may be used, for example, to simulate 16 hidden layers of network 30. For simplicity, only two hidden layers of network 30 are shown in FIG. 3. In one example, a single one of cores 1002 may be configured to simulate two or more hidden layers of network 30.

[0163] The architecture 1000 may include a global processor 1003 for configuring each of the cores 1002. The processor 1003 may be configured to send a corresponding configuration message to each configured core 1002 via the bus 1001. The configuration message may be read by a corresponding configuration and control circuit 503 of each configured core 1002. Upon receipt of each configuration message, each configuration and control circuit 503 may configure the NNA 12 of the corresponding one of the configured cores 1002 according to the contents of the configuration message. 1~m may be switched to either the first mode or the second mode.

[0164] The global processor 1003 may be considered a control circuit. The global processor 1003 may include a timer for synchronizing the cores 1002. In one example, the first core 1002 11 The second core 1002 may be clocked at a first time step size. 12 The clock may be synchronized with a second time step size, and the first time step size is an integer multiple of the second time step size.

[0165] 11 is a flowchart of a method for generating an output value 18 of an IC 10. In step 801, adjustment of state variables 15 may be performed using a current input signal x(t) of a first neuromorphic neuron device 12 and a decay function indicative of the decay behavior of the device 12. In step 802, a current input signal x(t) may be received via input 13. In step 803, an intermediate value 16 may be generated as a function of state variables 15 when the first neuromorphic neuron device 12 is switched in a first mode. In step 804, an output value 18 of the integrated circuit 10 may be generated as a function of intermediate value 16 when the first neuromorphic neuron device 12 is switched in a second mode.

[0166] The method may further include additional steps 805, 806, and 807. In step 805, a current input signal x(t) may be generated using a first output current of the first assembly of memristors 704. In step 806, corresponding voltages v...v n are the input connections 7031, 7032, ... 703 n Each memristor 701 i1 , 701 i2 ,...701 in A single current I 11 , I 12 ,...I 1n In step 807, the first output current I1 may be generated as a single current I 11 , I 12 ,...I 1n may be generated as the sum of

[0167] In one example, each RME701 ij The conductance value of each RME701 ij After programming, each RME 701 may become misaligned, e.g., decayed, after a certain period of time ΔT. ij The conductance deviation state of each of the aforementioned conductance values ​​G ij Each RME701 may be ij The conductance of each RME701 in the damped state may be approximately equal to the target state. ij The conductance value of each RME701 ij The conductance G ij By way of further example, each RME 701 in a damped state may deviate by less than 10 percent from its target state. ij The conductance value of each RME701 ij The conductance G ij may deviate from each target state by less than 1 percent. The particular time period ΔT may depend on when the RME 701 is used.

[0168] RME701 each ij is RME701 ij Each conductance of each initial state G ij_init, and for each initial state G ij_init From RME701 to each shifted state ij Each conductance G ij_init Each initial state of may be calculable by the processor using a respective initialization function. Each initialization function may be, in one example, ij In another example, each initialization function may be different for each RME 701. ij , and may be, for example, the initialization function 200 shown in FIG.

[0169] The initialization function 200 is target_i Each RME701 in Figure 12 is shown as ij The conductance G ij Each goal state of G init_i Each RME701 in Figure 12 is shown as ij The initialization function 200 may map the RME 701, and in particular each RME 701 ij The polynomial may be obtained by experiments performed using

[0170] The processor may be an external processor or may be a global processor 1003. The processor may be a ij The conductance G ij Based on each target state, each RME701 ij Each initial state G ij_init The parameters or coefficients of the initialization function 200 may be stored to calculate

[0171] Each RME701 requires ij A setup method for setting up the RME 701 may include measuring the elapsed time from an initial point in time to an actual point in time at which the conductance is programmed to a calculated initial state of the conductance. Further, the setup method may include comparing the measured elapsed time to a specific period of time ΔT. The specific period of time ΔT may be set to a value that is greater than or equal to the time at which each RME 701 is programmed. ijThe setup method may depend on the time of use, for example, the use of the crossbar array 700 as a whole. The setup method may include releasing the crossbar array 700 for operation when the measured elapsed time is greater than a particular period ΔT.

[0172] For example, the voltage v 1~n are input connections 7031, 7032, ... 703 n Or in other words, when the elapsed time is greater than a certain period ΔT, the voltage v 1~n are input connections 7031, 7032, ... 703 n In one example, the voltage v may be applied only if the elapsed time is greater than a certain period ΔT. 1~n are input connections 7031, 7032, ... 703 n may be added to.

[0173] In most cases, a specific period ΔT is reached after which further decay in conductance over time is observed for each RME701 ij may be chosen to be low compared to the decay of conductance over time immediately after programming to the initial state.

[0174] In one example, G in Figure 13 init_sel Each RME701 shown as ij The conductance of each initial state G ij_init is shown in Figure 13. target_sel Each RME701 shown as ij The conductance G ij , and each RME 701 based on a global initialization function 900. ij At each selected time point ΔT of the operation sel is shown in Figure 13. Each RME 701 ij In one example, each selected point in time of operation of the RME 701 may be equal. ij Each selected point in time of operation of each RME 701 may be different from each other. ijThis may be practical if each respective point in time of operation of can be known in advance.

[0175] For example, the second core 1002 12 may be configured to simulate the second hidden layer 33, and the first core 1002 11 may be configured to simulate a previous layer, e.g., first hidden layer 32. Because a simulation of network 30 may begin with a simulation of first hidden layer 32 and proceed to a simulation of second hidden layer 33, a first point in time of use of a first core may be earlier than a second point in time of use of a second core. Thus, in one example, RME 701 of the second core ij Each of the conductances of ij The first core's RME701 ij Each conductance of ij The RME701 of the first core is ij Each conductance of each initial state G ij_init may be set to

[0176] The conductance of RME 701 is calculated for each initial state, preferably for each RME 701 ij The programming of the conductance may allow for a more accurate calculation of the current input signal of the first NNA 2, 12. This may improve the accuracy of the first NNA 2, 12 when the first NNA 2, 12 is switched in the first mode, since the output value 18 depends on the progression of the state variable 15 over time. ij If the change over time of is lower, the output value 18 may be calculated more accurately. This may also be advantageous when one of the cores 1002 is switched in a first mode and another of the cores 1002 is switched in a second mode. For example, results calculated using a core switched in a first mode may be compared to results calculated using a core switched in a second mode.

[0177] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0178] The present invention may be a system, a method, and / or a computer program product, which may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0179] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not itself be construed as being ephemeral signals such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0180] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof) that may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0181] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object code written in one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0182] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0183] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to create a machine, where the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in the blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in the blocks of the flowcharts and / or block diagrams.

[0184] Computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0185] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or in the reverse order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified function(s) or operation(s), or executes a combination of special-purpose hardware and computer instructions. According to this specification, the following items are also disclosed. [Item 1] an integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an input and an accumulation block including state variables for performing an inference task based on input data including a time series, the first neuromorphic neuron device being switchable between a first mode and a second mode; The accumulation block is configured to perform the adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more previously received input signals of the first neuromorphic neuronal device; The first neuromorphic neuronal device, receiving the current input signal via the input; generating an intermediate value as a function of said state variable when said first neuromorphic neuron device is switched in said first mode; generating said intermediate value as a function of said current input signal and independent of said state variables when said first neuromorphic neuron device is switched in said second mode; and generating an output value as a function of said intermediate value. [Item 2] 2. The integrated circuit of claim 1, comprising: a first assembly of memory elements, the first assembly of memory elements having input connections for applying corresponding voltages to each input connection to generate a single current in each of the memory elements, and at least one output connection for outputting an output current, the memory elements being connected to each other such that the output current is a sum of the single currents, the output connections of the first assembly being coupled to the inputs of the first neuromorphic neuron device, and the integrated circuit being configured to generate the current input signal based on the output currents. [Item 3] further assemblies of memory elements, each of said further assemblies of memory elements connected to said input connection of said first assembly for applying said corresponding voltage to said memory elements of each of said further assemblies to generate a respective further single current in each of said memory elements of each of said further assemblies; Each of the further assemblies a respective further output connection for outputting a respective further output current, the memory elements of each of the further assemblies being connected to each other such that each of the further output currents is a respective sum of each of the further single currents in the memory elements of each assembly, and the integrated circuit generating a respective further current input signal of the first neuromorphic neuron device or a further neuromorphic neuron device of the integrated circuit based on each of the further output currents; and generating, using the first neuromorphic neuron device or the further neuromorphic neuron device, a further output value based on each of the further current input signals, respectively. [Item 4] Item 3. The integrated circuit of item 2, wherein the memory element is a resistive memory element. [Item 5] Item 4. The integrated circuit of item 3, further comprising an analog-to-digital converter and a first memory, wherein the analog-to-digital converter is configured to convert the output current of the first neuromorphic neuron device to the current input signal and to convert the further output current to each of the further current input signals, the first memory is configured to store the current input signal and the further current input signal, and the integrated circuit is configured to generate the further output values ​​based on each of the further current input signals using the first neuromorphic neuron device. [Item 6] the integrated circuit further comprises neuromorphic neuron devices, each of the additional neuromorphic neuron devices comprising an input and an accumulation block including state variables for performing the inference task based on the input data including the time series, each additional neuromorphic neuron device being switchable between a first mode and a second mode, each of the additional output connections of the additional assembly being coupled to one of the inputs of the additional neuromorphic neuron devices; the accumulation block of each of said further neuromorphic neuronal devices configured to perform adjustment of the state variables of each of the accumulation blocks using the further current input signals of each of the further neuromorphic neuron devices and a decay function indicative of a decay behavior of each of the further neuromorphic neuron devices, wherein the state variables of each of the accumulation blocks depend on one or more input signals received before each of the further neuromorphic neuron devices; each said further neuromorphic neuronal device: receiving the further current input signal of each of the further neuromorphic neuronal devices via the input of each of the further neuromorphic neuronal devices; generating an intermediate value of each of said further neuromorphic neuron devices as a function of said state variables of said each accumulation block when said further neuromorphic neuron devices are switched in a first mode; generating the intermediate value of each of the additional neuromorphic neuron devices as a function of the additional current input signal of each of the additional neuromorphic neuron devices, independent of the state variables of each of the accumulation blocks, when each of the additional neuromorphic neuron devices is switched in the second mode; and generating each said further output value as a function of the intermediate value of each neuromorphic neuron device. [Item 7] Item 4. The integrated circuit of item 3, wherein the memory elements of the first assembly and the memory elements of the further assembly are arranged in rows and columns, each representing an entry of a matrix, each entry of the matrix representing a weight of a connection between two neurons of an artificial neural network. [Item 8] 3. The integrated circuit of claim 2, wherein the integrated circuit further comprises an analog-to-digital converter, wherein the output connection of the first assembly of memory elements is coupled to the input of the first neuromorphic neuron device via the analog-to-digital converter, the output connection of the first assembly is coupled to the input connection of the analog-to-digital converter, and the output connection of the analog-to-digital converter is coupled to the input of the first neuromorphic neuron device, the analog-to-digital converter configured to convert the output current into the current input signal, and the current input signal is a digital signal. [Item 9] the integrated circuit further comprising a first switchable circuit, the first switchable circuit running in a first mode or a second mode, generating the intermediate value as a function of the state variable when the first switchable circuit is switched in the first mode; Item 1. The integrated circuit of item 1, configured to generate the intermediate value as a function of the current input signal and independently of the state variable when the first switchable circuit is switched in the second mode. [Item 10] 10. The integrated circuit of claim 9, wherein the first switchable circuit is configured to generate the intermediate value as a function of the current input signal and a parameter value derived from a batch normalization algorithm of a training data set for training the first neuromorphic neuron device when the first switchable circuit is switched in the second mode. [Item 11] 10. The integrated circuit of claim 9, wherein the integrated circuit further comprises a second switchable circuit and a configuration circuit, the second switchable circuit configured to execute in a first mode or a second mode, generate the output value according to a first activation function based on the intermediate value when the second switchable circuit is switched in the first mode, and generate the output value according to a second activation function based on the intermediate value when the second switchable circuit is switched in the second mode, and the configuration circuit configured to switch the first switchable circuit and the second switchable circuit between the first mode and the second mode. [Item 12] Item 7. The integrated circuit of item 6, further comprising configuration circuitry configured to simultaneously switch the first neuromorphic neuronal device and each of the additional neuromorphic neuronal devices to the first mode or the second mode. [Item 13] Item 7. The integrated circuit of item 6, further comprising a rectifying linear unit configured to generate a further intermediate value as a function of the intermediate value, regardless of whether the first neuromorphic neuronal device is switched in the first mode or whether the first neuromorphic neuronal device is switched in the second mode, and the first neuromorphic neuronal device configured to generate the output value based on the further intermediate value. [Item 14] Item 14. The integrated circuit of item 13, further comprising a comparison circuit, wherein when the first neuromorphic neuron device is switched in the first mode, the comparison circuit is configured to compare the further intermediate value with a threshold value, and the first neuromorphic neuron device is configured to set the output value equal to 1 if the further intermediate value is greater than the threshold value, and to set the output value equal to 0 if the further intermediate value is less than or equal to the threshold value. [Item 15] Item 6. The integrated circuit of item 5, further comprising an input conversion circuit configured to modify the magnitude of the current input signal using scaling, the scaling being dependent on the range of output values ​​of the analog-to-digital converter and independent of the mode of the first neuromorphic neuron device. [Item 16] Item 16. The integrated circuit of any one of items 1 to 15, wherein the first neuromorphic neuronal device is configured to generate the output value such that a range of acceptable values ​​for the output value is independent of the mode of the first neuromorphic neuronal device. [Item 17] 17. The integrated circuit of any one of claims 1 to 16, further comprising an accumulation block comprising a memory element, the memory element comprising a modifiable physical quantity for storing the state variable, the physical quantity being in a displaced state, the memory element being configured for setting the physical quantity to an initial state, the memory element comprising a displacement of the physical quantity from the initial state to the displaced state, the initial state of the physical quantity being computable using an initialization function, the initialization function being dependent on a target state of the physical quantity, the target state of the physical quantity being approximately equal to the displaced state of the physical quantity and dependent on the state variable. [Item 18] 3. The integrated circuit of claim 2, wherein each resistive memory element includes a respective alterable conductance, the each alterable conductance being a respective shifted state, the each resistive memory element is configured to set the each alterable conductance to a respective initial state, the each resistive memory element includes a respective shift of the each alterable conductance from the respective initial state to the respective shifted state, the each initial state of the each alterable conductance is calculable using a respective initialization function, the each initialization function is dependent on a respective target state of the each alterable conductance, and the each target state of the each alterable conductance is approximately equal to the respective shifted state of the each alterable conductance. [Item 19] A multi-core chip architecture, the multi-core chip architecture comprising integrated circuits as cores, each integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an input and an accumulation block including state variables for performing an inference task based on input data including a time series, the first neuromorphic neuron device being switchable between a first mode and a second mode; the accumulation block is configured to perform the adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more input signals previously received by the first neuromorphic neuronal device; said first neuromorphic neuron device receiving said current input signal via said input; generating an intermediate value as a function of said state variable when said first neuromorphic neuron device is switched in said first mode; generating said intermediate value as a function of said current input signal and independent of said state variables when said first neuromorphic neuron device is switched in said second mode; generating an output value as a function of the intermediate value; and [Item 20] 20. The multi-core chip architecture of claim 19, wherein each integrated circuit further comprises a respective first assembly of memory elements, each first assembly of memory elements having input connections for applying a corresponding voltage to each input connection to generate a single current in each of the memory elements, and at least one output connection for outputting a corresponding output current of each of the first assemblies, wherein the memory elements are connected to each other such that the corresponding output currents are the sum of the single currents, and the output connections of each of the first assemblies are coupled to the inputs of the first neuromorphic neuron devices of each of the integrated circuits, each integrated circuit being configured to generate the current input signal for the first neuromorphic neuron device of each of the integrated circuits based on the corresponding output currents, and wherein at least two of the integrated circuits are connected to each other to simulate a neural network comprising at least two hidden layers. [Item 21] 21. The multi-core chip architecture of claim 19 or 20, wherein the first neuromorphic neuronal device of at least one of the integrated circuits is switched in the first mode and the first neuromorphic neuronal device of at least one other integrated circuit is switched in a second mode. [Item 22] 22. The multi-core chip architecture of any one of claims 19 to 21, wherein the integrated circuits are controlled by a control circuit, the control circuit comprising a timer for synchronizing the integrated circuits. [Item 23] 23. The multi-core chip architecture of any one of claims 19 to 22, wherein a first one of the integrated circuits is clocked with a first time step size and the first neuromorphic neuron device of the first integrated circuit is switched in the first mode, a second one of the integrated circuits is clocked with a second time step size and the first neuromorphic neuron device of the second integrated circuit is switched in the second mode, and the second time step size is an integer multiple of the first time step size. [Item 24] 1. A method for generating an output value of an integrated circuit, the integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an input and an accumulation block including state variables for performing an inference task based on input data including a time series, the first neuromorphic neuron device being switchable between a first mode and a second mode, the method comprising: performing adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more previously received input signals of the first neuromorphic neuronal device; receiving the current input signal via the input; generating an intermediate value as a function of the state variable when said first neuromorphic neuron device is switched in said first mode, or generating said intermediate value as a function of said current input signal, independent of said state variable, when said first neuromorphic neuron device is switched in said second mode; generating the output value of the integrated circuit as a function of the intermediate value. [Item 25] The above method is generating the current input signal using an output current of a first assembly of memory elements, the first assembly of memory elements comprising an input connection; applying a corresponding voltage to each of said input connections to generate a single current in each of said memory elements; and generating the output current as the sum of the single currents. [Item 26] A computer program comprising computer readable program code, the computer readable program code comprising: 1. A method for generating an output value from an integrated circuit, the integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an input and an accumulation block including state variables for performing an inference task based on input data including a time series, the first neuromorphic neuron device being switchable between a first mode and a second mode, the method comprising: performing adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more previously received input signals of the first neuromorphic neuronal device; receiving the current input signal via the input; generating an intermediate value as a function of the state variable when said first neuromorphic neuron device is switched in said first mode, or generating said intermediate value as a function of said current input signal, independent of said state variable, when said first neuromorphic neuron device is switched in said second mode; generating the output value of the integrated circuit as a function of the intermediate value.

Claims

1. an integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an input, an accumulation block containing state variables for performing an inference task based on the input data comprising a time series, and a first assembly of memory elements in a crossbar arrangement, the first neuromorphic neuron device being switchable between a first mode and a second mode; The accumulation block is configured to perform the adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more input signals previously received by the first neuromorphic neuronal device; said first neuromorphic neuronal device comprising: receiving the current input signal via the input; generating an intermediate value as a function of the state variable in response to the first neuromorphic neuron device being in the first mode; generating the intermediate value in response to the first neuromorphic neuron device being in the second mode as a function of the current input signal, independent of the state variables; and generating an output value according to a function of said intermediate value.

2. 2. The integrated circuit of claim 1, wherein the memory elements are connected to each other such that the first assembly of memory elements comprises input connections for applying corresponding voltages to each input connection to generate a single current in each of the memory elements and at least one output connection for outputting an output current, the output current being a sum of the single currents, the output connections of the first assembly being coupled to the inputs of the first neuromorphic neuron device, and the integrated circuit is configured to generate the current input signal based on the output currents.

3. the first neuromorphic neuron device further comprising additional assemblies of memory elements, the additional assemblies of memory elements each connected to the input connection of the first assembly to apply the corresponding voltage to the memory elements of each of the additional assemblies to generate a respective additional single current in each of the memory elements of each of the additional assemblies; Each of the further assemblies a respective further output connection for outputting a respective further output current, the memory elements of each of the further assemblies being connected to each other such that each of the further output currents is a respective sum of each of the further single currents in the memory elements of each assembly, and the integrated circuit generating a respective further current input signal of the first neuromorphic neuron device or a further neuromorphic neuron device of the integrated circuit based on each of the further output currents; and generating, using the first neuromorphic neuron device or the further neuromorphic neuron device, a further output value based on each of the further current input signals, respectively.

4. The integrated circuit of claim 2 wherein the memory elements are resistive memory elements.

5. 4. The integrated circuit of claim 3, wherein the first neuromorphic neuronal device further comprises an analog-to-digital converter and a first memory, the analog-to-digital converter configured to convert the output current of the first neuromorphic neuronal device to the current input signal and the further output current to each of the further current input signals, the first memory configured to store the current input signal and the further current input signal, and the integrated circuit configured to generate, using the first neuromorphic neuronal device, the further output values ​​based on each of the further current input signals.

6. the integrated circuit further comprises neuromorphic neuron devices, each of the additional neuromorphic neuron devices comprising an input and an accumulation block including state variables for performing the inference task based on the input data including the time series, each additional neuromorphic neuron device being switchable between a first mode and a second mode, each of the additional output connections of the additional assembly being coupled to one of the inputs of the additional neuromorphic neuron devices; the accumulation block of each of said further neuromorphic neuronal devices configured to perform adjustment of the state variables of each of the accumulation blocks using the further current input signals of each of the further neuromorphic neuron devices and a decay function indicative of a decay behavior of each of the further neuromorphic neuron devices, wherein the state variables of each of the accumulation blocks depend on one or more input signals received before each of the further neuromorphic neuron devices; each said further neuromorphic neuronal device: receiving the further current input signal of each of the further neuromorphic neuronal devices via the input of each of the further neuromorphic neuronal devices; generating an intermediate value of each of said further neuromorphic neuron devices as a function of said state variables of said respective accumulation blocks in response to said each further neuromorphic neuron device being in a first mode; generating the intermediate value of each of the further neuromorphic neuron devices in response to each of the further neuromorphic neuron devices being in the second mode as a function of the further current input signal of each of the further neuromorphic neuron devices, independent of the state variable of each of the accumulation blocks; and generating each said further output value as a function of the intermediate value of each neuromorphic neuron device.

7. 4. An integrated circuit according to claim 3, wherein the memory elements of the first assembly and the memory elements of the further assembly are arranged in rows and columns, the memory elements each representing an entry of a matrix, the entries of the matrix representing each weight of a connection between two neurons of an artificial neural network.

8. 3. The integrated circuit of claim 2, wherein the first neuromorphic neuronal device further comprises an analog-to-digital converter, wherein the output connection of the first assembly of memory elements is coupled to the input of the first neuromorphic neuronal device via the analog-to-digital converter, the output connection of the first assembly is coupled to the input connection of the analog-to-digital converter, and the output connection of the analog-to-digital converter is coupled to the input of the first neuromorphic neuronal device, and the analog-to-digital converter is configured to convert the output current into the current input signal, and the current input signal is a digital signal.

9. the first neuromorphic neuron device further comprises a first switchable circuit, the first switchable circuit being configured to execute in a first mode or a second mode, and generating the intermediate value as a function of the state variable in response to the first switchable circuit being in the first mode; 2. The integrated circuit of claim 1, configured to generate the intermediate value in response to the first switchable circuit being in the second mode in a function of the current input signal and independent of the state variable.

10. 10. The integrated circuit of claim 9, wherein the first switchable circuit is configured, in response to the first switchable circuit being in the second mode, to generate the intermediate value by a function of the current input signal and parameter values ​​derived from a batch normalization algorithm of a training data set for training the first neuromorphic neuron device.

11. 10. The integrated circuit of claim 9, wherein the first neuromorphic neuron device further comprises a second switchable circuit and a configuration circuit, the second switchable circuit configured to run in a first mode or a second mode, to generate the output value according to a first activation function based on the intermediate value depending on whether the second switchable circuit is in the first mode, and to generate the output value according to a second activation function based on the intermediate value depending on whether the second switchable circuit is in the second mode, and the configuration circuit configured to switch the first switchable circuit and the second switchable circuit between the first mode and the second mode.

12. 7. The integrated circuit of claim 6, wherein the first neuromorphic neuronal device further comprises configuration circuitry, the configuration circuitry configured to simultaneously switch the first neuromorphic neuronal device and each of the additional neuromorphic neuronal devices into the first mode or the second mode.

13. 7. The integrated circuit of claim 6, wherein the first neuromorphic neuronal device further comprises a rectifying linear unit, the rectifying linear unit configured to generate a further intermediate value according to a function of the intermediate value, regardless of whether the first neuromorphic neuronal device is in the first mode or whether the first neuromorphic neuronal device is in the second mode, and the first neuromorphic neuronal device generates the output value based on the further intermediate value.

14. 14. The integrated circuit of claim 13, wherein the first neuromorphic neuron device further comprises a comparison circuit, wherein, in response to the first neuromorphic neuron device being in the first mode, the comparison circuit is configured to compare the further intermediate value with a threshold, and wherein the first neuromorphic neuron device sets the output value equal to 1 if the further intermediate value is greater than the threshold, and sets the output value equal to 0 if the further intermediate value is less than or equal to the threshold.

15. 6. The integrated circuit of claim 5, wherein the first neuromorphic neuron device further comprises an input transformation circuit, the input transformation circuit modifies the magnitude of the current input signal using scaling, the scaling being dependent on a range of output values ​​of the analog-to-digital converter and being independent of a mode of the first neuromorphic neuron device.

16. 16. The integrated circuit of claim 1, wherein the first neuromorphic neuronal device is configured to generate output values ​​such that a range of allowable values ​​for the output values ​​is independent of a mode of the first neuromorphic neuronal device.

17. 17. The integrated circuit of claim 1, further comprising an accumulation block comprising a memory element, the memory element comprising a modifiable physical quantity for storing the state variable, the physical quantity being a displaced state, the memory element being configured for setting the physical quantity to an initial state, the memory element comprising a displacement of the physical quantity from the initial state to the displaced state, the initial state of the physical quantity being computable using an initialization function, the initialization function being dependent on a target state of the physical quantity, the target state of the physical quantity being equal to the displaced state of the physical quantity and dependent on the state variable.

18. 3. The integrated circuit of claim 2, wherein each resistive memory element comprises a respective alterable conductance, the respective alterable conductances being in respective offset states, the respective resistive memory elements being configured to set the respective alterable conductances to respective initial states, the respective resistive memory elements comprising respective offsets of the respective alterable conductances from the respective initial states to the respective offset states, the respective initial states of the respective alterable conductances being computable using respective initialization functions, the respective initialization functions being dependent on respective target states of the respective alterable conductances, the respective target states of the respective alterable conductances being equal to the respective offset states of the respective alterable conductances.

19. A multi-core chip architecture, the multi-core chip architecture comprising integrated circuits as cores, each integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an accumulation block including state variables for performing an inference task based on inputs and input data including time series, and a respective first assembly of memory elements in a crossbar arrangement, the first neuromorphic neuron device being switchable between a first mode and a second mode; the accumulation block is configured to perform the adjustment of the state variables using a current input signal of the first neuromorphic neuron device and a decay function indicative of a decay behavior of the first neuromorphic neuron device, the state variables being dependent on one or more input signals previously received by the first neuromorphic neuron device; the first neuromorphic neuron device receiving the current input signal via the input; generating an intermediate value as a function of the state variable in response to the first neuromorphic neuron device being in the first mode; generating the intermediate value in response to the first neuromorphic neuron device being in the second mode as a function of the current input signal, independent of the state variables; and generating an output value as a function of said intermediate value.

20. 20. The multi-core chip architecture of claim 19, wherein each first assembly of memory elements comprises an input connection for applying a corresponding voltage to each input connection to generate a single current in each of the memory elements, and at least one output connection for outputting a corresponding output current of each of the first assemblies, the corresponding output currents being the sum of the single currents, the output connections of each of the first assemblies being coupled to the inputs of the first neuromorphic neuron devices of each of the integrated circuits, each integrated circuit being configured to generate the current input signal for the first neuromorphic neuron device of each of the integrated circuits based on each of the corresponding output currents, and at least two of the integrated circuits are connected to each other to simulate a neural network comprising at least two hidden layers.

21. 21. The multi-core chip architecture of claim 19 or 20, wherein the first neuromorphic neuronal device of at least one of the integrated circuits is in the first mode and the first neuromorphic neuronal device of at least one other integrated circuit is in a second mode.

22. 22. The multi-core chip architecture of any one of claims 19 to 21, wherein the integrated circuits are controlled by a control circuit, the control circuit comprising a timer for synchronizing the integrated circuits.

23. 23. The multicore chip architecture of claim 19, wherein a first one of the integrated circuits is clocked at a first time step size and the first neuromorphic neuron device of the first integrated circuit is in the first mode, and a second one of the integrated circuits is clocked at a second time step size and the first neuromorphic neuron device of the second integrated circuit is in the second mode, the second time step size being an integer multiple of the first time step size.

24. 1. A method for generating an output value of an integrated circuit, the integrated circuit comprising: a first neuromorphic neuron device; the first neuromorphic neuron device comprising: an accumulation block including inputs and state variables for performing an inference task based on input data including a time series; and a first assembly of memory elements in a crossbar arrangement; the first neuromorphic neuron device being switchable between a first mode and a second mode; the method comprising: performing an adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more input signals previously received by the first neuromorphic neuronal device; receiving the current input signal via the input; generating an intermediate value as a function of the state variable in response to the first neuromorphic neuron device being in the first mode, or generating the intermediate value as a function of the current input signal, independent of the state variable, in response to the first neuromorphic neuron device being in the second mode; generating the output value of the integrated circuit as a function of the intermediate value.

25. The method comprises: generating the current input signal using an output current of a first assembly of memory elements, the first assembly of memory elements comprising an input connection; applying a corresponding voltage to each of said input connections to generate a single current in each of said memory elements; 25. The method of claim 24, further comprising: generating the output current as the sum of the single currents.

26. A computer program comprising computer readable program code, said computer readable program code comprising: and a computer readable program code configured to generate an output value for an integrated circuit, the integrated circuit comprising a first neuromorphic neuron device, the first neuromorphic neuron device comprising an accumulation block including inputs and state variables for performing an inference task based on input data including a time series, and a first assembly of memory elements in a crossbar arrangement, the first neuromorphic neuron device being switchable between a first mode and a second mode, the computer readable program code comprising: performing an adjustment of the state variables using a current input signal of the first neuromorphic neuronal device and a decay function indicative of a decay behavior of the first neuromorphic neuronal device, the state variables being dependent on one or more input signals previously received by the first neuromorphic neuronal device; receiving the current input signal via the input; generating an intermediate value as a function of the state variable in response to the first neuromorphic neuron device being in the first mode, or generating the intermediate value as a function of the current input signal, independent of the state variable, in response to the first neuromorphic neuron device being in the second mode; generating the output value of the integrated circuit as a function of the intermediate value; A computer program containing instructions to perform the following:

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