Optimizing Reconfigurable Hardware Using Data Sampling

Abstract

1. A computing device comprising: a processing circuit configured to calculate a result of executing a set of computer instructions including a set of data variables, the calculation including: identifying an initial state of the processing circuit; executing an expected set of computer instructions generated based on the set of computer instructions and an estimated data value, the estimated data value being a value of one of the set of data variables expected to be calculated by executing the set of computer instructions and calculated using at least one program data value; and upon identification of a prediction failure during execution of the expected set of computer instructions in which the data variable does not equal the estimated data value, restoring the initial state of the processing circuit; and executing an alternative set of computer instructions generated based on the set of computer instructions and the at least one estimated data value.

Description

[Technical Field]

[0001] Related Applications This application claims the benefit of priority to U.S. Patent Application No. 17 / 145,490, filed January 11, 2021, which is incorporated herein by reference in its entirety. [Background technology]

[0002] Some embodiments described in this disclosure relate to executing computer instructions, and more particularly, but not exclusively, to improving the performance of processing circuits that execute sets of computer instructions.

[0003] As used herein, the term "processing device" refers to any type of programmable or non-programmable circuitry configured to perform a sequence of operations. A processing device may include hardware as well as software. For example, a processing device may include one or more processors and temporary or non-temporary memory that holds programs that, when executed by the one or more processors, cause the processing device to perform respective operations.

[0004] The demand for high-performance processing units is increasing. Two common metrics used to measure the performance of a processing unit are latency and throughput. Latency refers to the time it takes a processing unit to perform an identified operation. Examples of an identified operation include sending a data packet from a source to a destination and executing a specific set of computer instructions in response to input values. Throughput refers to the amount of a specific operation a processing unit performs in a given period of time, such as the amount of data packets sent in that period. Another example of a system's throughput is the amount of input values ​​that a processing unit executes a specific set of computer instructions in that period of time.

[0005] For the sake of brevity, hereinafter, unless otherwise specified, the term "instructions" will mean "computer instructions" and the terms will be used interchangeably, and the term "pipeline" will mean "instruction pipeline" and the terms will be used interchangeably.

[0006] There are various methods for improving the performance of a processing unit. Some methods increase throughput, while others reduce latency. There are also methods that achieve both increased throughput and reduced latency, but there is usually a trade-off between these two metrics.

[0007] Another way to improve the performance of a processor is to use instruction pipelining to introduce a degree of parallelism into the processor. In a processor that implements instruction pipelining, instructions are divided into sequential steps that are executed in parallel, with each step being performed by a part of the processor.

[0008] In some existing processing architectures, computer instruction sets are implicitly sequential, i.e., after execution of one computer instruction in a computer instruction set, the processing unit, by default, executes the next consecutive computer instruction. Control flow instructions are computer instructions that control the order in which a computer instruction set is executed. Control flow instructions instruct the processing unit, after executing one computer instruction, to execute another computer instruction that is not consecutive. Examples include jump instructions, conditional branch instructions, and function call instructions. For simplicity, the term "branch instruction" will be used hereinafter to refer to a control flow instruction, which may be conditional or non-conditional.

[0009] In some existing processing architectures, when a processing unit executes a set of computer instructions, data values ​​are communicated between the computer instructions using explicit storage. The storage may be a memory area. The storage may be a register of the processing unit. Executing a set of computer instructions by a processing unit that implements an instruction pipeline requires care to ensure that each computer instruction operates on one or more data values ​​that are consistent with completing the execution of all previous instructions. If an instruction set does not include branch instructions, the order in which the instruction set is executed is predictable. However, if an instruction set includes branch instructions, the order in which the instruction set is executed may depend on one or more data values ​​calculated during the execution of the instruction set. Thus, if an instruction set includes one or more branch instructions, the order in which the instruction set is executed may not be completely predictable. Summary of the Invention [Means for solving the problem]

[0010] In some embodiments described in the present disclosure, computing the set of computer instructions includes executing a predicted set of computer instructions generated based on one or more likely data values ​​of one or more data variables of the set of computer instructions, and, if at least one data variable is not equal to the respective likely data value, restoring the processing circuitry to an initial state and executing an alternative set of computer instructions.

[0011] These and other objects are achieved by the features of the independent claims. Further embodiments are evident from the dependent claims, the description and the drawings.

[0012] According to a first aspect of the present invention, a computing device includes at least one processing circuit configured to calculate a result of executing a set of computer instructions including a set of data variables, said calculation including: identifying an initial state of at least one processing circuit; identifying at least one estimated data value; said at least one estimated data value being at least one value of at least one set of data variables predicted by executing said set of computer instructions, said at least one estimated data value being at least one value of at least one set of data variables calculated using one or more program data values ​​of said set of computer instructions; causing said at least one processing circuit to execute at least a portion of an expected set of computer instructions generated according to an estimated order of execution of said set of computer instructions, such that said expected set of computer instructions is not limited by an amount of branch instructions; and detecting a failed prediction during execution of at least a portion of said expected set of computer instructions when said at least one data variable is not equal to said at least one estimated data value according to at least one data variable test. and upon identifying a predicted execution order of the set of computer instructions, restoring an initial state of the at least one processing circuit and executing one of at least one alternative set of computer instructions generated based on the set of computer instructions and the at least one estimated data value. Executing at least a portion of the predicted set of computer instructions generated based on the at least one estimated data value predicted to be calculated by executing the set of computer instructions increases the likelihood of correctly predicting the execution order of the predicted set of computer instructions, thereby improving performance of the at least one processing circuit by reducing the number of times its execution pipeline needs to be flushed. Calculating the at least one estimated data value using one or more program data values ​​of the set of computer instructions improves the accuracy of the one or more estimated data values, further increasing the likelihood of correctly predicting the execution order of the predicted set of computer instructions.

[0013] According to a second aspect of the present invention, a method for computing comprises: identifying an initial state of at least one processing circuit; identifying at least one estimated data value, the at least one estimated data value being at least one value of at least one set of data variables expected to be computed by executing the set of computer instructions, the at least one estimated data value being computed using one or more program data values ​​of the set of computer instructions; executing at least a portion of an expected set of computer instructions generated according to an estimated order of execution of the set of computer instructions predicted based on the set of computer instructions and the at least one estimated data value, such that the expected set of computer instructions is not limited by an amount of branch instructions; and upon identifying a failure of the prediction, such that the at least one data variable is not equal to the at least one estimated data value according to at least one data variable test, during execution of the at least part of the expected set of computer instructions, restoring an initial state of the at least one processing circuit and configuring the at least one processing circuit to execute one of the set of computer instructions and at least one alternative set of computer instructions generated based on the at least one estimated data value.

[0014] According to a third aspect of the present invention, a computing device includes at least one hardware processor adapted to: identify at least one estimated data value expected to be calculated by executing the set of computer instructions, the at least one estimated data value being at least one value of at least one set of data variables calculated using one or more program data values ​​of the set of computer instructions; identify an initial state of at least one processing circuit; generate an expected set of computer instructions and at least one alternative set of computer instructions generated according to an expected order of execution of the set of computer instructions predicted based on the set of computer instructions and the at least one estimated data value such that the expected set of computer instructions is not limited by an amount of branch instructions; execute at least a portion of the expected set of computer instructions; and upon identifying a failure of the prediction, in which the at least one data variable is not equal to the at least one estimated data value according to at least one data variable test, during execution of at least a portion of the expected set of computer instructions, restore an initial state of the at least one processing circuit; and configure the at least one processing circuit to execute the set of computer instructions by executing one of the at least one alternative set of computer instructions. Generating a predicted set of computer instructions based on one or more estimated data values ​​reduces the likelihood of identifying a misprediction when executing the predicted set of computer instructions, thereby reducing the number of times the pipeline of the at least one processing circuit needs to be flushed. Calculating the one or more estimated data values ​​using one or more program data values ​​of the set of computer instructions improves the accuracy of the one or more estimated data values, further reducing the likelihood of identifying a misprediction when executing the predicted set of computer instructions.

[0015] According to a fourth aspect of the present invention, a computing method includes: identifying at least one estimated data value that is expected to be calculated by executing the set of computer instructions, the at least one estimated data value being at least one value of at least one set of data variables calculated using one or more program data values ​​of the set of computer instructions; identifying an initial state of at least one processing circuit; generating an expected set of computer instructions and at least one alternative set of computer instructions generated according to an expected order of execution of the set of computer instructions, predicted based on the set of computer instructions and the at least one estimated data value, such that the expected set of computer instructions is not limited by an amount of branch instructions; executing at least a portion of the expected set of computer instructions; and upon identifying a prediction failure during execution of at least a portion of the expected set of computer instructions, that is, the at least one data variable is not equal to the at least one estimated data value according to at least one data variable test, restoring the initial state of the at least one processing circuit and configuring the at least one processing circuit to execute the set of computer instructions by executing one of the at least one alternative set of computer instructions.

[0016]

[0013] Referring to the first and second aspects, in a first possible embodiment of the first and second aspects of the present invention, the at least one processing circuit is further configured to: collect, during execution of the set of computer instructions, a plurality of statistics, the plurality of statistics including a plurality of data statistics indicative of one or more data values ​​of the set of data variables and, additionally or alternatively, at least one branch statistic indicative of a selected instruction to be executed in response to executing at least one branch instruction of the set of computer instructions; and provide the plurality of statistics to at least one hardware processor for identifying at least one estimated data value according to the plurality of statistics. Optionally, the at least one processing circuit includes telemetry circuitry for collecting at least one of the plurality of statistical values. Optionally, the set of computer instructions includes at least one monitoring instruction for collecting at least one of the plurality of statistical values. Using a telemetry circuitry and, additionally or alternatively, at least one monitoring instruction to collect the plurality of statistical values ​​improves the accuracy of identifying at least one estimated data value, thereby improving the accuracy of the predicted set of instructions.

[0017] Referring to the first and second aspects, in a second possible embodiment of the first and second aspects of the present invention, the at least one processing circuit includes a processing circuit having a Von Neumann architecture. Optionally, the at least one processing circuit includes at least one of a central processing unit, a data processing unit (DPU), a multi-core central processing unit (CPU), a microcontroller unit (MCU), and an accelerated processing unit (ACU). Optionally, the at least one processing circuit includes a processing circuit having a non-Von Neumann architecture. Optionally, the at least one processing circuit includes at least one of a data processing unit (DPU), a field programmable gate array (FPGA), a coarse-grained reconfigurable array (CGRA), a neural network accelerator, an intelligence processing unit (IPU), an application-specific integrated circuit (ASIC), a quantum computer, and an interconnected computational grid including a plurality of reconfigurable logic elements connected by a plurality of configurable data routing junctions.

[0018] With reference to the first and second aspects of the present invention, in a third possible embodiment of the first and second aspects of the present invention, the at least one processing circuit includes a first processing circuit and a second processing circuit, the first processing circuit is not the second processing circuit, and executing the at least some of the expected set of computer instructions is performed by the first processing circuit, and executing the alternative set of computer instructions is performed by the second processing circuit. Optionally, identifying an initial state of the at least one processing circuit includes identifying a plurality of state values ​​of the first processing circuit, and restoring the initial state of the at least one processing circuit includes configuring the second processing circuit according to the plurality of state values. Executing the alternative set of computer instructions on a second processing circuit different from the first processing circuit that executes the expected set of instructions allows each of the alternative set of computer instructions and the expected set of computer instructions to be optimized according to their respective processing circuits, thereby improving overall performance of an apparatus implemented in accordance with the present disclosure.

[0019] With reference to the first and second aspects, in a fourth possible embodiment of the first and second aspects of the present invention, the at least one processing circuit has a supported instruction set, the supported instruction set including restore instructions for configuring a state of the processing circuit according to a previously known state of the processing circuit. Optionally, restoring the initial state of the at least one processing circuit includes executing the restore instructions conditional on identifying the prediction failure while executing the at least part of the predicted computer instruction set. Using restore instructions of the supported instruction set of the at least one processing circuit simplifies restoring the initial state of the at least one processing circuit upon identifying the prediction failure, and simplifies execution of the alternative computer instruction set, thus simplifying ease of use compared to requiring multiple instructions to restore the initial state.

[0020] Referring to the third and fourth aspects, in a first possible embodiment of the third and fourth aspects of the present invention, the at least one hardware processor is further configured to receive from at least one other hardware processor a plurality of statistical values ​​during execution of the set of computer instructions, the plurality of statistical values ​​including a plurality of data statistical values ​​indicative of one or more data values ​​of a group of data variables and additionally or alternatively at least one branch statistical value indicative of a selected instruction to be executed in response to executing at least one branch instruction of the set of computer instructions, and to identify the at least one estimated data value according to the plurality of statistical values.

[0021] With reference to the third and fourth aspects or first embodiments of the third and fourth aspects, in a second possible embodiment of the third and fourth aspects of the present invention, generating the predicted set of computer instructions includes adding to the predicted set of computer instructions at least one store instruction for storing an initial state of the at least one processing circuit, at least a portion of the predicted set of computer instructions generated based on the set of computer instructions and the at least one estimated data value, at least one state test instruction for identifying a failure of the prediction, and at least one restore instruction for restoring the initial state of the at least one processing circuit. Optionally, generating at least a portion of the predicted set of computer instructions includes identifying, in the set of computer instructions, at least one tentative instruction set, each tentative instruction associated with at least one local test instruction, such that each set of tentative instructions is predicted to be executed conditional on a result of the associated respective at least one local test instruction. Optionally, the at least one state test instruction storing an initial state of the at least one processing circuit generated in accordance with the at least one local test instruction enables correct execution of the alternative computer instruction set when the prediction failure is identified after executing more instructions of the expected computer instruction set than supported by flushing a pipeline of the at least one processing circuit.

[0022]

[0013] Referring to the third and fourth aspects or first embodiments of the third and fourth aspects, in a third possible embodiment of the third and fourth aspects of the present invention, generating the predicted set of computer instructions comprises identifying, among the set of computer instructions, at least one loop of computer instructions, identifying an expected number of iterations of the loop of computer instructions according to the plurality of statistical values, and generating a rolled-out loop of instructions by repeating at least a portion of the loop of computer instructions for the expected number of iterations of the loop. Optionally, generating the predicted set of computer instructions further comprises identifying, in the rolled-out loop of instructions, a plurality of data-independent operations, wherein an expected result of executing the plurality of data-independent operations does not depend on changing another runtime value of a group of data variables during execution of the rolled-out loop of instructions, and generating the predicted set of computer instructions according to the expected result. Optionally, generating the predicted set of computer instructions according to the expected results further comprises identifying, in the rolled-out loop of instructions, multiple memory access operations on multiple vector elements of a vector data variable of the set of computer instructions, and replacing the multiple memory access operations with a single equivalent memory operation. Repeating at least a portion of a loop of computer instructions for the expected number of iterations of the loop reduces the amount of branch instructions in the predicted set of computer instructions, thereby facilitating an increased likelihood of correctly predicting the order of execution of the predicted set of computer instructions. Generating the predicted set of computer instructions according to expected results of execution of multiple data-independent operations can reduce the amount of branch instructions in the predicted set of computer instructions, thereby facilitating an increased likelihood of correctly predicting the order of execution of the predicted set of computer instructions.

[0023]

[0013] Referring to the third and fourth aspects or first embodiments of the third and fourth aspects, in a fourth possible embodiment of the third and fourth aspects of the present invention, generating the predicted set of computer instructions comprises generating the first set of predicted computer instructions according to the expected result, identifying a plurality of other data-independent operations in the first set of predicted computer instructions, where the other expected result of executing the plurality of other data-independent operations is independent of changing further runtime values ​​of the set of data variables during execution of the first set of predicted computer instructions, and generating a second set of predicted computer instructions according to the other expected result. Optionally, generating the predicted set of computer instructions comprises generating a first other set of predicted instructions based on the at least one estimated data value, identifying at least one other estimated data value according to the plurality of statistics, where the at least one other estimated data value is at least one other value of at least one other set of the data variables expected during execution of the first other set of predicted instructions, and generating a second other set of predicted instructions based on the at least one other estimated data value. By identifying a plurality of other data-independent operations in the first set of predicted computer instructions, and additionally or alternatively by identifying at least one other estimated data value according to the plurality of statistical values, the accuracy of the additional set of predicted instructions can be improved, further improving performance of systems implemented in accordance with the present disclosure.

[0024] With reference to the third and fourth aspects or first embodiments of the third and fourth aspects, in a fourth possible embodiment of the third and fourth aspects of the present invention, configuring the at least one processing circuit comprises calculating at least one expected data flow graph according to the expected set of computer instructions and projecting the at least one data flow graph onto at least a portion of the at least one processing circuit. Optionally, configuring the at least one processing circuit comprises calculating at least one alternative data flow graph according to at least one of the at least one alternative set of computer instructions and projecting the at least one alternative data flow graph onto at least another portion of the at least one processing circuit. Projecting one or more data flow graphs onto one or more portions of the at least one processing circuit enables the expected set of computer instructions and, additionally or alternatively, at least one alternative set of computer instructions to be executed on a processing circuit adapted to execute data flow, thereby improving performance of a system implemented in accordance with the present disclosure.

[0025] Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of this disclosure, and be protected by the accompanying claims.

[0026] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the embodiments, exemplary methods and / or materials are described below. In case of conflict, the patent specification, including definitions, will control. Additionally, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

[0027] Some embodiments will now be described, by way of example only, with reference to the accompanying drawings. Referring now to the drawings in detail, it will be emphasized that the particulars shown are by way of example only and are for the purpose of illustrative discussion of the embodiments. In this regard, the description using the drawings will make apparent to those skilled in the art how the embodiments may be practiced. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a schematic block diagram of an exemplary apparatus, according to some embodiments. [Figure 2] 1 is a flowchart that schematically illustrates an optional flow of operations for computing, according to some embodiments. [Figure 3] 10 is a flowchart that schematically illustrates an optional flow of operations for collecting statistics, according to some embodiments. [Figure 4] 10 is a flowchart that schematically illustrates another optional flow of operations for computing, according to some embodiments. [Figure 5] 10 is a flowchart that schematically illustrates another optional flow of operations for generating a set of anticipated computer instructions, in accordance with some embodiments. [Figure 6] 1 is a flowchart that schematically illustrates an optional flow of operations for generating a predicted set of computer instructions that includes a loop, according to some embodiments. [Figure 7] 1 is a flowchart that schematically illustrates an optional flow of operations for generating an expected set of computer instructions that includes multiple memory accesses, according to some embodiments. [Figure 8] 10 is a flowchart that schematically illustrates an optional sequence of operations for configuring the device, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0029] In many existing computer architectures, executing an instruction involves fetching that instruction from code storage, which contains a set of computer instructions, and loading that instruction into a dedicated area of ​​the processing circuitry of a processing unit. If the processing unit includes an instruction pipeline, new instructions are loaded into the instruction pipeline before the previous instruction has completed execution.

[0030] Using an instruction pipeline to execute a set of computer instructions is relatively straightforward if the order in which the set of computer instructions are executed is predictable, and is subject primarily to limitations on explicit storage for communicating data values. If there is sufficient storage to communicate data values ​​between computer instructions, the set of computer instructions can be loaded into the instruction pipeline in a predictable order.

[0031] However, when the execution order of an instruction set is unpredictable, it is not always clear which new instruction to load into the pipeline. For example, a particular data value calculated in an instruction preceding a conditional branch instruction may determine the outcome of executing the conditional branch instruction. In such an example, identifying the correct next instruction to load into the instruction pipeline after loading the conditional branch instruction requires calculating the particular data value by completing execution of the instruction preceding the conditional branch instruction.

[0032] A simple approach to loading an instruction set into a pipeline is to refrain from fetching and loading the correct next instruction until a specific data value has been calculated. This approach stifles processor performance gains because the pipeline is not fully utilized.

[0033] Another approach is to use a default criterion for next instruction selection, for example, always selecting the instruction following a conditional branch instruction. However, this approach can result in the wrong next instruction being loaded into the pipeline, known as a failed prediction. To recover from a failed prediction, once it is determined that the wrong next instruction has been loaded into the pipeline, it is necessary to flush (remove) any other instructions loaded after the wrong next instruction from the pipeline and load the correct next instruction instead. Because pipeline flushing affects processor performance in a similar way to stalling a processor until a specific data value is calculated, this approach requires reducing the amount of failed predictions, and therefore the amount of incorrect next instructions loaded into the pipeline.

[0034] To reduce the number of times the pipeline is flushed, some processor architectures implement one or more branch prediction methods to predict the outcome of a branch instruction before it can be deterministically known. Such solutions typically include dedicated hardware that collects multiple historical results of the execution of one or more branch instructions and calculates a new expected outcome of executing a particular branch instruction based on the multiple historical results. Some solutions use the historical results of executing a particular branch instruction to calculate the new expected outcome. Other solutions use the historical results of executing multiple branch instructions to calculate the new expected outcome. However, because of the need for dedicated hardware, such solutions are limited in the amount of branch instructions for which branch prediction can be performed at any given time, for example, by limiting the depth of the decision tree. Such limitations increase the likelihood of stalling the pipeline load or loading the wrong next instruction into the pipeline, thereby reducing processor performance, i.e., reducing processor throughput and additionally or alternatively increasing processor latency.

[0035] In some computer architectures, the processing unit computes multiple possible outcomes of a particular branch instruction in parallel, but such solutions are limited in the amount of branch instructions that can compute multiple possible outcomes in parallel.

[0036] Furthermore, a particular branch instruction may be executed along multiple execution paths of a program. The result of executing a particular branch instruction when called by one part of a program may not be indicative of the alternative result of executing that particular branch instruction when called by another part of the program. For example, argument values ​​to a function may affect the outcome of executing a particular branch instruction of that function. When called multiple times, the function may be called with different argument values ​​each time. This increases the likelihood that one outcome of executing a particular branch instruction may not be indicative of the alternative outcome of executing that branch instruction, resulting in increased mispredictions and pipeline flushes.

[0037] In some embodiments described herein, the present disclosure proposes predicting an estimated execution order of a set of computer instructions based on estimated data values ​​of one or more data variables of the set of computer instructions. The one or more estimated data values ​​are one or more values ​​of at least one data variable expected to be calculated by executing the set of computer instructions. Optionally, the one or more estimated data values ​​are calculated using one or more program data values ​​of the set of computer instructions, the set of computer instructions having program data, and the program data values ​​are program data values ​​of the set of computer instructions. Optionally, the one or more estimated data values ​​are calculated by applying one or more arithmetic operations to one or more program data values ​​of the set of computer instructions. This is in contrast to, for example, an expected program counter value. For example, the estimated data value may be calculated by calculating a bitwise Boolean NOT of the program data values. In another example, the estimated data value is calculated by adding two or more program data values. Optionally, the one or more estimated data values ​​are obtained during execution of the set of computer instructions, for example, from a memory storing program data of the set of computer instructions. The memory may be non-volatile digital storage. The memory may be a memory component, such as a random access memory (RAM) component. Optionally, the one or more estimated data values ​​are received through a digital communications network interface. Optionally, the one or more estimated data values ​​are used by at least one of the set of computer instructions in executing the set of computer instructions. For example, the one or more estimated data values ​​may be one or more arguments of at least one of the set of computer instructions, e.g., where at least one computer instruction includes an arithmetic or comparison operation.Optionally, predicting that one or more estimated data values ​​will be calculated by executing the set of computer instructions is done when compiling the set of computer instructions or when compiling source code from which the set of computer instructions is generated. Optionally, predicting that one or more estimated data values ​​will be calculated by executing the set of computer instructions is done when recompiling the set of computer instructions, for example during execution of the set of computer instructions. Optionally, recompiling the set of computer instructions is done from the source code. Optionally, recompiling the set of computer instructions is done from another representation of the computer program, for example from a programming language independent intermediate representation. Optionally, the one or more estimated data values ​​comprise a range of estimated data values. Optionally, predicting that one or more estimated data values ​​will be calculated by executing the set of computer instructions comprises predicting one or more relationships between the one or more estimated data values, and additionally or alternatively predicting one or more correlations between the one or more estimated data values. In such embodiments, the present disclosure proposes using one or more estimated data values ​​to generate the predicted set of computer instructions. Further, one or more alternative sets of computer instructions are optionally generated based on the one or more estimated data values. In such an embodiment, the present disclosure proposes identifying an initial state of a processing circuit that executes the set of computer instructions, and identifying a prediction failure in which one or more of the data variables are not equal to the one or more estimated data values ​​during execution of at least a portion of the expected set of computer instructions. Optionally, determining that the one or more data variables are not equal to the respective estimated data values ​​is via one or more data variable tests. Optionally, the one or more data variable tests include comparing the one or more data variables to a range of estimated data values. Optionally, the one or more data variable tests include applying one or more bit masks to the one or more data variables.Optionally, applying the one or more data variable tests comprises calculating a relationship between one or more estimated data values. Optionally, applying the one or more data variable tests comprises identifying a correlation between one or more data values, optionally according to the one or more estimated data values.

[0038] Optionally, upon identifying a misprediction, the present disclosure proposes restoring an initial state of the processing circuit and executing one of one or more alternative sets of computer instructions. Generating a predicted set of computer instructions based on one or more estimated data values ​​predicted to be calculated by executing a set of computer instructions increases the likelihood of correctly predicting the execution order of the predicted set of computer instructions, reducing the number of times the pipeline needs to be flushed. Calculating one or more estimated data values ​​using one or more program data values ​​of the set of computer instructions improves the accuracy of the one or more estimated data values, further increasing the likelihood of correctly predicting the execution order of the predicted set of computer instructions. Furthermore, the predicted set of computer instructions generated based on the one or more estimated data values ​​is not limited by the amount of branch instructions, and when the amount of simultaneously active branch instructions exceeds the limit of the processing unit's dedicated hardware for branch prediction, executing the predicted set of computer instructions improves the performance of the processing unit, i.e., increases throughput, and additionally or alternatively reduces latency, compared to using other branch prediction methods. Furthermore, generating a predicted set of computer instructions based on one or more estimated data values ​​reduces the likelihood of identifying a misprediction when executing the predicted set of computer instructions, thereby reducing the number of times the pipeline needs to be flushed.

[0039] For example, in some embodiments, if a first set of computer instructions of a program includes a call to a function with an argument equal to a first data value, a first set of predicted computer instructions is generated based on the first data value. In such embodiments, if a second set of computer instructions of the program includes another call to the function with an argument equal to a second data value, a second set of predicted computer instructions is generated based on the second data value. In this example, when executing the program, the processing unit executes the first set of computer instructions by executing the first set of predicted computer instructions and executes the second set of computer instructions by executing the second set of predicted computer instructions. The first set of predicted computer instructions may differ from the second set of predicted computer instructions depending on the difference between the first and second data values, thereby reducing the need to flush the pipeline when executing either of the two sets of predicted computer instructions.

[0040] Furthermore, generating one or more alternative computer instruction sets facilitates executing at least a portion of the one or more alternative computer instruction sets on another processing circuit other than, and optionally connected to, the processing circuit that executes the expected computer instruction set. By executing the alternative computer instruction sets on the other processing circuit, each of the alternative computer instruction sets and the expected computer instruction set can be optimized for the respective processing circuit, thereby improving the overall performance of an apparatus that includes the processing circuit and the other processing circuits, i.e., increasing throughput, and additionally or alternatively reducing latency of the apparatus. In some embodiments of the present invention, the apparatus includes one or more processing units for calculating the expected computer instruction set and, optionally, for calculating the one or more alternative computer instruction sets. Optionally, the one or more processing units execute the expected computer instruction set. Optionally, upon identification of a prediction failure, one of the one or more alternative computer instruction sets is executed by the one or more processing units. Optionally, the one or more processing units configure the one or more processing circuits to execute the expected computer instruction set. Optionally, the one or more processing devices configure one or more processing circuits to execute one of one or more alternative computer instruction sets when a misprediction is identified. In a contemplated example, the processing device executing the set of computer instructions configures a portion of a reconfigurable processing grid connected thereto to execute the predicted computer instructions, e.g., to speed up execution of the set of computer instructions. In this contemplated example, the alternative computer instruction set is executed by the processing device when a misprediction is identified. In another example, when a misprediction is identified, or in parallel, the processing device configures a portion of the reconfigurable processing grid to execute the predicted computer instruction set and configures another portion of the reconfigurable processing grid to execute the alternative computer instruction set. Optionally, when a misprediction is identified, the processing device configures one or more memory values ​​in a memory coupled to the processing device.Additionally or alternatively, when a misprediction is identified, the processing unit provides one or more other memory values ​​read from memory, optionally as input to an alternative set of computer instructions when executing the expected set of computer instructions. Still additionally or alternatively, when a misprediction is identified, the processing unit provides at least one instruction to write one or more further memory values ​​to memory as input to the alternative set of computer instructions. Optionally, the one or more further memory values ​​are written to memory when executing the expected set of computer instructions. Optionally, the one or more further memory values ​​are written to memory when configuring the one or more processing circuits to execute the alternative set of computer instructions. Optionally, if the memory is transactional memory, when a misprediction is identified, the processing unit rolls back one or more memory write accesses to the transactional memory made when executing the expected set of instructions. Additionally or alternatively, when a misprediction is identified, the processing unit refrains from committing one or more memory write accesses to the transactional memory.

[0041] Furthermore, generating one or more alternative sets of computer instructions facilitates execution of at least some of the one or more alternative sets of computer instructions in parallel with the execution of the predicted set of computer instructions, thereby reducing the latency of recovering from mispredictions and improving device performance.

[0042] In some embodiments described in this disclosure, the one or more estimated data values ​​are identified by collecting a plurality of statistical values ​​during execution of the set of computer instructions. One example of a statistical value is a data statistical value indicative of one or more data values ​​of a set of data variables calculated by executing the set of computer instructions. Another example of a statistical value is a branch statistical value indicative of a taken instruction executed in response to execution of at least one branch instruction of the set of computer instructions. Using the plurality of data statistical values ​​indicative of one or more data values ​​of a set of data variables during execution of the set of computer instructions, and additionally or alternatively, the one or more branch statistical values ​​indicative of a taken instruction executed in response to execution of at least one branch instruction of the set of computer instructions, may improve the accuracy of the predicted set of computer instructions, e.g., when at least some of the one or more data values ​​are repeated over time, resulting in improved performance, i.e., increased throughput, and additionally or alternatively, reduced latency of the processing device.

[0043] Optionally, one or more of the plurality of statistical values ​​are collected by hardware, for example using telemetry circuitry of the processing circuit. Optionally, one or more other values ​​of the plurality of statistical values ​​are collected by software, for example using one or more monitoring instructions of a computer instruction set, also known as instrumentation instructions.

[0044] In some embodiments, predicting the probable execution order of the set of computer instructions is a dynamic process, i.e., the expected set of computer instructions is dynamically changed. In such embodiments, in each of a plurality of iterations, a new set of expected computer instructions is generated, the new set of expected computer instructions being generated based on one or more new estimated data values ​​of the set of data variables. Optionally, the one or more new estimated data values ​​are identified according to a plurality of new statistics collected during execution of the expected set of computer instructions generated in a previous iteration.

[0045] Before describing at least one embodiment in detail, it is to be understood that the embodiments are not necessarily limited in their application to the details of construction and arrangement of components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. The embodiments described herein are capable of other embodiments or of being practiced or carried out in various ways.

[0046] The embodiments may be systems, methods, and / or computer program products, which may include computer-readable storage medium(s) having computer-readable program instructions for causing a processor to perform aspects of the embodiments.

[0047] A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. While not exhaustive, a more specific list of examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, and any suitable combination thereof. The computer-readable storage medium in this context should not be construed as a transitory signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0048] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium into each computing / processing device, or may be downloaded to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0049] The computer-readable program instructions for carrying out the operations of an embodiment may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or conventional procedural programming languages, such as natively compiled or just-in-time (JIT) compiled object-oriented programming languages ​​such as Smalltalk, C++, Java, object-oriented Fortran, interpreted programming languages ​​such as JavaScript, Python, and the like, and the "C" programming language, Fortran, or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, such as a local area network (LAN) or a wide area network (WAN), or a connection to an external computer may be established (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may utilize state information of the computer readable program instructions to execute the computer readable program instructions and personalize the electronic circuitry in order to perform aspects of the embodiments.

[0050] Aspects of the embodiments are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to the embodiments. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0051] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus for manufacturing a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in the flowchart and / or block diagram blocks. These computer-readable program instructions may also be stored on a computer-readable storage medium that can cause a computer, programmable data processing apparatus, and / or other device to function in a particular way, such that the computer-readable storage medium on which the instructions are stored constitutes an article of manufacture containing instructions that implement aspects of the functions / acts specified in the flowchart and / or block diagram blocks.

[0052] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational steps to generate a computer-implemented process, such that the instructions, which run on the computer, other programmable apparatus, or other device, perform the functions / acts specified in the flowchart and / or block diagram blocks.

[0053] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of an instruction, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative embodiments, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, depending on the functionality involved, or the blocks may be executed in the reverse order. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified function or operation or executes a combination of dedicated hardware or computer instructions.

[0054] Reference is now made to FIG. 1 , which illustrates a schematic block diagram of an exemplary apparatus 100 according to some embodiments. In such an embodiment, the apparatus 100 includes one or more processing circuits 110. Optionally, at least one of the one or more processing circuits 110 has a von Neumann architecture. Some examples of processing circuits having a von Neumann architecture include a central processing unit, a multi-core central processing unit (CPU), a data processing unit (DPU), a microcontroller unit (MCU), and an accelerated processing unit (ACU). Optionally, at least one of the one or more processing circuits 110 has a non-von Neumann architecture. Examples of processing circuits having non-von Neumann architectures include graphical processing units (GPUs), data processing units (DPUs), field programmable gate arrays (FPGAs), coarse-grained reconfigurable arrays (CGRAs), neural network accelerators, intelligence processing units (IPUs), application-specific integrated circuits (ASICs), quantum computers, and interconnected computational grids. Optionally, the interconnected computational grids include a plurality of reconfigurable logic elements connected by a plurality of configurable data routing junctions. An example of a reconfigurable logic element is a processing circuit that can be configured to perform one of a set of specific arithmetic and logical operations. Examples of arithmetic operations include addition and subtraction. Examples of logical operations include a logical NOT operation and a logical AND operation.

[0055] Optionally, apparatus 100 includes at least one other processing circuit 120, which is not one of the one or more processing circuits 110. Optionally, the at least one other processing circuit 120 has a von Neumann architecture. Optionally, the at least one other processing circuit 120 has a non-von Neumann architecture.

[0056] For the sake of brevity, unless expressly stated otherwise, the term "processing circuitry" will hereinafter be used to mean both "one or more processing circuits" and "at least one processing circuit," and these terms are used interchangeably.

[0057] Optionally, processing circuit 110 is connected to other processing circuitry 120. Optionally, processing circuit 110 is electrically coupled to the other processing circuitry 120, optionally using an interconnection bus. Examples of interconnection buses include, but are not limited to, a Compute Express Link (CXL)® interconnect, a Gen-Z cache coherent interconnect for accelerators (CCIX), a Coherent Accelerator Processor Interface (CAPI), and a Peripheral Component Interconnect Express (PCI-e)®. Optionally, processing circuit 110 is connected to the other processing circuitry 120 via one or more digital communication network interfaces (not shown) of processing circuit 110. Optionally, the one or more digital communication network interfaces are connected to a local area network (LAN), such as an Ethernet network or a wireless network.

[0058] Optionally, the other processing circuitry 120 is a host processing unit and executes a software program including a set of computer instructions. Optionally, the processing circuitry 110 is an accelerated processing circuit and is connected to the other processing circuitry for the purpose of accelerating the execution of the software program. In one example, the other processing circuitry 120 is a CPU and the processing circuitry is a GPU. In another example, the other processing circuitry 120 is a CPU and the processing circuitry 110 is an interconnected computational grid accelerator. In yet another example, the other processing circuitry 120 is a CPU and the processing circuitry 110 is part of an interconnected computational grid accelerator.

[0059] Optionally, processing circuitry 110 is configured to calculate a result of executing a set of computer instructions. Optionally, the set of computer instructions includes a set of data variables. Optionally, the set of computer instructions is one code block of a plurality of code blocks of a software program. Optionally, processing circuitry 110 is configured to additionally execute one or more other code blocks of the plurality of code blocks.

[0060] Optionally, processing circuit 110 includes telemetry circuit 112, optionally for collecting one or more statistics while processing circuit 110 executes the one or more computer instructions. Optionally, the one or more statistics include at least one data statistic. Optionally, the one or more statistics include at least one branch statistic. Optionally, telemetry circuit 112 includes one or more counters. Optionally, telemetry circuit 112 includes one or more memory areas for collecting historical values ​​of at least some of the data variables. Optionally, the historical values ​​include one or more memory network hop counters, and additionally or alternatively, one or more translation look-side buffer (TLB) hit counters. Other examples of historical values ​​of data variables include RISC-V processor counters, high-bandwidth memory controller counters, and memory channel counters.

[0061] Optionally, the apparatus 100 includes one or more processing units 101, optionally for the purpose of configuring the processing circuitry 110, additionally or alternatively for the purpose of configuring other processing circuits 120.

[0062] For the sake of brevity, unless expressly stated otherwise, the term "processing device" will hereinafter be used to mean "one or more processing devices."

[0063] Optionally, the processing unit 101 includes processing circuitry with a von Neumann architecture. Optionally, the processing unit 101 includes processing circuitry with a non-von Neumann architecture.

[0064] Optionally, processing unit 101 is connected to processing circuit 110, and additionally or alternatively to processing circuit 120, via one or more other digital communication network interfaces (not shown) of processing unit 101. Optionally, the one or more other digital communication network interfaces are connected to another LAN. Optionally, the one or more other digital communication network interfaces are connected to a wide area network (WAN), such as, for example, the Internet. Optionally, processing unit 101 is electrically coupled to one or more of processing circuit 110 and processing circuit 120, optionally using an interconnect bus, such as, for example, CXL®, Gen-Z CCIX, CAPI, PCI-e®, etc.

[0065] To compute the result of executing the set of computer instructions, in some embodiments, the apparatus 100 performs the following optional method.

[0066] Reference is now also made to Figure 2, which shows a flowchart that schematically illustrates an optional flow of operations 200 for calculation, according to some embodiments. In such embodiments, processing circuit 110 identifies its initial state at 201. Optionally, processing device 101 identifies the initial state of processing circuit 110.

[0067] Optionally, the initial state is a state prior to execution of a root branch instruction of the plurality of computer instructions, and has statistical significance for a distribution of multiple outcomes of executing one or more future branches, and additionally or alternatively one or more future loops, in multiple iterations during execution of the plurality of computer instructions. Optionally, identifying the initial state of the processing circuit 110 includes identifying multiple state values ​​thereof. One example of a state value is a register value of the processing circuit 110. Other examples of state values ​​are local variable values ​​of the plurality of computer instructions, global variable values ​​of the plurality of computer instructions, thread-local values ​​of the plurality of computer instructions, memory state, and program locations within the plurality of computer instructions.

[0068] At 203, processing circuitry 110 optionally executes at least a portion of the expected set of computer instructions. Optionally, processing device 101 configures processing circuitry 110 to execute at least a portion of the expected set of computer instructions. Optionally, the expected set of computer instructions is generated based on the set of computer instructions and one or more estimated data values. Optionally, the estimated data value is a value of one of a set of data variables of the set of computer instructions that is expected to be calculated by executing the set of computer instructions. Optionally, the one or more estimated data values ​​are calculated using one or more program data values ​​of the set of computer instructions. Optionally, the one or more estimated data values ​​are calculated by applying one or more arithmetic operations to one or more program data values ​​of the set of computer instructions. Examples of arithmetic operations include addition, subtraction, multiplication, division, unitary Boolean operators such as NOT, bitwise unitary Boolean operators such as bitwise NOT, binary Boolean operators such as AND, OR, XOR, and bitwise binary operators such as bitwise AND, bitwise OR, bitwise XOR. Optionally, the one or more estimated data values ​​are obtained during execution of the set of computer instructions, e.g., from a memory component connected to processing circuit 110. Optionally, the one or more estimated data values ​​are received via a digital communication network interface connected to processing circuit 110. Optionally, predicting that the one or more estimated data values ​​will be calculated by executing the set of computer instructions is done when compiling the set of computer instructions or when compiling source code from which the set of computer instructions is generated. Optionally, predicting that the one or more estimated data values ​​will be calculated by executing the set of computer instructions is done when recompiling the set of computer instructions, e.g., at run-time of the set of computer instructions. Optionally, recompiling the set of computer instructions is done from source code.Optionally, recompiling the set of computer instructions is done from another representation of the computer program, for example from a programming language independent intermediate representation. Optionally, the one or more estimated data values ​​are identified based on a plurality of statistics collected during execution of the set of computer instructions. For example, a plurality of statistics may be collected as the set of computer instructions is executed by executing at least a portion of the expected set of computer instructions.

[0069] Reference is now also made to Figure 3, which illustrates a flowchart that schematically illustrates an optional flow of operations 300 for collecting statistics, according to some embodiments. In such embodiments, at 310, a processing circuit collects a plurality of statistics. Optionally, the plurality of statistics includes a plurality of data statistics. The data statistics are indicative of one or more data values ​​of a group of data variables during execution of the set of computer instructions. Optionally, the plurality of statistics includes a plurality of branch statistics. The branch statistics are indicative of selected instructions executed in response to execution of one or more branch instructions of the set of computer instructions.

[0070] Optionally, at least some of the plurality of statistical values ​​are collected using telemetry circuit 112, which updates its hardware counters. Optionally, the set of computer instructions includes instrumentation code for collecting at least some other of the plurality of statistical values, whereby at least some other of the plurality of statistical values ​​are collected using one or more monitoring instructions of the set of computer instructions. Optionally, the monitoring instructions update hardware counters of processing circuit 110, e.g., hardware counters of processing circuit 112. Optionally, the monitoring instructions update software counters of the set of computer instructions. Optionally, the counters, whether hardware or software counters, are updated according to one or more actual values ​​of one or more data variables during execution of the set of computer instructions. Optionally, the counters are updated according to an execution result of a branch operation of the set of computer instructions.

[0071] Optionally, at 320, processing circuitry 110 provides a plurality of statistics to processing unit 101, optionally for the purpose of processing unit 101 identifying one or more estimated data values.

[0072] Referring again to Figure 2, optionally at 210, processing circuit 110 identifies a failure of prediction where one or more data variables are not equal to one or more estimated data values. Optionally, identifying the failure of prediction includes applying one or more data variable tests to the one or more data variables. Optionally, the one or more estimated data values ​​include a range of estimated data values. Optionally, applying the one or more data variable tests includes comparing the one or more data variables to the range of estimated data values. Optionally, applying the one or more data variable tests includes applying one or more bit masks to the one or more data variables. Optionally, applying the one or more data variable tests includes calculating a relationship between the one or more estimated data values. Optionally, applying the one or more data variable tests includes identifying a correlation between one or more data values, optionally according to the one or more estimated data values.

[0073] Upon identifying the prediction failure at 210, processing circuitry 110 optionally restores to its initial state at 211, and processing circuitry 110 optionally executes one of the at least one alternative set of computer instructions at 212. Optionally, processing device 101 configures processing circuitry 110 to restore to its initial state and execute one of the at least one alternative set of computer instructions. Optionally, the at least one alternative set of computer instructions is generated based on the set of computer instructions and one or more estimated data values. For example, the alternative set of computer instructions may include one or more test instructions whose execution results depend on one or more actual values ​​of at least some of the data variables.

[0074] Optionally, restoring the initial state of the processing circuit 110 includes the processing circuit 110 generating a restoration signal in response to identifying the prediction failure at 210, and configuring at least a portion of the processing circuit 110 according to a plurality of state values ​​in response to identifying the restoration signal. Optionally, restoring the initial state of the processing circuit 110 includes configuring one or more memory values ​​of a memory coupled to the processing circuit 110. Optionally, restoring the initial state of the processing circuit 110 includes providing as input to an alternative set of computer instructions at least one instruction for configuring the one or more memory values. Optionally, restoring the initial state of the processing circuit 110 includes providing as input to the alternative set of computer instructions one or more other memory values ​​read from the memory when executing the optionally expected set of computer instructions. Additionally or alternatively, restoring the initial state of the processing circuit 110 includes providing as input to the alternative set of computer instructions at least one other instruction for writing one or more further memory values ​​to the memory. Optionally, one or more further memory values ​​are written to memory when executing the anticipated set of computer instructions.

[0075] Optionally, if the memory is transactional memory, restoring the initial state of the processing circuit 110 includes rolling back one or more memory write accesses to the transactional memory made when executing the expected set of instructions. Additionally or alternatively, restoring the initial state of the processing circuit 110 includes refraining from committing one or more memory write accesses to the transactional memory.

[0076] Optionally, processing circuit 110 has a supported instruction set. Optionally, the supported instruction set includes a restore instruction for configuring a state of processing circuit 110 according to a previous known state. Optionally, restoring the initial state of processing circuit 110 at 211 includes executing the restore instruction. Optionally, the restore instruction is executed conditional on identifying a prediction failure at 210.

[0077] Optionally, restoring the initial state of the processing circuit 110 at 211 includes configuring the other processing circuit 120 according to the plurality of state values. Optionally, at 212, the alternative set of computer instructions is executed by the other processing circuit 120 instead of or in addition to the processing circuit 110.

[0078] In some embodiments, the apparatus 100 performs the following optional methods for generating expected sets of computer instructions and calculating the results of executing the sets of computer instructions.

[0079] Reference is now also made to FIG. 4, which illustrates a flow chart that generally depicts another optional flow of operations 400 for calculation, according to some embodiments.

[0080] While the following description focuses on an embodiment in which method 400 is performed at least in part by processing unit 101, it should be noted that other embodiments exist in which method 400 is performed entirely by processing circuitry 110, for example.

[0081] Optionally, at 401, processing unit 101 optionally receives a plurality of statistics from processing circuitry 110. Optionally, the plurality of statistics includes a plurality of data statistics and additionally or alternatively at least one branch statistic. Optionally, processing circuitry 110 collects the plurality of statistics using method 300 described above.

[0082] Optionally, at 405, the processing unit 101 identifies one or more estimated data values. As mentioned above, an estimated data value is a value of one of a set of data variables of the set of computer instructions that is expected to be calculated by executing the set of computer instructions, optionally using one or more program data values ​​of the set of computer instructions. Optionally, 405 is performed when compiling the set of computer instructions or when compiling source code from which the set of computer instructions is generated.

[0083] Optionally, at 410, the processing unit 101 generates a predicted set of computer instructions, optionally based on the set of computer instructions and one or more estimated data values.

[0084] Reference is now also made to FIG. 5, which shows a flow chart that generally illustrates an optional operational flow 500 for generating a set of anticipated computer instructions, according to some embodiments.

[0085] Optionally, to generate the predicted set of computer instructions, at 501, the processing unit 101 adds one or more store instructions for storing an initial state of the processing circuit 110 to the predicted set of computer instructions. At 503, the processing unit 101 optionally adds at least a portion of the predicted set of computer instructions to the predicted set of computer instructions for execution at 203. Optionally, at least a portion of the predicted set of computer instructions is generated based on the set of computer instructions and one or more estimated data values. For example, the predicted set of computer instructions may replace data variables of the group of data variables with predicted static values ​​identified according to data statistical values ​​of the plurality of statistical values. In another example, the predicted set of computer instructions includes one or more sets of computer instructions that do not reference the data variables.

[0086] Optionally, generating at least a portion of the predicted set of computer instructions includes generating an inline path of execution of the plurality of branch instructions according to a predicted path selected according to the one or more predicted data values. To that end, generating at least a portion of the predicted set of computer instructions optionally includes identifying one or more tentative instruction sets among the set of computer instructions. Optionally, each set of tentative instructions is associated with at least one local test instruction. Optionally, each set of tentative instructions is predicted to be executed conditional on a result of the associated respective at least one local test instruction.

[0087] At 505, the processing unit 101 optionally adds one or more state test instructions to the set of expected computer instructions for identifying a failure of the prediction at 210. Optionally, the one or more state test instructions are generated according to the at least one local test instruction.

[0088] Optionally, at 508, the processing unit 101 adds one or more restoration instructions to the expected set of computer instructions to restore the initial state of the processing circuit 110.

[0089] In some embodiments, the set of computer instructions includes a loop. Reference is now also made to Figure 6, which shows a flowchart that schematically illustrates an optional operation flow 600 for generating a predicted set of computer instructions including a loop, according to some embodiments. In such an embodiment, at 601, the processing unit 101 identifies at least one loop of computer instructions in the set of computer instructions. Optionally, at 603, the processing unit 101 identifies a predicted number of iterations of the loop of computer instructions according to a plurality of statistical values. Optionally, the processing unit 101 identifies the predicted number of iterations according to one or more data statistics of the plurality of statistical values, the data statistics indicating one or more actual data values ​​of a group of data variables while executing the set of computer instructions. Optionally, the processing unit 101 identifies the predicted number of iterations according to one or more branch statistics of the plurality of statistical values.

[0090] At 607, the processing unit 101 optionally generates a rolled-out loop of instructions by repeating at least a portion of the loop of computer instructions. Optionally, the processing unit 101 repeats at least a portion of the loop of computer instructions a number of times equal to or less than the expected number of iterations of the loop.

[0091] In some embodiments, the expected results of executing the rolled-out loop operations of the instruction do not depend on the runtime values ​​of other data variables of the set of data variables during execution of the rolled-out loop of the instruction. Such operations are referred to as data-independent operations. For example, computing a convolution involves multiple loop iterations that include multiple data-independent operations.

[0092] Optionally, at 610, the processing unit 101 identifies multiple data-independent operations in the rolled-out loop of instructions. At 620, the processing unit 101 optionally generates a predicted set of computer instructions according to the expected results.

[0093] Optionally, 610 and 620 are repeated in each of a plurality of iterations, and new data-independent operations are identified in the set of expected computer instructions generated in the previous iteration, where other expected results of executing the new data-independent operations are made independent of further run-time value changes of the data variables while executing the set of expected computer instructions generated in the previous iteration. Optionally, the processing unit 101 generates a second set of expected computer instructions according to the other expected results.

[0094] In some embodiments, calculating the expected result includes performing multiple memory access operations, e.g., performing multiple memory accesses for each of multiple vector elements of the vector data variable. Reference is now also made to FIG. 7, which shows a flowchart that schematically illustrates an optional operational flow 700 for generating an expected computer instruction set including multiple memory accesses, according to some embodiments. In such an embodiment, at 701, the processing unit 101 identifies, in the rolled-out computer instruction set, multiple memory operations for multiple vector elements of the vector data variable of the computer instruction set. At 705, the processing unit 101 optionally replaces the multiple memory access operations with a single equivalent memory operation.

[0095] In some embodiments, the processing circuit 110 is a quantum computer. Optionally, generating the predicted computer instruction set includes identifying a quantum algorithm that corresponds to at least a portion of the computer instruction set according to a plurality of statistics. Optionally, the predicted computer instruction set is generated for implementing a particular quantum algorithm.

[0096] Now, reference is made again to FIG.

[0097] Optionally, the processing unit 110 repeats 405 and 410 in each of another plurality of iterations, such that the processing unit 101 identifies one or more other estimated data values ​​according to the plurality of statistics. Optionally, the one or more other estimated data values ​​are one or more other values ​​of one or more other data variables of the set of data variables that are expected during execution of the expected set of instructions generated in another, previous iteration. Optionally, the processing unit 101 generates another set of expected computer instructions based on the one or more other estimated data values.

[0098] Optionally, at 415, the processing unit 101 generates at least one alternative set of computer instructions, optionally based on the set of computer instructions and the one or more estimated data values. Optionally, to generate the at least one alternative set of computer instructions, the processing unit 101 replaces one or more operands of at least the set of computer instructions with at least one data value. Optionally, the at least one data value is not a member of the one or more estimated data values.

[0099] At 420, the processing unit 101 configures the processing circuitry 110, and additionally or alternatively other processing circuitry 120, to execute a set of computer instructions, optionally using the method 200 described above.

[0100] A dataflow graph for a set of operations is a representation of the set of operations that includes a number of nodes and a number of arcs, each connecting two of the nodes. In the dataflow graph, nodes represent locations where data variables of the set of operations are assigned or used, and arcs show relationships between locations where data variables are assigned and other locations where the data variables are used. As used herein, the term "projecting a dataflow graph onto a processing circuit" refers to configuring a configurable processing circuit to implement the dataflow graph. In some embodiments, apparatus 100 configures processing circuit 110 using one or more dataflow graphs.

[0101] Reference is now also made to Figure 8, which illustrates a flowchart that generally illustrates an optional flow of operations 800 for configuring an apparatus, according to some embodiments. In such an embodiment, at 801, processing unit 101 calculates one or more expected data flow graphs according to an expected set of computer instructions. At 802, processing unit 101 optionally projects the one or more data flow graphs onto at least a portion of processing circuitry 110.

[0102] For example, if processing circuit 110 is an interconnected computational grid including a plurality of reconfigurable logic elements connected by a plurality of configurable data routing junctions, projecting the one or more data flow graphs onto at least a portion of processing circuit 110 optionally includes modifying at least one reconfigurable logic element of the plurality of reconfigurable logic elements such that at least a portion of the interconnected computational grid computes one or more result values ​​in response to input data according to the one or more data flow graphs. Additionally or alternatively, projecting the one or more data flow graphs onto at least a portion of processing circuit 110 includes modifying at least one configurable data routing junction of the plurality of configurable data routing junctions such that at least a portion of the interconnected computational grid computes one or more result values ​​in response to input data according to the one or more data flow graphs.

[0103] Optionally, at 810, processing unit 101 computes one or more alternative data flow graphs according to at least one alternative set of computer instructions. Optionally, at 812, processing unit 101 projects the one or more alternative data flow graphs onto at least other portions of processing circuitry 110.

[0104] The description of various embodiments has been provided for illustrative purposes and is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements over commercially available technology, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0105] It is anticipated that many related processing and telemetry circuitry will be developed during the life of the patent emanating from this application, and the scope of the terms "processing circuitry" and "telemetry circuitry" is intended to include all such new technologies a priori.

[0106] As used herein, the term "about" means plus or minus 10%.

[0107] The terms "comprises," "comprising," "includes," "including," "having," and their conjugations mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of."

[0108] The phrase "consisting essentially of" means that the composition or method may include additional components and / or steps, provided that the additional components and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0109] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" can include a plurality of compounds, including mixtures thereof.

[0110] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." An embodiment described as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments and / or as excluding the incorporation of features from other embodiments.

[0111] The phrase "optionally" is used herein to mean "provided in some embodiments and not provided in other embodiments." Any particular embodiment may include multiple "optional" features, unless inconsistent.

[0112] Throughout this application, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the embodiments. Accordingly, range descriptions should be considered to have specifically disclosed all possible subranges as well as individual numerical values ​​within that range. For example, description of a range such as 1 to 6 should be considered to have specifically disclosed subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numerical values ​​within that range, e.g., 1, 2, 3, 4, 5, 6. The above applies regardless of the breadth of the range.

[0113] Whenever a range of numerical values ​​is given herein, it is meant to include the cited numbers (fractional or integral) within the stated range. The expressions "range / ranging" between a first and second designator number and "range / ranging" from a first designator number to a second designator number are used interchangeably herein and are meant to include the first and second designator numbers and all fractional and integer numbers therebetween.

[0114] It should be understood that certain features of embodiments that are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of embodiments that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or in any other described embodiment, as appropriate. Certain features described in the context of various embodiments should not be construed as essential features of those embodiments, unless the embodiments cannot function without those elements.

[0115] While the embodiments have been described in connection with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0116] Applicant intends that all publications, patents, and patent applications referenced herein be incorporated herein by reference in their entirety as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated herein by reference. Furthermore, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent section headings are used, they should not be construed as necessarily limiting. Additionally, any priority documents of this application are incorporated herein by reference in their entirety.

Claims

1. An apparatus (100) for computing, comprising at least one processing circuit (110) configured to compute a result of executing a set of computer instructions of a software program, said set of computer instructions including a set of data variables, said computing comprising: Identifying (201) an initial state of at least one processing circuit; identifying (405) at least one estimated data value, the at least one estimated data value being at least one value of at least one set of data variables that is expected to be calculated by executing the set of computer instructions and that is calculated using one or more program data values ​​of the set of computer instructions; the at least one processing circuit, Executing (203) at least a portion of a predicted set of computer instructions generated according to an estimated order of execution of the set of computer instructions predicted based on the set of computer instructions and the at least one estimated data value; identifying (210) a prediction failure during execution (203) of at least a portion of the predicted set of computer instructions, where the at least one data variable is not equal to the at least one estimated data value according to at least one data variable test; Restoring (211) an initial state of said at least one processing circuit; Executing (212) one of at least one alternative set of computer instructions generated based on the set of computer instructions and the at least one estimated data value. 420) configuring the Including, program data values ​​are values ​​of data variables of program data of said set of computer instructions; the at least one estimated data value is used by at least one of the sets of computer instructions when the set of computer instructions is executed; Calculating the at least one estimated data value comprises: applying a unitary Boolean operator to at least one of the at least one program data value; applying an arithmetic operation to two or more of the at least one program data value; While executing the set of computer instructions, obtaining the at least one estimated data value from a memory component coupled to the at least one processing circuit. The apparatus includes at least one of the following:

2. The at least one processing circuit collecting (310) a plurality of statistics during execution of the set of computer instructions, the statistics including a plurality of data statistics indicative of one or more data values ​​of a set of data variables, and additionally or alternatively at least one branch statistic indicative of a selected instruction executed in response to executing at least one branch instruction of the set of computer instructions; providing (320) the plurality of statistical values ​​to at least one hardware processor for the purpose of identifying at least one estimated data value according to the plurality of statistical values; The apparatus of claim 1 further configured to:

3. The apparatus of claim 2 , wherein the at least one processing circuit includes telemetry circuitry (112) for collecting at least one of the plurality of statistics.

4. The apparatus of claim 2 , wherein the set of computer instructions includes at least one monitoring instruction for collecting at least one of the plurality of statistics.

5. The apparatus of claim 1 , wherein the at least one processing circuit comprises a processing circuit having a von Neumann architecture.

6. The apparatus of claim 1 , wherein the at least one processing circuit comprises a processing circuit having a non-von Neumann architecture.

7. the at least one processing circuit includes a first processing circuit and a second processing circuit; the first processing circuit is not the second processing circuit; executing the at least a portion of the anticipated set of computer instructions by the first processing circuit; execution of the alternative set of computer instructions by the second processing circuit; identifying an initial state of the at least one processing circuit includes identifying a plurality of state values ​​of the first processing circuit; Restoring the initial state of the at least one processing circuit includes configuring the second processing circuit according to the plurality of state values.

10. The apparatus of claim 1.

8. the at least one processing circuit has a supported instruction set; the supported instruction set includes a restore instruction for configuring a state of the processing circuit according to a previous known state of the processing circuit; Restoring the initial state of the at least one processing circuit includes executing the restore instruction conditioned on identifying a failure of the prediction during execution of the at least a portion of the predicted set of computer instructions.

10. The apparatus of claim 1.

9. Identifying (201) an initial state of at least one processing circuit; identifying (405) at least one estimated data value, the at least one estimated data value being expected to be calculated by executing a set of computer instructions of a software program, the at least one estimated data value being at least one value of at least one set of data variables of the set of computer instructions calculated using one or more program data values ​​of the set of computer instructions, the set of computer instructions including the at least one set of data variables; the at least one processing circuit, Executing (203) at least a portion of a predicted set of computer instructions generated according to an estimated order of execution of the set of computer instructions predicted based on the set of computer instructions and the at least one estimated data value; identifying (210) a prediction failure during execution (203) of at least a portion of the predicted set of computer instructions, where the at least one data variable is not equal to the at least one estimated data value according to at least one data variable test; Restoring (211) an initial state of said at least one processing circuit; Executing (212) one of at least one alternative set of computer instructions generated based on the set of computer instructions and the at least one estimated data value. 420) configuring the Including, program data values ​​are values ​​of data variables of program data of said set of computer instructions; the at least one estimated data value is used by at least one of the sets of computer instructions when the set of computer instructions is executed; Calculating the at least one estimated data value comprises: applying a unitary Boolean operator to at least one of the at least one program data value; applying an arithmetic operation to two or more of the at least one program data value; While executing the set of computer instructions, obtaining the at least one estimated data value from a memory component coupled to the at least one processing circuit. A calculation method including at least one of the following.

10. At least one hardware processor (101) for generating (410, 415) the predicted set of computer instructions and the at least one alternative set of computer instructions, the predicted set of computer instructions being generated according to an estimated order of execution of the set of computer instructions predicted based on the set of computer instructions and the at least one estimated data value. The apparatus of claim 1 further comprising:

11. The at least one hardware processor further comprises: receiving (401) from at least one other hardware processor a plurality of statistics including a plurality of data statistics indicative of one or more data values ​​of a set of data variables during execution of the set of computer instructions, and additionally or alternatively at least one branch statistic indicative of a selected instruction executed in response to executing at least one branch instruction of the set of computer instructions; identifying at least one estimated data value according to the plurality of statistical values; The device of claim 10, configured to:

12. Generating the predicted computer instruction set includes: at least one store instruction (501) for storing an initial state of said at least one processing circuit; at least a portion of the predicted set of computer instructions (503) generated based on the set of computer instructions and the at least one estimated data value; at least one condition test instruction (505) for identifying a failure of prediction; at least one restore instruction (508) for restoring the initial state of the at least one processing circuit; The apparatus of claim 10, further comprising:

13. generating at least a portion of the predicted computer instruction sets includes identifying at least one provisional instruction set in the computer instruction sets, each provisional instruction set associated with at least one local test instruction, each provisional instruction set being predicted to execute conditional on a result of the associated respective at least one local test instruction; The at least one state test instruction is generated in accordance with the at least one local test instruction.

13. The apparatus of claim 12.

14. generating the anticipated computer instruction set includes: identifying (601) at least one loop of computer instructions within said set of computer instructions; identifying (603) an expected number of iterations of the loop of computer instructions according to the plurality of statistics; generating (607) a rolled-out loop of instructions by repeating at least a portion of said loop of computer instructions for an expected number of iterations of said loop; 12. The apparatus of claim 11, comprising:

15. generating the anticipated computer instruction set includes: identifying (610) a plurality of data-independent operations in the rolled-out loop of instructions, wherein an expected result of executing the plurality of data-independent operations does not depend on changing another runtime value of a set of data variables during execution of the rolled-out loop of instructions; generating (620) the predicted set of computer instructions according to the predicted results; The apparatus of claim 14 further comprising:

16. generating the predicted set of computer instructions according to the expected result; Identifying (701) a plurality of memory access operations for a plurality of vector elements of a vector data variable of the set of computer instructions in the rolled-out loop of instructions; Replacing (705) the multiple memory access operations with a single equivalent memory operation.

16. The apparatus of claim 15, further comprising:

17. generating the anticipated computer instruction set includes: generating (620) a first set of the expected computer instructions according to the expected results; Identifying (610) a plurality of other data-independent operations in the first set of anticipated computer instructions; generating (620) a second set of expected computer instructions according to other expected results from executing the plurality of other data-independent scans; The apparatus of claim 11 , comprising:

18. generating the anticipated computer instruction set includes: generating (410) another first set of predicted instructions based on the at least one estimated data value; identifying (405) at least one other estimated data value according to the plurality of statistical values, wherein the at least one other estimated data value is at least one other value of at least one other set of said data variables that is predicted during execution of the other first predicted set of instructions; generating (410) a second set of other predicted instructions based on the at least one other estimated data value; The apparatus of claim 11 , comprising:

19. Configuring the at least one processing circuit includes: Computing (801) at least one predicted data flow graph according to said predicted computer instruction set; projecting (802) the at least one data flow graph onto at least a portion of the at least one processing circuit; Computing (810) at least one alternative data flow graph according to at least one of the at least one alternative computer instruction sets; projecting (812) the at least one alternative data flow graph onto at least another portion of the at least one processing circuit; 12. The apparatus of claim 11, comprising:

20. The predicted set of computer instructions and the at least one alternative set of computer instructions are generated according to an estimated order of execution of the set of computer instructions predicted based on the set of computer instructions and the at least one estimated data value.

10. The method of claim 9.

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