Power Module

Abstract

a positive voltage BUS having at least one pair of integrated power boards with at least two embedded power semiconductor dies, a first integrated power board of the pair having a first positive terminal, a first power semiconductor die, a first midpoint terminal, a second power semiconductor die, and a first negative terminal in line with a first current flow direction from the first negative terminal to the first positive terminal, and a second integrated power board of the pair having a second positive terminal, another first power semiconductor die, a second midpoint terminal, another second power semiconductor die, and a second negative terminal in line with a second current flow direction from the second negative terminal to the second positive terminal; and a PCB busbar providing a + current supply and a negative voltage BUS- current supply to the first integrated power board and the second integrated power board, the first integrated power board being positioned on the first side of the PCB busbar and having its first positive terminal connected to connection pads on the first side of the PCB busbar, a first midpoint terminal and a first negative terminal, and the second integrated power board being positioned on the second side of the PCB busbar and having its first positive terminal connected to further connection pads on the second side of the PCB busbar, the first integrated power board and the second integrated power board being oriented head-to-tail such that first and second current flow directions are in opposite directions.

Description

[Technical Field]

[0001] The present disclosure relates to a power module. [Background technology]

[0002] In power electronics, power semiconductors control electrical power by turning current flow on and off. In transistor-based (bipolar or MOSFET) voltage-source converters, this switching means rectifying current back and forth between the transistor, the freewheeling diode, and the power supply. In an ideal circuit, the transistor driver controls the shape of the voltage and current waveforms. There are no voltage spikes or oscillations. The only deviations from the ideal waveforms are the reverse recovery currents in the diodes and the transistor tail currents. Such switching transitions can be considered "clean switching."

[0003] However, real power circuits contain inductance and capacitance as major parasitic components, which cause serious deviations from clean switching. The basic effect of parasitic inductance is: - voltage dip during turn-on of the controlled transistor caused by a rise in current; -Voltage spikes across the diode when the reverse recovery current is decreasing; -Voltage spikes during transistor turn-off caused by current decay; is. Additionally, the parasitic capacitance forms a resonant circuit with the parasitic inductance, resulting in undesirable oscillations after each switching transition.

[0004] In addition to these fundamental effects, parasitic inductances modify the switching characteristics of bipolar power semiconductors. Consequently, an optimal circuit design with minimum parasitic inductance is a prerequisite for optimizing power semiconductors for lowest losses, as discussed in [1].

[0005] Non-Patent Document 2 provides a good example of how stray inductance can be reduced using an anti-parallel arrangement of each phase leg of a converter. The stray inductance drops from 19.8 nH to 3.8 nH between the parallel and anti-parallel arrangements. This reduction is brought about by electromagnetic field cancellation of two adjacent conductors carrying currents in opposite directions within the same substrate.

[0006] As seen above, parasitic inductance is a well-known problem that every power module designer tries to reduce as much as possible. One of the ways to stabilize the transistor and its power cell, including the parasitic inductance, is to add decoupling capacitors closest to the switching device. The goal of this decoupling capacitor is to provide a clean energy source to the power die at a minimum distance to avoid RLC parasitics that would contaminate the clean energy source close to the power transistor. These decoupling capacitors are often ceramic-based and are combined with film capacitors that provide filtering due to their energy density for their behavior at high frequencies.

[0007] In the case of power modules using integrated power board (IPB) technology, another challenge to be addressed is the compatibility between the materials used in the PCB stack of such IPBs, as discussed in Non-Patent Document 3. Copper, epoxy resin, silicone, etc. have different thermal expansion coefficients (CTE), which limits the reliability of the package when subjected to high thermal stresses.

[0008] It is also known that in packaging design, matching the different CTEs of each selected material is key to increasing product reliability. In the case of PCB-based packaging, the CTE mismatch between copper and epoxy resin can already be quite high. Adding and soldering ceramic capacitors on top has been identified as a weak point during cycling, as discussed in Non-Patent Document 4. Potting is often used to remove the constraints on the package and avoid cracking of the capacitor ceramic.

[0009] In the case of IPB designs, adding ceramic-based capacitors increases the difference in thermal expansion coefficients in the stack, thus reducing the reliability of the package.

[0010] Moreover, IPB packaging is targeted at high-density applications, where designers prioritize avoiding adding components to the package and limiting their footprint. However, there continues to be a need for higher energy density capacitors, such as ceramic-based or film capacitors.

[0011] In this situation, a solution should be found to avoid the use of decoupling capacitors close to the die in IPB packages by reducing the stray inductance within the package.

[0012] An intermediate solution could be considered where silicon capacitors are incorporated into the IPB. However, because silicon capacitors have a low capacitive density, while such capacitors can provide local decoupling for fast switching, there is still a need for higher energy density decoupling capacitors. [Prior art documents] [Non-patent literature]

[0013] [Non-Patent Document 1] Miller, Gerhard, “New Semiconductor Technologies challenge Package and System Setups” (CIPS, Nurnberg, 2010) [Non-patent document 2] K. Takao and S. Kyogoku, "Ultra low inductance power module for fast switching SiC power devices," presented at the International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2015, pp. 313-316. [Non-patent document 3] S. Lu, T. Zhao, RP Burgos, G. Lu, S. Bala, and J. Xu, “PCB-Interposer-on-DBC Packaging of 650 V, 120 A GaN HEMTs,” 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2020, pp. 370-373, doi: 10.1109 / APEC39645.2020.9124159) [Non-patent document 4] K. McKinney, R. Rice, and C. Wu, "Mechanical Failure Characteristics of Ceramic Multilayer Capacitors" (J. Amer. Ceram. Soc., vol. 69, no. 10, pp. C228, 1986) Summary of the Invention [Problem to be solved by the invention]

[0014] The present disclosure relates to a power module based on a capacitor-less integrated power board (IPB) design made possible by developing a specific PCB bus bar between IPBs, in particular at least one pair of IPBs each forming a half-bridge electrically connected in parallel, and an anti-parallel assembly of an integrated power module on such PCB bus bar. [Means for solving the problem]

[0015] More precisely, the present disclosure relates to at least one pair of integrated power boards having at least two embedded power semiconductor dies, wherein a first integrated power board of the pair has a first positive terminal, a first power semiconductor die, a first mid-point terminal, a second power semiconductor die, and a first negative terminal in line, with a first current flow direction from the first negative terminal to the first positive terminal, and a second integrated power board of the pair has a second positive terminal, another first power semiconductor die, a second mid-point terminal, another second power semiconductor die, and a second negative terminal in line, with a second current flow direction from the second negative terminal to the second positive terminal; a PCB bus bar having opposing first and second surfaces and having power conductive tracks and connection pads on both the first and second surfaces, providing a positive voltage BUS+ current supply and a negative voltage BUS- current supply to the first and second integrated power boards, the first integrated power board being positioned on the first surface of the PCB bus bar and having its first positive terminal connected to a connection pad on the first surface of the PCB bus bar; a PCB bus bar having a first positive terminal, a first midpoint terminal, and a first negative terminal, the second integrated power board being positioned on the second surface of the PCB bus bar and having its first positive terminal, first midpoint terminal, and first negative terminal connected to further connection pads on the second surface of the PCB bus bar, the first integrated power board and the second integrated power board being oriented head-to-tail such that first and second current flow directions are in opposite directions; The present invention relates to a power module having:

[0016] In this design, the IPBs in a pair of IPBs are connected by a PCB bus bar. The IPBs are rotated 180 degrees and face each other. In each IPB, current flows from the BUS- connection to the BUS+ connection, generating an electromagnetic field. The generated counter-electromagnetic fields cancel each other out. Parasitic inductance is thus reduced, and the interconnection with the bus bar also keeps the parasitic inductance low.

[0017] The IPB on each side of the busbar comprises two power semiconductors arranged to form a half-bridge, and the use of PCB busbars allows for high-speed switching characteristics due to the minimization of parasitic inductance and capacitance made possible with such a design.

[0018] In implementations or alternatives that can be combined, The PCB busbar may comprise at least one positive voltage distribution conductive track and at least one negative voltage distribution conductive track insulated from one another using an insulating substrate, and on a first side of the PCB busbar: a first connection area may be provided on the first side of the PCB bus bar connecting the positive voltage distribution conductive track to a positive voltage BUS+, the first connection area being connected through the positive voltage distribution conductive track and a first via in the PCB bus bar to a first connection pad on the first side of the PCB bus bar connecting a first positive terminal of the first integrated power board and a second connection pad on the second side of the PCB bus bar connecting a second positive terminal thereof; A second connection area may be provided on the second side of the PCB bus bar connecting the negative voltage distribution conductive track to a negative voltage BUS+, the second connection area being connected through the negative voltage distribution conductive track and a second via in the PCB to a third connection pad on the second side of the PCB bus bar connecting a second negative terminal and to a fourth connection pad on the first side connecting the first negative terminal.

[0019] The PCB bus bar may further comprise at least one third connection area providing an output electrical connection on a second side of the PCB bus bar; at least one output connection track, an output connection via, and an output connection pad connecting the first intermediate point terminal on the first side of the PCB and the second intermediate point terminal on the second side of the PCB; It can be equipped with:

[0020] The first side may be a first longitudinal side of the PCB bus bar, and the second side may be a first lateral side of the PCB bus bar.

[0021] The power semiconductor die may have gate or base terminals connected to gate or base control terminals on the PCB bus bars through gate or base connection pads and gate or base connection tracks.

[0022] The power module may comprise further integrated power boards arranged in pairs on the opposing first and second faces of the PCB beside the first pair of integrated power boards and connected to PCB busbar tracks.

[0023] The integrated power boards may be oriented such that the direction of current flow in each integrated power board is opposite to the direction of current flow in its nearest neighbor integrated power board.

[0024] Parasitic RLC components can be at least partially tuned within a PCB busbar by adapting the thicknesses of the insulating and conductive layers of the PCB busbar.

[0025] In a preferred embodiment, the PCB busbar may include a main decoupling capacitor connected to the positive voltage distribution conductive track and the negative voltage distribution conductive track. This allows reducing the size of the IPB and limiting thermal stress thereon, since the main decoupling capacitor, ceramic or film, is external to the IPB. Such filtering capacitors may be located on contact pads on the third side of the PCB busbar.

[0026] The advantage of this design is that the sub-nH parasitic stray inductance resulting from this assembly allows for the elimination of decoupling capacitors external to the complex IPB module assembly. By lowering the parasitic inductance to the sub-nH range, it is not necessary to maintain a clean energy source close to the die to obtain clean switching behavior of the die. Therefore, it is not necessary to place a decoupling capacitor acting as an energy source close to the die or dies.

[0027] The assembly may also include at least one additional silicon decoupling capacitor on the busbar substrate, such silicon capacitor exhibiting little capacitance while maintaining a temperature expansion coefficient matched to that of the PCB busbar.

[0028] The power module can include heat sinks on the integrated power board on both sides of the PCB busbars, allowing for a compact yet efficiently cooled design.

[0029] Each board of a pair of integrated power boards can form a half-bridge.

[0030] In another design, all pairs of integrated power boards are connected in parallel to form a single half-bridge.

[0031] A detailed description of exemplary embodiments of the present invention is discussed below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a perspective view of a power module according to the present disclosure. [Figure 2A] 1A-1C are side cutaway views of different locations of an implementation of a power module according to the present disclosure. [Figure 2B] 1A-1C are side cutaway views of different locations of an implementation of a power module according to the present disclosure. [Figure 2C] 1A-1C are side cutaway views of different locations of an implementation of a power module according to the present disclosure. [Figure 3] FIG. 1 is a schematic diagram of an example of a portion of a PCB layout compatible with a power module according to the present disclosure. [Figure 4] FIG. 10 is a diagram illustrating an example of a power module according to a further embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention relates to a power module as disclosed in Figure 1, which comprises at least a pair of integrated power boards (IPBs) 1a, 1b arranged on a PCB busbar 2. Such a PCB busbar provides at least BUS+ and BUS- contact pads 31, 32 for supplying current to the pair of IPBs.

[0034] As shown in FIG. 2A, which is a first transverse cutaway view of the power module at a first position, a pair of integrated power boards 1a, 1b each include two embedded power semiconductor dies 1a, 12a, 11b, 12b. While such semiconductors are depicted as MOSFET transistors, they may be any type of power switch (IGBT, FET, etc.) or any other solid-state power switching semiconductor. A first IPB 1a, located at the top of the PCB bus bar in the figure, includes two power semiconductor dies 11a, 12a, and a second IPB located at the bottom of the PCB bus bar includes two power semiconductor dies 11b, 12b. The second IPB 1b is rotated 180 degrees from the first IPB 1a.

[0035] Each IPB has a first positive terminal 110a, 110b, a first power semiconductor die 11a, 11b, a first midpoint terminal 112a, 113a, 112b, 113b, a second power semiconductor die 12a, 12b, and a first negative terminal 114a, 114b, in line. The direction of current flow in an IPB in use is from the first negative terminal 114a to the first positive terminal 110a.

[0036] The PCB bus bars are arranged to provide a positive voltage BUS+ current supply and a negative voltage BUS- current supply to the first IPB and the second IPB.

[0037] According to the disclosed design, the PCB busbar has a BUS+ connection area 31 on a first surface 2a and a BUS− connection area 32 on a second surface 2b at a first longitudinal end, also shown as a first side 2c of the PCB busbar. Since the IPBs are arranged head-to-tail on both sides of the PCB busbar, the connections of the positive terminals 110a, 110b of such IPBs must be made on both sides of the PCB. From the BUS+ connection area 31, a first track 211a is connected to a via 221 traversing the thickness of the PCB, comprising a connection pad 21a connecting the first positive terminal 110a. Such a via is connected to a second track 211b comprising a further pad 21b on the other side of the PCB, connecting the second positive terminal 110b.

[0038] 2B is a transverse cutaway view of the power module in another position, but upside down. Fig. 2B shows the paths connecting the negative terminals 22a, 22b of the two IPBs to the BUS-connection area 32. A third track 212b starts from the connection area 32 at the first longitudinal end 2c of the PCB, comprises the third connection pad 22b of the second negative terminal 114b, and is connected through a via 222 to a fourth track 212a on the other side of the PCB. The fourth track 212a is connected to the fourth connection pad 22a and ends at the second longitudinal end, also called the third side 2e, of the PCB.

[0039] This case can be explained as follows: Two IPBs with a 2-in-1 configuration are connected by a PCB busbar. The IPBs are rotated 180 degrees and face each other. In each IPB, current flows from the BUS- connection to the BUS+ connection, generating an electromagnetic field. The generated counter-electromagnetic fields cancel each other out. Parasitic inductance is consequently reduced, and the interconnection with the busbar also keeps the parasitic inductance low.

[0040] Figure 2C shows a possible connection between the first midpoint terminal 112a of the first IPB 1a and the second midpoint connection 112b of the second IPB 1b through embedded tracks 213a, 213b and embedded via 223. The output track 225 shown in the example PCB layout of Figure 3 is connected to an output pad 33 on the second side 2d, i.e., the first lateral end, of the PCB.

[0041] The connections of the gates, not shown, are made according to the wiring of the module. All gates can be separated and connected to their own contact pads on side 2f of the module, or the gates of the upper branch power semiconductors can be connected together to contact pad 7a in Figure 4, while the lower branch semiconductors can have their gates connected together to contact pad 7b.

[0042] FIG. 3 provides an example of a PCB layout in which the BUS+ and BUS− tracks are laterally offset on the PCB to avoid via 221 in FIG. 2A and via 222 in FIG. 2B. The BUS+ circuit includes BUS+ connection pad 32, track 212a, first positive connection pad 22a, and capacitor connection pad 5 on the first side of the PCB. The output of the midpoint connection in the drawing showing the second side of the PCB includes connection pad 23a, embedded track 225, via 227, and surface connection pad 33. The same configuration is provided on the first side of the PCB (dotted lines in the drawing). Such a simplified layout can be improved to provide larger connection pads for the power terminals of the IPB. The gate connection circuitry may comprise connection pads 24a, 24' on the upper surface and gate connection pads 24b, 24'b (not shown) on the lower surface, with embedded tracks 226, 226' arranged to provide the necessary gate control connections to connection pads 7a, 7b. Possible wiring arrangements include wiring the gates of semiconductors 11a, 11b together to a first gate connection pad, e.g., 7a, and wiring the gates of semiconductors 12a, 12b together to a second gate connection pad, e.g., 7b, or wiring each gate to its own connection pad.

[0043] Returning to Figure 2B, capacitor connections 5, 6 on the third side 2e of the PCB receive a main decoupling capacitor 40 connected to the positive and negative voltage distribution conductive tracks. This capacitor, external to the integrated power board, provides an overall energy source close enough to the power transistors without reducing the life of the IPB.

[0044] The resulting design, in which each side and face of the PCB has a connection area, makes connections simple and efficient.

[0045] Additional silicon decoupling capacitors 41 can be incorporated into the busbar substrate, which is less susceptible to temperature cycling than the IPB.

[0046] By lowering the stray inductance of the package and IPB interconnects, it is possible to avoid the constraints on integrating close-range decoupling ceramic capacitors. Sub-nH PCB busbars and anti-parallel techniques avoid large decoupling ceramic capacitors near the die. In other words, capacitive devices are placed far away from the switching cells with busbar interconnects between them.

[0047] By placing the capacitive element outside the IPB, manufacturing is much easier, package reliability is improved, and costs are reduced due to the simplified manufacturing process.

[0048] In the packaging design, the matching of different TECs is not limited by the ceramic capacitors, thus providing improved reliability of the product.

[0049] FIG. 4 shows a power module provided with two pairs of IPBs, each pair having two power semiconductor dies 11a, 12a, 11'a, 12', to form a four IPB module.

[0050] The module may include two or more pairs of IPBs to increase the current capacity of the power module.

[0051] Power modules in which the gate and midpoint terminals of the IPBs are separated can also be constructed using IPBs on both sides of the PCB busbar configuration of the present disclosure.

[0052] In each IPB, the current flowing from the BUS- connection to the BUS+ connection generates an electromagnetic field. In addition, because each pair of IPBs is rotated 180 degrees and faces each other, the generated counter electromagnetic fields cancel each other out. As a result, parasitic inductance is reduced.

[0053] When two or more pairs of head-to-tail oriented IPBs are used, the integrated power boards can be oriented such that the current direction in each integrated power board is opposite to the current direction in its nearest neighbor integrated power board or boards.

[0054] Furthermore, the interconnections to the bus bars are designed to keep parasitic inductance low by reducing the height of the connection pads and limiting the track length. The overall package assembly is poorly inductive, and the sub-nH parasitic stray inductance caused by this assembly allows decoupling capacitors to be placed outside the complex IPB module assembly. By lowering the parasitic inductance to the sub-nH range, it is not necessary to maintain a clean energy source close to the die to obtain clean switching behavior of the die. Therefore, there is no need to place decoupling capacitors acting as an energy source close to the die.

[0055] The busbar can be a four-layer PCB with DC+ and DC- on two opposing layers, with one embedded layer providing the crossover tracks and an additional layer used for midpoint-to-gate connections when the gates are connected through the PCB busbar. The external midpoint connections are preferably perpendicular to the DC+ and DC- for electromagnetic decoupling. The IPB connections use either a double anti-parallel or single anti-parallel configuration, which means alternating the DC+ and DC- connections on both sides by flipping two facing IPBs.

[0056] IPB modules can be brazed to the busbar, silver sintered, or mechanically attached. To limit inductance, short connections to the PCB busbar are preferred.

[0057] The subject matter of this disclosure can be used in applications requiring power switching, such as power converters, motor controls, or inverters.

[0058] The above description is of implementation examples and should not be considered limiting. Other designs are possible within the scope of the appended claims, in particular, a power module can comprise two or more pairs of IPBs on a single PCB busbar, and the midpoint terminal connections can be separate or common on each side, while the gate connections can be separate or grouped depending on the configuration of the module.

Claims

[Claim 1] at least one pair of integrated power boards each having at least two embedded power semiconductor dies, wherein a first integrated power board of the pair has a first positive terminal, a first power semiconductor die, a first midpoint terminal, a second power semiconductor die, and a first negative terminal in a row, with a first current flow direction from the first negative terminal through the first power semiconductor, the first midpoint terminal, and the second semiconductor to the first positive terminal, and a second integrated power board of the pair has a second positive terminal, another first power semiconductor die, a second midpoint terminal, another second power semiconductor die, and a second negative terminal in a row, with a second current flow direction from the second negative terminal through the other first power semiconductor, the second midpoint terminal, and the other second semiconductor to the second positive terminal; a PCB bus bar having opposing first and second sides and having power conductive tracks and connection pads on both the first and second sides, providing a positive voltage BUS+ current supply and a negative voltage BUS− current supply to the first and second integrated power boards, the first integrated power board being positioned on the first side of the PCB bus bar and having its first positive terminal connected to connection pads on the first side of the PCB bus bar, a first midpoint terminal, and a first negative terminal, and the second integrated power board being positioned on the second side of the PCB bus bar and having its first positive terminal connected to further connection pads on the second side of the PCB bus bar, the first and second integrated power boards being oriented head-to-tail such that the first and second current flow directions are in opposite directions; A power module having:

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